A method and system for multi-target end-point shortest delay network layout based on integrated circuits

Abstract

The application discloses a kind of multi-target end point shortest delay network layout method and system based on integrated circuit, first, multi-target end point identification and automatic grouping.Second, when all leaf nodes complete grouping, buffer network construction is needed, the key is how to guarantee that all branch nodes are connected to starting point while forming common network, reduce the number of buffer.The solution is to construct the buffer network of the farthest branch node in the group first.Finally, through the grouping of target end point and the construction of buffer network, the number of buffers is reduced on the basis of connecting all end points by forming common buffer network;For the target node with blocking or special delay requirement, separate optimization is completed to improve flexibility.The application can be widely applied to the buffer network construction of layout and wiring link in various designs, typical applications include the realization of module-related shortest delay path in a certain chip, the timing optimization of memory access path in a certain high-performance processor project.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor components and integrated circuits, and relates to a method and system for laying out multi-objective endpoint shortest delay networks based on integrated circuits. Background Technology

[0002] In the design of modern large-scale digital integrated circuits, EDA tools are used for placement and routing. However, when building buffer networks with multiple endpoints, complex situations arise, such as hard core regions blocking the routing area, limited routing areas, and special timing requirements for some endpoints. In such cases, the processing capabilities of EDA tools are clearly insufficient. In particular, the tools perform poorly in meeting the requirements of specifying paths, prioritizing delays, and ensuring equal lengths for multiple endpoints in buffer networks within large-scale memory arrays. The controllability of the tools during the optimization process is insufficient, and they are gradually failing to meet the design requirements of high-performance SOC chips. Summary of the Invention

[0003] The purpose of this invention is to solve the problem that when using EDA tools for layout and routing in the prior art, hard core areas block and routing areas are limited when building buffer networks with multiple target endpoints. This invention provides a method and system for laying out multi-target endpoint shortest delay networks based on integrated circuits.

[0004] To achieve the above objectives, the present invention employs the following technical solution:

[0005] This invention proposes a multi-objective endpoint shortest delay network layout method based on integrated circuits, comprising the following steps:

[0006] Obtain the multi-target endpoints of the integrated circuit and group the multi-target endpoints;

[0007] Construct a buffer network for the furthest branch node in the group;

[0008] Record the points in the grid of the buffer network as driving nodes;

[0009] The list of driver nodes and branch nodes is updated gradually until all branch nodes have been connected to the driver nodes, thus achieving the layout of the minimum buffer network.

[0010] Preferably, the coordinates of the multi-target endpoints are obtained based on the starting point of the multi-target endpoints and the preliminary layout of the integrated circuit.

[0011] Preferably, the method for grouping multiple target endpoints is as follows:

[0012] The endpoint logic and coordinates are obtained by identifying the connection relationships of integrated circuits and marked as leaf nodes;

[0013] A grid-type coordinate system is constructed with the starting point of the multi-target endpoint as the center, based on the step values ​​in the X and Y directions specified by the user.

[0014] A grid is formed based on the difference between the coordinates of the leaf nodes and the endpoints of multiple targets, and a grid-type coordinate system;

[0015] If there are leaf nodes in the grid, record the grid number as a branch node;

[0016] Group all leaf nodes and record their information.

[0017] Preferably, the connection distances of other branch nodes in each group are automatically compared with the existing driver nodes in order of distance from farthest to nearest, and the nearest driver node is selected to construct the buffer network.

[0018] Preferably, manual intervention is used for driving nodes in special locations, and the path of the driving node is specified through a separate command.

[0019] Preferably, when constructing the grid-type coordinate system, it is divided into 8 groups according to a 45° angle.

[0020] Preferably, redundant driver nodes are deleted once all branch nodes have completed the connection with the nearest driver node.

[0021] This invention proposes a multi-objective endpoint shortest delay network layout system based on integrated circuits, comprising:

[0022] The target endpoint grouping module is used to acquire multiple target endpoints of the integrated circuit and group the multiple target endpoints.

[0023] A buffer network construction module is used to construct a buffer network for the furthest branch node in a group;

[0024] A driver node acquisition module is used to record points of the grid in the buffer network as driver nodes.

[0025] The node matching module is used to gradually update the list of driving nodes and branch nodes until all branch nodes have been connected to the driving nodes, thereby realizing the layout of the minimum buffer network.

[0026] A computer device includes a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement steps of a multi-objective endpoint shortest delay network layout method based on integrated circuits.

[0027] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of a multi-objective endpoint shortest delay network layout method based on integrated circuits.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] This invention proposes a multi-target endpoint shortest latency network placement method based on integrated circuits. First, multi-target endpoints are identified and automatically grouped. Second, after all leaf nodes are grouped, a buffer network needs to be constructed. The key is to ensure that all branch nodes are connected to the starting point while forming a common network, thus reducing the number of buffers. The solution is to first construct the buffer network for the farthest branch node in the group. Finally, through the grouping of target endpoints and the construction of the buffer network, on the one hand, by forming a common buffer network, the number of buffers is reduced while connecting all endpoints; on the other hand, target nodes with obstructions or special latency requirements are individually optimized, improving flexibility. The placement method proposed in this invention not only achieves automated optimal buffer network allocation and construction, but also can be applied to the placement and routing process to solve the problem of multi-target endpoint buffer network construction under placement and routing constraints. By combining automatic buffer network planning with manual intervention, a buffer network implementation scheme that meets design requirements is finally completed, improving design performance. This invention can be widely applied to buffer network construction in the placement and routing stages of various designs. Typical applications include the implementation of module-related shortest latency paths in a chip and memory access path timing optimization in a high-performance processor project.

[0030] Furthermore, the groups are divided into 8 groups at 45° angles. This is to avoid the four-quadrant grouping method causing branch nodes to be far apart and resulting in poor performance when the distance is too far.

[0031] Furthermore, it simultaneously supports a combination of manual intervention and automatic optimization, improving the flexibility and controllability of the optimization process and building a buffer network that better meets design requirements.

[0032] This invention proposes a multi-target endpoint shortest delay network layout system based on integrated circuits. By dividing the system into a target endpoint grouping module, a buffer network construction module, a driver node acquisition module, and a node matching module, it achieves the layout of a minimum buffer network. The modular approach ensures that each module is independent, facilitating unified management of all modules. Attached Figure Description

[0033] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a flowchart of the multi-objective endpoint shortest delay network layout method based on integrated circuits according to the present invention.

[0035] Figure 2 This is a system diagram of the multi-objective endpoint shortest delay network layout based on integrated circuits according to the present invention. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0037] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0038] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0039] In the description of the embodiments of the present invention, it should be noted that if terms such as "upper," "lower," "horizontal," or "inner" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, terms such as "first" and "second" are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0040] Furthermore, the use of the term "horizontal" does not imply that the component must be absolutely horizontal, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0041] In the description of the embodiments of the present invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific circumstances.

[0042] The present invention will now be described in further detail with reference to the accompanying drawings:

[0043] This invention proposes a multi-target endpoint shortest delay network layout method based on integrated circuits. The core idea is to transform the connection of multiple target endpoints into shortest path connection planning for several groups of regional driving nodes by grouping the target endpoints and constructing a coordinate system buffer network. This invention reduces the number of buffers by forming a common buffer network while connecting all endpoints; furthermore, it improves flexibility by individually optimizing target nodes with obstructions or special delay requirements. Figure 1 As shown, it includes the following steps:

[0044] S1. Obtain the multi-target endpoints of the integrated circuit and group the multi-target endpoints;

[0045] Based on the starting point of the multi-target endpoint and the preliminary layout of the integrated circuit, the coordinates of the multi-target endpoint are obtained.

[0046] The method for grouping multi-target endpoints is as follows:

[0047] The endpoint logic and coordinates are obtained by identifying the connection relationships of integrated circuits and marked as leaf nodes;

[0048] A grid-type coordinate system is constructed with the starting point of the multi-target endpoint as the center, based on the step values ​​in the X and Y directions specified by the user.

[0049] A grid is formed based on the difference between the coordinates of the leaf nodes and the endpoints of multiple targets, and a grid-type coordinate system;

[0050] If there are leaf nodes in the grid, record the grid number as a branch node;

[0051] Group all leaf nodes and record their information.

[0052] When constructing the grid-type coordinate system, it is divided into 8 groups according to a 45° angle.

[0053] S2. Construct a buffer network for the furthest branch node in the group;

[0054] The system automatically compares the connection distances of other branch nodes in each group with the existing driver nodes in order of distance from farthest to nearest, and selects the nearest driver node to build the buffer network.

[0055] S3. Record the points of the grid in the buffer network as driving nodes;

[0056] When manual intervention is required in special locations, the path of the driving node can be specified through a separate command.

[0057] S4. Gradually update the list of driver nodes and branch nodes until all branch nodes have been connected to the driver nodes, thus achieving the layout of the minimum buffer network.

[0058] Once all branch nodes have completed their connection to the nearest driver node, delete redundant driver nodes.

[0059] Specifically, it includes the following three steps:

[0060] Step 1: Multi-target endpoint identification and automatic grouping

[0061] Given the starting point and integrated circuit layout of the multi-target endpoint, the coordinates of the multi-target endpoint are obtained. The endpoint logic and coordinates are obtained by identifying the integrated circuit connection relationships and recorded as leaf nodes. This invention uses the starting point of the multi-target endpoint as the central origin and constructs a grid-type coordinate system using user-specified X and Y direction step values ​​(buffer intervals, adjustable). Eight groups are formed according to 45° angles (to avoid the four quadrant grouping method leading to large branch node distances and poor implementation when the distance is too far). The difference between the leaf node and the multi-target endpoint coordinates is rounded according to the step value (grid-type coordinate system) to form a rounded grid. For leaf nodes in the rounded grid, their grid number (X, Y) is recorded as a branch node, indicating that the subsequent node needs to build a buffer to connect with the leaf node, and related leaf node information is recorded until all leaf nodes are grouped.

[0062] Step 2: Buffer Network Construction and Path Selection

[0063] After all leaf nodes have been grouped, a buffer network needs to be constructed. The key is to ensure that all branch nodes are connected to the starting point while forming a common network, thus reducing the number of buffers. The solution is to first construct the buffer network for the branch node furthest from the 8 groupings. Since the buffer units are distributed on grid points in (X, Y) and the logical function of the buffers is the same as that of the starting point, these buffer grid points are recorded as driving nodes, which can be used to connect other branch nodes. Branch nodes can also act as driving nodes to connect other nodes.

[0064] In this invention, other branch nodes in each group are automatically compared with existing driving nodes in order of distance from farthest to nearest. The nearest driving node is selected for buffer network construction, and its connection scheme is recorded. For paths greater than one grid point (one X or one Y step value) from the nearest driving node, a new driving path needs to be generated, and the traversed grid points are updated in the driving node list. The driving node and branch node lists are updated progressively until all branch nodes have been connected to driving nodes. At this point, the constructed buffer network is the minimum buffer network connecting all leaf nodes.

[0065] In this step, for situations where manual intervention is required in special locations, the path strategy of the driving node can be specified through a separate command to avoid hard cores and wiring-restricted areas, and prioritize the processing of delayed areas (forming separate paths to avoid reusing the driving network can reduce latency). By introducing this approach, the design flexibility is improved, and the problems of poor controllability and inability to prioritize optimization of EDA tools are solved.

[0066] For special needs where multiple sets of endpoints have equal delay lengths, the system can automatically calculate the difference between the maximum path length and different path groups. By using identical path intervals and lengths, it extends other shorter paths to the same length as the longest path, thereby achieving an effect of approximately equal delay lengths.

[0067] Step 3: Buffer Network Connection and Optimization

[0068] Once all automatic buffer networks and manual interventions for the specified strategies are completed, this invention automatically connects the driver nodes and connects the corresponding leaf nodes to the driver nodes. Simultaneously, it performs functions such as deleting redundant driver nodes and optimizing connection strategies, thus completing the implementation of the entire buffer network.

[0069] This invention proposes a multi-objective endpoint shortest delay network layout system based on integrated circuits, such as... Figure 2 As shown, it includes a target endpoint grouping module, a buffer network construction module, a driver node acquisition module, and a node matching module;

[0070] The target endpoint grouping module is used to acquire multiple target endpoints of the integrated circuit and group these multiple target endpoints.

[0071] The buffer network building module is used to build a buffer network for the furthest branch node in a group;

[0072] The driver node acquisition module is used to record the points of the grid in the buffer network as driver nodes;

[0073] The node matching module is used to gradually update the list of driver nodes and branch nodes until all branch nodes have been connected to the driver nodes, thus realizing the layout of the minimum buffer network.

[0074] An embodiment of the present invention provides a terminal device comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps in the various method embodiments described above. Alternatively, when the processor executes the computer program, it implements the functions of each module / unit in the various device embodiments described above.

[0075] The computer program can be divided into one or more modules / units, which are stored in the memory and executed by the processor to complete the present invention.

[0076] The terminal device may be a desktop computer, laptop, handheld computer, or cloud server, etc. The terminal device may include, but is not limited to, a processor and a memory.

[0077] The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0078] The memory can be used to store the computer program and / or module. The processor implements various functions of the terminal device by running or executing the computer program and / or module stored in the memory and calling the data stored in the memory.

[0079] If the modules / units integrated into the terminal device are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0080] This invention proposes a multi-target endpoint shortest delay network placement method for integrated circuits. Belonging to the field of semiconductor components and integrated circuits, this invention relates to the placement and routing stage in the semi-custom flow of large-scale digital circuits. The algorithm primarily addresses the buffer network construction and optimization problem in placement and routing processes with a single starting point and multiple target endpoints, especially under complex conditions such as hard core region obstruction and routing constraints. This invention not only enables automated optimal buffer network allocation and construction but also supports a combination of manual intervention and automatic optimization, improving the flexibility and controllability of the optimization process and resulting in buffer networks that better meet design requirements.

[0081] A complete algorithm based on the TCL language has been developed and can be applied to the place-and-route process to solve the problem of building multi-target endpoint buffer networks under place-and-route constraints. By combining automatic buffer network planning with manual intervention, a buffer network implementation scheme that meets design requirements is ultimately achieved, improving design performance. For example, in large-scale memory array design, compared to the results automatically achieved by EDA tools, this invention reduces the latency of the furthest memory by 20% by increasing the number of buffers by 15%, while simultaneously solving routing congestion problems in the design. This invention can be widely applied to buffer network construction in the place-and-route stage of various designs and has been successfully applied in multiple projects, demonstrating its versatility. Typical applications include implementing the shortest latency path related to modules in a chip and optimizing memory access path timing in a high-performance processor project. The purpose of this invention is to use a self-developed algorithm to solve the problem of building multi-target endpoint buffer networks under place-and-route constraints. By combining automatic buffer network planning with manual intervention, it accomplishes functions that EDA tools cannot achieve, such as formulating path strategies, prioritizing latency, and implementing equal-length multi-endpoint buffers, ultimately achieving a buffer network implementation scheme that meets design requirements and improving design performance.

[0082] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for layouting multi-objective endpoint shortest delay networks based on integrated circuits, characterized in that, Includes the following steps: Obtain the multi-target endpoints of the integrated circuit and group the multi-target endpoints; Construct a buffer network for the furthest branch node in the group; Record the points in the grid of the buffer network as driving nodes; The list of driver nodes and branch nodes is updated gradually until all branch nodes have been connected to the driver nodes, thus realizing the layout of the minimum buffer network. The method for grouping multi-target endpoints is as follows: The endpoint logic and coordinates are obtained by identifying the connection relationships of integrated circuits and marked as leaf nodes; A grid-type coordinate system is constructed with the starting point of the multi-target endpoint as the center, based on the step values ​​in the X and Y directions specified by the user. A grid is formed based on the difference between the coordinates of the leaf nodes and the endpoints of multiple targets, and a grid-type coordinate system; If there are leaf nodes in the grid, record the grid number as a branch node; Group all leaf nodes and record their information.

2. The multi-objective endpoint shortest delay network layout method based on integrated circuits according to claim 1, characterized in that, Based on the starting point of the multi-target endpoint and the preliminary layout of the integrated circuit, the coordinates of the multi-target endpoint are obtained.

3. The multi-objective endpoint shortest delay network layout method based on integrated circuits according to claim 1, characterized in that, The system automatically compares the connection distances of other branch nodes in each group with the existing driver nodes in order of distance from farthest to nearest, and selects the nearest driver node to build the buffer network.

4. The multi-objective endpoint shortest delay network layout method based on integrated circuits according to claim 1, characterized in that, For drive nodes in special locations, manual intervention is used, and the path of the drive node is specified through a separate command.

5. The multi-objective endpoint shortest delay network layout method based on integrated circuits according to claim 1, characterized in that, When constructing the grid-type coordinate system, it is divided into 8 groups according to a 45° angle.

6. The multi-objective endpoint shortest delay network layout method based on integrated circuits according to claim 1, characterized in that, Once all branch nodes have completed their connection to the nearest driver node, delete redundant driver nodes.

7. A multi-objective endpoint shortest delay network layout system based on integrated circuits, characterized in that, The method for laying out a multi-objective endpoint shortest delay network based on integrated circuits, as described in any one of claims 1 to 6, includes: The target endpoint grouping module is used to acquire multiple target endpoints of the integrated circuit and group the multiple target endpoints. A buffer network construction module is used to construct a buffer network for the furthest branch node in a group; A driver node acquisition module is used to record points of the grid in the buffer network as driver nodes. The node matching module is used to gradually update the list of driving nodes and branch nodes until all branch nodes have been connected to the driving nodes, thereby realizing the layout of the minimum buffer network.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes a computer program, it implements the steps of the integrated circuit-based multi-target endpoint shortest delay network layout method as described in any one of claims 1 to 6.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the integrated circuit-based multi-objective endpoint shortest delay network layout method as described in any one of claims 1 to 6.

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