Universal Verification Platform and Method for Ethernet PHY Based on UVM

Abstract

This application discloses a UVM-based universal Ethernet PHY verification platform and method, belonging to the field of PHY verification, to achieve comprehensive and accurate verification of PHY functional behavior. The verification platform includes: a network cable model, a scoring board, two modules to be tested, a first sequence generator, a first Ethernet proxy module, a first physical interface, a second Ethernet proxy module, and a second physical interface. The first module to be tested is located at one end of the verification platform, and the second module to be tested is located at the other end of the verification platform.

Description

Technical Field

[0001] This application belongs to the field of Ethernet port physical layer (PHY) verification, specifically involving a UVM-based general verification platform and method for Ethernet PHY. Background Technology

[0002] Currently, verification plays an equally important role in the modern integrated circuit design process. Verification can ensure the correctness of the design and improve its productivity, thus providing a guarantee for shortening the chip development cycle. This makes verification a key bottleneck in chip design. The Universal Verification Methodology (UVM) platform, based on traditional hardware description languages, has become the mainstream verification solution in the industry.

[0003] However, test platforms written in traditional hardware description languages ​​cannot provide complete verification of reusability, thus failing to fully and accurately verify the functional behavior of the PHY. Summary of the Invention

[0004] This application provides a UVM-based Ethernet PHY universal verification platform and method, which can solve the problem of not being able to fully and accurately verify the functional behavior of PHY.

[0005] In a first aspect, embodiments of this application provide a UVM-based universal verification platform for Ethernet PHY, comprising: a network cable model, a scoring board, two modules to be tested, a first sequence generator, a first Ethernet proxy module, a first physical interface, a second Ethernet proxy module, and a second physical interface. The first module to be tested is located at one end of the verification platform, and the second module to be tested is located at the other end of the verification platform. The first sequence generator is used to generate a sequence request, wherein the sequence request includes a transaction-level sequence. The first Ethernet proxy module is used to receive the sequence request, convert the transaction-level sequence into a pin-level stimulus, and transmit it to the first physical interface. The first physical interface is used to output a first pin-level signal to the first module to be tested based on the pin-level stimulus. The first Ethernet proxy module is also used to acquire the first physical interface... The first pin-level signal is output from the port, and the first pin-level signal is converted into a transaction-level first target sequence, which is then transmitted to the scoring board. The first module under test is used to encode the first pin-level signal, convert the encoded data into serial data, and output it to the network cable model. The network cable model is used to transmit the serial data to the second module under test. The second module under test is used to decode the received serial data to obtain a second pin-level signal and output it. The second Ethernet proxy module is used to obtain the second pin-level signal output by the second module under test, convert the second pin-level signal into a transaction-level second target sequence, and transmit the second target sequence to the scoring board. The scoring board is used to compare whether the first target sequence and the second target sequence are the same, and determine whether the function of the module under test is accurate based on the comparison result.

[0006] Secondly, embodiments of this application provide a verification method, comprising: a first Ethernet proxy module of the verification platform receiving a sequence request, converting the sequence in the sequence request into a pin-level stimulus and transmitting it to a first physical interface of the verification platform; the first physical interface outputting a first pin-level signal to a first module under test of the verification platform based on the pin-level stimulus; the first Ethernet proxy module acquiring the first pin-level signal output by the first physical interface, converting the first pin-level signal into a transaction-level first target sequence, and transmitting the first target sequence to the scoreboard of the verification platform; and the first module under test encoding the first pin-level signal, and transmitting the encoded signal... The obtained data is converted into serial data and output to the network cable model of the verification platform; the network cable model transmits the serial data to the second module under test of the verification platform; the second module under test decodes the received serial data to obtain a second pin-level signal and outputs it; the second Ethernet proxy module of the verification platform obtains the second pin-level signal output by the second module under test, converts the second pin-level signal into a transaction-level second target sequence, and transmits the second target sequence to the scoring board; the scoring board compares whether the first target sequence and the second target sequence are the same, and determines whether the function of the module under test is accurate based on the comparison result.

[0007] Thirdly, embodiments of this application provide an electronic device that includes the verification platform described in the first aspect.

[0008] Fourthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the verification method as described in the second aspect.

[0009] In this embodiment, the verification platform includes: a network cable model, a scoreboard, two modules to be tested, a first sequence generator, a first Ethernet proxy module, a first physical interface, a second Ethernet proxy module, and a second physical interface. The first module to be tested is located at one end of the verification platform, and the second module to be tested is located at the other end of the verification platform. The first sequence generator generates a sequence request, which includes a transaction-level sequence. The first Ethernet proxy module receives the sequence request and converts the transaction-level sequence into a pin-level stimulus, transmitting it to the first physical interface. The first physical interface outputs a first pin-level signal to the first module to be tested based on the pin-level stimulus. The first Ethernet proxy module also acquires the first pin-level signal output by the first physical interface, converts the first pin-level signal into a transaction-level first target sequence, and transmits the first target sequence to the scoreboard. The first module under test is used to encode the first pin-level signal, convert the encoded data into serial data, and output it to the network cable model. The network cable model is used to transmit the serial data to the second module under test. The second module under test is used to decode the received serial data to obtain a second pin-level signal and output it. The second Ethernet proxy module is used to acquire the second pin-level signal output by the second module under test, convert the second pin-level signal into a transaction-level second target sequence, and transmit the second target sequence to the scoring board. The scoring board is used to compare whether the first target sequence and the second target sequence are the same, and determine whether the function of the module under test is accurate based on the comparison result. Thus, the verification platform has a clear structure, which is conducive to error location and can be used to verify the behavior of Ethernet PHY in the scenario of error injection mechanism. It can achieve the effect of comprehensive and overall verification of Ethernet PHY and solve the problem of not being able to comprehensively and accurately verify the functional behavior of Ethernet PHY. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a UVM-based Ethernet PHY universal verification platform provided in an embodiment of this application;

[0011] Figure 2 This is a schematic diagram illustrating the verification of the internal PCS module of the Ethernet PHY provided in an embodiment of this application;

[0012] Figure 3 This is a schematic diagram of the basic architecture of a verification platform provided in an embodiment of this application;

[0013] Figure 4This is a schematic diagram of the workflow for system-level verification of a verification platform provided in an embodiment of this application;

[0014] Figure 5 This is a schematic diagram illustrating the workflow of a PCS layer bus driver for internal module-level verification, provided in an embodiment of this application.

[0015] Figure 6 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0016] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0017] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0018] The following description, in conjunction with the accompanying drawings, details the UVM-based Ethernet PHY universal verification platform and verification method provided in this application through specific embodiments and application scenarios.

[0019] Figure 1 This invention illustrates an embodiment of a UVM-based universal Ethernet PHY verification platform. The method can be executed by an electronic device, which may include a terminal device, such as a computer terminal. In other words, the method can be executed by software or hardware installed on the terminal device. The verification platform includes: a network cable model, a scoring board, two modules to be tested, a first sequence generator, a first Ethernet proxy module, a first physical interface, a second Ethernet proxy module, and a second physical interface. The first module to be tested is located at one end of the verification platform, and the second module to be tested is located at the other end of the verification platform.

[0020] The first sequence generator is used to generate sequence requests, which include transaction-level sequences.

[0021] In one embodiment, the first Ethernet proxy module includes: a first sequence generator, configured to determine whether to accept the sequence request, and if the sequence request is accepted, forward the sequence request to a first driver; the first driver, configured to convert the transaction-level sequence into a pin-level stimulus and transmit it to the first physical interface; and a first monitor, configured to acquire the first pin-level signal output by the first physical interface, convert the first pin-level signal into a transaction-level first target sequence, and transmit the first target sequence to the scoreboard.

[0022] The first module under test is used to encode the first pin-level signal, convert the encoded data into serial data, and output it to the network cable model; the network cable model is used to transmit the serial data to the second module under test; the second module under test is used to decode the received serial data, obtain the second pin-level signal, and output it, so as to achieve the effect of clear source and destination of received and transmitted serial data.

[0023] In one embodiment, the second Ethernet proxy module includes: a second sequence generator, a second driver, and a second monitor, wherein the second sequence generator and the second driver are different from the first sequence generator and the first driver only in name, but have the same specific function; the second monitor is used to acquire the second pin-level signal output by the second module under test, convert the second pin-level signal into a transaction-level second target sequence, and transmit the second target sequence to the scoring board; the scoring board is used to compare whether the first target sequence and the second target sequence are the same, and determine whether the function of the module under test is accurate based on the comparison result, so as to achieve comprehensive and accurate verification of the Ethernet PHY functional behavior.

[0024] In one embodiment, see further. Figure 2The verification platform further includes: a first Physical Coding Sublayer (PCS) bus driver and a third physical interface, wherein the first physical interface, second physical interface, and third physical interface are only different in name and have the same function; wherein, the first Ethernet proxy module is further used to input the pin-level stimulus to the first PCS bus driver and transmit the transaction-level sequence to the scoring board; the first PCS bus driver is used to encode the pin-level stimulus, convert the encoded parallel data into serial data, and transmit it to the PCS module of the first module under test through the third physical interface; the PCS module of the first module under test is used to decode the received serial data, and convert the pin-level stimulus into serial data. The decoded Ethernet data is sent to the second Ethernet proxy module; the second Ethernet proxy module is further configured to convert the Ethernet data into a transaction-level sequence and transmit it to the scoreboard; the scoreboard is further configured to compare whether the transaction-level sequence from the first Ethernet proxy module is the same as the transaction-level sequence from the second Ethernet proxy module, and determine whether the function of the PCS module of the module under test is accurate based on the comparison result, that is, the electrical behavior of the first PCS bus driver conforming to the Ethernet protocol can effectively verify the functional accuracy of the PCS layer, thereby achieving the verification of the internal PCS module level of the Ethernet PHY and solving the problem of lack of verification of the accuracy of internal modules.

[0025] In one embodiment, a verification method is also provided, the verification method comprising: a first Ethernet proxy module of the verification platform receiving a sequence request, converting the sequence in the sequence request into a pin-level stimulus and transmitting it to a first physical interface of the verification platform; the first physical interface outputting a first pin-level signal to a first module under test of the verification platform based on the pin-level stimulus; a first sequence generator of the first Ethernet proxy module determining whether to accept the sequence request; if the sequence request is accepted, forwarding the sequence request to a first driver of the first Ethernet proxy module; the first driver converting the transaction-level sequence into a pin-level stimulus and transmitting it to the first physical interface; and a first monitor of the first Ethernet proxy module acquiring the first pin-level signal output by the first physical interface and converting the first pin-level signal into a transaction-level first target sequence. The first target sequence is transmitted to the scoring board. The first module under test encodes the first pin-level signal and converts the encoded data into serial data, which is then output to the network cable model of the verification platform. The network cable model transmits the serial data to the second module under test on the verification platform. The second module under test decodes the received serial data to obtain a second pin-level signal and outputs it. The second monitor of the second Ethernet proxy module acquires the second pin-level signal output by the second module under test and converts it into a transaction-level second target sequence. The second target sequence is transmitted to the scoring board. The scoring board compares whether the first target sequence and the second target sequence are the same. Based on the comparison result, it determines whether the function of the module under test is accurate, thereby achieving a comprehensive and accurate verification of the Ethernet PHY functional behavior.

[0026] In one embodiment, the verification method further includes: the first Ethernet proxy module inputting the pin-level stimulus to the first physical encoding sublayer PCS bus driver of the verification platform, and transmitting the transaction-level sequence to the scoring board; the first PCS bus driver encoding the pin-level stimulus, converting the encoded parallel data into serial data, and transmitting it to the PCS module of the first module under test through the third physical interface of the verification platform; the PCS module of the first module under test decoding the received serial data, and sending the decoded Ethernet data to the second Ethernet proxy module; the second Ethernet proxy module converting the Ethernet data into a transaction-level sequence and transmitting it to the scoring board; the scoring board comparing whether the transaction-level sequence from the first Ethernet proxy module is the same as the transaction-level sequence from the second Ethernet proxy module, and determining whether the function of the PCS module of the module under test is accurate based on the comparison result, that is, the electrical behavior of the first PCS bus driver conforming to the Ethernet protocol can effectively verify the functional accuracy of the PCS layer, achieving verification of the internal PCS module level of the Ethernet PHY, and solving the problem of lack of verification of the accuracy of internal modules.

[0027] The following specific examples illustrate... Figure 1 The basic architecture of the verification platform and its various components are explained in detail.

[0028] In one embodiment, Figure 3 The diagram shows a basic architecture of the verification platform, wherein the verification environment (env) of the verification platform is derived from uvm_env and is used to include other components. The components include the first sequence generator, the first Ethernet proxy module, the first physical interface, the second Ethernet proxy module, the second physical interface, the network cable model, the two modules to be tested, and the PCS layer bus driver in the above embodiments. During testing, it is only necessary to instantiate the verification environment.

[0029] The verification agent (including the first Ethernet agent module or the second Ethernet agent module mentioned above), derived from uvm_agent, is responsible for encapsulating the sequencer (including the first sequencer or the second sequencer mentioned above), driver (including the first driver or the second driver mentioned above), and monitor (including the first monitor or the second monitor mentioned above) together. For example, the sequencer forwards sequence requests to the driver, the driver converts the transaction-level sequence into pin-level stimuli and transmits them to the interface (including the first physical interface, the second physical interface, or the third physical interface mentioned above). Based on the pin-level stimuli, the interface outputs pin-level signals to the first module under test. The first module under test encodes the pin-level signals and converts the encoded data into serial data, which is then output to the network cable model. The network cable model transmits serial data to the second module under test. The monitor acquires the pin-level signals and converts them into a transaction-level target sequence (i.e., the first target sequence or the second target sequence mentioned above), and transmits the target sequence to the scoreboard.

[0030] The system comprises the following components: a sequencer (derived from uvm_sequencer) for monitoring for stimulus sequence transmission requests; a driver (derived from uvm_driver) for receiving stimulus sequence transmission requests, converting transaction-level transmissions into pin-level transmissions, and transmitting them to the design under test (i.e., the first and second modules under test mentioned above); a monitor (derived from uvm_monitor) for collecting pin information of the design under test; a transaction (derived from uvm_sequence_item) for transaction-level communication with the verification platform; a sequence (derived from uvm_sequence) for pre-generating stimulus sequences in test cases; an interface for signal communication between the verification platform and the design under test; a channel model that uses an industry-standard register-level transmission model to simulate the behavior of a network cable in a real-world environment by digitally simulating the transmission behavior of signals on the cable; and a scoreboard for comparing the transmitted frame data with the received frame data.

[0031] The PCS layer bus driver (bfm) encodes the pin-level stimuli, converts the encoded parallel data into serial data, and transmits it to the PCS module of the first module under test through the third physical interface. The PCS module of the first module under test decodes the received serial data and sends the decoded Ethernet data to the second Ethernet proxy module. The second Ethernet proxy module converts the Ethernet data into a transaction-level sequence and transmits it to the scoring board. The scoring board compares the transaction-level sequence from the first Ethernet proxy module with the transaction-level sequence from the second Ethernet proxy module to determine whether the function of the PCS module of the module under test is accurate based on the comparison result. The electrical behavior of the first PCS bus driver conforming to the Ethernet protocol can effectively verify the functional accuracy of the PCS layer.

[0032] The PCS layer bus driver (bfm) is used to create stimuli for the internal PCS modules of the design under test and to receive and parse information sent by the PCS modules. Of course, this embodiment does not impose specific limitations on the components of the verification platform and can be selected according to actual needs.

[0033] The following detailed description of the workflow of a verification method of the verification platform is provided through specific embodiments.

[0034] Figure 4This diagram illustrates the workflow of a UVM-based Ethernet PHY universal verification platform, showing the system-level verification process. For example, when a sequence request arrives, the sequence transmitter arbitrates whether to accept it. If accepted, the sequence request is sent to the driver, simulating data request and arbitration in a real-world scenario. The driver then converts the transaction-level sequence in the request into pin-level stimuli and transmits them to the interface, simulating the conversion of high-level transmission into low-level stimuli, which are then transmitted to the module under test. At this point, the monitor tracks the signals on the pins, converts the pin-level signals into transaction-level signals, and records them. The device under test (DUT) then... The DUT (Distributed Under Test) encodes the signal, converting parallel data into serial data operations, and then transmits it to the peer DUT via a network cable model. The peer DUT receives the data, and its monitor converts the pin-level signals into transaction-level signals and records them. At this point, the two monitors have two transaction-level records, each transmitted to a scoring board. The scoring board compares the two transaction-level records and determines the accuracy of the Ethernet PHY function under test based on the comparison result. Thus, the verification platform performs a comprehensive and holistic verification of the Ethernet PHY, effectively verifying its functional accuracy. Furthermore, the components of the verification platform are reusable and can be easily ported to verification platforms for other chips. Of course, this embodiment does not impose specific limitations on the components of the verification platform; they can be selected according to actual needs.

[0035] In one embodiment, the PCS layer bus driver can be used to verify the internal codec module. This PCS layer bus driver simulates the encoding and decoding behavior during Ethernet transmission. It encodes Ethernet frames internally within the model and uses this encoding as an stimulus to transmit to the decoding module inside the DUT via an interface. Alternatively, it receives Ethernet frames encoded by the DUT and performs decoding to recover the Ethernet frame data. This is used as an example to verify the internal PCS module of the module under test. Figure 5 A flowchart illustrating a process for verifying the internal encoding and decoding of a PC S-layer bus driver within the module under test is shown below. Figure 5As shown, when a sequence request is received, the sequence transmitter arbitrates whether to accept the request. If accepted, the sequence request is sent to the driver. This behavior simulates data request and arbitration in a real-world scenario. Next, the driver converts the transaction-level transmission into pin-level stimuli and transmits them to the PCS layer bus driver. Simultaneously, the monitor records the transaction. Inside the PCS layer bus driver (bfm), the pin-level stimuli are encoded. For example, for 100Mb / s, the received 100Mb / s data stream is encoded using a 4B / 5B encoding method, converting the original 100Mb / s to 125Mb / s. Then, the state machine switches to baseband encoding (Multi-Level Transmit-3, MTL-3) mode, using MTL-3 encoding and decoding to encode the 5B data stream, reducing the signal frequency. Finally, the state machine switches to parallel data to serial data conversion mode, transmitting the final encoded PCS serial signal to the DU. The PCS module within the DUT decodes the signals processed by the PCS layer bus driver, packages Ethernet data, and sends it to the monitor at the other end via an interface. At this point, the two monitors have two transaction-level records, each transmitted to a scoring board. The scoring board compares the two transaction-level records and determines whether the Ethernet PHY function under test is accurate based on the comparison result. Thus, the verification platform structure is clear, which is beneficial for error localization. At the same time, the addition of the Ethernet PCS layer bus driver enables the verification platform to accurately simulate the internal encoding and decoding of the Ethernet PHY, verify the functional accuracy of the PCS layer, and verify the behavior of the Ethernet PHY under error injection mechanism scenarios. This solves the problem of insufficient verification of the internal modules of the Ethernet PHY in existing verification platforms.

[0036] This application also provides an electronic device for executing the aforementioned UVM-based Ethernet PHY universal verification platform. Figure 6 This is a schematic diagram of the structure of an electronic device to implement the various embodiments of this application. The electronic device can vary significantly due to differences in configuration or performance, and may include a processor 601, a communications interface 602, a memory 603, and a communication bus 604. The processor 601, communications interface 602, and memory 603 communicate with each other via the communication bus 604. The processor 601 can call a computer program stored in the memory 603 and executable on the processor 601. Specific execution steps can be found in the various steps of the above-described embodiments of the method for identifying small-class service traffic, and the same technical effects can be achieved. To avoid repetition, these steps will not be repeated here.

[0037] It should be noted that the electronic devices in the embodiments of this application include: servers, terminals, or other devices besides terminals.

[0038] The above electronic device structure does not constitute a limitation on the electronic device. An electronic device may include more or fewer components than illustrated, or combine certain components, or arrange them differently. For example, an input unit may include a Graphics Processing Unit (GPU) and a microphone, and a display unit may use a liquid crystal display (LCD), organic light-emitting diode (OLED), or other similar display panels. User input units include at least one of a touch panel and other input devices. A touch panel is also called a touchscreen. Other input devices may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, and joysticks, which will not be elaborated further here.

[0039] Memory can be used to store software programs and various data. Memory can primarily include a first storage area for storing programs or instructions and a second storage area for storing data. The first storage area can store the operating system, application programs or instructions required for at least one function (such as sound playback, image playback, etc.). Furthermore, memory can include volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (Synchlink DRAM, SLDRAM), and direct memory bus RAM (DRRAM).

[0040] The processor may include one or more processing units; optionally, the processor integrates an application processor and a modem processor, wherein the application processor mainly handles operations related to the operating system, user interface, and applications, while the modem processor mainly handles wireless communication signals, such as a baseband processor. It is understood that the aforementioned modem processor may also not be integrated into the processor.

[0041] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the process of the above-described verification method embodiment and achieve the same technical effect. To avoid repetition, this will not be repeated here.

[0042] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0043] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0044] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the verification platform and verification method described in the various embodiments of this application.

[0045] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A universal verification platform for Ethernet PHY based on UVM, characterized in that, The verification platform includes: a network cable model, a scoreboard, two modules to be tested, a first sequence generator, a first Ethernet proxy module, a first physical interface, a second Ethernet proxy module, and a second physical interface. The first of the two modules to be tested is located at one end of the verification platform, and the second of the two modules to be tested is located at the other end of the verification platform. The first sequence generator is used to generate a sequence request, wherein the sequence request includes a transaction-level sequence; The first Ethernet proxy module is used to receive the sequence request, convert the transaction-level sequence into a pin-level stimulus, and transmit it to the first physical interface; The first physical interface is used to output a first pin-level signal to the first module under test based on the pin-level excitation; The first Ethernet proxy module is further configured to acquire the first pin-level signal output by the first physical interface, convert the first pin-level signal into a transaction-level first target sequence, and transmit the first target sequence to the scoreboard; The first module to be tested is used to encode the first pin-level signal and convert the encoded data into serial data for output to the network cable model. The network cable model is used to transmit the serial data to the second module under test; The second module to be tested is used to decode the received serial data to obtain and output a second pin-level signal; The second Ethernet proxy module is used to acquire the second pin-level signal output by the second module under test, convert the second pin-level signal into a transaction-level second target sequence, and transmit the second target sequence to the scoreboard; The scoreboard is used to compare whether the first target sequence and the second target sequence are the same, and to determine whether the function of the module under test is accurate based on the comparison result. It also includes: a first PCS bus driver and a third physical interface for verification at the PCS module level within the Ethernet PHY; among which, The first Ethernet proxy module is further configured to input the pin-level stimulus to the first PCS bus driver and transmit the transaction-level sequence to the scoreboard; The first PCS bus driver is used to encode the pin-level stimulus, convert the encoded parallel data into serial data, and transmit it to the PCS module of the first module under test through the third physical interface. The PCS module of the first module under test is used to decode the received serial data and send the decoded Ethernet data to the second Ethernet proxy module. The second Ethernet proxy module is further configured to convert the Ethernet data into a transaction-level sequence and transmit it to the scoreboard; The scoreboard is also used to compare whether the transaction-level sequence from the first Ethernet proxy module is the same as the transaction-level sequence from the second Ethernet proxy module, and to determine whether the PCS module of the module under test is functionally accurate based on the comparison result.

2. The verification platform according to claim 1, characterized in that, The first Ethernet proxy module includes: A first sequence generator is used to determine whether to accept the sequence request, and if it is determined that the sequence request is accepted, forwards the sequence request to a first driver; The first driver is configured to convert the transaction-level sequence into pin-level stimuli and transmit them to the first physical interface; A first monitor is configured to acquire the first pin-level signal output from the first physical interface, convert the first pin-level signal into a transaction-level first target sequence, and transmit the first target sequence to the scoreboard.

3. The verification platform according to claim 1, characterized in that, The second Ethernet proxy module includes: The second monitor is used to acquire the second pin-level signal output by the second module under test, convert the second pin-level signal into a transaction-level second target sequence, and transmit the second target sequence to the scoreboard.

4. A verification method, characterized in that, The verification method is applied to the verification platform according to any one of claims 1 to 3, and the verification method includes: The first Ethernet proxy module of the verification platform receives a sequence request, converts the sequence in the sequence request into a pin-level stimulus, and transmits it to the first physical interface of the verification platform. The first physical interface is based on pin-level excitation and outputs a first pin-level signal to the first module under test of the verification platform; The first Ethernet proxy module acquires the first pin-level signal output by the first physical interface, converts the first pin-level signal into a transaction-level first target sequence, and transmits the first target sequence to the scoreboard of the verification platform. The first module under test encodes the first pin-level signal, converts the encoded data into serial data, and outputs it to the network cable model of the verification platform. The network cable model transmits the serial data to the second module to be tested on the verification platform; The second module under test decodes the received serial data to obtain and output the second pin-level signal; The second Ethernet proxy module of the verification platform acquires the second pin-level signal output by the second module under test, converts the second pin-level signal into a transaction-level second target sequence, and transmits the second target sequence to the scoreboard; The scoreboard compares whether the first target sequence and the second target sequence are the same, and determines whether the function of the module under test is accurate based on the comparison result.

5. The method according to claim 4, characterized in that, The first Ethernet proxy module acquires the first pin-level signal output from the first physical interface, converts the first pin-level signal into a transaction-level first target sequence, and transmits the first target sequence to the scoring board of the verification platform, including: The first sequence generator of the first Ethernet proxy module determines whether to accept the sequence request. If it determines that the sequence request is accepted, it forwards the sequence request to the first driver of the first Ethernet proxy module. The first driver converts the transaction-level sequence into pin-level stimuli and transmits them to the first physical interface; The first monitor of the first Ethernet proxy module acquires the first pin-level signal output by the first physical interface, converts the first pin-level signal into a transaction-level first target sequence, and transmits the first target sequence to the scoreboard.

6. The method according to claim 4, characterized in that, The second Ethernet proxy module of the verification platform acquires the second pin-level signal output by the second module under test, converts the second pin-level signal into a transaction-level second target sequence, and transmits the second target sequence to the scoring board, including: The second monitor of the second Ethernet proxy module acquires the second pin-level signal output by the second module under test, converts the second pin-level signal into a transaction-level second target sequence, and transmits the second target sequence to the scoreboard.

7. The method according to claim 4, characterized in that, Also includes: The first Ethernet proxy module inputs the pin-level stimulus to the first PCS bus driver of the verification platform and transmits the transaction-level sequence to the scoreboard; The first PCS bus driver encodes the pin-level stimulus, converts the encoded parallel data into serial data, and transmits it to the PCS module of the first module under test through the third physical interface of the verification platform. The PCS module of the first module under test decodes the received serial data and sends the decoded Ethernet data to the second Ethernet proxy module. The second Ethernet proxy module converts the Ethernet data into a transaction-level sequence and transmits it to the scoreboard; The scoreboard compares the transaction-level sequence from the first Ethernet proxy module with the transaction-level sequence from the second Ethernet proxy module to determine whether the PCS module of the module under test is functionally accurate based on the comparison result.

8. An electronic device, characterized in that, Includes the verification platform described in any one of claims 1 to 3.

9. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the verification method as described in any one of claims 4 to 7.

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