Data processing method and device, electronic equipment and computer readable storage medium
By determining the input current probability distribution of postneuron clusters in a large-scale brain simulation system, the problem of high time cost of synaptic weight reading and matrix multiplication operations is solved, thus improving system efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- LYNXI TECH CO LTD
- Filing Date
- 2022-12-31
- Publication Date
- 2026-07-31
AI Technical Summary
In large-scale brain simulation systems, the time cost of reading and calculating synaptic weights and connection information severely impacts efficiency.
By determining the probability distribution of the input current of the postneuron cluster based on the weight distribution of the synaptic array and the pulse array of the preneuron cluster, an input current array is generated, avoiding the need to read synaptic weights and perform matrix multiplication operations.
This reduces the time cost of computation and improves the efficiency of large-scale brain simulation.
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Figure CN116306843B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of computer technology, and in particular to a data processing method and apparatus, electronic device, and computer-readable storage medium. Background Technology
[0002] High-performance neuromorphic computing and brain simulation technologies are crucial tools for studying brain science. The development of computational neuroscience has significantly impacted fields such as intelligent science, cognitive science, information processing, and artificial intelligence. To more accurately simulate the basic functions of the human brain performed by the coordinated activity of millions of neurons, large-scale brain simulation systems are needed.
[0003] Large-scale brain simulation systems typically employ sparse synaptic integral operations. However, the time cost of reading and computing synaptic weights and connectivity information can severely impact the efficiency of such systems. Summary of the Invention
[0004] This disclosure provides a data processing method and apparatus, a processing core, an electronic device, and a computer-readable storage medium based on a many-core system.
[0005] In a first aspect, this disclosure provides a data processing method, comprising: determining a first probability distribution of input current corresponding to at least one postneuron cluster based on the weight distribution of at least one synaptic array and the pulse array of the preneuron clusters corresponding to each of the synaptic arrays, wherein the postneuron clusters are interconnected with the preneuron clusters corresponding to each of the synaptic arrays through the at least one synaptic array; and generating an input current array of the postneuron clusters based on the first probability distribution.
[0006] In a second aspect, this disclosure provides a data processing apparatus, characterized in that it includes: a statistics module, configured to determine a first probability distribution of input current corresponding to at least one postneuron cluster based on the weight distribution of at least one synaptic array and the pulse array of the preneuron clusters corresponding to each of the synaptic arrays, wherein the postneuron clusters are interconnected with the preneuron clusters corresponding to each of the synaptic arrays through the at least one synaptic array; and a processing module, configured to generate an input current array of the postneuron clusters based on the first probability distribution.
[0007] Thirdly, this disclosure provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores one or more computer programs executable by the at least one processor, the one or more computer programs being executed by the at least one processor to enable the at least one processor to perform the data processing method described above.
[0008] Fourthly, this disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor / processor core, implements the above-described data processing method.
[0009] In the embodiments of this disclosure, the first probability distribution of the input current corresponding to the post-neuron cluster can be determined based on the weight distribution of the synaptic array and the pulse array of the pre-neuron cluster. Then, an input current array composed of the input current values of each post-neuron in the post-neuron cluster is generated based on the first probability distribution. In the whole process, it is not necessary to read the synaptic weights of each synapse in the synaptic array, nor is it necessary to perform matrix multiplication of the pulse array and the weight matrix of the synaptic array. This helps to reduce the time cost of the entire calculation process and improve the efficiency of large-scale brain simulation.
[0010] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description
[0011] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:
[0012] Figure 1 A flowchart of a data processing method provided in an embodiment of this disclosure;
[0013] Figure 2 This is a schematic diagram of a neuron connection relationship in an embodiment of this disclosure;
[0014] Figure 3 This is a schematic diagram of another neuron connection relationship in an embodiment of this disclosure;
[0015] Figure 4 This is a schematic diagram of a synaptic array according to an embodiment of the present disclosure;
[0016] Figure 5 This is a schematic diagram of a multi-neuron cluster interconnection in an embodiment of this disclosure;
[0017] Figure 6 This is a schematic diagram of another multi-neuron cluster interconnection in an embodiment of this disclosure;
[0018] Figure 7 This is a schematic diagram of yet another type of multi-neuron cluster interconnection in an embodiment of this disclosure;
[0019] Figure 8A block diagram of a data processing apparatus provided in an embodiment of this disclosure;
[0020] Figure 9 This is a block diagram of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation
[0021] To enable those skilled in the art to better understand the technical solutions of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of this disclosure to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.
[0022] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.
[0023] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.
[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, they specify the presence of features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Words such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.
[0025] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.
[0026] The data processing method according to embodiments of this disclosure can be executed by electronic devices such as terminal devices or servers. The terminal device can be an in-vehicle device, user equipment (UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, in-vehicle device, wearable device, etc. This method can be implemented by a processor calling computer-readable program instructions stored in memory. Alternatively, the method can be executed by a server. The data processing method provided according to embodiments of this disclosure can also be implemented by a many-core system / many-core chip.
[0027] Firstly, referring to Figure 1 This disclosure provides a data processing method, including:
[0028] S1. Based on the weight distribution of at least one synaptic array and the pulse array of the preneuron clusters corresponding to each synaptic array, determine the first probability distribution of the input current corresponding to at least one postneuron cluster, wherein the postneuron clusters are interconnected with the preneuron clusters corresponding to each synaptic array through at least one synaptic array.
[0029] S2. Generate the input current array of the post-neuron cluster according to the first probability distribution.
[0030] Figure 2 This is a schematic diagram of neuronal connections. Figure 2 The illustrated connectivity includes a group (or multiple) of neurons, a group of axons, a group of dendrites, and a synaptic array, which can simulate the behavior of a biological cluster of neurons. Dendrites can be structures that receive external stimuli and generate input current; axons can be structures that transmit impulses to subsequent neurons; synapses can be structures that connect neurons; and a synaptic array can be an array of multiple synapses connecting a group of axons and a group of dendrites. The synaptic array can be used to simulate the connectivity between one group of neurons and another group of neurons. Synapses in the synaptic array have corresponding synaptic weights; the synaptic weights of each synapse in the synaptic array can be represented by a weight matrix.
[0031] In this embodiment of the disclosure, each synapse may correspond to a preneuron and a postneuron, wherein the preneuron and postneuron can be relative concepts and can be used to describe the connection and firing relationship of the neurons corresponding to the synapse. For example, Figure 3 This is a schematic diagram illustrating the connection relationships of some neurons in an embodiment of this disclosure. For example... Figure 3As shown, multiple neurons A and multiple neurons C are fully connected, with the neurons A connected to the neurons C via a synaptic array. For any synapse in the synaptic array, the neuron A corresponding to that synapse is the predecessor neuron, and the neuron C corresponding to that synapse is the successor neuron.
[0032] In this embodiment of the disclosure, multiple anterior neurons constitute an anterior neuron cluster, and multiple posterior neurons constitute a posterior neuron cluster; an anterior neuron cluster is interconnected with a posterior neuron cluster through a synaptic array.
[0033] In this embodiment of the disclosure, the synaptic weight can indicate whether there is a connection between the preneuron and postneuron corresponding to the synapse. For example, a synaptic weight of zero indicates that there is no connection between the preneuron and postneuron corresponding to the synapse; a synaptic weight of non-zero indicates that there is a connection between the preneuron and postneuron corresponding to the synapse.
[0034] In this embodiment of the disclosure, the pulse array consists of firing data of each preneuron in the preneuron cluster. The firing data of a preneuron indicates whether the preneuron has fired in a time slice. For example, a firing data of 1 indicates that the preneuron has fired; a firing data of 0 indicates that the preneuron has not fired; the pulse array can be represented by a vector composed of 0s and 1s.
[0035] In embodiments of this disclosure, the input current array may be composed of the input current values of each postneuron in the postneuron cluster. In some embodiments, the input current array may be represented by a vector composed of the input current values of each postneuron.
[0036] In this embodiment, the weight distribution of the synaptic array can characterize the random distribution characteristics of the synaptic weights corresponding to each synapse in the synaptic array, that is, the values of non-zero synaptic weights are random numbers that satisfy a certain random distribution. This embodiment does not impose any special limitations on the weight distribution. In some embodiments, the weight distribution can be a Gaussian distribution, that is, the non-zero synaptic weights in the synaptic array can be N(μ, σ). 2 Gaussian distributed random numbers.
[0037] In this embodiment, the input current array of the postneurons is I, the pulse array of the preneuron cluster is S, and the weight matrix is W. In traditional large-scale brain simulations, I, S, and W satisfy: I = S × W. Given the random distribution of synaptic weights in the synaptic array, the input current values of the postneurons also exhibit random distribution characteristics. In this embodiment, step S1 determines the first probability distribution of the input current of each postneuron in the postneuron cluster based on the weight distribution of the synaptic array and the pulse array of the preneuron cluster. The first probability distribution characterizes the random distribution of the input current values of the postneurons. Then, in step S2, for each postneuron, an input current value satisfying the first probability distribution is directly generated based on its first probability distribution. In some embodiments, the pulse array can be a pulse array within a time frame, indicating whether the preneuron fires within that time frame; the generated input current array is the input current array within that time frame.
[0038] As an example, Figure 4 This is a schematic diagram of a synaptic array corresponding to one time beat. In Figure 4 In the diagram, the pulse array S = [S0, S1, S2, S3, S4], the input current array I = [I0, I1, I2, I3, I4], and circles or dots represent synapses with non-zero synaptic weights. Given the current time-beat pulse array S = [0, 1, 0, 1, 0], when calculating the input current value I0, the corresponding non-zero synaptic weight is W. 1,0 and W 3,0 Among them, W 1,0 and W 3,0 All satisfy a Gaussian distribution N(μ, σ) 2 Then the first probability distribution satisfied by I0 is N(2μ, 2σ). 2 ); thereby generating N(2μ, 2σ) 2 The current estimate of the distribution is used as the input current value I0. Similarly, the current estimates corresponding to I1, I2, I3, and I4 can be generated to obtain the input current array for the current time step.
[0039] The data processing method provided in this embodiment can determine the first probability distribution of the input current corresponding to the postneuron cluster based on the weight distribution of the synaptic array and the pulse array of the preneuron cluster. Then, an input current array composed of the input current values of each postneuron in the postneuron cluster is generated based on the first probability distribution. In the entire process, it is not necessary to read the synaptic weights of each synapse in the synaptic array, nor is it necessary to perform matrix multiplication of the pulse array and the weight matrix of the synaptic array. This helps to reduce the time cost of the entire calculation process and improve the efficiency of large-scale brain simulation.
[0040] This disclosure does not impose any special limitations on how to determine the first probability distribution corresponding to the postneuron cluster based on the weight distribution of the synaptic array and the pulse array of the preneuron cluster.
[0041] In some embodiments, determining a first probability distribution of the input current corresponding to at least one post-neuron cluster based on the weight distribution of at least one synaptic array and the pulse array of the pre-neuron clusters corresponding to each synaptic array includes:
[0042] Based on the connection information of each synaptic array and the pulse array of the preneuron cluster corresponding to each synaptic array, the number of effective pulse events corresponding to each postneuron in the postneuron cluster is determined, wherein the postneuron cluster includes multiple postneurons;
[0043] Based on the weight distribution and the number of effective impulse events corresponding to each post-neuron, the first probability distribution of the input current corresponding to each post-neuron is determined.
[0044] In this embodiment, the connection information of the synaptic array can characterize the connection relationship between the preneurons and postneurons corresponding to the synapses in the synaptic array. For example, a synaptic weight of zero indicates that the preneurons and postneurons corresponding to the synapses are not connected; a non-zero synaptic weight indicates that the preneurons and postneurons corresponding to the synapses are connected. The pulse array can characterize the firing status of each preneuron in a time frame. For example, a firing data of 1 in the pulse array indicates that the preneuron has fired; a firing data of 0 indicates that the preneuron has not fired.
[0045] In this embodiment, for a postneuron, a valid impulse event can refer to the firing of a preneuron, and the preneuron being connected to the postneuron. For example... Figure 4 As shown, circles or dots can represent synapses with non-zero synaptic weights. Circles can represent the corresponding preneuron that has not fired, and dots can represent the corresponding preneuron that has fired. Therefore, the number of effective impulse events corresponding to I0 is 2, the number of effective impulse events corresponding to I1 is 1, the number of effective impulse events corresponding to I2 is 0, the number of effective impulse events corresponding to I3 is 2, and the number of effective impulse events corresponding to I4 is 0.
[0046] In this embodiment of the disclosure, only valid impulse events affect the input current of the post-neuron. Since the synaptic weights of each synapse in the synaptic array follow the same random distribution, the first probability distribution of the input current corresponding to the post-neuron can be determined after determining the number of valid impulse events. For example, as... Figure 4 As shown, the non-zero synaptic weights in the synaptic array satisfy a Gaussian distribution N(μ, σ). 2 If the number of valid impulse events corresponding to I0 is 2, then the first probability distribution satisfied by I0 is N(2^3)^3.μ ,2σ 2 ).
[0047] In this embodiment of the disclosure, the number of effective pulse events corresponding to the post-neuron is determined based on the connection information and the pulse array. Then, the probability distribution of the input current is determined based on the weight distribution and the number of effective pulse events. This can improve the accuracy of the generated input current value and further enhance the computational efficiency.
[0048] This disclosure does not impose any special limitations on how to determine the number of effective pulse events corresponding to the postneuron based on the connection information of the synaptic array and the pulse array.
[0049] In some embodiments, the number of valid pulse events corresponding to each post-neuron is counted based on the pulse sequence and connection information. Determining the number of valid pulse events through direct statistics improves accuracy and is beneficial for improving the accuracy of the generated input current value.
[0050] In some embodiments, the connection density of a synapse can refer to the proportion of connected synapses (with non-zero synaptic weights) out of all synapses, i.e., the connection probability. The connection density of synapses in a synaptic array is fixed, but the positions of connected synapses can be random, meaning that the positions of connected synapses may differ for different post-neurons. For a pulse sequence, the number of pulse events (the number of 1s in the pulse sequence) and the position of the pulse events (the positions of 1s in the pulse sequence) are determined. Given the random distribution of connected synapse positions, the effective pulse events corresponding to subsequent neurons also have a random distribution. Therefore, the probability distribution of effective pulse events can be determined based on the random distribution of effective pulse events, thereby generating the number of effective pulse events that satisfy the second probability distribution. Determining the number of effective pulse events based on their random distribution is beneficial for improving computational efficiency.
[0051] Accordingly, in some embodiments, the connection information may include the connection probabilities of synaptic arrays; determining the number of effective pulse events corresponding to each postneuron in the postneuron cluster based on the connection information of each synaptic array and the pulse array corresponding to each synaptic array includes:
[0052] For any synaptic array, the second probability distribution of effective pulse events corresponding to each postneuron is determined based on the connection probability of the synaptic array and the number of pulse events in the pulse array corresponding to the synaptic array.
[0053] The number of valid impulse events corresponding to each postneuron is determined based on the second probability.
[0054] In this embodiment of the disclosure, the number of valid pulse events can be a random number that satisfies a second probability distribution.
[0055] In this embodiment of the disclosure, the number of effective pulse events corresponding to the post-neuron is generated according to the connection probability, thereby realizing the random distribution characteristics of synaptic weights and synaptic connections based on the synaptic array, directly generating the input current of the post-neuron, and further improving the computational efficiency.
[0056] The embodiments disclosed herein do not impose any special limitations on the second distribution probability.
[0057] In some embodiments, the second probability distribution can be represented by formula (1):
[0058] Sr(j)=Binomial(St,p) (1)
[0059] Formula (1) can be simplified to Formula (2):
[0060] Sr(j)=B(St,p) (2)
[0061] Where Sr(j) can represent the number of effective pulse events corresponding to the j-th postneuron in the postneuron cluster, Binomial represents the binomial distribution, St can represent the number of pulse events in the pulse array corresponding to the synaptic array, and p can represent the connection probability of the synaptic array.
[0062] The binomial distribution can be interpreted as a discrete probability distribution of the number of successes in t independent yes / no trials. In this embodiment, t independent trials refer to the preneuron firing t pulses, with each pulse having a probability p of acting on the postneuron. For a pulse sequence, according to the binomial distribution, with St pulse events, the number of pulse events that actually act on the j-th postneuron is Sr(j), which is a random number satisfying the binomial distribution; Sr may be different for different postneurons.
[0063] In this embodiment of the disclosure, determining the second distribution probability based on the binomial distribution can improve the accuracy of the calculation.
[0064] The data processing method provided in this disclosure can be applied to the interconnection of one neuron cluster with another, or to the interconnection of multiple neuron clusters. This disclosure does not impose any special limitations on this approach.
[0065] The interconnection of multiple neuron clusters includes one group of neuron clusters interconnecting with another group of neuron clusters in sync; or multiple neuron clusters interconnecting, i.e., multiple neuron clusters acting as pre-neurons and post-neurons to each other. This disclosure does not impose any specific limitations on this aspect.
[0066] When multiple neuron clusters are interconnected, a neuron cluster that is a post-neuron cluster corresponds to multiple neuron clusters that are pre-neuron clusters.
[0067] Accordingly, in some embodiments, a postneuron cluster is interconnected with multiple preneuron clusters via multiple synaptic arrays; a first probability distribution of the input current corresponding to at least one postneuron cluster is determined based on the weight distribution of at least one synaptic array and the pulse array of the preneuron clusters corresponding to each synaptic array, including:
[0068] Based on the weight distribution of each synaptic array and the pulse array of the preneuron corresponding to each synaptic array, the third probability distribution of the input current components of the postneuron corresponding to each synaptic array is determined respectively.
[0069] The first probability distribution is determined based on the third probability distribution of the input current components of each synaptic array corresponding to the postneuron.
[0070] In this embodiment of the disclosure, when multiple neuron clusters are interconnected, the pulse sequence corresponding to a post neuron cluster needs to be statistically analyzed by cluster; the third probability distribution of the input current components of different pre neuron clusters corresponding to a post neuron cluster also needs to be statistically analyzed separately, and the first probability distribution corresponding to the post neuron cluster is determined based on this.
[0071] Multiple clusters of neurons interconnected, such as Figure 5 As shown. In Figure 5 In the diagram, neuron clusters 23E, 23I, 4E, 4I, 5E, 5I, 6E, and 6I are interconnected, with each neuron cluster represented by a rectangle. Taking neuron cluster 23E as an example, it receives pulse sequences from neuron clusters 23E, 23I, 4E, 4I, 5E, 5I, 6E, and 6I, which are the preceding neuron clusters. The third probability distributions of the input current components corresponding to neuron clusters 23E, 23I, 4E, 4I, 5E, 5I, 6E, and 6I are statistically analyzed.
[0072] In embodiments of this disclosure, the weight distribution and connection probability of multiple interconnected neuron clusters may be the same or different. In some embodiments, the weight distribution of multiple interconnected neuron clusters is different. In some embodiments, the connection probability of multiple interconnected neuron clusters is different. In some embodiments, both the weight distribution and connection probability of multiple interconnected neuron clusters are different. This disclosure does not impose any particular limitations on these embodiments.
[0073] In this embodiment of the disclosure, when multiple neuron clusters are interconnected, the pulse sequence is statistically analyzed by cluster, and the third probability distribution of the input electrical component is statistically analyzed by cluster. This makes it applicable to various scenarios where the weight distribution and connection probability of multiple neuron clusters are the same or different, which is beneficial to improving computational efficiency.
[0074] In some embodiments, multiple neuron clusters are interconnected, and the weight distribution of the multiple neuron clusters satisfies a Gaussian distribution, the second probability distribution satisfies a binomial distribution, and the first probability distribution can be represented by formula (3) or formula (4):
[0075] I(j)=N(∑ i B(St(i), p(i, j))·μ, ∑ i β·B(St(i), p(i, j))·σ 2 (3)
[0076]
[0077] Where I(j) can represent the input current corresponding to the postneuron, B(St(i), p(i,j)) can represent the second probability distribution of the effective pulse events corresponding to the i-th synaptic array of the postneuron, St(i) can represent the number of pulse events in the pulse array corresponding to the i-th synaptic array, p(i,j) can represent the connection probability of the i-th synaptic array, and β can be a correction constant.
[0078] The present disclosure does not impose any special limitation on the value of β. In some embodiments, β∈[0, 1]. In some embodiments, β∈[0.2, 0.5]. For example, β=0.36.
[0079] In some embodiments, synapses in a cluster of neurons have a delay, and the delay may vary between different synapses. For example, after receiving a firing pulse from a preneuron, a synapse may immediately output a pulse that acts on the postneuron; it may output a pulse after a one-time-beat delay; or it may output a pulse after multiple time-beat delays.
[0080] Fire pulses with varying delays affect the input current of post-neurons at different time beats. For example, a fire pulse delayed by one time beat will affect the input current one time beat later; a fire pulse delayed by two time beats will affect the input current two time beats later. Alternatively, the input current of a post-neuron at a given time beat can be affected by fire pulses delayed by different numbers of time beats. For instance, the input current at the current time beat might be affected by a pulse fired by a pre-neuron one time beat earlier, or it might be affected by a pulse fired by a pre-neuron two time beats earlier.
[0081] In this embodiment of the disclosure, when multiple neuron clusters are interconnected, it is necessary to perform clustering statistics based on the synaptic delays in the multiple neuron clusters.
[0082] Accordingly, in some embodiments, a postneuron cluster is interconnected with multiple preneuron clusters via multiple synaptic arrays; a first probability distribution of the input current corresponding to at least one postneuron cluster is determined based on the weight distribution of at least one synaptic array and the pulse array of the preneuron clusters corresponding to each synaptic array, including:
[0083] Based on the weight distribution of each synaptic array, the pulse array of the preneuron corresponding to each synaptic array, and the delay of each synapse in each synaptic array, the fourth probability distribution of the input current components of the postneuron corresponding to each synaptic array is determined:
[0084] The first probability distribution is determined based on the fourth probability distribution of the input current components of each synaptic array corresponding to the postneuron.
[0085] Multiple clusters of neurons with delay interconnected as follows Figure 6 As shown, a rectangle can represent a cluster of neurons, and the vertical axis can represent different delays. The pulse sequences corresponding to different delays are different; the pulse sequence is obtained by applying the same delay to the firing pulses of the preceding neurons.
[0086] In this embodiment of the disclosure, when multiple neuron clusters are interconnected, the pulse sequence is statistically analyzed in clusters based on the synaptic delays in the multiple neuron clusters, and the fourth probability distribution of the input electrical component is statistically analyzed in clusters. This makes it applicable to scenarios where the synaptic delays in multiple neuron clusters are different, which is beneficial to improving computational efficiency.
[0087] In some embodiments, multiple neuron clusters are interconnected, and the weight distribution of the multiple neuron clusters satisfies a Gaussian distribution and the second probability distribution satisfies a binomial distribution, wherein the first probability distribution is represented by formula (5) or formula (6):
[0088] I(j)=N(∑ i ∑ d B(St(i,d),p′(i,j,d))·μ,∑ i ∑ d β·B(St(i,d),p′(i,j,d))·σ 2 (5)
[0089]
[0090] Where I(j) can represent the input current corresponding to the postneuron, B(St(i,d), p′(i,j,d)) can represent the second probability distribution of the effective pulse events corresponding to the i-th synaptic array and the j-th delay of the postneuron, St(i,d) can represent the number of pulse events in the pulse array corresponding to the i-th synaptic array and the j-th delay, p′(i,j,d) can represent the connection probability of the i-th synaptic array and the j-th delay, and β is a correction constant.
[0091] In some embodiments, a cluster of neurons may specifically contain multiple channels. These multiple channels may include excitatory current channels, inhibitory current channels, etc. For example, multiple channels may include AMPA channels, NMDA channels, GAPAA channels, and GAPAAb channels. This disclosure does not impose any specific limitations on these channels.
[0092] In this embodiment of the disclosure, when multiple neuron clusters are interconnected, multiple channels need to be calculated separately, and each channel can only calculate the pulse events related to that channel.
[0093] Accordingly, in some embodiments, the post-neuron cluster corresponds to multiple channels, and each channel corresponds to at least one synaptic array; based on the weight distribution of the at least one synaptic array and the pulse array of the pre-neuron cluster corresponding to each synaptic array, a first probability distribution of the input current corresponding to the at least one post-neuron cluster is determined, including:
[0094] Based on the weight distribution of the synaptic arrays corresponding to each channel and the pulse sequence of the preneuron corresponding to each synaptic array, the first probability distribution of the input electrical components of each channel corresponding to the postneuron is determined.
[0095] In this embodiment of the disclosure, when multiple neuron clusters are interconnected, pulse sequences are statistically analyzed in clusters according to different channels in the multiple neuron clusters, and the fourth probability distribution of the input electrical component is statistically analyzed in clusters. This can be applied to scenarios where multiple neuron clusters have multiple channels, which is beneficial to improving computational efficiency.
[0096] In some embodiments, based on the weight distribution of the synaptic array corresponding to each channel and the pulse sequence of the preneuron corresponding to each synaptic array, a first probability distribution of the input electrical components of each channel of the postneuron is determined, including:
[0097] The transmission statistics for each preneuron cluster are calculated separately;
[0098] The number of pulse statistics corresponding to different delays is determined based on the transmitted statistics;
[0099] The initial current distribution of each channel corresponding to the neuron cluster is determined;
[0100] Based on the pulse statistics and the initial current distribution of each channel corresponding to the post-neuron cluster, the first probability distribution of the input electrical components of each channel corresponding to the post-neuron is determined.
[0101] Multiple clusters of neurons with multiple channels interconnected, such as Figure 7 As shown, a rectangle represents a cluster of neurons, and different weight matrices are used to represent different channels.
[0102] In some embodiments, the number of pulse statistics can be determined using a delay chain, including: putting the transmission statistics into the delay chain to determine the number of pulse statistics corresponding to different delays.
[0103] In some embodiments, multiple neuron clusters are interconnected, and the weight distribution of the multiple neuron clusters satisfies a Gaussian distribution and the second probability distribution satisfies a binomial distribution. The first probability distribution of the input electrical component of each channel corresponding to the subsequent neuron can be expressed by formula (7) or formula (8):
[0104] I(j, c) = N(∑ i,i∈c ∑ d B(St(i,d),p′(i,j,d))·μ,∑ i,i∈c ∑ d β·B(St(i,d),p′(i,j,d))·σ 2 ) (7)
[0106]
[0107] Where I(j,c) can represent the input current of channel c corresponding to the post-neuron, B(St(i,d), p′(i,j,d)) can represent the second probability distribution of the effective pulse events of the post-neuron corresponding to the i-th synaptic array and the j-th delay, St(i,d) can represent the number of pulse events in the pulse array corresponding to the i-th synaptic array and the j-th delay, p′(i,j,d) can represent the connection probability of the i-th synaptic array and the j-th delay, and β can be a correction constant.
[0108] In some embodiments, the input current array generated after the neuron cluster includes:
[0109] The firing pulses are clustered and statistically analyzed. K(i) can represent the number of neurons in the i-th neuron cluster, and S(i, k) can represent the firing value (0 or 1) of the k-th neuron in the i-th neuron cluster.
[0110]
[0111] The output statistics are placed into the delay chain, and the number of pulses for each delay is calculated:
[0112] Sr(i, d)=Sr(i, d-1), d∈[1, Dmax];
[0113] For each channel c of each neuron, a Gaussian distributed current I0(j, k, c) is generated, representing the initial current value of the kth neuron in the jth neuron cluster, which follows N(0, 1); alternatively, a batch of data satisfying the N(0, 1) Gaussian distribution can be generated in advance, and a portion of this batch of data can be extracted for use each time.
[0114] Traverse j∈[0, NJ-1], k∈[0, K(j)-1], c∈[0, C-1], and calculate the input current of the j-th neuron cluster, the k-th neuron, and the c-th channel according to formula (7) or formula (8):
[0115] for j=0 to NJ-1
[0116] for k=0 to K(j)-1
[0117] for c=0 to C-1
[0118] t=∑ i,i∈c ∑ d p′(i,j,d))·B(Sr(i,d),p(i,j,c))
[0119]
[0120] Wherein, NJ can represent the total number of neuron clusters, K(j) can represent the total number of neurons in the j-th neuron cluster, and C can represent the total number of channels. It is understood that the various method embodiments mentioned above in this disclosure can be combined with each other to form combined embodiments without violating the underlying logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.
[0121] In addition, this disclosure also provides a data processing apparatus, an electronic device, and a computer-readable storage medium, all of which can be used to implement any of the data processing methods provided in this disclosure. The corresponding technical solutions and descriptions are described in the corresponding section of the method and will not be repeated here.
[0122] Secondly, referring to Figure 8 This disclosure provides a data processing apparatus, characterized in that it includes:
[0123] The statistics module 101 is used to determine the first probability distribution of the input current corresponding to at least one post-neuron cluster based on the weight distribution of at least one synaptic array and the pulse array of the pre-neuron clusters corresponding to each synaptic array, wherein the post-neuron clusters are interconnected with the pre-neuron clusters corresponding to each synaptic array through at least one synaptic array.
[0124] Processing module 102 is used to generate an input current array for the post-neuron clusters according to a first probability distribution.
[0125] Thirdly, referring to Figure 9 This disclosure provides an electronic device, which includes: at least one processor 201; at least one memory 202; and one or more I / O interfaces 203 connected between the processor 201 and the memory 202; wherein the memory 202 stores one or more computer programs that can be executed by the at least one processor 201, and the one or more computer programs are executed by the at least one processor 201 to enable the at least one processor 201 to perform the above-described data processing method.
[0126] This disclosure also provides a computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor / processor core, implements the data processing method described above. The computer-readable storage medium may be volatile or non-volatile.
[0127] This disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in the processor of an electronic device, the processor in the electronic device executes the above-described data processing method.
[0128] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer storage media (or non-transitory media) and communication media (or transient media).
[0129] As is known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable program instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technologies, portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable program instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.
[0130] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.
[0131] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, etc., and conventional procedural programming languages such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.
[0132] The computer program product described herein can be implemented specifically through hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.
[0133] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.
[0134] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.
[0135] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.
[0136] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.
[0137] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.
Claims
1. A data processing method applied to a brain simulation system, the brain simulation system comprising anterior neuron clusters, posterior neuron clusters, and a synaptic array, wherein the posterior neuron clusters comprise multiple posterior neurons, the anterior neuron clusters comprise multiple anterior neurons, and the synaptic array is used to simulate the connection relationship between one group of neurons and another group of neurons, the method comprising: Based on the connection information of each synaptic array and the pulse array of the preneuron cluster corresponding to each synaptic array, the number of effective pulse events corresponding to each postneuron in the postneuron cluster is determined, wherein the postneuron cluster includes multiple postneurons; Based on the weight distribution of at least one synaptic array and the number of effective pulse events corresponding to each post-neuron, a first probability distribution of the input current corresponding to each post-neuron is determined, wherein the post-neuron clusters are interconnected with the pre-neuron clusters corresponding to each synaptic array through the at least one synaptic array; The input current array of the post-neuron cluster is generated according to the first probability distribution.
2. The data processing method according to claim 1, wherein, The connection information includes the connection probability of the synaptic array; based on the connection information of each synaptic array and the corresponding pulse array, the number of effective pulse events corresponding to each postneuron in the postneuron cluster is determined, including: For any given synaptic array, a second probability distribution of effective pulse events corresponding to each postneuron is determined based on the connection probability of the synaptic array and the number of pulse events in the pulse array corresponding to the synaptic array. The number of valid pulse events corresponding to each of the post-neurons is determined based on the second probability.
3. The data processing method according to claim 2, wherein, The second probability distribution is expressed by the following formula: in, Indicating the first neuron in the post-neuron cluster The number of effective impulse events corresponding to each postneuron. Represents a binomial distribution. This indicates the number of pulse events in the pulse array corresponding to the synaptic array. This represents the connection probability of the synaptic array.
4. The data processing method according to any one of claims 1 to 3, wherein, A postneuron cluster is interconnected with multiple preneuron clusters via multiple synaptic arrays; a first probability distribution of the input current corresponding to at least one postneuron cluster is determined based on the weight distribution of at least one synaptic array and the pulse array of the preneuron cluster corresponding to each synaptic array, including: Based on the weight distribution of each synaptic array and the pulse array of the preneuron corresponding to each synaptic array, the third probability distribution of the input current component of the postneuron corresponding to each synaptic array is determined respectively. The first probability distribution is determined based on the third probability distribution of the input current components of each synaptic array corresponding to the postneuron.
5. The data processing method according to claim 4, wherein, The first probability distribution is expressed by the following formula: in, This represents the input current corresponding to the post-neuron. This indicates that the postneuron corresponds to the first The second probability distribution of effective pulse events of a synaptic array. Indicates the first The number of pulse events in the pulse array corresponding to each synaptic array. Indicates the first The connection probability of each synaptic array This is a correction constant.
6. The data processing method according to any one of claims 1 to 3, wherein, A postneuron cluster is interconnected with multiple preneuron clusters via multiple synaptic arrays; a first probability distribution of the input current corresponding to at least one postneuron cluster is determined based on the weight distribution of at least one synaptic array and the pulse array of the preneuron cluster corresponding to each synaptic array, including: Based on the weight distribution of each synaptic array, the pulse array of the preneuron corresponding to each synaptic array, and the delay of each synapse in each synaptic array, the fourth probability distribution of the input current component of the postneuron corresponding to each synaptic array is determined respectively. The first probability distribution is determined based on the fourth probability distribution of the input current components of each synaptic array corresponding to the postneuron.
7. The data processing method according to claim 6, wherein, The first probability distribution is expressed by the following formula: Among them, among them, This represents the input current corresponding to the post-neuron. This indicates that the postneuron corresponds to the first The first synaptic array, the first The second probability distribution of a delayed effective pulse event Indicates the first The first synaptic array, the first The number of pulse events in the pulse array corresponding to each delay Indicates the first The first synaptic array, the first The connection probability with delay. This is a correction constant.
8. The data processing method according to any one of claims 1 to 3, wherein, The post-neuron cluster corresponds to multiple channels, and each channel corresponds to at least one synaptic array; based on the weight distribution of the at least one synaptic array and the pulse array of the pre-neuron cluster corresponding to each synaptic array, a first probability distribution of the input current corresponding to the at least one post-neuron cluster is determined, including: Based on the weight distribution of the synaptic arrays corresponding to each channel and the pulse sequence of the preneurons corresponding to each synaptic array, the first probability distribution of the input electrical components of the postneurons corresponding to each channel is determined.
9. The data processing method according to claim 8, wherein, Based on the weight distribution of the synaptic arrays corresponding to each channel and the pulse sequence of the preneurons corresponding to each synaptic array, a first probability distribution of the input electrical components of the postneurons corresponding to each channel is determined, including: The transmission statistics of each of the aforementioned preneuron clusters are counted separately; The number of pulse statistics corresponding to different delays is determined based on the transmitted statistics; Determine the initial current distribution of each channel corresponding to the post-neuron cluster; Based on the pulse count and the initial current distribution of each channel corresponding to the post-neuron cluster, a first probability distribution of the input electrical component of each channel corresponding to the post-neuron is determined.
10. The data processing method according to claim 9, wherein, The first probability distribution of the input electrical components of each channel corresponding to the post-neuron is expressed by the following formula: in, Indicates the channel corresponding to the postneuron The input current, This indicates that the postneuron corresponds to the first The first synaptic array, the first The second probability distribution of a delayed effective pulse event Indicates the first The first synaptic array, the first The number of pulse events in the pulse array corresponding to each delay Indicates the first The first synaptic array, the first The connection probability with delay. This is a correction constant.
11. A data processing apparatus, characterized in that, An apparatus for use in a brain simulation system, the brain simulation system comprising an anterior neuron cluster, a posterior neuron cluster, and a synaptic array, wherein the posterior neuron cluster comprises multiple posterior neurons, the anterior neuron cluster comprises multiple anterior neurons, and the synaptic array is used to simulate the connection relationship between one group of neurons and another group of neurons, the apparatus comprising: A statistics module is used to determine the number of effective pulse events corresponding to each postneuron in the postneuron cluster based on the connection information of each synaptic array and the pulse array of the preneuron cluster corresponding to each synaptic array, wherein the postneuron cluster includes multiple postneurons; and to determine a first probability distribution of the input current corresponding to each postneuron based on the weight distribution of at least one synaptic array and the number of effective pulse events corresponding to each postneuron, wherein the postneuron cluster is interconnected with the preneuron cluster corresponding to each synaptic array through the at least one synaptic array respectively; The processing module is used to generate the input current array of the post-neuron cluster according to the first probability distribution.
12. An electronic device, characterized in that, include: Multiple processing cores; as well as An on-chip network is configured to interact with data between the plurality of processing cores and external data; wherein one or more of the processing cores store one or more instructions, and the one or more of the instructions are executed by one or more of the processing cores to enable the one or more of the processing cores to perform the data processing method as described in any one of claims 1-10.
13. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the data processing method as described in any one of claims 1-10.