Graphics processing unit and vertex processing method thereof, and terminal device

Abstract

The application provides a graphics processing unit and a vertex processing method and a terminal device thereof. The graphics processing unit comprises: a plurality of operation units for processing a to-be-displayed graphics to obtain processed vertices; and a vertex collection unit for collecting vertex data output by each operation unit in a task segmentation order. Each operation unit has a tag cache for caching an identifier of an output vertex. For each processed vertex, the operation unit determines whether the vertex hits in the tag cache. If the vertex hits, compressed vertex data is output. The compressed vertex data comprises an identifier of the vertex and / or a storage position of corresponding vertex data content of the vertex in the vertex collection unit. The technical scheme of the application can reduce transmission bandwidth of vertex data in the graphics processing unit and reduce data processing delay.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a graphics processing unit and its vertex processing method and terminal device. Background Technology

[0002] In recent years, with the continuous development of computing power and chip size of Graphics Processing Units (GPUs), the number of processing cores (also known as processing units) inside GPUs has been increasing. Processing units can be used for calculations, texture processing, and other processes. To fully utilize these processing units, GPUs need to divide large computational tasks into many smaller computational tasks and distribute them to different processing units for parallel processing. After these smaller computational tasks are completed, the results need to be aggregated according to the task division order for further data input or as the final result.

[0003] However, the computational results of existing computing units are massive, which makes GPUs demand high data transmission bandwidth; in addition, the large amount of data also causes unnecessary processing delays. Summary of the Invention

[0004] This invention provides a graphics processing unit and its vertex processing method and storage medium, which can reduce the transmission bandwidth of vertex data in the graphics processing unit and reduce data processing latency.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] In a first aspect, a graphics processing unit is provided, comprising: multiple arithmetic units for processing graphics to be displayed and obtaining processed vertices; a vertex collection unit for collecting vertex data output by each arithmetic unit in the order of task segmentation; each arithmetic unit has a tag cache for caching the identifiers of the output vertices; for each processed vertex, the arithmetic unit determines whether the vertex is matched in the tag cache; if the vertex is matched, it outputs compressed vertex data, the compressed vertex data including the identifier of the vertex and / or the storage location of its corresponding vertex data content in the vertex collection unit.

[0007] Optionally, the computing unit may also output the hit result to the vertex collection unit.

[0008] Optionally, when the vertex is hit in the tag cache, the vertex collection unit obtains the vertex data content corresponding to the vertex's identifier from the storage location in the compressed vertex data.

[0009] Optionally, if the vertex is not found in the label cache, the vertex data output by the computing unit includes the vertex's identifier, vertex data content, and its storage location in the vertex collection unit.

[0010] Optionally, the computing unit has a cache for caching the identifier of the vertex and its corresponding vertex data content. When the vertex is not found in the label cache, the computing unit outputs the identifier of the vertex and its storage location in the vertex collection unit to the vertex collection unit. The vertex collection unit searches for and reads the vertex data content corresponding to the identifier of the vertex from the cache according to the identifier of the vertex.

[0011] Optionally, the vertex collection unit has a vertex cache for caching the vertex data content, and the storage location is a storage location in the vertex cache; the vertex collection unit also has an input cache for caching the vertex identifier and / or the storage location.

[0012] Optionally, the vertex collection unit collects the vertex data output by the multiple collection and processing units one by one at different times according to the task segmentation order.

[0013] Secondly, this application also discloses a vertex processing method for a graphics processing unit, the graphics processing unit including multiple computing units and a vertex collection unit, the method being applied to the computing units, the method including: processing a graphic to be displayed to obtain processed vertices; determining whether the vertex is matched in a tag cache, the tag cache being used to cache the identifiers of output vertices; if matched, outputting compressed vertex data to the vertex collection unit, the compressed vertex data including the identifier of the vertex and / or the storage location of its corresponding vertex data content in the vertex collection unit.

[0014] Optionally, the vertex processing method of the graphics processing unit further includes: if a vertex is not found, outputting vertex data to the vertex collection unit, wherein the vertex data includes the vertex identifier, vertex data content, and storage location in the vertex collection unit.

[0015] Thirdly, this application also discloses a vertex processing method for a graphics processing unit, the graphics processing unit including multiple computing units and a vertex collection unit, the method being applied to the vertex collection unit, the method including: receiving compressed vertex data, the compressed vertex data including the vertex identifier and / or the storage location of the corresponding vertex data content in the vertex collection unit, the compressed vertex data being output by the computing unit after determining whether the vertex is hit in the tag cache, the tag cache being used to cache the identifiers of the output vertices.

[0016] Optionally, the vertex processing method further includes: obtaining the vertex data content corresponding to the vertex identifier from the storage location in the compressed vertex data.

[0017] Fourthly, this application also discloses a terminal device including the aforementioned graphics processing unit.

[0018] Fifthly, a computer-readable storage medium is provided having a computer program stored thereon, the computer program being executed by a processor to perform the steps of the above-described method.

[0019] In a sixth aspect, the present invention also provides a chip on which a computer program is stored, and when the computer program is executed by the chip, the steps of the above method are implemented.

[0020] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0021] In this invention, the graphics processing unit includes multiple processing units and a vertex collection unit. Each processing unit has a tag cache for caching the identifiers of already output vertices. When outputting vertex data, the processing unit first checks whether the vertex is in the tag cache. If the vertex is in the tag cache, the processing unit outputs compressed vertex data, which includes the vertex identifier and the storage location of its corresponding vertex data content in the vertex collection unit. By setting a tag cache to store the identifiers of already output vertices, the processing unit can determine whether the vertex data content has already been output by performing a hit test on the vertex before outputting the vertex data. This avoids repeatedly sending vertex data content, reduces the amount of data transmitted, and thus reduces the transmission bandwidth of vertex data in the graphics processing unit, further reducing data processing latency.

[0022] Furthermore, when a vertex is matched in the tag cache, the vertex collection unit retrieves the vertex data content corresponding to the vertex's identifier from the storage location within the compressed vertex data. In this invention, the storage location of the vertex data content in the vertex collection unit is generated by the processing unit, allowing the vertex collection unit to obtain the vertex data content through this storage location without the processing unit needing to send the vertex data content. This ensures normal data processing while reducing the transmission bandwidth of vertex data in the graphics processing unit. Attached Figure Description

[0023] Figure 1 This is a structural diagram of a graphics processing unit provided in an embodiment of the present invention;

[0024] Figure 2 This is a schematic diagram of an application scenario provided by an embodiment of the present invention;

[0025] Figure 3 This is a structural diagram of another graphics processing unit provided in an embodiment of the present invention.

[0026] Figure 4 This is a flowchart of a vertex processing method provided in an embodiment of the present invention;

[0027] Figure 5 This is an interactive flowchart of a vertex processing method provided in an embodiment of the present invention. Detailed Implementation

[0028] As described in the background section, the computational results of existing computing units involve a large amount of data, which leads to high requirements for data transmission bandwidth in GPUs; in addition, the large amount of data also causes unnecessary processing delays.

[0029] In the technical solution of this invention, by setting a tag cache to store the identifiers of the output vertices, the computing unit can determine whether the vertex data content of the vertex has been output by performing a hit test on the vertex before outputting the vertex data. This can avoid repeatedly sending vertex data content, reduce the amount of data transmitted, thereby reducing the transmission bandwidth of vertex data in the graphics processing unit and further reducing data processing latency.

[0030] Furthermore, when a vertex is matched in the tag cache, the vertex collection unit retrieves the vertex data content corresponding to the vertex's identifier from the storage location within the compressed vertex data. In this invention, the storage location of the vertex data content in the vertex collection unit is generated by the processing unit, allowing the vertex collection unit to obtain the vertex data content through this storage location without the processing unit needing to send the vertex data content. This ensures normal data processing while reducing the transmission bandwidth of vertex data in the graphics processing unit.

[0031] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0032] See Figure 1 The graphics processing unit provided by this invention includes multiple processing units 101 and a vertex collection unit 102. The processing units 101 process the graphics to be displayed to obtain the processed vertices. The vertex collection unit 102 collects the vertex data output by each processing unit 101 according to the task segmentation order.

[0033] In this embodiment of the invention, a vertex can refer to a vertex included in the actual geometric structure of the primitive to be rendered, such as the vertex of a triangle.

[0034] The graphic to be displayed referred to in the embodiments of the present invention can be a two-dimensional planar graphic or a three-dimensional graphic.

[0035] The computing unit referred to in this embodiment of the invention can be a computing unit capable of processing vertices in the graphic to be displayed. For example, it can perform deformation processing on vertices or change the color of vertices.

[0036] It should be noted that the operation unit can also be any other feasible name, as long as its function is to process vertices; correspondingly, the vertex collection unit can also be any other feasible name, as long as its function is to collect vertex data according to the task segmentation order, and the present invention does not impose any restrictions on this.

[0037] In practice, when processing a graphic to be displayed that has multiple vertices, these vertices can be assigned to multiple processing units 101 according to the task partitioning order. That is, multiple subtasks are divided and processed by multiple processing units 101 according to the task partitioning order. For example, for vertices labeled 0-9999, the first processing unit 101 can be assigned vertices labeled 0-999, the second processing unit 101 can be assigned vertices labeled 1000-1999, and so on, with the tenth processing unit 101 assigned vertices labeled 9000-9999. Parallel processing of vertices by multiple processing units 101 improves vertex processing efficiency.

[0038] Specifically, the processing unit 101 processes the vertices to obtain the processed vertices, that is, the vertex data content. The vertex data content may include the vertex coordinates and vertex attributes. The vertex attributes may include, but are not limited to, one or more of the following: coordinates, color, normal vector, texture, material, lighting information, etc.

[0039] In this embodiment, each processing unit 101 has a label cache 1011, which stores the identifiers of the vertices that the processing unit 101 has output. Specifically, the label cache 1011 can be a newly added cache storage space in the processing unit, or it can be a reused cache storage space in the processing unit 101. Since the amount of vertex identifier data is small, the storage space of the label cache 1011 does not need to be too large. Therefore, whether the label cache 1011 is newly added or reused, the impact on the processing unit 101 is very small, and the processing performance of the processing unit 101 can be guaranteed.

[0040] Furthermore, after obtaining the processed vertex, the processing unit 101 performs a hit test in the label buffer 1011 before outputting the vertex data. That is, the processing unit 101 determines whether the vertex is found in the label buffer 1011. If the vertex is found in the label buffer 1011, it means that the processing unit 101 has already output the vertex data. In this case, the processing unit 101 outputs compressed vertex data, which includes the vertex's identifier and / or the storage location of its corresponding vertex data content in the vertex collection unit 102. In other words, the processing unit 101 no longer outputs the vertex data content at this time. This is because the vertex data content contains many attributes and has a large data volume; by avoiding repeated transmission of vertex data content, the amount of data transmitted from the processing unit 101 to the vertex collection unit 102 can be greatly reduced. The storage location of the vertex data content corresponding to the vertex in the vertex collection unit 102 is generated by the processing unit 101 when it first outputs the vertex data content.

[0041] Furthermore, although the processing unit 101 no longer outputs the vertex data content, the vertex collection unit 102 may still need the vertex data content. Therefore, in order for the vertex collection unit 102 to still obtain the vertex data content, the processing unit 101 needs to output the vertex identifier and / or the storage location of its corresponding vertex data content in the vertex collection unit 102. In this way, the vertex collection unit 102 can use the vertex identifier to search for the vertex data content in its own storage space; or, the vertex collection unit 102 can directly retrieve the vertex data content from the storage location.

[0042] In specific implementation, the vertex collection unit 102 collecting vertex data output by each computing unit according to the task segmentation order means that the vertex collection unit 102 processes the vertices from each computing unit 101 in the input buffer according to the task segmentation order. In other words, the vertex collection unit 102 processes the vertex data output by one computing unit 101 before processing the vertex data output by the next computing unit 101. The vertex collection unit 102 does not process vertex data from two computing units 101 simultaneously.

[0043] Furthermore, the vertex collection unit 102 collects the vertex data output by each computing unit 101 in the order of task segmentation. This means that the time for data interaction between each computing unit 101 and the vertex collection unit 102 is independent. Therefore, when the computing unit 101 outputs the storage location of the vertex data content, it can ensure that the storage location contains the vertex data content that the computing unit 101 has already output. This ensures that the vertex collection unit 102 can retrieve the correct vertex data content at the storage location, thus ensuring the normal operation of vertex processing by the graphics processing unit.

[0044] Furthermore, the vertex collection unit 102 needs to collect and process a large amount of vertex data, which can easily lead to data congestion. In this application, by generating storage locations in the processing unit 101 and sending them to the vertex collection unit 102, the vertex collection unit 102 avoids calculating and allocating storage locations, thereby reducing the workload of the vertex collection unit 102, improving its efficiency, and reducing data congestion. In addition, since the number of processing units 101 in the graphics processing unit is much larger than the number of vertex collection units 102, and each processing unit processes a limited number of vertices, generating storage locations in the processing unit 101 does not affect the performance of the processing unit 101; moreover, the amount of data in the storage locations is small, and it does not increase the transmission bandwidth between the processing unit 101 and the vertex collection unit 102.

[0045] In one specific embodiment, when a vertex is not found in the label cache 1011, it indicates that the operation unit 101 has not output vertex data for that vertex. At this time, the operation unit 101 can generate the storage location of the vertex data content in the vertex collection unit, and then output the vertex's identifier, vertex data content, and its storage location in the vertex collection unit. Compared to the aforementioned case where a vertex is found, the data output by the operation unit 101 includes additional vertex data content.

[0046] In this case, vertex collection unit 102 receives the vertex identifier, vertex data content and its storage location in the vertex collection unit, and stores the vertex data content in the storage location.

[0047] In one specific embodiment, the processing unit 101 typically processes the vertices of a triangle. Figure 2 An example of a vertex is shown. In this example, there are two triangles: one consisting of vertices 0, 1, and 2, and the other consisting of vertices 0, 2, and 3. These two triangles share a common edge, meaning they have two identical vertices 0 and 2. After processing the vertices of the first triangle, the processing unit 101 can obtain and output the vertex data of vertices 0, 1, and 2; after processing the vertices of the second triangle, it can obtain the vertex data of vertices 0, 1, and 2.

[0048] In existing technologies, for the two triangles mentioned above, vertex data for vertices 0, 1, and 2, and vertices 0, 2, and 3 (a total of 6 vertices) needs to be output. However, this invention only needs to send vertex data for vertices 0, 1, 2, and 3 (a total of 4 vertices). Correspondingly, when there are 100 triangles, existing technologies require outputting vertex data for 300 vertices, while this invention only requires outputting vertex data for 102 vertices. Therefore, even with a large number of triangles, this invention can reduce the transmission of massive amounts of vertex data, thus reducing data transmission bandwidth. Furthermore, the reduction in data transmission also reduces the processing latency of the graphics processing unit.

[0049] In a non-limiting embodiment, please refer to Figure 3 The vertex collection unit 302 includes a vertex cache 3022, which is used to cache vertex data content. The storage location of the vertex data content in the vertex collection unit 302 refers to the storage location of the vertex data content in the vertex cache 3022.

[0050] The vertex collection unit 302 also includes an input buffer 3021, which is used to cache the identifiers and / or storage locations of vertices.

[0051] In this embodiment, the arithmetic unit 301 has a cache 3012, which is used to cache vertex identifiers and their corresponding vertex data content. When a vertex is not found in the label cache 3011, the arithmetic unit 301 outputs the vertex identifier and the storage location of the vertex data content in the vertex cache 3022 to the vertex collection unit 302. The vertex collection unit 302 searches for and reads the vertex data content corresponding to the vertex identifier from the cache 3012 according to the vertex identifier. The vertex collection unit 302 stores the read vertex data content in the storage location in the vertex cache 3022.

[0052] from Figure 3 As can be seen, the graphics processing unit includes multiple label caches 3011 and one vertex cache 3022. That is, multiple label caches 3011 correspond to the same vertex cache 3022. As mentioned earlier, the data interaction time between each processing unit 301 and the vertex collection unit 302 is independent. This means that for a period of time, a single processing unit 301 exclusively occupies the vertex cache 3022. Therefore, the processing unit 301 can perform hit tests in the label cache 3011 and pre-allocate the storage location of vertex data content in the vertex cache 3022.

[0053] Furthermore, the computation unit 301 can also output the hit result to the vertex collection unit 302. The vertex collection unit 302 can determine whether it needs to search for and read the vertex data content corresponding to the vertex's identifier from the cache 3012 based on the hit result. Specifically, if the hit result is a miss, it means that the computation unit 301 has not output the vertex, and the vertex collection unit 302 needs to search for and read the vertex data content corresponding to the vertex's identifier from the cache 3012 based on the vertex's identifier. Conversely, if the hit result is a miss, it means that the computation unit 301 has output the vertex, and the vertex collection unit 302 does not need to search for and read the vertex data content corresponding to the vertex's identifier from the cache 3012, but can directly obtain the vertex data content corresponding to the vertex's identifier from the corresponding storage location in the vertex cache 3022.

[0054] In an alternative embodiment, the input buffer 3021 can also be replaced by a data queue. That is, the vertex identifier and / or storage location are placed in this data queue. Specifically, this data queue is a first-in-first-out queue.

[0055] Furthermore, the graphics processing unit in this invention also includes a rasterization unit 303. The vertex collection unit 302 outputs the vertex data collected in the order of task segmentation to the rasterization unit 303, and the rasterization unit 303 performs rasterization processing on the vertex data.

[0056] It should be noted that the rasterization unit 303 is only an example. In actual application scenarios, the vertex collection unit 302 can output the vertex data collected in the order of task segmentation to any implementable processing unit, or output it directly. The present invention does not limit this.

[0057] In a specific application scenario, the computation unit is selected from one or more of the vertex shader, domain shader, and geometry shader. The vertex shader reads vertex data and outputs processed vertex data; the domain shader converts control points, additional data from the hull shader, and subdivision point positions from the tessellator stage into vertex data; and the geometry shader selectively uses vertex adjacency information based on the input primitives to output different primitives, where each vertex has vertex data.

[0058] Please refer to Figure 4 , Figure 4 A vertex processing method is shown. This vertex processing method can be executed by the arithmetic unit in the graphics processing unit.

[0059] The vertex processing method may specifically include the following steps:

[0060] Step 401: Process the graphic to be displayed to obtain the processed vertices;

[0061] Step 402: Determine whether the vertex is matched in the label cache, whereby the label cache is used to cache the identifiers of the output vertices;

[0062] Step 403: If a match is found, output compressed vertex data to the vertex collection unit. The compressed vertex data includes the identifier of the vertex and / or the storage location of its corresponding vertex data content in the vertex collection unit.

[0063] It should be noted that the sequence number of each step in this embodiment does not represent a limitation on the execution order of each step.

[0064] It is understood that, in specific implementations, the vertex processing method can be implemented using software programs, which run within a processor integrated into the chip or chip module. This method can also be implemented using a combination of software and hardware; this invention does not impose any limitations on this approach.

[0065] Furthermore, the vertex processing method also includes the following steps: if a vertex is not found, the vertex data content and its storage location in the vertex collection unit are generated, and the vertex data is output. The vertex data includes the vertex identifier, the vertex data content, and its storage location in the vertex collection unit.

[0066] In this embodiment of the invention, the computing unit can determine whether the vertex data has been output before outputting vertex data by performing a hit test on the vertex. This avoids repeatedly sending vertex data, reduces the amount of data transmitted, reduces the transmission bandwidth of vertex data in the graphics processing unit, and further reduces data processing latency.

[0067] Please refer to Figure 5 , Figure 5 The interactive flow of a vertex processing method is shown.

[0068] The vertex processing method may specifically include the following steps:

[0069] In step 501, the processing unit processes the graphic to be displayed and determines whether the vertices are matched in the label cache.

[0070] In one implementation, if a vertex is hit in the label cache, steps 502 and 503 are executed.

[0071] In step 502, the processing unit sends compressed vertex data. Correspondingly, the vertex collection unit receives the compressed vertex data. The compressed vertex data includes the vertex identifier and the storage location of its corresponding vertex data content in the vertex collection unit.

[0072] In step 503, the vertex collection unit obtains the vertex data content corresponding to the vertex identifier from the storage location in the compressed vertex data.

[0073] In another implementation, if the vertex is not found in the label cache, steps 504, 505 and 506 are executed.

[0074] In step 504, the processing unit sends vertex data. Correspondingly, the vertex collection unit receives the vertex data. The vertex data includes the vertex identifier, the vertex data content, and its storage location in the vertex collection unit.

[0075] In step 505, the vertex collection unit searches for and reads the vertex data content corresponding to the vertex identifier from the cache according to the vertex identifier.

[0076] In step 506, the vertex collection unit stores the vertex data content into the storage location indicated in the vertex data.

[0077] For more specific implementations of the embodiments of the present invention, please refer to the foregoing embodiments, which will not be repeated here.

[0078] Regarding the modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, hardware modules / units, or a combination of both. For example, for devices and products applied to or integrated into a chip, all modules / units can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs running on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits. For devices and products applied to or integrated into a chip module, all modules / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The implementation is achieved through a software program that runs on a processor integrated within the chip module. The remaining modules / units (if any) can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into terminal equipment, each of their modules / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components within the terminal equipment. Alternatively, at least some modules / units can be implemented using a software program that runs on a processor integrated within the terminal equipment, while the remaining modules / units (if any) can be implemented using hardware methods such as circuits.

[0079] This invention also discloses a storage medium, which is a computer-readable storage medium storing a computer program thereon, the computer program being executable during runtime. Figure 4 or Figure 5 The steps of the method shown are illustrated. The storage medium may include read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, etc. The storage medium may also include non-volatile memory or non-transitory memory, etc.

[0080] In the embodiments of this invention, "multiple" refers to two or more.

[0081] The descriptions of "first," "second," etc., appearing in the embodiments of this invention are for illustrative purposes and to distinguish the objects being described. They do not indicate any particular order and do not imply any special limitation on the number of devices in the embodiments of this invention. They do not constitute any limitation on the embodiments of this invention.

[0082] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer program are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means.

[0083] It should be understood that, in various embodiments of the present invention, the order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0084] In the several embodiments provided by this invention, it should be understood that the disclosed methods, apparatuses, and systems can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for example, the division of units is merely a logical functional division, and other division methods may exist in actual implementation; for example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0085] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0086] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can be physically comprised separately, or two or more units can be integrated into one unit. The integrated unit described above can be implemented in hardware or in the form of hardware plus software functional units.

[0087] The integrated unit implemented as a software functional unit described above can be stored in a computer-readable storage medium. This software functional unit, stored in a storage medium, includes several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute some steps of the methods described in the various embodiments of the present invention.

[0088] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A graphics processing unit, characterized in that, include: Multiple processing units are used to process the graphic to be displayed and obtain the processed vertices; The vertex collection unit is used to collect vertex data output by each processing unit in the order of task segmentation; Each processing unit has a tag cache for caching the identifiers of the output vertices. For each processed vertex, the processing unit determines whether the vertex is matched in the tag cache. If the vertex is matched, compressed vertex data is output. The compressed vertex data includes the identifier of the vertex and / or the storage location of its corresponding vertex data content in the vertex collection unit. The computing unit has a cache, which is used to cache the identifier of the vertex and its corresponding vertex data content. When the vertex is not found in the label cache, the computing unit outputs the identifier of the vertex and its storage location in the vertex collection unit to the vertex collection unit. The vertex collection unit searches for and reads the vertex data content corresponding to the identifier of the vertex from the cache according to the identifier of the vertex.

2. The graphics processing unit according to claim 1, characterized in that, The computing unit also outputs the hit result to the vertex collection unit.

3. The graphics processing unit according to claim 1, characterized in that, When a vertex is matched in the tag cache, the vertex collection unit retrieves the vertex data content corresponding to the vertex's identifier from the storage location in the compressed vertex data.

4. The graphics processing unit according to claim 1, characterized in that, If the vertex is not found in the label cache, the vertex data output by the computing unit includes the vertex's identifier, vertex data content, and its storage location in the vertex collection unit.

5. The graphics processing unit according to claim 1, characterized in that, The vertex collection unit has a vertex cache, which is used to cache the vertex data content, and the storage location is the storage location in the vertex cache; the vertex collection unit also has an input cache, which is used to cache the vertex identifier and / or the storage location.

6. The graphics processing unit according to claim 1, characterized in that, The vertex collection unit collects the vertex data output by the multiple computing units one by one at different times according to the task segmentation order.

7. The graphics processing unit according to claim 1, characterized in that, The computation unit is selected from one or more of the vertex shader, domain shader, and geometry shader.

8. A vertex processing method for a graphics processing unit, characterized in that, The graphics processing unit includes multiple computing units and a vertex collection unit, and the method is applied to the computing units; The method includes: Process the graphic to be displayed to obtain the processed vertices; Determine whether the vertex is matched in the label cache, which is used to cache the identifiers of the output vertices; If a match is found, compressed vertex data is output to the vertex collection unit. The compressed vertex data includes the vertex's identifier and / or the storage location of its corresponding vertex data content in the vertex collection unit. The processing unit has a cache, which is used to cache the identifier of the vertex and its corresponding vertex data content. If a cache miss occurs, the identifier of the vertex and its storage location in the vertex collection unit are output to the vertex collection unit. The vertex collection unit searches for and reads the vertex data content corresponding to the identifier of the vertex from the cache according to the identifier of the vertex.

9. A vertex processing method for a graphics processing unit, characterized in that, The graphics processing unit includes multiple computing units and a vertex collection unit, and the method is applied to the vertex collection unit; The method includes: The unit receives compressed vertex data, which includes the vertex identifier and / or the storage location of the corresponding vertex data content in the vertex collection unit. The compressed vertex data is output by the processing unit after determining whether the vertex is hit in the tag cache. The tag cache is used to cache the identifier of the output vertex. The computing unit has a cache, which is used to cache the identifier of the vertex and its corresponding vertex data content. If the computing unit determines that the vertex is not found in the label cache, the vertex collection unit receives the identifier of the vertex output by the computing unit and its storage location in the vertex collection unit, and searches for and reads the vertex data content corresponding to the identifier of the vertex from the cache according to the identifier of the vertex.

10. The vertex processing method of the graphics processing unit according to claim 9, characterized in that, Also includes: The vertex data content corresponding to the vertex identifier is obtained from the storage location in the compressed vertex data.

11. A terminal device, characterized in that, Includes the graphics processing unit as described in any one of claims 1 to 7.

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