Electroluminescent display device and method for detecting display defects thereof

Abstract

The present disclosure relates to an electroluminescent display apparatus and a display defect detection method thereof. The electroluminescent display apparatus includes a display panel including at least one sub-pixel connected to a data line, a gate line, and a low-level power line, and a comparator connected to the at least one sub-pixel through the data line and the low-level power line to compare a first input voltage from the data line with a second input voltage from the low-level power line to generate a comparison output. The first input voltage is a reference voltage, and the second input voltage is a voltage of a specific node of the at least one sub-pixel which is able to be offset from an initialization voltage.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0177968, filed on December 13, 2021. Technical Field

[0003] This disclosure relates to electroluminescent display devices and methods for detecting display defects thereon. Background Technology

[0004] Electroluminescent display devices are classified into inorganic and organic light-emitting display devices based on the material of their emitting layer. Each sub-pixel of an electroluminescent display device includes a self-emissive light-emitting device, and the amount of light emitted from the light-emitting device is controlled by a data voltage based on the grayscale level of the image data to adjust the brightness.

[0005] As subpixels degrade over time, hotspot defects may occur due to abnormal short circuits. A separate detection line is needed to detect defective subpixels identified as hotspots, and in this case, the pixel array may be complex and / or the panel's aperture ratio may be reduced. Aperture ratio is the ratio of the luminescent area of ​​a pixel to the total area of ​​the pixel. Summary of the Invention

[0006] In order to overcome the aforementioned problems of the related technologies, this disclosure provides an electroluminescent display device and a method for detecting display defects therewith, which can detect defective sub-pixels caused by abnormal short circuits without a separate detection line.

[0007] To achieve these and other advantages, and for the purposes of this disclosure, as embodied and broadly described herein, an electroluminescent display device includes: a display panel including at least one sub-pixel connected to a first data line and a first low-level power line; and a first comparator connected to the at least one sub-pixel via the first data line and the first low-level power line, wherein the first comparator is arranged to compare a first input voltage from the first data line with a second input voltage from the first low-level power line to generate a comparison output, wherein the first input voltage is a reference voltage and the second input voltage is a voltage at a specific node of the at least one sub-pixel.

[0008] In another aspect of this disclosure, a method for detecting display defects in an electroluminescent display device is provided. The electroluminescent display device includes at least one sub-pixel connected to a first data line and a first low-level power line. The method for detecting display defects includes: receiving a first input voltage through the first data line and receiving a second input voltage through the first low-level power line; and comparing the first input voltage with the second input voltage to generate a comparison output, wherein the first input voltage is a reference voltage and the second input voltage is the voltage of a specific node of the at least one sub-pixel. Attached Figure Description

[0009] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate one or more embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure. In the drawings:

[0010] Figure 1 This is a block diagram illustrating an electroluminescent display device according to an embodiment;

[0011] Figure 2 This is a diagram illustrating the pixel connection configuration according to an embodiment;

[0012] Figure 3 This is a diagram illustrating the connection configuration between the sub-pixel and the defect detection circuit according to an embodiment;

[0013] Figure 4 This is a diagram showing the operational waveforms of each of the sub-pixel and defect detection circuits according to the embodiment; and

[0014] Figures 5 to 8 This is a diagram showing various examples of the placement of defect detection circuits. Detailed Implementation

[0015] In the following description, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this specification, when adding reference numerals to elements in each drawing, it should be noted that similar reference numerals already used to indicate similar elements in other drawings are used for elements in any possible context. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the essential points of the present disclosure.

[0016] Figure 1 This is a block diagram illustrating an electroluminescent display device according to an embodiment.

[0017] Reference Figure 1According to the embodiments, the electroluminescent display device may include a display panel 10, a timing controller 11, a data driver 12, a gate driver 13, a defect detection circuit 14, and a power circuit 15.

[0018] In the screen area on the display panel 10 where the input image is displayed, data lines DL extending along the column direction (or vertical direction) may intersect with gate lines GL extending along the row direction (or horizontal direction), and pixels PXL may be arranged in a matrix type in multiple intersecting areas to configure a pixel array. In the pixel array, low-level power lines PW2 may extend along the column direction, and multiple sub-pixels arranged on the same column line may be connected to the same low-level power line PW2. Each of the low-level power lines PW2 and data lines DL may be connected to a sub-pixel adjacent to it in the column direction, and each of the gate lines GL may be connected to a sub-pixel adjacent to it in the row direction. Multiple sub-pixels can be configured into one pixel PXL.

[0019] As subpixels degrade over time, hotspot defects caused by abnormal short circuits may occur. The low-level power line PW2 and data line DL can be used to detect the presence or absence of defects in subpixels, thus eliminating the need for separate detection lines.

[0020] The timing controller 11 can receive timing signals from the host system, such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, and the dot clock DCLK. Figure 1 (Not shown in the original text) to generate timing control signals for controlling the operation timing of each of the data driver 12 and the gate driver 13. The timing control signals may include a gate timing control signal GDC for controlling the gate driver 13 and a data timing control signal DDC for controlling the data driver 12.

[0021] The data driver is arranged to supply data voltage (i.e., video data DATA) to the sub-pixels via data lines, where the level of the data voltage is based on a comparator output. For example, the timing controller 11 can receive video data DATA from the host system and can receive a comparator output OUT from the defect detection circuit 14 (e.g., from the comparator COMP). When the comparator output OUT is input to the timing controller, the timing controller 11 can execute a dark spot processing algorithm (defective sub-pixel compensation algorithm) to modulate the video data DATA to be input to the corresponding defective sub-pixel. A pixel PXL can be determined to be defective when at least one sub-pixel of a pixel PXL is defective. In this case, the timing controller 11 can either replace only the video data DATA to be applied to the defective sub-pixel with black grayscale data, or it can replace all the video data DATA to be applied to the defective pixel PXL with black grayscale data. The timing controller 11 can supply black grayscale data and other video data DATA for dark spot processing to the data driver 12.

[0022] The timing controller 11 can divide the display drive and the detection drive in time based on the timing control signals DDC and GDC. The display drive can be an operation that applies video data DATA, including black and grayscale data, to pixel PXL to display an input image on the screen. The detection drive can be an operation that detects defective sub-pixels and performs dark spot processing on the defective sub-pixels.

[0023] The defect detection circuit 14 can receive the sampling clock SCLK from the timing controller 11, and then output the comparison output OUT to the timing controller.

[0024] Display driving can be performed during the vertically active period, during which the data enable signal DE transitions from logic high to logic low within one frame. Alternatively, detection driving can be performed when the display panel's screen is off. For example, detection driving can be performed during the power-on period from when system mains power is applied until screen playback begins, or during the power-off period from when screen playback ends until system mains power is released. The power-on period can be the time period that occurs before screen playback begins but after system mains power is applied to the display device. The power-off period can be the time period that occurs after screen playback ends but before system mains power is removed from the display device. Screen playback can be described as the time period when the screen area displays an input image on the display panel.

[0025] Data driver 12 can be connected to the sub-pixel via data line DL. Based on the data timing control signal DDC, data driver 12 can generate the data voltage required for display driving or detection driving of the sub-pixel, and can supply the data voltage to data line DL. The data voltage used for display driving can be the result of digital-to-analog conversion of video data DATA, and for this purpose, data driver 12 can include multiple digital-to-analog converters. The data voltage used for detection driving ( Figure 4 Vdata can be the detection data voltage with an off level. Figure 4 The detection data voltage and the detection reference voltage can each be a fixed or preset voltage, independent of the video data DATA. In the detection drive, the data driver 12 can supply the detection data voltage to the data line DL, and then can supply the detection reference voltage to the data line DL. The detection reference voltage can include different first reference voltages (VOFF). Figure 4 VL) and second reference voltage ( Figure 4 (VH).

[0026] The data driver 12 may be configured with multiple source driver integrated circuits (ICs). Each source IC may be mounted on a flexible circuit film and bonded to the display panel 10, and may further include shift registers, latches, digital-to-analog converters, and output buffers. Each source IC may also include separate circuitry for generating a detection data voltage and a detection reference voltage.

[0027] Gate driver 13 can be connected to sub-pixels via gate line GL.

[0028] In the display driver, the gate driver 13 can generate scan signals based on the gate timing control signal GDC, and can supply scan signals to the gate lines GL respectively based on the data voltage supply timing. The horizontal display line to be supplied with data voltage can be selected by the scan signals. Each scan signal can be generated in the form of a pulse that oscillates between a gate on level and a gate off level. A scan signal with an on level can be set to a voltage higher than the threshold voltage of the transistor, while a scan signal with an off level can be set to a voltage lower than the threshold voltage of the transistor. The transistors included in the sub-pixels can be turned on in response to the scan signal with an on level and turned off in response to the scan signal with an off level.

[0029] Furthermore, in the detection drive, the gate driver 13 can generate a detection scan signal based on the gate timing control signal GDC. Figure 4 The system can perform a scan (SCAN) and supply a detection scan signal to a predetermined gate line GL. The horizontal display line to be supplied with the detection data voltage can be selected by using the scan signal.

[0030] The gate driver 13 may include a gate shift register containing multiple output stages. The gate shift register may be located in a bezel area outside the screen area of ​​the display panel 10. The multiple output stages of the gate shift register can be cascaded together and can transmit and receive carry signals. The multiple output stages can be independently connected to the gate line GL and can output scan signals to the gate line GL.

[0031] Gate driver 13 may include a level shifter that converts a gate timing control signal GDC with swing widths having on and off levels, and supplies the converted gate timing control signal GDC to a gate shift register. The level shifter may be mounted on a printed circuit board (PCB) electrically connected to display panel 10. The gate timing control signal GDC generated by the timing controller swings with transistor-to-transistor level (TTL). The level shifter converts the TTL of the gate timing control signal GDC to on and off levels. The voltage swing width of the on and off levels is greater than the voltage swing width of the TTL.

[0032] The defect detection circuit 14 can be connected to the sub-pixel via the data line DL and the low-level power line PW2. In the detection drive, a first input voltage can be supplied to the defect detection circuit 14 via the data line DL, and a second input voltage can be supplied to the defect detection circuit 14 via the low-level power line PW2. The defect detection circuit 14 can compare the first input voltage with the second input voltage to generate a comparison output OUT. Here, the first input voltage can be a detection reference voltage, and the second input voltage can be the voltage of a specific node (e.g., a source node) of the sub-pixel that is capable of offsetting from a predetermined or preset initialization voltage. Due to defects, for example, in the pixel, the voltage of a specific node may be able to offset from the initialization voltage, resulting in charging or discharging of the specific node, even if the specific node floats by disconnecting from other lines (e.g., from the initialization power terminal and the low-level power terminal as described herein).

[0033] In the detection drive, the detection data voltage has a cutoff level, and an initialization voltage can be applied to the corresponding sub-pixel. The driving element included in the corresponding sub-pixel can be cut off by the detection data voltage with a cutoff level, and therefore, the driving current may not flow in the driving element. At this time, the specific node connected to the driving element can be floating (e.g., in the absence of any connection to the initialization power terminal or the low-level power terminal), and therefore, if no abnormal short-circuit defects of any type occur in the corresponding sub-pixel, the specific node should maintain the applied initialization voltage. However, if abnormal short-circuit defects of any type occur in the corresponding sub-pixel, the voltage of the specific node may not remain at the initialization voltage and may be lower or higher than the initialization voltage (e.g., by decreasing or increasing from the initialization voltage over a certain period of time). The defect detection circuit 14 can receive the voltage of the specific node of the corresponding sub-pixel that can be offset from the initialization voltage as described above via the low-level power line PW2.

[0034] The power circuit 15 can generate high-level and low-level drive voltages for the display drive of the sub-pixel. The power circuit 15 can also generate the initialization voltage required for the detection drive of the sub-pixel. In the detection drive, the power circuit 15 can supply the initialization voltage to a specific node of the sub-pixel via the low-level power line PW2.

[0035] Figure 2 This is a diagram illustrating the connection configuration of pixel PXL according to an embodiment.

[0036] Reference Figure 2 According to the implementation method, the pixel PXL may include multiple sub-pixels SP. Multiple sub-pixels SP can be configured with a pixel PXL to achieve various color combinations. Multiple sub-pixels SP may include red (R) sub-pixels SP, green (G) sub-pixels SP, blue (B) sub-pixels SP, and white (W) sub-pixels SP, but are not limited thereto.

[0037] Each sub-pixel SP may include a light-emitting device, which is an inverted organic light-emitting diode (OLED). A high-level driving voltage can be supplied to the inverted OLED as a common voltage, and therefore, the anode electrodes of all OLEDs of the sub-pixel SP configured with a pixel PXL can be connected to the high-level power terminal EVDD via a common high-level power line PW1.

[0038] A sub-pixel SP configured with a pixel PXL can be connected to a low-level power terminal EVSS via different low-level power lines PW2. These different low-level power lines PW2 can be physically separated from each other and can therefore each be used as a detection line.

[0039] A subpixel SP of a pixel PXL can be connected to a data driver via different data lines DL, and therefore, a data voltage Vdata can be supplied by the data driver. The data lines DL can be physically separated from each other, and therefore each can be used as a detection line.

[0040] A subpixel SP configured with a pixel PXL can be connected to a gate driver via a gate line GL, and therefore, a scan signal SCAN can be supplied by the gate driver.

[0041] Figure 3 This is a diagram showing the connection configuration between the sub-pixel SP and the defect detection circuit according to an embodiment.

[0042] Reference Figure 3 A subpixel SP may include a light-emitting device EL, a driving element DT, a switching element ST, and a storage capacitor Cst, and can be implemented in an inverted form. The reason for implementing the subpixel SP in an inverted form may be because a low-level power line PW2 is used as the detection line. Furthermore, when the subpixel SP is implemented in an inverted form, its structure can be simplified, and therefore, the aperture ratio of a display panel with high resolution and a large area can be easily increased.

[0043] The light-emitting device EL can be implemented as an OLED. The anode electrode of the OLED can be connected to the high-level power terminal EVDD via a common high-level power line PW1, and the cathode electrode of the OLED can be connected to one electrode of the driving element DT.

[0044] The driving element DT may include a gate electrode connected to a first node N1 (gate node), a drain electrode (first electrode) connected to the cathode electrode of the light-emitting device EL, and a source electrode (second electrode) connected to a second node N2 (source electrode). Here, the second node N2 may be a specific node to be detected. In the following text, the specific node may be referred to as the source node.

[0045] The switching element ST can be connected between the data line DL and the first node N1, and can be turned on / off based on the scan signal SCAN supplied through the gate line GL.

[0046] The storage capacitor Cst can be connected to the first node N1 and the second node N2, and can maintain the gate-source voltage of the driving element DT.

[0047] Reference Figure 3 The sub-pixel SP can be connected to the defect detector 14A via the data line DL and the low-level power line PW2. The defect detector 14A may include a comparator COMP, a first switch SW1, and a second switch SW2.

[0048] The first input (+) of comparator COMP can be connected to the data line DL, and the second input (-) of comparator COMP can be connected to the low-level power line PW2. Comparator COMP can receive a first input voltage via the data line DL, a second input voltage via the low-level power line PW2, and a sampling clock SCLK from the timing controller 11. The first input voltage can be a predetermined detection reference voltage, and the second input voltage can be the voltage of the source node N2 of the sub-pixel SP.

[0049] The comparator COMP compares the detected reference voltage with the voltage at the source node N2 based on the sampling clock SCLK to generate a comparison output OUT. That is, it outputs the comparison output OUT in response to the sampling clock signal SCLK. The comparator COMP can transmit the comparison output OUT to the timing controller 11. The timing controller 11 can determine the presence or absence of a defect in the sub-pixel SP and the defect type based on the logic value of the comparison output OUT. For this purpose, a defect type table predetermined through experimentation can be stored in advance. The timing controller 11 can perform a dark spot processing algorithm on the defective sub-pixel to modulate the video data DATA to be input to the corresponding defective sub-pixel.

[0050] The first switch SW1 supplies the low-level driving voltage required to drive the sub-pixel SP to the source node N2. The first switch SW1 can be connected between the low-level power line PW2 and the low-level power terminal EVSS. The first switch SW1 can remain in the on state in display driving and in the off state in detection driving. In detection driving, the first switch SW1 can be off, and therefore, the low-level power line PW2 can be used as a detection line.

[0051] The second switch SW2 can supply an initialization voltage Vpre to the source node N2 of the sub-pixel SP. The second switch SW2 can be connected between the low-level power line PW2 and the initialization power terminal. The second switch SW2 can be turned on during the initialization period of the detection drive and turned off during other periods of the detection drive.

[0052] Figure 4 This is a diagram showing the operating waveforms of each of the sub-pixel and defect detection circuits according to the embodiment.

[0053] Reference Figure 4 The detection driver can be executed in the order of initialization period X1, transition period X2, and detection period X3.

[0054] The scan signal SCAN applied to the sub-pixel SP can have an on level during the initialization period X1 and the transition period X2, and can have an off level during the detection period X3.

[0055] The first switch SW1 included in the defect detector 14A can remain in the off state during the initialization period X1, the transition period X2, and the detection period X3.

[0056] The second switch SW2 included in the defect detector 14A can remain in the on state during the initialization period X1 and can remain in the off state during the transition period X2 and the detection period X3.

[0057] The data driver can supply a detection data voltage VOFF with a cutoff level to the data line DL during initialization period X1 and transition period X2, and can supply a detection reference voltage to the data line DL during detection period X3. The detection reference voltage can include a first reference voltage VR lower than the initialization voltage Vpre and a second reference voltage VH higher than the initialization voltage Vpre. The first reference voltage VL can be a detection reference voltage for detecting a first defect type 1 (underflow type), in which the source node voltage VN2 is lower than the initialization voltage Vpre. The second reference voltage VH can be a detection reference voltage for detecting a second defect type 2 (overflow type), in which the source node voltage VN2 is higher than the initialization voltage Vpre.

[0058] The first type of underflow defect may be caused by a short-circuit defect in the switching element of the sub-pixel SP and / or a short-circuit defect in the storage capacitor of the sub-pixel SP. A short-circuit defect in the switching element may include a gate-source short circuit, a gate-drain short circuit, and / or a drain-source short circuit in the switching element. A short-circuit defect in the storage capacitor may represent a short circuit between the two electrodes of the storage capacitor.

[0059] The second type of overflow defect may be caused by short-circuit defects in the driving elements of the sub-pixel SP and / or short-circuit defects in the light-emitting device of the sub-pixel SP. Short-circuit defects in the driving elements may include gate-source short circuits, gate-drain short circuits, and drain-source short circuits in the driving elements. Short-circuit defects in the light-emitting device may represent a short circuit between the anode and cathode electrodes of the light-emitting device.

[0060] When the above-mentioned defect type appears in sub-pixel SP, the source node voltage VN2 of sub-pixel SP may not be able to maintain the initial voltage Vpre, and may be lower or higher than the initial voltage Vpre during the transition period X2 and the detection period X3.

[0061] During the detection period X3, the data driver can supply a first reference voltage VL to the data line DL, and then can supply a second reference voltage VH to the data line DL.

[0062] The comparator COMP can be based on the first sampling clock SCLK (i.e., when the first sampling clock SCLK signal is high for the first time, such as...). Figure 4 (As shown in the SCLK signal diagram) the first reference voltage VL is compared with the source node voltage N2 of the sub-pixel SP, in order to... Figure 4 The first comparison output is generated at the first timing point of the detection period X3 shown on the OUT signal diagram, and can be based on the second sampling clock SCLK (i.e., when the second sampling clock SCLK is high for the second time, such as...). Figure 4 (As shown in the SCLK diagram) The second reference voltage VH is compared with the source node voltage N2 of the sub-pixel SP to generate a second comparison output at the second timing of the detection period X3, which is after the first timing and as shown in the diagram. Figure 4 The OUT signal is shown in the diagram. Each of the first and second comparator outputs can be one of a "1" indicating a high voltage and a "0" indicating a low voltage. The sampling clock SCLK acts as a clock / latch for latching the OUT signal. For example, the OUT signal can rise to "1" (or fall to "0") from the rising edge of the first sampling clock SCLK, and if the timing of the OUT signal changes at the second sampling clock SCLK, the OUT signal will fall to "0" (or rise to "1") from the rising edge of the second sampling clock SCLK.

[0063] At the first timing point of the SCLK signal, when the source node voltage VN2 of the sub-pixel SP is lower than the first reference voltage VL, the comparator COMP can generate a high voltage "1" as the first comparison output, and when the source node voltage VN2 of the sub-pixel SP is higher than or equal to the first reference voltage VL, the comparator COMP can generate a low voltage "0" as the first comparison output. This is likely because the source node voltage VN2 of the sub-pixel SP, which serves as the detection target voltage, is input to the second input terminal (-) of the comparator COMP.

[0064] At the second timing of the SCLK signal, when the source node voltage VN2 of the sub-pixel SP is higher than the second reference voltage VH, the comparator COMP can generate a low voltage "0" as the second comparison output, and when the source node voltage VN2 of the sub-pixel SP is lower than or equal to the second reference voltage VH, the comparator COMP can generate a high voltage "1" as the second comparison output.

[0065] The comparator COMP can transmit a first comparison output and a second comparison output to the timing controller 11. The timing controller 11 can determine whether a defect has occurred or not in the sub-pixel SP based on the logical combination of the first comparison output and the second comparison output. Specifically, the timing controller 11 can determine that the sub-pixel SP is in a normal state only when the logical combination of the first comparison output and the second comparison output is (1, 0), and otherwise, it can determine that the sub-pixel SP is in a defective state.

[0066] Furthermore, when the logic combination is (1, 1), the timing controller 11 can determine that the first defect of the underflow type occurs in the sub-pixel SP, and when the logic combination is (0, 0), the timing controller 11 can determine that the second defect of the overflow type occurs in the sub-pixel SP.

[0067] Figures 5 to 8 This is a diagram showing various examples of the placement of defect detection circuitry. In Figures 5 to 8 In Chinese, "SPCB" can represent source printed circuit board, "COF" can represent flexible circuit film, and "SIC" can represent source IC.

[0068] exist Figures 5 to 7 In this circuit, the first switch SW1 is connected between the low-level power line PW2 and the low-level power terminal EVSS. The second switch SW2 is connected between the low-level power line PW2 and the initialization power terminal that supplies the initialization voltage Vpre to multiple sub-pixels SP. The low-level power terminal EVSS is connected between the power circuit 15 and the first switch SW1, and the initialization power terminal is connected between the power circuit 15 and the second switch SW2.

[0069] exist Figures 5 to 8 In this circuit, the output terminal of comparator COMP is connected to timing controller 11.

[0070] Reference Figure 5 The comparator COMP, configuring the defect detector 14A, along with the first switch SW1 and the second switch SW2, can be located in the pseudo-region DMY of the display panel 10 where no image is displayed. Advantageously, this allows for a reduction in the size of the source printed circuit board (SPCB). In this case, multiple sub-pixels SP arranged in the same column line COL of the image display area ACT of the display panel 10 can share the defect detector 14A located in the pseudo-region DMY. The defect detector 14A can be connected to the data line DL and the low-level power line PW2 arranged in the same column line COL.

[0071] Defect detectors 14A can be provided in multiple pseudo-regions DMY of the display panel 10. Multiple defect detectors 14A can each correspond to multiple column lines COL.

[0072] Reference Figure 6 The comparator COMP, configuring the defect detector 14A, along with the first switch SW1 and the second switch SW2, can be mounted on the source printed circuit board SPCB, which is connected to the data driver via a flexible circuit film COF. In this case, multiple sub-pixels SP arranged in the same column line COL in the display panel 10 can share the defect detector 14A mounted on the source printed circuit board SPCB. The defect detector 14A can be connected to the data line DL and the low-level power line PW2 arranged in the same column line COL.

[0073] Multiple defect detectors 14A can be provided on the source printed circuit board (SPCB). The multiple defect detectors 14A can each correspond to multiple column lines (COL).

[0074] The comparator COMP can be connected to the timing controller 11.

[0075] Reference Figure 7 The comparator COMP, configuring the defect detector 14A, along with the first switch SW1 and the second switch SW2, can be housed within the source IC SIC used to implement the data driver. Compared to other display sensing configurations, the use of the defect detector (including the comparator COMP) described herein allows for the omission of one or more sensing components (e.g., sensing transistors) per pixel, as well as the associated ADC components within the source IC SIC. The placement of the comparator COMP within the source IC SIC effectively utilizes space and minimizes the need for redesigning the layout in other areas of the display to make room for the comparator COMP. In this configuration, multiple sub-pixels SP arranged in the same column line COL of the display panel 10 can share the defect detector 14A housed within the source IC SIC. The defect detector 14A can be connected to the data line DL and the low-level power line PW2 arranged in the same column line COL.

[0076] Multiple source ICs (SiCs) may be required to drive the display panel 10 with a large area, and each source IC (SiC) may provide a defect detector 14A. Multiple defect detectors 14A may each correspond to multiple column lines (COL).

[0077] Reference Figure 8The comparator COMP, configuring the defect detector 14A, along with the first switches SW1a, SW1b, and the second switch SW2, can be disposed on the source printed circuit board SPCB, which is connected to the data driver via a flexible circuit film COF. In this case, multiple sub-pixels SP arranged in multiple column lines COL1 and COL2 in the display panel 10 can share a single defect detector 14A disposed on the source printed circuit board SPCB. The defect detector 14A can be connected to multiple data lines DL and multiple low-level power lines PW2 arranged in multiple column lines COL1 and COL2, and can detect defects in sub-pixels through block units including multiple column lines COL1 and COL2.

[0078] A first multiplexer M1 can be connected between a comparator COMP and multiple data lines DL, and a second multiplexer M2 can be connected between the comparator COMP and multiple low-level power lines PW2. The first multiplexer M1 can selectively connect any one of the multiple data lines DL to the comparator COMP. The second multiplexer M2 can selectively connect any one of the multiple low-level power lines PW2 to the comparator COMP. The first multiplexer M1 selects a data line from the multiple data lines DL and connects it to the first input terminal of the comparator COMP, and the second multiplexer M2 selects a low-level power line PW2 from the multiple low-level power lines PW2 and connects it to the second input terminal of the comparator COMP.

[0079] The first switch SW1a and the second switch SW2 can be connected to the power circuit 15.

[0080] and Figures 5 to 7 Compared to the layout example, Figure 8 The arrangement example can reduce the number of comparators COMP, thereby reducing manufacturing complexity and cost.

[0081] This implementation method can achieve the following effects.

[0082] In this embodiment, since each of the data lines and low-level power lines required to drive the subpixels is used as a detection line, a separate detection line for detecting subpixel defects may not be necessary.

[0083] Because this embodiment uses an inverted simple subpixel structure and does not require a separate detection line, it can be easily applied to display panels with high resolution and large areas requiring high aperture ratio.

[0084] In this embodiment, because the specific node voltage of the sub-pixel received via the low-level power line is double-sampled based on two detection reference voltages, the presence or absence of defects and the type of defect can be effectively determined. Therefore, in this embodiment, by detecting and compensating for hotspot defects caused by abnormal short circuits, display quality can be improved, and product lifespan and reliability can be increased.

[0085] The effects of this disclosure are not limited to the examples above, and various other effects may be included in the specification.

[0086] Although this disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the scope of this disclosure as defined by the appended claims.

[0087] This article also discloses the following numbered terms:

[0088] Clause 1. An electroluminescent display device, comprising:

[0089] A display panel, comprising at least one sub-pixel connected to data lines, gate lines, and power lines; and

[0090] A comparator, connected to the at least one sub-pixel via the data line and the low-level power line, compares a first input voltage from the data line with a second input voltage from the low-level power line to generate a comparison output.

[0091] Wherein, the first input voltage is a preset reference voltage, and

[0092] The second input voltage is the voltage of a specific node of the at least one sub-pixel that can be offset from a preset initialization voltage.

[0093] Clause 2. The electroluminescent display device according to Clause 1, wherein the reference voltage includes a first reference voltage lower than the initialization voltage and a second reference voltage higher than the initialization voltage.

[0094] Clause 3. An electroluminescent display device according to Clause 1 or Clause 2, wherein, during a preset detection period, the comparator compares the first reference voltage with the voltage of the specific node of the at least one sub-pixel based on a first sampling clock to generate a first comparison output, and compares the second reference voltage with the voltage of the specific node of the at least one sub-pixel based on a second sampling clock to generate a second comparison output.

[0095] Clause 4. The electroluminescent display device according to any of the preceding clauses further includes:

[0096] A data driver that supplies the first reference voltage to the data line during a preset detection period, and then supplies the second reference voltage to the data line; and

[0097] A power circuit that, during an initialization period prior to the detection period, generates the initialization voltage to be supplied to the specific node of the at least one sub-pixel via the low-level power line.

[0098] Clause 5. The electroluminescent display device according to any of the preceding clauses further includes:

[0099] A first switch, connected between the low-level power line and the low-level power terminal, supplies the low-level drive voltage required to drive the at least one sub-pixel to the specific node of the at least one sub-pixel; and

[0100] A second switch is connected between the low-level power line and the initialization power terminal to supply the initialization voltage to the specific node of the at least sub-pixel.

[0101] Clause 6. An electroluminescent display device according to any of the preceding clauses, wherein the first switch remains in the off state during the initialization period and the detection period, and

[0102] The second switch remains in the ON state during the initialization period and remains in the OFF state during the detection period.

[0103] Clause 7. An electroluminescent display device according to any of the preceding clauses, wherein the comparator, the first switch, and the second switch are disposed in a pseudo-region of the display panel where no image is displayed, and

[0104] Multiple sub-pixels arranged in the same column of the display panel share the comparator, the first switch, and the second switch disposed in the pseudo-region.

[0105] Clause 8. An electroluminescent display device according to any of the preceding clauses, wherein the comparator, the first switch, and the second switch are disposed on a source printed circuit board connected to the data driver, and

[0106] Multiple sub-pixels arranged in at least one column line of the display panel share the comparator, the first switch, and the second switch disposed on the source printed circuit board.

[0107] Clause 9. An electroluminescent display device according to any of the preceding clauses, wherein the comparator, the first switch, and the second switch are disposed in a source integrated circuit for implementing the data driver, and

[0108] Multiple sub-pixels arranged in the same column of the display panel share the comparator, the first switch, and the second switch disposed in the source integrated circuit.

[0109] Clause 10. An electroluminescent display device according to any of the preceding clauses, wherein the at least one sub-pixel comprises:

[0110] The light-emitting device is connected to a high-level power terminal at one of its electrodes and is supplied with a high-level driving voltage required to drive the at least one sub-pixel through the high-level power terminal;

[0111] A driving element, comprising a gate electrode connected to a first node, a first electrode connected to other electrodes of the light-emitting device, and a second electrode connected to the specific node;

[0112] A switching element, connected between the data line and the first node; and

[0113] A storage capacitor is connected between the first node and the specific node.

[0114] Clause 11. A method for detecting display defects in an electroluminescent display device, the electroluminescent display device comprising at least one sub-pixel connected to a data line, a gate line, and a power line, the method comprising:

[0115] A first input voltage is received via the data line, and a second input voltage is received via the power line; and

[0116] The first input voltage is compared with the second input voltage to generate a comparison output, wherein the first input voltage is a reference voltage, and

[0117] The second input voltage is the voltage of a specific node of the at least one sub-pixel that can be offset from the initial voltage.

[0118] Clause 12. The defect detection method according to Clause 11, wherein the reference voltage includes a first reference voltage lower than the initialization voltage and a second reference voltage higher than the initialization voltage.

[0119] Clause 13. The display defect detection method according to Clause 11 or Clause 12, wherein comparing the first input voltage with the second input voltage to generate the comparison output includes:

[0120] During a preset detection period, the first reference voltage is compared with the voltage of the specific node of the at least one sub-pixel based on a first sampling clock to generate a first comparison output; and

[0121] During the detection period, the second reference voltage is compared with the voltage of the specific node of the at least one sub-pixel based on the second sampling clock to generate a second comparison output.

[0122] Clause 14. The display defect detection method according to any one of Clauses 11 to 13 further comprises: supplying the initialization voltage to the specific node of the at least one sub-pixel via the power line during an initialization period prior to the detection period.

[0123] In addition, exemplary embodiments of this disclosure may also be described as follows:

[0124] Appendix 1. An electroluminescent display device, comprising:

[0125] A display panel, comprising at least one sub-pixel connected to a first data line and a first low-level power line; and

[0126] A first comparator, connected to the at least one sub-pixel via the first data line and the first low-level power line, is configured to compare a first input voltage from the first data line with a second input voltage from the first low-level power line to generate a comparison output.

[0127] Wherein, the first input voltage is a reference voltage, and

[0128] The second input voltage is the voltage of a specific node of the at least one sub-pixel.

[0129] Note 2. The electroluminescent display device according to Note 1, wherein the reference voltage includes a first reference voltage lower than the initialization voltage and a second reference voltage higher than the initialization voltage.

[0130] Note 3. In the electroluminescent display device according to Note 2, the first comparator is arranged as follows during the detection period:

[0131] Upon receiving the first clock signal, the first reference voltage is compared with the voltage of the specific node of the at least one sub-pixel to generate a first comparison output; and

[0132] Upon receiving the second clock signal, the second reference voltage is compared with the voltage of the specific node of the at least one sub-pixel to generate a second comparison output.

[0133] Note 4. The electroluminescent display device according to Note 2 or Note 3 further includes:

[0134] A data driver, configured to supply the first reference voltage to the first data line during a detection period, and then supply the second reference voltage to the first data line; and

[0135] A power circuit is arranged to generate, during an initialization period prior to the detection period, the initialization voltage to be supplied to the specific node of the at least one sub-pixel via the first low-level power line.

[0136] Note 5. The electroluminescent display device according to any of the foregoing notes further includes:

[0137] A first switch, connected between the first low-level power line and a low-level power terminal, supplies a low-level driving voltage to the specific node of the at least one sub-pixel for driving the at least one sub-pixel; and

[0138] A second switch is connected between the first low-level power line and the initialization power terminal to supply the initialization voltage to the specific node of the at least one sub-pixel.

[0139] Note 6. The electroluminescent display device according to Note 5 when subordinate to Note 4, wherein the first switch remains in the off state during the initialization period and the detection period, and

[0140] The second switch remains in the ON state during the initialization period and remains in the OFF state during the detection period.

[0141] Note 7. The electroluminescent display device according to Note 5 when subordinate to Note 4, wherein the first comparator, the first switch, and the second switch are disposed on:

[0142] The source printed circuit board connected to the data driver,

[0143] Flexible circuit film,

[0144] Source integrated circuit, or

[0145] The pseudo-area of ​​the display panel where no image is displayed.

[0146] Note 8. The electroluminescent display device according to any of the foregoing notes further includes a first plurality of sub-pixels arranged in a first column, the first plurality of sub-pixels including the at least one sub-pixel.

[0147] Note 9. The electroluminescent display device according to Note 8, wherein the first plurality of sub-pixels share the first comparator, the first switch, and the second switch.

[0148] Note 10. The electroluminescent display device according to Note 8 or 9, wherein the display panel further includes a second plurality of sub-pixels connected to a second data line and a second low-level power line; and

[0149] The first comparator is connected to the second plurality of sub-pixels via the second data line and the second low-level power line. The first comparator is arranged to compare a third input voltage from the second data line with a fourth input voltage from the second low-level power line to generate another comparison output.

[0150] Wherein, the third input voltage is another reference voltage, and

[0151] The fourth input voltage is the voltage of a specific node of the second plurality of sub-pixels.

[0152] Note 11. The electroluminescent display device according to Note 10, wherein, in a first mode, the first comparator is connected to the first plurality of sub-pixels, and in a second mode, the first comparator is connected to the second plurality of sub-pixels.

[0153] Note 12. The electroluminescent display device according to Note 10 or 11 further includes:

[0154] A first switch, connected between the first low-level power line and a low-level power terminal, supplies a low-level driving voltage to the specific node of the first plurality of sub-pixels for driving the first plurality of sub-pixels; and

[0155] A second switch, connected between each of the first and second low-level power lines and an initialization power terminal, supplies the initialization voltage to a specific node of each of the first and second plurality of sub-pixels; and

[0156] A third switch is connected between the second low-level power line and the low-level power terminal to supply a low-level driving voltage to the specific node of the second plurality of sub-pixels for driving the second plurality of sub-pixels.

[0157] Note 13. The electroluminescent display device according to Note 12, wherein the first comparator, the first switch, the second switch and the third switch are disposed on a source printed circuit board connected to the data driver via a flexible circuit film.

[0158] Note 14. The electroluminescent display device according to any one of Notes 10 to 13, wherein the second plurality of sub-pixels are arranged in a second column.

[0159] Note 15. The electroluminescent display device according to any of the foregoing notes, wherein each sub-pixel includes:

[0160] The light-emitting device is connected to a high-level power terminal at one of its electrodes and is supplied with a high-level driving voltage, which drives the at least one sub-pixel through the high-level power terminal;

[0161] A driving element, comprising a gate electrode connected to a first node, a first electrode connected to another electrode of the light-emitting device, and a second electrode connected to the specific node;

[0162] A switching element, connected between the data line and the first node; and

[0163] A storage capacitor is connected between the first node and the specific node.

[0164] Note 16. The electroluminescent display device according to any of the foregoing notes, wherein the reference voltage is a preset reference voltage and the initialization voltage is a preset initialization voltage.

[0165] Note 17. The electroluminescent display device according to any of the foregoing notes further includes a data driver arranged to supply a data voltage to the at least one sub-pixel via the first data line, wherein the level of the data voltage is based on the comparison output.

[0166] Note 18. In any of the electroluminescent display devices described in the foregoing notes, a defect in the at least one sub-pixel causes the floating voltage of the particular node to increase or decrease from the initial voltage applied to the particular node.

[0167] Appendix 19. A method for detecting display defects in an electroluminescent display device, the electroluminescent display device comprising at least one sub-pixel connected to a first data line and a first low-level power line, the method comprising:

[0168] The first input voltage is received through the first data line, and the second input voltage is received through the first low-level power line; and

[0169] The first input voltage is compared with the second input voltage to generate a comparison output, wherein the first input voltage is a reference voltage, and

[0170] The second input voltage is the voltage of a specific node of the at least one sub-pixel.

[0171] Note 20. The defect detection method according to Note 19, wherein the reference voltage includes a first reference voltage lower than the initialization voltage and a second reference voltage higher than the initialization voltage.

[0172] Appendix 21. The display defect detection method according to Appendix 20, wherein comparing the first input voltage with the second input voltage to generate the comparison output includes:

[0173] During the detection period, and in response to a first clock signal, the first reference voltage is compared with the voltage of the specific node of the at least one sub-pixel to generate a first comparison output; and

[0174] During the detection period, and in response to a second clock signal, the second reference voltage is compared with the voltage of the specific node of the at least one sub-pixel to generate a second comparison output.

[0175] Note 22. The display defect detection method according to Note 21 further includes: during an initialization period prior to the detection period, supplying the initialization voltage to the specific node of the at least one sub-pixel via the first low-level power line.

[0176] Note 23. The display defect detection method according to any one of Notes 19 to 22 further includes: supplying a data voltage to the at least one sub-pixel via the first data line, wherein the level of the data voltage is based on the comparison output.

[0177] Note 24. The display defect detection method according to any one of Notes 19 to 23, wherein a defect in the at least one sub-pixel causes the floating voltage of the particular node to increase or decrease from the initial voltage applied to the particular node.

[0178] Note 25. The display defect detection method according to any one of Notes 19 to 24, wherein, during a period when no image is displayed on the display panel, the comparison of the first input voltage with the second input voltage is performed to generate the comparison output.

Claims

1. An electroluminescent display device, comprising: The display panel includes at least one sub-pixel connected to a first data line and a first low-level power line; as well as A first comparator, connected to the at least one sub-pixel via the first data line and the first low-level power line, is configured to compare a first input voltage from the first data line with a second input voltage from the first low-level power line to generate a comparison output. Wherein, the first input voltage is a reference voltage, and The second input voltage is the voltage of a specific node of the at least one sub-pixel.

2. The electroluminescent display device according to claim 1, wherein, The reference voltage includes a first reference voltage lower than the initialization voltage and a second reference voltage higher than the initialization voltage, wherein the initialization voltage is supplied to the specific node of the at least one sub-pixel via a second switch.

3. The electroluminescent display device according to claim 2, wherein, During the detection period, the first comparator is arranged as follows: Upon receiving the first clock signal, the first reference voltage is compared with the voltage of the specific node of the at least one sub-pixel to generate a first comparison output; and Upon receiving the second clock signal, the second reference voltage is compared with the voltage of the specific node of the at least one sub-pixel to generate a second comparison output.

4. The electroluminescent display device according to claim 2 or claim 3, further comprising: A data driver is arranged to supply the first reference voltage to the first data line during a detection period, and then supply the second reference voltage to the first data line. as well as A power circuit is arranged to generate, during an initialization period prior to the detection period, the initialization voltage to be supplied to the specific node of the at least one sub-pixel via the first low-level power line.

5. The electroluminescent display device according to claim 4, further comprising: A first switch, connected between the first low-level power line and the low-level power terminal, supplies a low-level driving voltage to the specific node of the at least one sub-pixel for driving the at least one sub-pixel. The second switch is connected between the first low-level power line and the initialization power terminal to supply the initialization voltage to the specific node of the at least one sub-pixel.

6. The electroluminescent display device according to claim 5, wherein, The first switch remains in the off state during the initialization period and the detection period, and The second switch remains in the ON state during the initialization period and remains in the OFF state during the detection period.

7. The electroluminescent display device according to claim 5, wherein, The first comparator, the first switch, and the second switch are configured as follows: The source printed circuit board connected to the data driver, or Flexible circuit film, or Source integrated circuit, or The pseudo-area of ​​the display panel where no image is displayed.

8. The electroluminescent display device according to claim 5, further comprising a first plurality of sub-pixels arranged in a first column, the first plurality of sub-pixels including the at least one sub-pixel.

9. The electroluminescent display device according to claim 8, wherein, The first plurality of sub-pixels share the first comparator, the first switch, and the second switch.

10. The electroluminescent display device according to claim 8, wherein, The display panel also includes a second plurality of sub-pixels connected to a second data line and a second low-level power line; and The first comparator is connected to the second plurality of sub-pixels via the second data line and the second low-level power line. The first comparator is arranged to compare a third input voltage from the second data line with a fourth input voltage from the second low-level power line to generate another comparison output. Wherein, the third input voltage is another reference voltage, and The fourth input voltage is the voltage of a specific node of the second plurality of sub-pixels.

11. The electroluminescent display device according to claim 10, wherein, In a first mode, the first comparator is connected to the first plurality of sub-pixels, and in a second mode, the first comparator is connected to the second plurality of sub-pixels.

12. The electroluminescent display device according to claim 10, further comprising: A third switch is connected between the second low-level power line and the low-level power terminal to supply a low-level driving voltage to the specific node of the second plurality of sub-pixels for driving the second plurality of sub-pixels. The first switch is connected between the first low-level power line and the low-level power terminal to supply a low-level driving voltage for driving the first plurality of sub-pixels to the specific nodes of the first plurality of sub-pixels. The second switch is connected between each of the first low-level power line and the second low-level power line and the initialization power terminal to supply the initialization voltage to a specific node of each of the first plurality of sub-pixels and the second plurality of sub-pixels.

13. The electroluminescent display device according to claim 12, wherein, The first comparator, the first switch, the second switch, and the third switch are disposed on the source printed circuit board of the data driver, which is connected to the data driver via a flexible circuit film.

14. The electroluminescent display device according to claim 10, wherein, The second plurality of sub-pixels are arranged in the second column.

15. The electroluminescent display device according to any one of claims 1 to 3, wherein, Each sub-pixel includes: The light-emitting device is connected to a high-level power terminal at one of its electrodes and is supplied with a high-level driving voltage, which drives the at least one sub-pixel through the high-level power terminal; A driving element, comprising a gate electrode connected to a first node, a first electrode connected to another electrode of the light-emitting device, and a second electrode connected to the specific node; A switching element, connected between the data line and the first node; and A storage capacitor is connected between the first node and the specific node.

16. The electroluminescent display device according to claim 2 or claim 3, wherein, The reference voltage is a preset reference voltage, and the initialization voltage is a preset initialization voltage.

17. The electroluminescent display device according to any one of claims 1 to 3, further comprising a data driver, the data driver being arranged to supply a data voltage to the at least one sub-pixel via the first data line, wherein, The level of the data voltage is based on the comparison output.

18. The electroluminescent display device according to any one of claims 1 to 3, wherein, Defects in at least one sub-pixel cause the floating voltage of the particular node to increase or decrease from the initial voltage applied to the particular node.

19. A method for detecting display defects in an electroluminescent display device, the electroluminescent display device comprising at least one sub-pixel connected to a first data line and a first low-level power line, the method comprising: The first input voltage is received through the first data line, and the second input voltage is received through the first low-level power line; as well as The first input voltage is compared with the second input voltage to generate a comparison output. Wherein, the first input voltage is a reference voltage, and The second input voltage is the voltage of a specific node of the at least one sub-pixel.

20. The display defect detection method according to claim 19, wherein, The reference voltage includes a first reference voltage lower than the initialization voltage and a second reference voltage higher than the initialization voltage, wherein the initialization voltage is supplied to the specific node of the at least one sub-pixel via a second switch.

21. The display defect detection method according to claim 20, wherein, Comparing the first input voltage with the second input voltage to generate the comparison output includes: During the detection period, and in response to a first clock signal, the first reference voltage is compared with the voltage of the specific node of the at least one sub-pixel to generate a first comparison output; and During the detection period, and in response to a second clock signal, the second reference voltage is compared with the voltage of the specific node of the at least one sub-pixel to generate a second comparison output.

22. The display defect detection method according to claim 21, further comprising: During the initialization period prior to the detection period, the initialization voltage is supplied to the specific node of the at least one sub-pixel via the first low-level power line.

23. The display defect detection method according to any one of claims 19 to 22, further comprising: A data voltage is supplied to the at least one sub-pixel via the first data line, wherein the level of the data voltage is based on the comparison output.

24. The display defect detection method according to any one of claims 19 to 22, wherein, Defects in at least one sub-pixel cause the floating voltage of the particular node to increase or decrease from the initial voltage applied to the particular node.

25. The display defect detection method according to any one of claims 19 to 22, wherein, During periods when no image is displayed on the display panel, the first input voltage is compared with the second input voltage to generate the comparison output.

Images