Display panel and display device

Abstract

This application discloses a display panel and a display device. The display panel includes pixel circuits, each pixel circuit including a first semiconductor portion. The first semiconductor portion includes a first end and a second end. The input terminal of a first reset transistor is connected to the first end, and the input terminal of a second reset transistor is connected to the second end. A first reset line is connected to the first end, and a second reset line is connected to the second end. The first end of one pixel circuit and the second end of another pixel circuit are connected through the second semiconductor portion. A first scan line is provided, wherein the gate of the second reset transistor in one pixel circuit and the gate of the first reset transistor in another pixel circuit are connected to the first scan line. A second scan line includes a first body portion and a first branch portion connected to each other, wherein the orthographic projections of the first branch portion and the second semiconductor portion on a substrate overlap. According to the embodiments of this application, it is beneficial to improve the problem of uneven display in the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] The display panel may include pixel circuits and light-emitting elements. The driving transistors of the pixel circuits can generate driving current to drive the light-emitting elements to emit light. Before the data signal is written to the gate of the driving transistor, the gate of the driving transistor can be reset to ensure that the data signal can be written effectively; before the light-emitting stage, the first electrode (e.g., the anode) of the light-emitting element can be reset to avoid image retention problems.

[0003] The inventors discovered that different reset lines can be used to transmit different reset signals to the gate of the driving transistor and the first electrode of the light-emitting element, so as to meet the different reset requirements of the gate of the driving transistor and the first electrode of the light-emitting element.

[0004] However, when using a dual reset line design, the semiconductor parts of different pixel circuits need to be disconnected, which can easily lead to uneven display (mura) on the display panel. Summary of the Invention

[0005] This application provides a display panel and display device that helps to improve the problem of display unevenness (mura) in the display panel.

[0006] In a first aspect, embodiments of this application provide a display panel, including a substrate; pixel circuits, wherein a plurality of pixel circuits are arranged in an array on one side of the substrate in a first direction and a second direction, the first direction and the second direction intersecting; each pixel circuit includes a first semiconductor portion, the first semiconductor portion including a first end and a second end; each pixel circuit includes a first reset transistor and a second reset transistor, the input terminal of the first reset transistor being connected to the first end and the input terminal of the second reset transistor being connected to the second end; a first reset line connected to the first end; a second reset line connected to the second end; in two adjacent pixel circuits in the second direction, the first end of one pixel circuit and the second end of the other pixel circuit are connected through a second semiconductor portion; and a first scan line, in two adjacent pixel circuits in the second direction, the gate of the second reset transistor in one pixel circuit and the gate of the first reset transistor in the other pixel circuit are connected to the first scan line.

[0007] The second scan line includes a first body portion and a first branch portion that are interconnected, and the orthographic projections of the first branch portion and the second semiconductor portion on the substrate overlap.

[0008] In one possible implementation of the first aspect, the display panel includes a semiconductor layer and a multilayer conductive layer stacked on one side of a substrate;

[0009] The first reset line includes a first branch line extending along a first direction, the first branch line overlapping the orthographic projection of the first branch portion on the substrate, and at least one conductive layer between the conductive layer where the first branch line is located and the conductive layer where the first branch portion is located.

[0010] In one possible implementation of the first aspect, the display panel includes a semiconductor layer and a multilayer conductive layer stacked on one side of a substrate. The multilayer conductive layer includes a first metal layer, a second metal layer, a third metal layer, and an anode layer sequentially away from the substrate. The first reset line includes a first branch line extending along a first direction. The first branch line overlaps with the orthographic projection portion of the first branch portion on the substrate. The first branch portion is located in the first metal layer, and the first branch line is located in the anode layer.

[0011] Preferably, the patterns of two adjacent first dividing lines are different;

[0012] Preferably, the first reset line further includes a second branch line extending along the second direction, and the multiple second branch lines are interconnected with the multiple first branch lines;

[0013] Preferably, the first branch line is connected to the first end through a first crossover line.

[0014] In one possible implementation of the first aspect, the display panel includes a semiconductor layer and a multilayer conductive layer stacked on one side of a substrate;

[0015] The second reset line includes a third branch line extending along the first direction. The third branch line does not overlap with the orthographic projection of the first branch on the substrate. The conductive layer where the third branch line is located is adjacent to the conductive layer where the first branch is located.

[0016] In one possible implementation of the first aspect, the multilayer conductive layer includes a first metal layer, a second metal layer, a third metal layer, and an anode layer sequentially away from the substrate, with a first branch located in the first metal layer and a third branch located in the second metal layer;

[0017] Preferably, the second reset line further includes a fourth branch line extending along the second direction, and multiple third branches and multiple fourth branches are interconnected.

[0018] In one possible implementation of the first aspect, the first reset line includes a first branch line extending along a first direction and a second branch line extending along a second direction, wherein a plurality of second branch lines are interconnected with a plurality of first branch lines.

[0019] The second and fourth lines are located in the same film layer;

[0020] Preferably, the second and fourth dividing lines are located in the third metal layer;

[0021] Preferably, the number of second sub-lines is greater than the number of fourth sub-lines;

[0022] Preferably, a fourth branch line is provided every two second branch lines.

[0023] In one possible implementation of the first aspect, the pixel circuit includes a driving transistor and a dual-gate transistor connected to the gate of the driving transistor.

[0024] The display panel includes power lines, and the orthographic projections of the power lines and the dual-gate nodes of the dual-gate transistors on the substrate overlap at least partially.

[0025] In one possible implementation of the first aspect, the power cord includes a second body portion and a second branch portion that are interconnected.

[0026] The pixel circuit includes a threshold compensation transistor, which is a dual-gate transistor, and the second branch at least partially overlaps with the orthographic projection of the dual-gate node of the threshold compensation transistor on the substrate.

[0027] Preferably, the second body portion extends along the second direction, one column of pixel circuits corresponds to one second body portion, and the second branch portion connected to the second body portion corresponding to the j-th column of pixel circuits at least partially overlaps with the orthogonal projection of the dual gate node of the threshold compensation transistor of the j+1-th column of pixel circuits on the substrate.

[0028] Preferably, the display panel includes a semiconductor layer and a multilayer conductive layer stacked on one side of the substrate. The multilayer conductive layer includes a first metal layer, a second metal layer, and a third metal layer sequentially away from the substrate. The second body portion is located in the third metal layer, and the second branch portion is located in the second metal layer.

[0029] In one possible implementation of the first aspect, the display panel includes a light-emitting element, and the pixel circuit drives the light-emitting element to emit light;

[0030] The pixel circuit includes a driving transistor and a transistor connected to the gate of the driving transistor. The light-emitting element includes a first electrode, a light-emitting layer and a second electrode stacked together. At least a portion of the first electrode includes a third body portion and a third branch portion connected to each other. The orthogonal projections of the third branch portion and the channel of the transistor connected to the gate of the driving transistor on the substrate at least partially overlap.

[0031] Based on the same inventive concept, in a second aspect, embodiments of this application provide a display device including a display panel as described in any embodiment of the first aspect.

[0032] According to the display panel and display device provided in the embodiments of this application, since the orthographic projections of the first branch and the second semiconductor portion on the substrate overlap, the first branch and the second semiconductor portion can constitute a transistor connected between the first reset transistor of one pixel circuit and the second reset transistor of another pixel circuit. However, since the conduction level on the second scan line does not overlap with the conduction level on the first scan line in time, when the first reset transistor and / or the second reset transistor are turned on, the transistor formed by the first branch and the second semiconductor portion is turned off. Therefore, the electrical isolation of this transistor allows the second reset transistor in one row of pixel circuits to reset the light-emitting element and the first reset transistor in another row of pixel circuits to reset the gate of the driving transistor to perform simultaneously without interference. In addition, by connecting the independent first semiconductor portions in the second direction through the second semiconductor portion, the various first semiconductor portions arranged in the second direction can be continuous as a whole, which helps to avoid the problem of transistor device failure due to electrostatic discharge. Attached Figure Description

[0033] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0034] Figure 1 A top view schematic diagram of a display panel in the related art is shown;

[0035] Figure 2 A schematic diagram of an equivalent circuit of a pixel circuit in related technologies is shown;

[0036] Figure 3 This diagram illustrates another top view of a display panel in the related art.

[0037] Figure 4 This diagram illustrates another top view of a display panel in the related art.

[0038] Figure 5 This diagram illustrates another top view of a display panel in the related art.

[0039] Figure 6 This diagram illustrates another top view of a display panel in the related art.

[0040] Figure 7 This diagram illustrates another top view of a display panel in the related art.

[0041] Figure 8 A schematic diagram of a manufacturing process for a display panel in the related art is shown.

[0042] Figure 9 This illustration shows a cross-sectional structural diagram of a display panel provided in an embodiment of this application;

[0043] Figure 10 This diagram illustrates another top view of the display panel provided in an embodiment of this application.

[0044] Figure 11 This diagram shows another top view of the display panel provided in an embodiment of this application;

[0045] Figure 12 This diagram shows another top view of the display panel provided in an embodiment of this application;

[0046] Figure 13 This diagram shows another top view of the display panel provided in an embodiment of this application;

[0047] Figure 14 This diagram shows another top view of the display panel provided in an embodiment of this application;

[0048] Figure 15 This illustration shows an equivalent circuit structure diagram of the pixel circuit in a display panel provided in an embodiment of this application;

[0049] Figure 16 This illustration shows a schematic diagram of the connection of scan lines in a display panel provided in an embodiment of this application;

[0050] Figure 17a This illustration shows a timing diagram of a pixel circuit in a display panel provided in an embodiment of this application;

[0051] Figure 17b This illustration shows a timing diagram of some signals in a display panel provided in an embodiment of this application;

[0052] Figure 18 Show Figure 14 Enlarged schematic diagram of region Q1;

[0053] Figure 19 This diagram shows another top view of the display panel provided in an embodiment of this application;

[0054] Figure 20 This diagram shows another top view of the display panel provided in an embodiment of this application;

[0055] Figure 21 This illustration shows a cross-sectional structural diagram of a display panel manufacturing process according to an embodiment of this application;

[0056] Figure 22 This illustration shows another cross-sectional structure diagram of the display panel manufacturing process provided in the embodiments of this application;

[0057] Figure 23 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0058] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0059] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0060] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0061] In the embodiments of this application, the term "connection" can refer to two components being directly connected, or it can refer to two components being connected via one or more other components.

[0062] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0063] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies:

[0064] As mentioned earlier, when a display panel adopts a dual reset line design, the semiconductor parts of different pixel circuits need to be disconnected, which can easily lead to display unevenness (mura) problems on the display panel.

[0065] In order to solve the above-mentioned technical problems, the inventors of this application first studied and analyzed the root causes of the above-mentioned technical problems. The specific research and analysis process is as follows:

[0066] Figures 1 to 5 This diagram illustrates some top-view structural schematics of display panels in related technologies. (Refer to reference...) Figures 1 to 5 The pixel arrangement of the display panel can be as follows: Figure 1 The V-style RGB pixel arrangement shown is Figure 1 The black fill represents the anode of each color of the light-emitting element, where R represents the anode of the red light-emitting element, G represents the anode of the green light-emitting element, and B represents the anode of the blue light-emitting element.

[0067] It should be noted that the pixel arrangement can be the same as the arrangement of light-emitting elements. Light-emitting elements can include stacked anodes, light-emitting layers, and cathodes. The cathodes of multiple light-emitting elements in a display panel can be connected together to form a surface electrode, while the anodes of different light-emitting elements can be independent of each other. Therefore, the pixel arrangement can be the same as the arrangement of the anodes of the light-emitting elements. For example... Figure 1 As shown, in the V-style pixel arrangement, two columns of light-emitting elements constitute a repeating unit, and then multiple repeating units are arranged in an array along the first direction G and the second direction S. For example, the first direction G is the row direction, and the second direction S is the column direction. In the repeating unit, one column is arranged with green light-emitting elements, red light-emitting elements, and blue light-emitting elements, and the other column is arranged with blue light-emitting elements, green light-emitting elements, and red light-emitting elements.

[0068] It should be noted that the V-style pixel arrangement shown in the accompanying drawings of this application is merely an example and is not intended to limit this application.

[0069] The structure of the pixel circuit in the display panel can be described as follows: Figure 2As shown, the pixel circuit may include 7 transistors and 1 storage capacitor. T1 represents a driving transistor, T2 a data writing transistor, T3 a threshold compensation transistor, T4 a first reset transistor, T5 a power writing transistor, T6 a light-emitting control transistor, T7 a second reset transistor, Cst a storage capacitor, OLED a light-emitting element, EM a light-emitting control signal line, Data a data line, VDD a power line transmitting a positive voltage signal, VSS a power line transmitting a negative voltage signal, Vref1 a first reset line, Vref2 a second reset line, and S1, S2, and S3 scan lines. The display panel adopts a dual reset line (Vref) design. The signal on the first reset line Vref1 can be transmitted via the first reset transistor T4 to the gate of the driving transistor T1 and the first plate of the storage capacitor Cst. The signal on the second reset line Vref2 can be transmitted via the second reset transistor T7 to the anode of the light-emitting element OLED.

[0070] like Figures 3 to 5 As shown, multiple pixel circuits can be arrayed in a first direction G and a second direction S. Each pixel circuit may include a first semiconductor portion 11. The first semiconductor portion 11 may include a portion forming the active layer of each transistor in the pixel circuit, and a portion connecting the active layers of adjacent transistors. The material of the first semiconductor portion 11 may include pSi. In related technologies, in order to ensure that the pixel circuit can work normally under a dual reset line (Vref) design, the first semiconductor portion 11 of each pixel circuit needs to be broken in the second direction S, that is, the first semiconductor portion 11 of each pixel circuit is independent of each other in the second direction S.

[0071] In addition, such as Figure 6 As shown, if the first semiconductor sections 11 (pSi) of each pixel circuit are connected along the first direction G using connecting traces, it will cause inconsistencies in the environment of the green sub-pixels (G pixels), resulting in display unevenness (Mura). Therefore, the first semiconductor sections 11 (pSi) of each pixel circuit need to be broken along the first direction G. Taking the first direction G as a row orientation as an example, the inconsistency in the environment of the green sub-pixels (G pixels) means that the relative positions of the connecting traces corresponding to adjacent green sub-pixels (G pixels) in the same row are different. For example, the connecting trace corresponding to the first green sub-pixel (G pixel) is on its upper side, while the connecting trace corresponding to the second green sub-pixel (G pixel) is on its lower side.

[0072] Through extensive production practice, the inventors discovered that with the independent design of the first semiconductor section 11 of each pixel circuit, such as Figure 7As shown, the end (the end can be understood as the tip) of the first semiconductor section 11 (pSi) is very prone to attracting static electricity during the manufacturing process, which eventually causes electrostatic discharge (ESD) damage to the transistors adjacent to the end (tip) of the first semiconductor section 11 (pSi), resulting in transistor device failure.

[0073] Furthermore, if the first semiconductor section 11 of each pixel circuit is designed independently, during the fabrication process of the display panel, for example in the doping process (e.g., 1700p-Doping), such as Figure 8 As shown, the support portion (PIN) of the ion implantation device generates static electricity through friction on the back side of the LTPS substrate of the display panel. The PIN is used to support the display panel. Since the device PIN is made of insulating material, it easily generates static charge through friction with the back side of the substrate. Therefore, when the two separate, a strong electric field is generated on the back side of the substrate, which induces static charge on the surface of the first semiconductor portion 11 (pSi). When the first semiconductor portion 11 (pSi) is designed independently, the induced static charge cannot be dispersed between the pSi patterns, causing changes in pSi characteristics and resulting in a shift in the threshold voltage (Vth) of the transistor.

[0074] This is because when the device PIN and the substrate come into contact, equal amounts of opposite charges are generated on the PIN and the back of the substrate. At this time, the distance between them is infinitesimally small. According to C = (εr*S) / (4π*k*d), where d is the dielectric layer thickness, d is small, so the resulting capacitance C is large. From the formula ΔU = ΔQ / C, we know that ΔU is small at this time. When the PIN and the substrate begin to separate, d increases, and C = (εr*S) / (4π*k*d) decreases. Therefore, ΔU = ΔQ / C increases sharply at this time, causing a strong electric field to be generated on the back of the substrate, which causes pSi to fail, resulting in a shift in the Vth of the transistor device and making it prone to Mura.

[0075] In view of the inventors’ above-mentioned research findings, the present application provides a display panel and a display device. The technical solutions of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0076] Reference Figures 9 to 15 In order to clearly show the structure of each component, Figure 10 Only the structure of the film layer containing the first semiconductor section and the second semiconductor section is shown. Figure 11 The diagram illustrates the structure of the film layers containing the first and second semiconductor sections, as well as the structure of the film layers containing the gate traces (scan lines, light emission control signal lines). Figure 12 The diagram illustrates the structure of the film layer containing the first reset line (second branch line) and the second reset line. Figure 13 The diagram illustrates the structure of the film layer containing the first reset line (first branch line and second branch line) and the second reset line. Figure 14 The diagram illustrates the structure of the semiconductor section, gate trace, first reset line (first branch line and second branch line), and the film layer containing the second reset line.

[0077] The display panel 100 may include a substrate 01 and pixel circuits 10 located on one side of the substrate 01. Multiple pixel circuits 10 may be arranged in an array along a first direction G and a second direction S. Each pixel circuit 10 may include a continuous first semiconductor portion 11. The first semiconductor portion 11 includes portions of active layers for forming each transistor of the pixel circuit 10 and portions of active layers of consecutively adjacent transistors. The first semiconductor portion 11 of a single pixel circuit is continuous. Figure 15 As shown, the pixel circuit may include a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first reset transistor T4, a second reset transistor T7, a power writing transistor T5, and a light-emitting control transistor T6. In a pixel circuit, each transistor structure includes an active layer, and the active layers of multiple transistors in a pixel circuit can be connected together to form a structure as shown below. Figure 10 and Figure 11 The patterned first semiconductor section 11 is shown.

[0078] Each pixel circuit 10 has a first semiconductor section 11 including a first end N1 and a second end N2. The input terminal of a first reset transistor T4 is connected to the first end N1, and a first reset line Vref1 is also connected to the first end N1. It is understood that when the first reset transistor T4 is turned on, it can transmit a first reset signal on the first reset line Vref1 to the gate g1 of the driving transistor T1 and the first plate c1 of the storage capacitor Cst. The input terminal of a second reset transistor T7 is connected to the second end N2, and a second reset line Vref2 is also connected to the second end N2. It is understood that when the second reset transistor T7 is turned on, it can transmit a second reset signal on the second reset line Vref2 to the anode of the light-emitting element.

[0079] For example, such as Figure 11 As shown, the first end N1 and the second end N2 in the same pixel circuit can be located on opposite sides of the driving transistor T1 in the second direction S.

[0080] In two adjacent pixel circuits in the second direction S, the first end of one pixel circuit and the second end of the other pixel circuit can be connected by the second semiconductor section 12.

[0081] In two adjacent pixel circuits along the second direction S, the gate of the second reset transistor in one pixel circuit and the gate of the first reset transistor in the other pixel circuit are connected to the first scan line. As an example, the first direction G is the row direction, and the second direction S is the column direction. The first end N1 of the (i+1)th row pixel circuit and the second end N2 of the i-th row pixel circuit in the same column are connected via a second semiconductor section 12. The first semiconductor section 11 and the second semiconductor section 12 are located in the same film layer and can be made of the same material; that is, the first semiconductor section 11 and the second semiconductor section 12 can be directly connected. For example, the materials of both the first semiconductor section 11 and the second semiconductor section 12 include pSi.

[0082] The gate of the first reset transistor T4 in the (i+1)th row pixel circuit and the gate of the second reset transistor T7 in the i-th row pixel circuit can be connected to the same scan line. In the accompanying drawings of this application, the scan line connected to the gate of the second reset transistor T7 in the i-th row pixel circuit is marked as S3(i), the scan line connected to the gate of the first reset transistor T4 in the i-th row pixel circuit is marked as S1(i), and the scan line connected to the gate of the first reset transistor T4 in the (i+1)th row pixel circuit is marked as S1(i+1). The scan line S3(i) and the scan line S1(i+1) are the same scan line. For example, the scan line S3(i) and the scan line S1(i+1) can be called the first scan line.

[0083] The gate of the data writing transistor T2 and the gate of the threshold compensation transistor T3 can be connected to the second scan line. In the accompanying drawings of this application, the second scan line connected to the i-th row pixel circuit is marked as S2(i), and the second scan line connected to the i+1-th row pixel circuit is marked as S2(i+1).

[0084] like Figure 11 As shown, the second scan line S2(i) / S2(i+1) may include a first body portion 21 and a first branch portion 22 connected to each other, and the orthographic projections of the first branch portion 22 and the second semiconductor portion 12 on the substrate overlap. It is understood that the conduction level on the second scan line may not overlap with the conduction level on the first scan line in time. Within one frame, the start time of the conduction level on the second scan line may be after the end time of the conduction level on the first scan line.

[0085] For example, each row of pixel circuits may be connected to a first scan line and a second scan line. In the embodiments of this application, the first scan line and the second scan line may refer to the scan lines connected to the same row of pixel circuits.

[0086] For example, the extension directions of the first body portion 21 and the first branch portion 22 of the second scan line may intersect. For instance, the first body portion 21 may extend along a first direction G, and the first branch portion 22 may extend along a second direction S. The extension direction of the first body portion 21 is the same as the extension direction of the first scan line. The first body portion 21 overlaps with the first semiconductor portion 11, which can constitute a portion of the transistors in the pixel circuit. For example, the overlap of the first body portion 21 and the first semiconductor portion 11 can constitute a transistor T2 in the pixel circuit that controls the writing of data signals.

[0087] In the embodiments of this application, such as Figure 11 As shown, due to the overlap of the orthographic projections of the first branch 22 and the second semiconductor portion 12 on the substrate, as Figure 15 As shown, the overlapping of the first branch 22 and the second semiconductor section 12 constitutes a transistor Tx, wherein the overlapping portion of the first branch 22 and the second semiconductor section 12 serves as the gate of the transistor Tx, and the second semiconductor section 12 serves as the active layer of the transistor Tx. However, since the conduction level on the second scan line does not overlap with the conduction level on the first scan line in time, when the first reset transistor T4 and / or the second reset transistor T7 are turned on, the transistor Tx is turned off. Therefore, the electrical isolation of the transistor Tx allows the second reset transistor T7 in the i-th row pixel circuit to reset the light-emitting element and the first reset transistor T4 in the i+1-th row pixel circuit to reset the gate of the driving transistor T1 to be performed simultaneously without interference. In addition, by connecting the independent first semiconductor sections 11 in the second direction through the second semiconductor section 12, the various first semiconductor sections 11 arranged in the second direction can be continuous as a whole, which helps to avoid the problem of transistor device failure due to electrostatic discharge.

[0088] For example, such as Figure 16 As shown, the display panel may include a scan driving circuit that generates a scan signal and transmits it to the pixel circuit 10 via scan lines. The scan driving circuit may include cascaded multi-stage shift register units.

[0089] For example, the pixel circuit in the i-th row can be connected to the output of the (p-1)-th level shift register unit VSR(p-1) via the first scan line S1(i), the pixel circuit in the i-th row can be connected to the output of the p-th level shift register unit VSR(p) via the second scan line S2(i), and the pixel circuit in the i-th row can be connected to the output of the p-th level shift register unit VSR(p) via the third scan line S3(i).

[0090] The pixel circuit in row i+1 can be connected to the output of the p-th level shift register unit VSR(p) via the first scan line S1(i+1), the pixel circuit in row i+1 can be connected to the output of the p+1 level shift register unit VSR(p+1) via the second scan line S2(i+1), and the pixel circuit in row i+1 can be connected to the output of the p+1 level shift register unit VSR(p+1) via the third scan line S3(i+1).

[0091] The scan signals on scan lines S2(i), S3(i), and S1(i+1) are the same.

[0092] like Figure 17a As shown, the operation of the pixel circuit can include a reset phase and a data writing phase, where t1(i) represents the reset phase of the i-th row pixel circuit, t2(i) represents the data writing phase of the i-th row pixel circuit, t1(i+1) represents the reset phase of the (i+1)-th row pixel circuit, and t2(i+1) represents the data writing phase of the (i+1)-th row pixel circuit.

[0093] During the reset phase t1(i), the reset signal on the first reset line Vref1 can be transmitted to the gate of the driving transistor T1 in the i-th row pixel circuit. During the data writing phase t2(i), the data signal on the data line Data can be transmitted to the gate of the driving transistor T1 in the i-th row pixel circuit, and the reset signal on the second reset line Vref2 can be transmitted to the anode of the light-emitting element connected to the i-th row pixel circuit.

[0094] The data writing phase t2(i) of the i-th row pixel circuit overlaps with the reset phase t1(i+1) of the (i+1)-th row pixel circuit.

[0095] During the reset phase t1(i+1), the reset signal on the first reset line Vref1 can be transmitted to the gate of the driving transistor T1 in the (i+1)th row pixel circuit. During the data writing phase t2(i+1), the data signal on the data line Data can be transmitted to the gate of the driving transistor T1 in the (i+1)th row pixel circuit, and the reset signal on the second reset line Vref2 can be transmitted to the anode of the light-emitting element connected to the (i+1)th row pixel circuit.

[0096] As an example, such as Figure 17bAs shown, G:N-1, G:N, and G:N+1 represent the scan signals on the scan lines connected to the pixel circuits in rows (N-1), N, and N+1, respectively. The display panel may include a DeMux circuit, which may include two switches controlled by control signals MUX1 and MUX2, respectively. Source represents the data signal output from the data signal terminal connected to the input terminal of the DeMux circuit, and R, G, and B represent the data signals corresponding to the red, green, and blue light-emitting elements, respectively. For example, the scan signal output by the Nth-level shift register unit VSR can simultaneously control the data writing (also known as Data Writing to Cst) and the anode initialization (or coated initialization) of the Nth-row pixel circuit, as well as the gate reset (also known as the storage capacitor reset, Cst initialization) of the driving transistor T1 of the N+1th-row pixel circuit. Therefore, when the anode initialization of the Nth-row pixel circuit and the storage capacitor initialization (Cst initialization) of the N+1th-row pixel circuit occur, the N+1th-level shift register unit VSR is turned off, meaning the signal output by the N+1th-level shift register unit VSR cannot turn on the transistor it controls. Consequently, the transistor Tx controlled by the first branch of the second scan line S2 connected to the N+1th-row pixel circuit is off, allowing the storage capacitor initialization (Cst initialization) and the anode initialization (Ast initialization) of the N+1th-row pixel circuit to occur independently without interference.

[0097] Figure 17b The diagram shows a low level when the control signals MUX1 and MUX2 are on. When these signals are on, the switches in the DeMux circuit controlled by MUX1 and MUX2 are turned on, and the data signal is transmitted to the data line through the switches in the DeMux circuit (which can be called Source Writing to Data).

[0098] In this application, reset can also be referred to as initialization.

[0099] like Figure 9As shown, the display panel 100 may include a semiconductor layer B and multiple conductive layers stacked on one side of the substrate 01, with an insulating layer disposed between adjacent conductive layers. Multiple pixel circuits are formed on the semiconductor layer B and the multiple conductive layers. For example, a first semiconductor portion 11 and a second semiconductor portion 12 of the pixel circuit are located on the semiconductor layer B. The multiple conductive layers may include a first metal layer M1, a second metal layer M2, a third metal layer M3, and an anode layer Anode, sequentially located away from the substrate. Scan lines and light-emitting control signal lines may be disposed on the first metal layer M1. The second metal layer M2, the third metal layer M3, and the anode layer Anode may be used to dispose of other signal lines or components.

[0100] like Figures 12 to 14 As shown, the first reset line Vref1 may include a first branch line Vref11 extending along the first direction G. (See reference...) Figure 14 and Figure 18 The orthographic projections of the first dividing line Vref11 and the first branch 22 on the substrate can partially overlap. Both the first body portion 21 and the first branch portion 22 of the second scan line can be disposed in the first metal layer M1. The inventors have discovered that if the first dividing line Vref11 is disposed in the second metal layer M2, a large parasitic capacitance will form between the first dividing line Vref11 and the second scan line, leading to an increase in the capacitive load of the second scan line and affecting the operation of the pixel circuit.

[0101] For example, at least one conductive layer may be spaced between the conductive layer containing the first branch line Vref11 and the conductive layer containing the first branch portion 22. As described above, an insulating layer is provided between adjacent conductive layers. In the thickness direction of the display panel, the more conductive layers are spaced between the first branch line Vref11 and the first branch portion 22, the more insulating layers will be between them. This helps to avoid the formation of a large parasitic capacitance between the first branch line Vref11 and the second scan line, thereby helping to improve the problem of increased loading of the second scan line.

[0102] like Figure 9 As shown, a gate insulating layer GI may be disposed between the first metal layer M1 and the semiconductor layer B; a capacitor insulating layer CI may be disposed between the second metal layer M2 and the first metal layer M1; an interlayer dielectric layer ILD may be disposed between the third metal layer M3 and the second metal layer M2; and a planarization layer PLA may be disposed between the anode layer and the third metal layer M3. Additionally, the display panel may also include a first buffer layer (buffer1), a second buffer layer (buffer2), a pixel definition layer (PDL), a cathode layer (Cathode), and support pillars (SPC). A light-emitting layer may be disposed between the anode layer and the cathode layer (Cathode).

[0103] For example, the first branch 22 is located in the first metal layer M1, and the first branch line Vref11 can be located in the anode layer. Since the planarization layer PLA is an organic dielectric layer and is relatively thick, the parasitic capacitance between the first branch line Vref11 and the first branch 22 can be ignored. This is more conducive to avoiding the formation of a large parasitic capacitance between the first branch line Vref11 and the second scan line, thereby more conducive to improving the problem of increased loading of the second scan line.

[0104] Understandably, since the anode of the light-emitting element is located on the anode layer, the first branch line Vref11 and the anode of the light-emitting element are located on the same layer. To avoid signal crosstalk, the first branch line Vref11 should bypass the area where the anode of the light-emitting element is located. For example, if the anode arrangements of two adjacent rows of light-emitting elements are different, such as... Figures 12 to 14 As shown in any of the attached figures, the patterns of two adjacent first dividing lines Vref11 in the column direction can be different, which is beneficial for bypassing the anode region of the light-emitting element. Multiple light-emitting elements connected to the same row of pixel circuits are considered to be in the same row, and multiple light-emitting elements connected to the same column of pixel circuits are considered to be in the same column.

[0105] like Figure 13 As shown, the first reset line Vref1 may further include a second branch line Vref12 extending along the second direction S, and multiple second branch lines Vref12 and multiple first branch lines Vref11 can be interconnected. In this way, multiple second branch lines Vref12 and multiple first branch lines Vref11 form a grid structure, which helps to reduce the voltage drop of the first reset line Vref1.

[0106] As an example, the first branch line Vref11 is located on the anode layer, and the second branch line Vref12 is located on the third metal layer M3. The two can be connected by vias.

[0107] To ensure that the signal on the first branch line Vref11 located at the anode layer can be transmitted to the input terminal of the first reset transistor T4, in conjunction with reference... Figure 13 and Figure 1 The first branch line Vref11 can be connected to the input terminal of the first reset transistor T4 via the first crossover line 41. In other words, the first branch line Vref11 can be connected to the first end N1 of the first semiconductor section 11 via the first crossover line 41. The first crossover line 41 can be located in the third metal layer M3. Additionally, the first reset line Vref1 can be connected to the first end N1 of the first semiconductor section 11 via the first via h1.

[0108] like Figure 13 or Figure 14 As shown, the second reset line Vref2 may include a third branch line Vref23 extending along the first direction G. (As...) Figure 18 As shown, the orthographic projections of the third branch line Vref23 and the first branch 22 on the substrate can be non-overlapping, thus the conductive layer where the third branch line Vref23 is located and the conductive layer where the first branch 22 is located can be adjacent. Since they do not overlap, even if the metal layers where they are located are adjacent, the parasitic capacitance between them can be ignored. Furthermore, the adjacent metal layers of the two are beneficial for optimizing the overall layout of the display panel and for achieving a thinner and lighter display panel.

[0109] For example, the first branch 22 is located in the first metal layer M1, and the third branch line Vref23 may be located in the second metal layer M2.

[0110] like Figure 13 As shown, the third branch line Vref23 can be connected to the input terminal of the second reset transistor via the second crossover line 42. In other words, the third branch line Vref23 can be connected to the second end N2 of the first semiconductor section 11 via the second crossover line 42. The second crossover line 42 can be located in the third metal layer M3. Furthermore, the second crossover line 42 can be connected to the second end N2 of the first semiconductor section 11 via the second via h2.

[0111] like Figure 12 or Figure 13 As shown, the second reset line Vref2 may further include a fourth branch line Vref24 extending along the second direction S, and multiple third branch lines Vref23 and multiple fourth branch lines Vref24 are interconnected. In this way, the multiple third branch lines Vref23 and multiple fourth branch lines Vref24 form a grid structure, which helps to reduce the voltage drop of the second reset line Vref2.

[0112] like Figure 13 As shown, the first reset line Vref1 includes a first branch line Vref11 extending along the first direction G and a second branch line Vref12 extending along the second direction S. Multiple second branch lines Vref12 can be interconnected with multiple first branch lines Vref11. The second reset line Vref2 includes a third branch line Vref23 extending along the first direction G and a fourth branch line Vref24 extending along the second direction S. Multiple third branch lines Vref23 and multiple fourth branch lines Vref24 are interconnected. In other words, both the first reset line Vref1 and the second reset line Vref2 can have a mesh-like structure.

[0113] For example, since the second branch line Vref12 and the fourth branch line Vref24 extend in the same direction and do not intersect, the second branch line Vref12 and the fourth branch line Vref24 can be located in the same film layer, which is beneficial to the thinner and lighter design of the display panel.

[0114] For example, the second branch line Vref12 and the fourth branch line Vref24 are located in the third metal layer M3.

[0115] For example, each row of pixel circuits can be configured with a first sub-line Vref11 and a third sub-line Vref23. As described above, the first sub-line Vref11 can be located in the anode layer. Since the resistance of the anode layer is relatively large, in order to make the overall resistance of the first reset line Vref1 and the second reset line Vref2 more consistent, the number of second sub-lines Vref12 can be greater than the number of fourth sub-lines Vref24. In this way, the grid of the first reset line Vref1 is denser than the grid of the second reset line Vref2, so as to compensate for the problem of increased resistance caused by the first sub-line Vref11 being located in the anode layer.

[0116] For example, such as Figure 13 As shown, a fourth branch line Vref24 can be set every two second branches Vref12.

[0117] like Figure 11 and Figure 15 As shown, the pixel circuit includes a driving transistor T1 and a dual-gate transistor connected to the gate of the driving transistor T1. For example, both the threshold compensation transistor T3 and the first reset transistor T4 can be dual-gate transistors. The threshold compensation transistor T3 includes a dual-gate node N3, and the first reset transistor T4 includes a dual-gate node N4. It is understood that both dual-gate nodes N3 and N4 belong to the first semiconductor section 11. Taking the threshold compensation transistor T3 as an example, the gate of the threshold compensation transistor T3 is connected to the second scan line. There is a parasitic capacitance between the second scan line and the dual-gate node N3. When the signal on the second scan line changes, the potential of the dual-gate node N3 changes, which makes it easy for leakage to occur between the gate of the driving transistor T1 and the dual-gate node N3. This is not conducive to the stability of the gate potential of the driving transistor T1 and can easily cause display flickering.

[0118] To more fully illustrate the structure of each film layer of the display panel, Figure 14 The structure of the semiconductor layer and multiple conductive layers is illustrated. To more clearly illustrate the power line VDD, Figure 13 Only a portion of the conductive layer structure is shown. For example... Figure 14 As shown, the orthographic projections of the power line VDD of the display panel and the dual-gate node of the dual-gate transistor on the substrate can overlap at least partially. This creates a parasitic capacitance between the power line VDD and the dual-gate node. Since the signal on the power line VDD is a fixed potential signal, the parasitic capacitance between the power line VDD and the dual-gate node can be used to stabilize the potential of the dual-gate node, thereby helping to stabilize the gate potential of the driving transistor T1 and improving the display flicker problem.

[0119] like Figure 13 or Figure 14 The power line VDD may include a second body portion 31 and a second branch portion 32 interconnected. The transistor connected to the gate of the driving transistor may include a threshold compensation transistor T3 and a first reset transistor T4. The threshold compensation transistor T3 may be a dual-gate transistor. The orthographic projection of the second branch portion 32 and the dual-gate node of the threshold compensation transistor T3 onto the substrate may at least partially overlap. The first reset transistor T4 may also be a dual-gate transistor, and the orthographic projection of the second body portion 31 and the dual-gate node of the first reset transistor T4 onto the substrate may at least partially overlap. In this way, the potentials of the dual-gate nodes of the threshold compensation transistor T3 and the first reset transistor T4 can be stabilized simultaneously, thereby more effectively stabilizing the gate potential of the driving transistor T1.

[0120] For example, such as Figure 14 As shown, the threshold compensation transistor T3 and the first reset transistor T4 can be connected to the gate of the driving transistor T1 through the third cross line 43, and the third cross line 43 and the second body part 31 can be located in the same film layer.

[0121] The second body portion 31 can extend along a second direction S, which can be a column direction. One column of pixel circuits corresponds to one second body portion 31. The third cross line 43 corresponding to the same column of pixel circuits is located on one side of the second body portion 31. The second branch portion 32 connected to the second body portion 31 corresponding to the j-th column of pixel circuits overlaps at least partially with the orthographic projection of the dual gate node of the threshold compensation transistor T3 of the (j+1)-th column of pixel circuits on the substrate. That is, the second branch portion 32 connected to the second body portion 31 is located on the other side of the second body portion 31. Since the third cross line 43 needs to connect the threshold compensation transistor T3 and the first reset transistor T4 through vias, the second branch portion 32 and the third cross line 43 are located on opposite sides of the second body portion 31, which avoids the second branch portion 32 intersecting with the vias connected to the third cross line 43. This is more conducive to the layout of the display panel.

[0122] For example, the second body portion 31 may be located in the third metal layer M3, and the second branch portion 32 may be located in the second metal layer M2. The third cross line 43 may be located in the third metal layer M3.

[0123] like Figure 9 As shown, the display panel includes an OLED (Light Emitting Device), and pixel circuitry drives the OLED to emit light. The OLED includes a first electrode RE, an OLED layer OL, and a second electrode CE stacked together. For example, the first electrode RE is the anode, and the second electrode CE is the cathode; the first electrode RE is located in the anode layer, and the second electrode CE is located in the cathode layer.

[0124] like Figure 15As shown, the pixel circuit includes a driving transistor T1 and transistors connected to the gate of the driving transistor T1, such as a threshold compensation transistor T3 and a first reset transistor T4 connected to the gate of the driving transistor T1. Under illumination, the transistor channel can cause changes in its characteristics, such as a shift in the transistor's threshold voltage, affecting display uniformity.

[0125] Taking the first electrode of the light-emitting element as the anode as an example, such as Figure 19 , Figure 20 As shown, R represents the anode of the red light-emitting element, G represents the anode of the green light-emitting element, and B represents the anode of the blue light-emitting element. Additionally, Figure 20 Only the film structure of the anode layer is illustrated. At least a portion of the first electrode may include a third body portion 51 and a third branch portion 52 interconnected with each other. The orthographic projection of the third branch portion 52 and the channel of the transistor connected to the gate of the driving transistor on the substrate may at least partially overlap. For example, the anode G of the green light-emitting element and the anode B of the blue light-emitting element may both include the third body portion 51 and the third branch portion 52. For example, the orthographic projection of the third branch portion 52 and the channel of the threshold compensation transistor T3 and the first reset transistor T4 on the substrate may at least partially overlap. In this way, the third branch portion 52 can block light, improving the problem of characteristic shift of the threshold compensation transistor T3 and the first reset transistor T4 due to illumination.

[0126] Understandably, the portion of the first semiconductor section 11 that overlaps with the scan line constitutes the channel of each transistor.

[0127] In addition, such as Figure 11 and Figure 13 As shown, the storage capacitor Cst may include a first plate c1 and a second plate c2. The first plate c1 and the gate g1 of the driving transistor T1 are the same component. The first plate c1 and the gate g1 of the driving transistor T1 are located in the first metal layer M1, and the second plate c2 may be located in the second metal layer M2.

[0128] For example, such as Figure 21 As shown, pSi and the first metal layer M1 film can be fabricated on substrate 01 to form a transistor structure. The pSi pattern is designed to be continuous, that is, the pSi is designed to be continuous between the second reset transistor T7 in the i-th row pixel circuit and the first reset transistor T4 in the (i+1)-th row, and the first semiconductor sections 11 of the pixel circuits in the same column are continuous through the second semiconductor sections 12.

[0129] For example, a structure such as can be formed on substrate 01 first. Figure 10 The pSi pattern shown is continuous in the second direction S. The pSi pattern includes each first semiconductor portion 11 of the pixel circuit and a second semiconductor portion 12 connecting the first semiconductor portions 11. Then, as shown... Figure 21 The diagram shows a gate insulating layer GI covering a pSi pattern. Next, a first metal layer M1 is formed on the side of the gate insulating layer GI facing away from the substrate 01. The first metal layer M1 may include, for example... Figure 11 The scan lines S1(i), S2(i), S3(i), etc., and the light emission control signal line EM(i) etc., connected to the pixel circuits of each row are shown.

[0130] Understandably, taking scan line S1(i) as an example, the overlap between the first semiconductor portion 11 and the scan line S1(i) can form a transistor. The portion of the first semiconductor portion 11 that overlaps with the scan line S1(i) is the channel of the transistor. The semiconductor on one side of the channel is the source of the transistor, and the semiconductor on the other side of the channel is the drain of the transistor. The portion of the scan line S1(i) that overlaps with the first semiconductor portion 11 is the gate of the transistor.

[0131] Next, as Figure 22 As shown, the second metal layer M2 and the third metal layer M3 are fabricated to form a pixel circuit.

[0132] Next, as Figure 9 As shown, the planarization layer PLA, the anode layer Anode, the pixel definition layer PDL, and the support pillar SPC are fabricated to form a complete array backplane.

[0133] For example, the material of the first buffer layer buffer1 may include SiNx, with a thickness of [missing information]. about.

[0134] The material of the second buffer layer, buffer2, may include SiOx, with a thickness of [missing information]. about.

[0135] The material of the gate insulating layer GI may include SiOx, with a thickness of [missing information]. about.

[0136] The material of the capacitor insulating layer CI may include SiNx, with a thickness of about.

[0137] The material of the interlayer dielectric layer (ILD) may include stacked SiOx and SiNx, wherein the SiOx thickness is [missing information]. The SiNx thickness is approximately [value missing]. about.

[0138] The planarization layer PLA can be made of organic materials and has a thickness of about 2.10 μm.

[0139] It should be noted that the transistors in the pixel circuits of this application embodiment are all illustrated as PMOS transistors. However, it is understood that the pixel circuits can also use NMOS transistors. For NMOS transistors, the on-state is high and the off-state is low. That is, when the gate of an NMOS transistor is high, its first and second terminals are connected; when the gate of an NMOS transistor is low, its first and second terminals are off. For PMOS transistors, the on-state is low and the off-state is high. That is, when the control terminal of a PMOS transistor is low, its first and second terminals are connected; when the control terminal of a PMOS transistor is high, its first and second terminals are off. In specific implementation, the gate of each transistor is used as its control electrode. Furthermore, depending on the signal and type of the gate of each transistor, its first electrode can be used as the source and its second electrode as the drain, or its first electrode can be used as the drain and its second electrode as the source. No distinction is made here. In addition, the on-level and off-level in the embodiments of the present invention are general terms. The on-level refers to any level that can turn on the transistor, and the off-level refers to any level that can turn off / turn off the transistor.

[0140] Based on the same inventive concept, this application also provides a display device, which includes the display panel provided in this application embodiment. Therefore, this display device possesses the technical features of the display panel provided in this application embodiment and can achieve the beneficial effects of the display panel provided in this application embodiment. Similarities can be found in the above description of the display panel provided in this application embodiment, and will not be repeated here.

[0141] For example, Figure 23 This diagram illustrates a structural schematic of a display device provided according to an embodiment of this application. For example... Figure 23 As shown, the display device 200 provided in the embodiments of this application includes the display panel provided in any of the above embodiments of this application. Figure 23 The embodiments use only a mobile phone as an example to illustrate the display device 200. It is understood that the display device 200 provided in the embodiments of this application can be any electronic product with display function, including but not limited to the following categories: mobile phone, television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, vehicle display, medical equipment, industrial control equipment, touch interactive terminal, etc. The embodiments of this invention do not make any special limitations in this regard.

[0142] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized by, include: Substrate; A pixel circuit, wherein a plurality of pixel circuits are arranged in an array on one side of a substrate in a first direction and a second direction, the first direction and the second direction intersecting, the pixel circuit including a first semiconductor portion, the first semiconductor portion including a first end portion and a second end portion, the pixel circuit including a first reset transistor and a second reset transistor, the input terminal of the first reset transistor being connected to the first end portion, and the input terminal of the second reset transistor being connected to the second end portion; The first reset line is connected to the first end; The second reset line is connected to the second end; In the second semiconductor section, in two adjacent pixel circuits in the second direction, the first end of one pixel circuit and the second end of the other pixel circuit are connected through the second semiconductor section. In the first scan line, in two adjacent pixel circuits in the second direction, the gate of the second reset transistor in one pixel circuit and the gate of the first reset transistor in the other pixel circuit are connected to the first scan line; The second scan line includes a first body portion and a first branch portion that are interconnected. The orthographic projections of the first branch portion and the second semiconductor portion on the substrate overlap. The overlap of the first branch portion and the second semiconductor portion constitutes a transistor Tx. Only one transistor Tx is connected between the second reset transistor of the pixel circuit in the i-th row and the first reset transistor of the pixel circuit in the (i+1)-th row. The conduction level on the second scan line does not overlap with the conduction level on the first scan line in time. The display panel includes a semiconductor layer and multiple conductive layers stacked on one side of the substrate; The first reset line includes a first branch line extending along the first direction, the first branch line overlapping the orthographic projection of the first branch portion on the substrate, and at least one conductive layer between the conductive layer where the first branch line is located and the conductive layer where the first branch portion is located.

2. The display panel according to claim 1, characterized in that, The display panel includes a semiconductor layer and multiple conductive layers stacked on one side of the substrate. The multiple conductive layers include a first metal layer, a second metal layer, a third metal layer and an anode layer sequentially away from the substrate. The first reset line includes a first branch line extending along the first direction. The first branch line overlaps with the orthographic projection of the first branch portion on the substrate. The first branch portion is located in the first metal layer and the first branch line is located in the anode layer.

3. The display panel of claim 1, wherein, The patterns of the two adjacent first dividing lines are different.

4. The display panel of claim 1, wherein, The first reset line also includes a second branch line extending along the second direction, and multiple second branches line are interconnected with multiple first branches line.

5. The display panel of claim 1, wherein, The first branch line is connected to the first end via a first crossover line.

6. The display panel of claim 1, wherein, The display panel includes a semiconductor layer and multiple conductive layers stacked on one side of the substrate, and the semiconductor layer and the multiple metal layers form a plurality of pixel circuits; The second reset line includes a third branch line extending along the first direction. The third branch line does not overlap with the orthographic projection of the first branch portion on the substrate. The conductive layer in which the third branch line is located is adjacent to the conductive layer in which the first branch portion is located.

7. The display panel according to claim 6, characterized in that, The multilayer conductive layer includes a first metal layer, a second metal layer, a third metal layer, and an anode layer, which are sequentially located away from the substrate. The first branch is located in the first metal layer, and the third branch is located in the second metal layer.

8. The display panel of claim 6, wherein, The second reset line also includes a fourth branch line extending along the second direction, and the plurality of the third branch lines are interconnected with the plurality of the fourth branch lines.

9. The display panel of claim 8, wherein, The first reset line includes a first branch line extending along the first direction and a second branch line extending along the second direction, and multiple second branch lines are interconnected with multiple first branch lines; The second branch line and the fourth branch line are located in the same film layer.

10. The display panel of claim 9, wherein, The second branch line and the fourth branch line are located in the third metal layer.

11. The display panel of claim 9, wherein, The number of the second sub-lines is greater than the number of the fourth sub-lines.

12. The display panel of claim 11, wherein, A fourth branch line is provided every two second branch lines.

13. The display panel of claim 1, wherein, The pixel circuit includes a driving transistor and a dual-gate transistor connected to the gate of the driving transistor. The display panel includes power lines, and the orthographic projections of the power lines and the dual-gate nodes of the dual-gate transistor on the substrate at least partially overlap.

14. The display panel of claim 13, wherein, The power cord includes a second body section and a second branch section that are interconnected. The pixel circuit includes a threshold compensation transistor, which is a dual-gate transistor, and the second branch at least partially overlaps with the orthographic projection of the dual-gate node of the threshold compensation transistor on the substrate.

15. The display panel of claim 14, wherein, The second body portion extends along the second direction, and one column of the pixel circuits corresponds to one second body portion. The second branch portion connected to the second body portion corresponding to the j-th column of the pixel circuits at least partially overlaps with the orthogonal projection of the dual gate node of the threshold compensation transistor of the (j+1)-th column of the pixel circuits on the substrate.

16. The display panel of claim 14, wherein, The display panel includes a semiconductor layer and multiple conductive layers stacked on one side of the substrate. The multiple conductive layers include a first metal layer, a second metal layer, and a third metal layer sequentially away from the substrate. The second body portion is located on the third metal layer, and the second branch portion is located on the second metal layer.

17. The display panel of claim 1, wherein, The display panel includes light-emitting elements, and the pixel circuit drives the light-emitting elements to emit light. The pixel circuit includes a driving transistor and a transistor connected to the gate of the driving transistor. The light-emitting element includes a first electrode, a light-emitting layer and a second electrode stacked together. At least a portion of the first electrode includes a third body portion and a third branch portion connected to each other. The orthogonal projections of the third branch portion and the channel of the transistor connected to the gate of the driving transistor on the substrate at least partially overlap.

18. A display device comprising: Includes the display panel as described in any one of claims 1 to 17.

Images