Display panel and display device

Abstract

Embodiments of the present application disclose a display panel and a display device. The display panel comprises a plurality of pixel circuits and a plurality of scan driving units. The plurality of scan driving units are arranged in the same column in a non-display area. One scan driving unit is connected to the light-emitting control end and the first control end of at least two rows of pixel circuits. The scan driving unit is used to generate a light-emitting control signal and a first scan signal, so as to provide the light-emitting control signal to the light-emitting control end of the at least two rows of pixel circuits, and provide the first scan signal to the first control end of the at least two rows of pixel circuits. The technical scheme of the embodiments of the present application helps to reduce the number of scan driving units, so as to realize a narrow frame design, thereby improving the screen-to-body ratio and optimizing the display effect.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the continuous development of display technology, people have increasingly higher requirements for the screen-to-body ratio of display panels. A display panel consists of a display area and a bezel area. The display area includes pixel circuits for driving light-emitting devices, while the bezel area contains scan driving units for providing scan signals to the pixel circuits. Currently, existing display panels have a large number of scan driving units, resulting in a large bezel area. This makes it difficult to achieve a narrow bezel design, hindering the improvement of the screen-to-body ratio and affecting the display effect. Summary of the Invention

[0003] This invention provides a display panel and display device to reduce the number of scanning driving units, which is beneficial for achieving a narrow bezel design, thereby increasing the screen-to-body ratio and optimizing the display effect.

[0004] In a first aspect, embodiments of the present invention provide a display panel having a display area and a non-display area, the display panel comprising:

[0005] A multi-row pixel circuit is located in the display area;

[0006] Multiple scanning driving units are arranged in the same column in the non-display area. One of the scanning driving units is connected to the light emission control terminal and the first control terminal of at least two rows of the pixel circuits. The scanning driving unit is used to generate a light emission control signal and a first scan signal to provide the light emission control signal to the light emission control terminal of the at least two rows of the pixel circuits, and at the same time provide the first scan signal to the first control terminal of the at least two rows of the pixel circuits.

[0007] Optionally, the time interval during which the light emission control signal is at the cutoff level covers the time interval during which the first scan signal is at the on level;

[0008] Alternatively, the scanning driving unit is used to simultaneously provide the light emission control signal to the light emission control terminal and the first control terminal of the at least two rows of the pixel circuit, the light emission control signal being multiplexed as the first scanning signal, and the conduction levels of the light emission control terminal and the first control terminal of the pixel circuit being opposite.

[0009] Optionally, one of the scanning driving units includes a light emission control signal generation circuit and an inverting module. The output terminal of the light emission control signal generation circuit is connected to the light emission control terminal of the pixel circuit and the input terminal of the inverting module. The output terminal of the inverting module is connected to the first control terminal of the pixel circuit. The light emission control signal generation circuit is used to generate the light emission control signal, and the inverting module is used to invert the light emission control signal to obtain the first scanning signal.

[0010] Optionally, one of the scanning driving units includes at least one light emission control signal generation circuit and at least one first scanning circuit. The number of light emission control signal generation circuits in each scanning driving unit is the same as the number of first scanning circuits. The output terminal of the light emission control signal generation circuit is connected to the light emission control terminal of the pixel circuit, and the output terminal of the first scanning circuit is connected to the first control terminal of the pixel circuit. The light emission control signal generation circuit is used to generate the light emission control signal, and the first scanning circuit is used to generate the first scanning signal.

[0011] Preferably, the display panel further includes a first clock signal line and a second clock signal line, the light emission control signal generation circuit and the first scanning circuit are located on the same side of the first clock signal line and the second clock signal line, and the light emission control signal generation circuit and the first scanning circuit are arranged in the same column.

[0012] Optionally, each of the light emission control signal generation circuits is cascaded, and each of the first scanning circuits is cascaded.

[0013] The output terminal of the nth light emission control signal generation circuit is connected to the light emission control terminals of the pixel circuits in rows 2n-1 and 2n, and the output terminal of the nth first scanning circuit is connected to the first control terminals of the pixel circuits in rows 2n-1 and 2n; where n is an integer greater than or equal to 1.

[0014] Preferably, the output terminal of each of the light emission control signal generation circuits is connected to the light emission control terminals of m adjacent rows of the pixel circuits, and each of the light emission control signal generation circuits is sequentially connected to the light emission control terminals of the corresponding m adjacent rows of the pixel circuits. The output terminal of each of the first scanning circuits is connected to the first control terminal of the m adjacent rows of the pixel circuits, and each of the first scanning circuits is sequentially connected to the first control terminal of the corresponding m adjacent rows of the pixel circuits; where m is an integer greater than 2.

[0015] Preferably, the light emission control signal generation circuit and the first scanning circuit are both connected to the first clock signal line and the second clock signal line. The light emission control signal generation circuit generates the light emission control signal in response to the signals on the first clock signal line and the second clock signal line, and the first scanning circuit generates the first scanning signal in response to the signals on the first clock signal line and the second clock signal line.

[0016] Preferably, the light emission control signal generation circuit and the first scanning circuit are arranged alternately in the same column; or, every two cascaded light emission control signal generation circuits and every two cascaded first scanning circuits are arranged alternately in the same column.

[0017] Optionally, the display panel further includes multiple cascaded second scanning circuits located in the non-display area. The output of the second scanning circuit is connected to the second control terminals of at least two rows of pixel circuits to provide a second scanning signal to the second control terminals of the pixel circuits.

[0018] Preferably, the waveforms and pulse timings of the second scan signal and the first scan signal are the same, the first scan circuit is multiplexed as the second scan circuit, and the first scan signal is multiplexed as the second scan signal;

[0019] Preferably, the signal waveforms of the third control terminal and the second control terminal of the pixel circuit are the same, and the pulse timing of the third control terminal is later than the pulse timing of the second control terminal. The second control terminal of the pixel circuit in the i-th row is connected to the output terminal of the i-th second scanning circuit, and the third control terminal of the pixel circuit in the i-th row is connected to the output terminal of the (i+1)-th second scanning circuit; where i is an integer greater than or equal to 1.

[0020] Optionally, one of the scanning driving units includes at least one light emission control signal generation circuit. The output terminal of the light emission control signal generation circuit is connected to the light emission control terminal and the first control terminal of the pixel circuit. The light emission control signal generation circuit is used to simultaneously provide light emission control signals to the light emission control terminal and the first control terminal of the pixel circuit. The light emission control signals are multiplexed into the first scanning signal. The transistor type in the pixel circuit that receives the light emission control signals is opposite to the transistor type that receives the first scanning signal.

[0021] Optionally, the pixel circuit includes:

[0022] A driving module, a light-emitting module, and a light-emitting control module are connected between a first power line and a second power line. The driving module is used to drive the light-emitting module. The control terminal of the light-emitting control module is the light-emitting control terminal. The light-emitting control module is used to respond to the signal of the light-emitting control terminal to control the connection or disconnection between the first power line and the second power line.

[0023] A first initialization module is connected to the first end of the light-emitting module. The control end of the first initialization module is the first control end. The first initialization module is used to respond to the signal of the first control end and write an initialization voltage to the first end of the light-emitting module.

[0024] The second initialization module is connected to the control terminal of the drive module. The control terminal of the second initialization module is a second control terminal. The second initialization module is used to respond to the signal of the second control terminal and write the initialization voltage to the control terminal of the drive module.

[0025] A data writing module is connected to the driving module. The control terminal of the data writing module is a third control terminal. The data writing module is used to respond to the signal of the third control terminal and write data voltage to the control terminal of the driving module.

[0026] Preferably, the pixel circuit further includes:

[0027] A threshold compensation module is connected between the first end and the control end of the drive module. The control end of the threshold compensation module is the third control end. The threshold compensation module is used to compensate the threshold voltage of the drive module in response to the signal of the third control end.

[0028] Preferably, when the refresh rate of the display panel is lower than a preset frequency, a display frame includes a write frame and at least one hold frame; the light emission control module responds to the signal of the light emission control terminal and controls the first power line and the second power line to be connected or disconnected in the write frame and the hold frame; the first initialization module responds to the signal of the first control terminal and writes the initialization voltage to the first terminal of the light emission module in the write frame and the hold frame.

[0029] Preferably, both the light emission control module and the first initialization module include transistors. The gate of the transistor in the light emission control module serves as the light emission control terminal, and the gate of the transistor in the first initialization module serves as the first control terminal. When the scan driving unit provides light emission control signals to the light emission control terminal and the first control terminal of the pixel circuit, one of the transistors in the light emission control module and the first initialization module is an N-type transistor, and the other is a P-type transistor.

[0030] Optionally, the threshold compensation module includes a dual-gate transistor, which is connected between the first terminal and the control terminal of the driving module;

[0031] The pixel circuit also includes:

[0032] A leakage current suppression module is connected between the initialization signal line and the dual-gate node of the dual-gate transistor. The initialization signal line is connected to an initialization voltage. The control terminal of the leakage current suppression module is the first control terminal. The leakage current suppression module is used to write the initialization voltage to the dual-gate node in response to the signal of the first control terminal to suppress leakage current at the control terminal of the driving module. The time interval during which the first control terminal is connected to the conduction level does not overlap with the time interval during which the third control terminal is connected to the conduction level.

[0033] Secondly, embodiments of the present invention provide a display device, including the display panel described in the first aspect.

[0034] The display panel and display device provided in this embodiment of the invention are configured such that each scan driving unit is connected to the light emission control terminal and the first control terminal of at least two rows of pixel circuits. Each scan driving unit can simultaneously generate a light emission control signal and a first scan signal, so that a single scan driving unit can simultaneously provide signals to the light emission control terminal and the first control terminal of at least two rows of pixel circuits. This eliminates the need to separately set two sets of scan driving units to provide signals to the light emission control terminal and the first control terminal of the pixel circuits, thereby reducing the number of scan driving units in the display panel. Furthermore, the arrangement of each scan driving unit in the same column is beneficial for achieving a narrow bezel design, thereby increasing the screen-to-body ratio of the display panel and optimizing the display effect.

[0035] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0038] Figure 2 This is a schematic diagram of the structure of a pixel circuit used in a display panel;

[0039] Figure 3 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0040] Figure 4 This is a schematic diagram illustrating the connection relationship between a scanning driving unit and a pixel circuit according to an embodiment of the present invention;

[0041] Figure 5 This is a schematic diagram illustrating the connection relationship between another scanning driving unit and pixel circuit provided in an embodiment of the present invention;

[0042] Figure 6 This is a schematic diagram illustrating the connection relationship between another scanning driving unit and pixel circuit provided in an embodiment of the present invention;

[0043] Figure 7 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0044] Figure 8 yes Figure 7 A schematic diagram showing the connection relationship between the light emission control signal generation circuit, the first scanning circuit, the second scanning circuit, and the pixel circuit in the diagram.

[0045] Figure 9 This is a schematic diagram of another pixel circuit used in display panels;

[0046] Figure 10 This is a schematic diagram of the driving timing of a pixel circuit provided in an embodiment of the present invention;

[0047] Figure 11 This is a schematic diagram illustrating the connection relationship between another scanning driving unit and pixel circuit provided in an embodiment of the present invention;

[0048] Figure 12 It is applicable Figure 11 A schematic diagram of a pixel circuit structure;

[0049] Figure 13 This is a schematic diagram of another pixel circuit used in display panels;

[0050] Figure 14 This is a schematic diagram of the driving timing of another pixel circuit provided in an embodiment of the present invention. Detailed Implementation

[0051] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0052] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0053] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a pixel circuit used in a display panel. (Combined with...) Figure 1 and Figure 2 The display panel has a display area AA and a non-display area NAA. The display panel includes multiple rows of pixel circuits 10 and multiple scan driving units 20. The pixel circuits 10 are located in the display area AA. Each scan driving unit 20 is arranged in the same column in the non-display area NAA. Each scan driving unit 20 is connected to the light-emitting control terminal EM and the first control terminal S1 of at least two rows of pixel circuits 10. The scan driving unit 20 generates a light-emitting control signal and a first scan signal to provide a light-emitting control signal to the light-emitting control terminal EM of the at least two rows of pixel circuits 10 connected to the scan driving unit 20, and simultaneously provides a first scan signal to the first control terminal S1 of the at least two rows of pixel circuits 10 connected to the scan driving unit 20.

[0054] Specifically, the display panel can be an organic light-emitting diode (OLED) display panel or a micron-scale light-emitting diode (Micro-LED) display panel, etc. The pixel circuit 10 is used to drive the light-emitting devices in the display panel to emit light. The pixel circuit 10 includes multiple operating stages, such as an initialization stage, a data writing stage, and a light-emitting stage. Figure 2The image shows the light-emitting control terminal EM and the first control terminal S1 of the pixel circuit 10. The light-emitting control terminal EM is used to control the light-emitting stage of the pixel circuit 10. The pixel circuit 10 drives the light-emitting device to emit light in response to the signal of the light-emitting control terminal EM. The first control terminal S1 is also used to control the working stage of the pixel circuit 10. For example, the first control terminal S1 is used to control the initialization stage of the pixel circuit 10. The pixel circuit 10 performs voltage initialization in response to the signal of the first control terminal S1, such as initializing the voltage of the first electrode of the light-emitting device.

[0055] The display panel also includes scan lines, and the scan driving unit 20 can be connected to the corresponding pixel circuit 10 through the scan lines. Each scan driving unit 20 is connected to the light emission control terminal EM and the first control terminal S1 of at least one row of pixel circuits 10. Figure 1 The illustration shows a scenario where each scan driving unit 20 is connected to the light-emitting control terminal EM and the first control terminal S1 of two rows of pixel circuits 10. For example, the nth scan driving unit 20 can be connected to the light-emitting control terminal EM and the first control terminal S1 of the (2n-1)th and 2nth rows of pixel circuits 10, where n is an integer greater than or equal to 1. In other embodiments, each scan driving unit 20 can also be connected to the light-emitting control terminal EM and the first control terminal S1 of two or more adjacent rows of pixel circuits 10, with each scan driving unit 20 sequentially connected to the light-emitting control terminal EM and the first control terminal S1 of the corresponding row of pixel circuits 10.

[0056] The scan driving unit 20 can simultaneously generate a light emission control signal and a first scan signal. Optionally, the time interval during which the light emission control signal is at a cutoff level covers the time interval during which the first scan signal is at a conduction level. In one embodiment, the levels of the light emission control signal and the first scan signal are completely opposite; the scan driving unit 20 can generate the light emission control signal and invert it to obtain the first scan signal. In another embodiment, when the first scan signal is at a conduction level, the light emission control signal is at a cutoff level, and when the light emission control signal is at a conduction level, the first scan signal is at a cutoff level. For example, when the first control terminal S1 is used to control the initialization phase of the pixel circuit 10, the scanning drive unit 20 provides a light emission control signal to the light emission control terminal EM of the pixel circuit 10 and a first scan signal to the first control terminal S1 of the pixel circuit 10, so that in the initialization phase, the pixel circuit 10 initializes the voltage of the first electrode of the light emission device in response to the on level in the first scan signal, and controls the light emission device not to emit light in response to the off level in the light emission control signal. In the light emission phase, the pixel circuit 10 stops initializing the voltage of the first electrode of the light emission device in response to the off level in the first scan signal, and drives the light emission device to emit light in response to the on level in the light emission control signal.

[0057] Figure 3 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. (In conjunction with...) Figure 2 and Figure 3 In another embodiment, the scan driving unit 20 is used to simultaneously provide light emission control signals to the light emission control terminals EM and S1 of at least two rows of pixel circuits 10. The light emission control signals are multiplexed into a first scan signal, and the conduction levels of the light emission control terminals EM and S1 of the pixel circuits 10 are opposite. Again, taking the initialization phase of the pixel circuits 10 controlled by the first control terminal S1 as an example, the scan driving unit 20 provides light emission control signals to the light emission control terminals EM and S1 of the pixel circuits 10, such that during the initialization phase, the level of the light emission control signal is the conduction level of the first control terminal S1 and the cutoff level of the light emission control terminal EM. The pixel circuits 10 initialize the voltage of the first electrode of the light-emitting device in response to the light emission control signal and control the light-emitting device to not emit light in response to the light emission control signal. During the light emission phase, the level of the light emission control signal is the cutoff level of the first control terminal S1 and the conduction level of the light emission control terminal EM. The pixel circuits 10 stop initializing the voltage of the first electrode of the light-emitting device in response to the light emission control signal and drive the light-emitting device to emit light in response to the light emission control signal.

[0058] It should be noted that the first control terminal S1 is not limited to the control terminal for the initialization stage of the pixel circuit 10. The first control terminal S1 can also be the control terminal for other working stages of the pixel circuit 10. Any control terminal in the pixel circuit 10 that satisfies the signal level relationship in the above embodiment can be used as the first control terminal S1. This embodiment does not limit this.

[0059] In summary, the technical solution of this invention involves configuring each scanning driving unit to connect to the light-emitting control terminal and the first control terminal of at least two rows of pixel circuits. Each scanning driving unit can simultaneously generate a light-emitting control signal and a first scanning signal, thereby providing signals to the light-emitting control terminal and the first control terminal of at least two rows of pixel circuits simultaneously through one scanning driving unit. This eliminates the need for two separate sets of scanning driving units to provide signals to the light-emitting control terminal and the first control terminal of the pixel circuits, reducing the number of scanning driving units in the display panel. Furthermore, the arrangement of each scanning driving unit in the same column facilitates a narrow bezel design, thereby increasing the screen-to-body ratio of the display panel and optimizing the display effect.

[0060] Based on the above embodiments, there are various specific structures for the scanning drive unit, and each scanning drive unit can be connected to the pixel circuit in various ways. Several of these methods will be used as examples for explanation below.

[0061] Figure 4This is a schematic diagram illustrating the connection relationship between a scan driving unit and a pixel circuit according to an embodiment of the present invention. Only four rows of pixel circuits 10 and their corresponding scan driving units 20 are shown in the display panel, with only one pixel circuit 10 shown in each row. In one embodiment, see... Figure 4 A scanning driving unit 20 includes a light emission control signal generation circuit 210 and an inverting module 220. The output terminal O1 of the light emission control signal generation circuit 210 is connected to the light emission control terminal EM of the pixel circuit 10 and the input terminal of the inverting module 220. The output terminal of the inverting module 220 is connected to the first control terminal S1 of the pixel circuit 10. The light emission control signal generation circuit 210 is used to generate a light emission control signal, and the inverting module 220 is used to invert the light emission control signal to obtain a first scanning signal.

[0062] Specifically, each light-emitting control signal generation circuit 210 is cascaded. The light-emitting control signal generation circuit 210 is used to shift the timing of the pulse signal input to its own input terminal EIN to obtain the light-emitting control signal, and provides the light-emitting control signal to the light-emitting control terminal EM of the corresponding pixel circuit 10 through its own output terminal O1. The input terminal EIN of the first light-emitting control signal generation circuit 210 inputs a start signal. In two consecutive light-emitting control signal generation circuits 210, the output terminal O1 of the first light-emitting control signal generation circuit 210 is connected to the input terminal EIN of the second light-emitting control signal generation circuit 210, so that the light-emitting control signal output by the first light-emitting control signal generation circuit 210 is used as the input signal of the second light-emitting control signal generation circuit 210, so that each light-emitting control signal generation circuit 210 outputs the light-emitting control signal with the timing shifted sequentially.

[0063] Optionally, the inverter module 220 includes an inverter, the input terminal of which is connected to the output terminal O1 of the corresponding light emission control signal generation circuit 210, and the output terminal of which is connected to the first control terminal S1 of the corresponding pixel circuit 10.

[0064] In each scan driving unit 20, the light emission control signal generation circuit 210 and the inverting module 220 are connected to the light emission control terminal EM and the first control terminal S1 of at least one row of pixel circuits 10. Taking the same order of the light emission control signal generation circuit 210 and the inverting module 220 in the same scan driving unit 20 as an example, when each scan driving unit 20 is connected to one row of pixel circuits 10, the output terminal O1 of the nth light emission control signal generation circuit 210 is connected to the light emission control terminal EM of the nth row of pixel circuits 10 and the input terminal of the nth inverting module 220, and the output terminal of the nth inverting module 220 is connected to the first control terminal S1 of the nth row of pixel circuits 10, thereby driving one row of pixel circuits 10 through a set of light emission control signal generation circuits 210 and inverting modules 220. Figure 4As shown, when each scan driving unit 20 is connected to two rows of pixel circuits 10, the output terminal O1 of the nth light emission control signal generation circuit 210 is connected to the light emission control terminal EM of the (2n-1)th and 2nth row pixel circuits 10 and the input terminal of the nth inverting module 220. The output terminal of the nth inverting module 220 is connected to the first control terminal S1 of the (2n-1)th and 2nth row pixel circuits 10, thereby enabling the simultaneous driving of two rows of pixel circuits 10 through a set of light emission control signal generation circuits 210 and inverting modules 220. Here, n is an integer greater than or equal to 1.

[0065] Similarly, when each scanning driving unit 20 is connected to m rows of pixel circuits 10, and m is an integer greater than 2, the output terminal O1 of the nth light emission control signal generation circuit 210 is connected to the light emission control terminal EM of the m adjacent pixel circuits 10 and the input terminal of the nth inverting module 220. The output terminal of the nth inverting module 220 is connected to the first control terminal S1 of the m adjacent pixel circuits 10. Each light emission control signal generation circuit 210 is sequentially connected to the light emission control terminal EM of the corresponding m adjacent pixel circuits 10, and each inverting module 220 is sequentially connected to the first control terminal S1 of the corresponding m adjacent pixel circuits 10, so as to realize that the m rows of pixel circuits 10 are driven simultaneously by a set of light emission control signal generation circuits 210 and inverting modules 220.

[0066] The technical solution of this invention provides a light-emitting control signal to the pixel circuit 10 through a light-emitting control signal generation circuit 210, and obtains a first scan signal by inverting the light-emitting control signal through an inverting module 220 and providing it to the pixel circuit 10. This eliminates the need for an additional set of cascaded scan driving units to generate the first scan signal, which helps to reduce the number of scan driving units in the display panel. When each set of light-emitting control signal generation circuit 210 and inverting module 220 is used to drive two or more rows of pixel circuits 10, the number of light-emitting control signal generation circuits 210 and inverting modules 220 can be further reduced, which is beneficial for achieving a narrow bezel design, thereby increasing the screen ratio of the display panel and optimizing the display effect.

[0067] Figure 4 The illustration shows the case where the light emission control signal generation circuit 210 and the inverting module 220 in the same scan driving unit 20 are arranged side by side along the row direction of the pixel circuit 10. In other embodiments, the light emission control signal generation circuit 210 and the inverting module 220 in the same scan driving unit 20 can also be arranged along the column direction of the pixel circuit 10. Each light emission control signal generation circuit 210 and the inverting module 220 can be arranged in the same column, and the light emission control signal generation circuit 210 and the inverting module 220 can appear alternately to further reduce the area occupied by the light emission control signal generation circuit 210 and the inverting module 220 in the non-display area NAA.

[0068] Figure 5 This is a schematic diagram illustrating the connection relationship between another scanning driving unit and pixel circuit provided in an embodiment of the present invention. In another embodiment, see... Figure 5 A scanning driving unit 20 includes at least one light emission control signal generation circuit 210 and at least one first scanning circuit 230. The number of light emission control signal generation circuits 210 and the number of first scanning circuits 230 in each scanning driving unit 20 are the same. The output terminal of the light emission control signal generation circuit 210 is connected to the light emission control terminal EM of the pixel circuit 10, and the output terminal of the first scanning circuit 230 is connected to the first control terminal S1 of the pixel circuit 10. The light emission control signal generation circuit 210 is used to generate a light emission control signal, and the first scanning circuit 230 is used to generate a first scanning signal.

[0069] Specifically, each of the first scanning circuits 230 is cascaded. Each first scanning circuit 230 shifts the timing of the pulse signal input to its input terminal SIN1 to obtain a first scanning signal, and provides this first scanning signal to the first control terminal S1 of the corresponding pixel circuit 10 through its output terminal O2. The first first scanning circuit 230 inputs a start signal to its input terminal SIN1. In two consecutive first scanning circuits 230, the output terminal O1 of the preceding first scanning circuit 230 is connected to the input terminal SIN1 of the following first scanning circuit 230, so that the first scanning signal output by the preceding first scanning circuit 230 is used as the input signal of the following first scanning circuit 230, causing each first scanning circuit 230 to output a first scanning signal with its timing shifted sequentially.

[0070] In this embodiment, each scanning drive unit 20 includes a light emission control signal generation circuit 210 and a first scanning circuit 230, which are connected to the light emission control terminal EM and the first control terminal S1 of at least two rows of pixel circuits 10. (See also...) Figure 5 Optionally, in one embodiment, the output terminal O1 of the nth light emission control signal generation circuit 210 is connected to the light emission control terminal EM of the (2n-1)th and (2n-2)th row pixel circuits 10, and the output terminal O2 of the nth first scanning circuit 230 is connected to the first control terminal S1 of the (2n-1)th and (2n-2)th row pixel circuits 10. Here, n is an integer greater than or equal to 1.

[0071] By providing light-emitting control signals to the light-emitting control terminals EM of the two adjacent rows of pixel circuits 10 through each light-emitting control signal generation circuit 210, and providing first scanning signals to the first control terminals S1 of the two adjacent rows of pixel circuits 10 through each first scanning circuit 230, the total number of light-emitting control signal generation circuits 210 and the total number of first scanning circuits 230 in the display panel can be halved. This helps to reduce the bezel area occupied by the light-emitting control signal generation circuits 210 and the first scanning circuits 230, thus achieving a narrow bezel design.

[0072] In other embodiments, the output terminal of each light-emitting control signal generation circuit 210 can be connected to the light-emitting control terminal EM of m adjacent rows of pixel circuits 10. Each light-emitting control signal generation circuit 210 is sequentially connected to the light-emitting control terminal EM of its corresponding m adjacent rows of pixel circuits 10. The output terminal of each first scanning circuit 230 is connected to the first control terminal S1 of m adjacent rows of pixel circuits 10. Each first scanning circuit 230 is sequentially connected to the first control terminal S1 of its corresponding m adjacent rows of pixel circuits 10. Here, m is an integer greater than 2. For example, the value of m can be 3 or 4, etc., so as to enable more rows of pixel circuits to work simultaneously through each light-emitting control signal generation circuit 210 and each first scanning circuit 230, thereby further reducing the number of light-emitting control signal generation circuits 210 and first scanning circuits 230 in the display panel, and thus reducing the bezel area occupied by the light-emitting control signal generation circuits 210 and first scanning circuits 230.

[0073] See Figure 5 Optionally, based on the above embodiments, the display panel further includes a first clock signal line 410 and a second clock signal line 420. Both the light emission control signal generation circuit 210 and the first scanning circuit 230 are connected to the first clock signal line 410 and the second clock signal line 420. The light emission control signal generation circuit 210 generates a light emission control signal in response to signals on the first clock signal line 410 and the second clock signal line 420, and the first scanning circuit 230 generates a first scanning signal in response to signals on the first clock signal line 410 and the second clock signal line 420.

[0074] Specifically, the first clock signal terminal ECK1 and the second clock signal terminal ECK2 of the light emission control signal generation circuit 210 are respectively connected to the corresponding first clock signal line 410 or second clock signal line 420. The first clock signal terminal ECK1 and the second clock signal terminal ECK2 of the first scanning circuit 230 are respectively connected to the corresponding first clock signal line 410 or second clock signal line 420. The first clock signal line 410 receives the first clock signal, and the second clock signal line 420 receives the second clock signal. Both the first and second clock signals are clock signals that alternate between high and low levels, and their pulse timings are different. The display panel also includes a first start signal line 430 and a second start signal line 440. The first start signal line 430 receives the first start signal, and the second start signal line 440 receives the second start signal. Both the first and second start signals are pulse signals, and their pulse widths can be the same or different. The input terminal EIN of the first light emission control signal generation circuit 210 is connected to the first start signal line 430, and the input terminal SIN1 of the first scanning circuit 230 is connected to the second start signal line 440. The light emission control signal generation circuit 210 responds to the signals on the first clock signal line 410 and the second clock signal line 420 by shifting the timing of the pulse signal input at its input terminal EIN to obtain the light emission control signal. The first scanning circuit 230 responds to the signals on the first clock signal line 410 and the second clock signal line 420 by shifting the timing of the pulse signal input at its input terminal SIN1 to obtain the first scanning signal.

[0075] In this embodiment, the light emission control signal generation circuit 210 and the first scanning circuit 230 share a set of first clock signal lines 410 and second clock signal lines 420. This eliminates the need to provide two separate sets of clock signals to the light emission control signal generation circuit 210 and the first scanning circuit 230, thereby reducing the number of signal lines in the display panel and eliminating the need to generate additional clock signals, which helps to reduce power consumption.

[0076] See Figure 5Optionally, the light-emitting control signal generation circuit 210 and the first scanning circuit 230 are located on the same side of the first clock signal line 410 and the second clock signal line 420, and are arranged in the same column. Compared with the scheme where the light-emitting control signal generation circuit 210 and the first scanning circuit 230 are located on opposite sides of the first clock signal line 410 and the second clock signal line 420, by arranging the light-emitting control signal generation circuit 210 and the first scanning circuit 230 on the same side of the first clock signal line 410 and the second clock signal line 420 in the same column, the two sets of circuits, the light-emitting control signal generation circuit 210 and the first scanning circuit 230, only occupy the area required by one cascaded scanning circuit, thereby reducing the bezel area occupied by both and achieving a narrow bezel design.

[0077] Furthermore, the light emission control signal generation circuit 210 and the first scanning circuit 230 can be arranged alternately in the same column. For example, the light emission control signal generation circuits 210 driving the pixel circuits 10 from the first row to the last row are arranged sequentially, and the first scanning circuits 230 driving the pixel circuits 10 from the first row to the last row are arranged sequentially, with the first scanning circuits 230 interspersed between adjacent light emission control signal generation circuits 210, so that the light emission control signal generation circuits 210 and the first scanning circuits 230 are arranged alternately in the same column. The advantage of this arrangement is that it facilitates the connection of the light emission control signal generation circuits 210 and the first scanning circuits 230 to the corresponding pixel circuits 10.

[0078] Figure 6 This is a schematic diagram illustrating the connection relationship between another scanning driving unit and pixel circuit provided in an embodiment of the present invention. See also... Figure 6 In another embodiment, the light emission control signal generation circuits 210 and the first scanning circuits 230 cascaded together can be arranged alternately in the same column. For example, the light emission control signal generation circuits 210 driving the pixel circuits 10 from the first row to the last row are arranged sequentially, the first scanning circuits 230 driving the pixel circuits 10 from the first row to the last row are arranged sequentially, and two first scanning circuits 230 are provided every two light emission control signal generation circuits 210. Figure 6 Only the connection relationship between the first four light emission control signal generation circuits 210 and the first scanning circuit 230 and the first four rows of pixel circuits 10 is shown. In the remaining light emission control signal generation circuits 210 and the first scanning circuit 230, every four light emission control signal generation circuits 210 and the first scanning circuit 230 form a cycle. The arrangement of the light emission control signal generation circuits 210 and the first scanning circuit 230 in each group, as well as their connection relationship with the pixel circuits 10, can be referred to the first four light emission control signal generation circuits 210 and the first scanning circuit 230.

[0079] Figure 7 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention; Figure 8 yes Figure 7 A schematic diagram showing the connection relationship between the light emission control signal generation circuit, the first scanning circuit, the second scanning circuit, and the pixel circuit. (Combined with...) Figure 7 and Figure 8 The display panel also includes multiple cascaded second scanning circuits 240. The second scanning circuits 240 are located in the non-display area NAA. The output terminal O3 of the second scanning circuit 240 is connected to the second control terminal S2 of at least two rows of pixel circuits 10, and is used to provide a second scanning signal to the second control terminal S2 of the pixel circuits 10.

[0080] Optionally, the display panel also includes a third clock signal line 450, a fourth clock signal line 460, and a third start signal line 470. The third clock signal line 450 receives a third clock signal, and the fourth clock signal line 460 receives a fourth clock signal. Both the third and fourth clock signals are clock signals that alternate between high and low levels, and their pulse timings are different. The first clock signal terminal SCK1 and the second clock signal terminal SCK2 of the second scanning circuit 240 are respectively connected to the corresponding third clock signal line 450 or fourth clock signal line 460. The third start signal line 470 receives a third start signal, which is a pulse signal. The second scanning circuit 240 can respond to the signals from the third clock signal line 450 and the fourth clock signal line 460 by shifting the timing of the pulse signal input to its own input terminal SIN2 to obtain a second scan signal, and then providing the second scan signal to the second control terminal S2 of the corresponding pixel circuit 10 through its own output terminal O3. The input terminal SIN2 of the first second scan circuit 240 is connected to the third start signal line 470. In two consecutive second scan circuits 240, the output terminal O3 of the previous second scan circuit 240 is connected to the input terminal SIN2 of the next second scan circuit 240, so that the second scan signal output by the previous second scan circuit 240 is used as the input signal of the next second scan circuit 240, so that each second scan circuit 240 outputs the second scan signal with the timing shifted sequentially.

[0081] The second control terminal S2 is also used to control the working phase of the pixel circuit 10. For example, the pixel circuit 10 initializes the gate voltage of the driving transistor in response to the signal of the second control terminal S2. Figure 7 and Figure 8The illustration shows a case where the output terminal O3 of the second scanning circuit 240 is connected to the second control terminal S2 of a row of pixel circuits 10. In other embodiments, the output terminal O3 of the second scanning circuit 240 can also be connected to the second control terminals S2 of two or more rows of pixel circuits 10, so as to drive at least two rows of pixel circuits 10 through the same second scanning circuit 240, thereby reducing the number of second scanning circuits 240 and facilitating the implementation of a narrow bezel design.

[0082] In another embodiment, when the waveform and pulse timing of the second scan signal are the same as those of the first scan signal, the first scan circuit 230 can be multiplexed into the second scan circuit 240 to multiplex the first scan signal into the second scan signal. For example, Figure 5 and Figure 6 Each of the first scanning circuits 230 can be reused as a second scanning circuit 240. Each first scanning circuit 230, while connected to the first control terminal S1 of the pixel circuit 10 in the corresponding row, can also be connected to the second control terminal of the pixel circuit 10 in the corresponding row. Figure 5 and Figure 6 (Not shown in the image), for example, the output of the nth first scanning circuit 230 can be simultaneously connected to the first control terminal S1 and the second control terminal of the (2n-1)th and 2nth pixel circuits 10. This eliminates the need for an additional second scanning circuit 240 in the display panel to provide a second scanning signal to the pixel circuits 10, effectively reducing the number of second scanning circuits 240 and facilitating a narrow bezel design.

[0083] Combination Figure 7 and Figure 8 Optionally, the signal waveforms of the third control terminal S3 and the second control terminal S2 of the pixel circuit 10 are the same, and the pulse timing of the third control terminal S3 is later than the pulse timing of the second control terminal S2. The second control terminal S2 of the i-th row pixel circuit 10 is connected to the output terminal of the i-th second scanning circuit 240, and the third control terminal S3 of the i-th row pixel circuit 10 is connected to the output terminal of the (i+1)-th second scanning circuit 240. Here, i is an integer greater than or equal to 1.

[0084] The third control terminal S3 is also used to control the working stage of the pixel circuit 10. For example, the second control terminal S2 is used to control the pixel circuit 10 to initialize the gate voltage of the driving transistor, and the third control terminal S3 is used to control the data writing stage of the pixel circuit 10. The second scan signal output by the (i+1)th second scan circuit 240 has the same waveform as the second scan signal output by the ith second scan circuit 240, and the pulse timing of the second scan signal output by the (i+1)th second scan circuit 240 is later than the pulse timing of the second scan signal output by the ith second scan circuit 240. Therefore, the second scan signals output by the ith and (i+1)th second scan circuits 240 can meet the signal requirements of the second control terminal S2 and the third control terminal S3 of the ith row pixel circuit 10. The advantage of this setting is that signals can be provided to the two control terminals of the pixel circuit 10 through a set of second scan circuits 240, without the need to set up an additional set of scan circuits to provide signals to the third control terminal S3 of the pixel circuit 10, reducing the number of scan circuits in the display panel and facilitating the implementation of a narrow bezel design.

[0085] Figure 9 This is a schematic diagram of another pixel circuit used in display panels. See also... Figure 9 Based on the above embodiments, the pixel circuit 10 may optionally include: a driving module 110, a light-emitting module 120, a light-emitting control module 130, a first initialization module 140, a second initialization module 150, a data writing module 160, and a storage module 170.

[0086] The driving module 110, the light-emitting module 120, and the light-emitting control module 130 are connected between the first power line VDD and the second power line VSS. The driving module 110 is used to drive the light-emitting module 120. The control terminal of the light-emitting control module 130 is the light-emitting control terminal EM. The light-emitting control module 130 is used to respond to the signal of the light-emitting control terminal EM and control the connection or disconnection between the first power line VDD and the second power line VSS.

[0087] The first initialization module 140 is connected between the initialization signal line Vref and the first terminal of the light-emitting module 120. The initialization signal line Vref is connected to the initialization voltage. The control terminal of the first initialization module 140 is the first control terminal S1. The first initialization module 140 is used to respond to the signal of the first control terminal S1 and write the initialization voltage to the first terminal of the light-emitting module 120.

[0088] The second initialization module 150 is connected between the initialization signal line Vref and the control terminal G of the drive module 110. The control terminal of the second initialization module 150 is the second control terminal S2. The second initialization module 150 is used to respond to the signal of the second control terminal S2 and write the initialization voltage to the control terminal G of the drive module 110.

[0089] The data writing module 160 is connected between the data line Data and the driver module 110. The control terminal of the data writing module 160 is the third control terminal S3. The data writing module 160 is used to respond to the signal of the third control terminal S3 and write data voltage to the control terminal G of the driver module 110.

[0090] The first terminal of the storage module 170 is connected to the control terminal G of the drive module 110, and the second terminal of the storage module 170 is connected to a fixed voltage. The storage module 170 is used to store the voltage of the control terminal G of the drive module 110. The fixed voltage connected to the second terminal of the second storage module 210 can be any constant voltage. For example, the second terminal of the storage module 170 is connected to the first power line VDD to receive the voltage on the first power line VDD.

[0091] Furthermore, the pixel circuit 10 also includes a threshold compensation module 180. The threshold compensation module 180 is connected between the first terminal of the driving module 110 and the control terminal G. The control terminal of the threshold compensation module 180 is the third control terminal S3. The threshold compensation module 180 is used to compensate the threshold voltage of the driving module 110 in response to the signal of the third control terminal S3.

[0092] Figure 4-6 and Figure 8 The light emission control terminal EM of the pixel circuit 10 can be the control terminal of the light emission control module 130, the first control terminal S1 can be the control terminal of the first initialization module 140, the second control terminal S2 can be the control terminal of the second initialization module 150, and the third control terminal S3 can be the control terminal of the data writing module 160 and the threshold compensation module 180.

[0093] See Figure 9 Optionally, the driving module 110 includes a driving transistor DT, the light-emitting module 120 includes a light-emitting device D1, the light-emitting control module 130 includes a first transistor T1 and a second transistor T2, the first initialization module 140 includes a third transistor T3, the second initialization module 150 includes a fourth transistor T4, the data writing module 160 includes a fifth transistor T5, the storage module 170 includes a storage capacitor Cst, and the threshold compensation module 180 includes a sixth transistor T6.

[0094] The driving transistor DT and the light-emitting device D1 are connected between the first power line VDD and the second power line VSS. The first transistor T1 is connected between the first power line VDD and the driving transistor DT. The second transistor T2 is connected between the driving transistor DT and the light-emitting device D1. The first terminal of the third transistor T3 is connected to the initialization signal line Vref, and the second terminal of the third transistor T3 is connected to the first terminal (e.g., the anode) of the light-emitting device D1. The first terminal of the fourth transistor T4 is connected to the initialization signal line Vref, and the second terminal of the fourth transistor T4 is connected to the gate of the driving transistor DT. The first terminal of the fifth transistor T5 is connected to the data line Data, and the second terminal of the fifth transistor T5 is connected to the first terminal of the driving transistor DT. The first terminal of the sixth transistor T6 is connected to the second terminal of the driving transistor DT, and the second terminal of the sixth transistor T6 is connected to the gate of the driving transistor DT.

[0095] Among them, the light-emitting device D1 includes organic light-emitting diodes (OLEDs) and micron-sized light-emitting diodes (Micro-LEDs). The transistors in the pixel circuit can be either P-type or N-type transistors. Figure 9 The illustration is based on the example where all transistors in a pixel circuit are P-type transistors.

[0096] Corresponding to Figure 4-6 and Figure 8 In the pixel circuit 10, the gates of the first transistor T1 and the second transistor T2 can be used as the light-emitting control terminal EM of the pixel circuit 10, the gate of the third transistor T3 can be used as the first control terminal S1 of the pixel circuit 10, the gate of the fourth transistor T4 can be used as the second control terminal S2 of the pixel circuit 10, and the fifth transistor T5 and the sixth transistor T6 can be used as the third control terminal S3 of the pixel circuit 10.

[0097] Figure 10 This is a schematic diagram of the driving timing of a pixel circuit according to an embodiment of the present invention. This driving timing can be applied to driving... Figure 9 The pixel circuitry operates within this system. Combined with... Figures 8 to 10 Optionally, when the refresh rate of the display panel is lower than a preset frequency, a display frame includes a write frame F1 and at least one hold frame F2. The light-emitting control module 130 responds to the signal from the light-emitting control terminal EM by controlling the connection or disconnection between the first power line VDD and the second power line VSS in the write frame F1 and hold frame F2. The first initialization module 140 responds to the signal from the first control terminal S1 by writing an initialization voltage to the first terminal of the light-emitting module 120 in the write frame F1 and hold frame F2.

[0098] The preset frequency is a relatively low frequency, and its specific value can be set according to requirements. For example, the preset frequency could be 60Hz. Write frame F1 includes a data writing phase; the control terminal of the drive module 110 writes data voltage in write frame F1 and does not write data voltage in hold frame F2. The following explanation, using the transistors in each module of the pixel circuit as an example where all transistors are P-type transistors, illustrates the working principle of the pixel circuit.

[0099] Combination Figures 8 to 10 In the first stage t1 of writing frame F1, the first control terminal S1 and the second control terminal S2 input low-level signals, while the third control terminal S3 and the light-emitting control terminal EM input high-level signals. The third transistor T3 is turned on, transmitting the initialization voltage on the initialization signal line Vref to the first terminal of the light-emitting device D1, initializing the voltage at the first terminal of D1 to reduce the impact of residual charge on the display effect. The fourth transistor T4 is turned on, transmitting the initialization voltage on the initialization signal line Vref to the gate of the driving transistor DT, initializing the gate voltage of the driving transistor DT to reduce the impact of residual charge on the display effect, and controlling the driving transistor DT to turn on.

[0100] In the second stage t2 of writing frame F1, the first control terminal S1 and the third control terminal S3 input low-level signals, while the second control terminal S2 and the light-emitting control terminal EM input high-level signals. The operating state of the third transistor T3 is the same as in the previous stage. The fifth transistor T5 and the sixth transistor T6 are turned on, and the data voltage on the data line Data is sequentially written to the gate of the driving transistor DT through the fifth transistor T5, the driving transistor DT, and the sixth transistor T6, so that the gate voltage of the driving transistor DT is related to the data voltage and the threshold voltage of the driving transistor DT. At the same time, the gate voltage of the driving transistor DT is stored through the storage capacitor Cst.

[0101] In the third stage t3 of writing frame F1, high-level signals are input to the first control terminal S1, the second control terminal S2, and the third control terminal S3, while a low-level signal is input to the light-emitting control terminal EM. The first transistor T1, the second transistor T2, and the driving transistor DT are turned on, while the remaining transistors are turned off. A discharge path is formed between the first power line VDD and the second power line VSS. The driving transistor DT generates a driving current based on its gate voltage, driving the light-emitting device D1 to emit light. Since the gate voltage of the driving transistor DT is related to both the data voltage and the threshold voltage of the driving transistor DT, it helps to eliminate the influence of the threshold voltage of the driving transistor DT on the driving current, thereby achieving threshold voltage compensation for the driving transistor DT.

[0102] The hold frame F2 includes a light-emitting phase and a non-light-emitting phase. The non-light-emitting phase is when the light-emitting control terminal EM inputs a high-level signal, and the light-emitting phase is when the light-emitting control terminal EM inputs a low-level signal. In the non-light-emitting phase of each hold frame F2, the first control terminal S1, the second control terminal S2, and the third control terminal S3 input high-level signals. When the first control terminal S1 inputs a low-level signal, the light-emitting control terminal EM inputs a high-level signal, the first transistor T1 and the second transistor T2 are turned off, disconnecting the first power line VDD and the second power line VSS. The third transistor T3 is turned on, transmitting the initialization voltage on the initialization signal line Vref to the first electrode of the light-emitting device D1, initializing the voltage of the first electrode of the light-emitting device D1, causing the current of the light-emitting device D1 to drop rapidly, and controlling the light-emitting device D1 to stop emitting light, so that the display panel can fully display a black screen.

[0103] During the light-emitting phase in each holding frame F2, high-level signals are input to the first control terminal S1, the second control terminal S2, and the third control terminal S3, while a low-level signal is input to the light-emitting control terminal EM. The first transistor T1, the second transistor T2, and the driving transistor DT are turned on, forming a discharge path between the first power line VDD and the second power line VSS. The driving transistor DT generates a driving current according to its own gate voltage, driving the light-emitting device D1 to emit light.

[0104] In existing technologies, when the refresh rate of the display panel is lower than 60Hz, the voltage of the first electrode of the light-emitting device D1 is generally initialized only during the initialization phase of the write frame F1. For example, at a refresh rate of 15Hz, the voltage of the first electrode of the light-emitting device D1 is initialized only every 64ms. This makes it possible for the human eye to perceive sudden changes in the brightness of the light-emitting device D1, resulting in screen flickering and affecting the display effect. Compared with the prior art, the technical solution of this embodiment allows the third transistor T3 to respond to the signal of the first control terminal S1 and initialize the voltage of the first electrode of the light-emitting device D1 during the initialization phases of both the write frame F1 and the hold frame F2. For example, at a refresh rate of 15Hz, the voltage of the first electrode of the light-emitting device D1 can maintain an initialization speed of 60Hz, achieving voltage initialization every 16ms. This makes it difficult for the human eye to perceive the brightness changes of the light-emitting device D1 during the initialization phases of the write frame F1 and the hold frame F2, thereby improving the screen flickering phenomenon and optimizing the display effect.

[0105] Combination Figures 8 to 10In this embodiment, the pulse timing of the signals input to the first control terminal S1 and the third control terminal S3 is different, requiring different scanning circuits to provide scanning signals to the first control terminal S1 and the third control terminal S3. Specifically, the first scanning circuit 230 provides a scanning signal to the first control terminal S1, and the third control terminal S3 provides a scanning signal to the third control terminal S3. Based on this, by setting each light-emitting control signal generation circuit 210 to simultaneously drive at least two rows of pixel circuits 10, and each first scanning circuit 230 to simultaneously drive at least two rows of pixel circuits 10, the light-emitting control signal generation circuit 210 and the first scanning circuit 230 are located on the same side of the first clock signal line 410 and the second clock signal line 420, and are arranged in the same column, the light-emitting control signal generation circuit 210 and the first scanning circuit 230 occupy at most the border area required for one set of scanning circuits, and each first scanning circuit 230 does not need to occupy the border area required for a separate set of scanning circuits. Therefore, the technical solution of this embodiment not only improves the screen flickering phenomenon but also facilitates the implementation of a narrow bezel design.

[0106] Figure 10 The diagram shows the light emission control signals and scan signals input to the pixel circuits in rows 2n-1 and 2n. Combined with... Figures 8 to 10 When each light-emitting control signal generation circuit 210 simultaneously drives two rows of pixel circuits 10, and each first scanning circuit 230 simultaneously drives two rows of pixel circuits 10, the nth light-emitting control signal generation circuit 210 simultaneously provides light-emitting control signals to the light-emitting control terminals EM of the (2n-1)th and (2n-1)th row pixel circuits 10, and the nth first scanning circuit 230 simultaneously provides first scanning signals to the first control terminals S1 of the (2n-1)th and (2n-1)th row pixel circuits 10. The signal S2(2n-1) of the second control terminal S2 of the (2n-1)th row pixel circuit 10 can be provided by the (2n-1)th second scanning circuit 240, and the signal S3(2n-1) of the third control terminal S3 of the (2n-1)th row pixel circuit 10 can be provided by the (2n)th second scanning circuit 240. The signal S2(2n) of the second control terminal S2 of the 2n-row pixel circuit 10 can be provided by the 2n-th second scanning circuit 240, and the signal S3(2n) of the third control terminal S3 of the 2n-row pixel circuit 10 can be provided by the (2n+1)-th second scanning circuit 240. Wherein, n is an integer greater than or equal to 1.

[0107] Figure 10 Only the case where the levels of a portion of the first scan signal input to the first control terminal S1 and the light emission control signal input to the light emission control terminal EM are opposite is shown; that is, when the first scan signal is at the on level, the light emission control signal is at the off level, and when the light emission control signal is at the on level, the first scan signal is at the off level. In other embodiments, for example in... Figure 4 In the technical solution shown, the levels of the first scanning signal input to the first control terminal S1 and the light emission control signal input to the light emission control terminal EM can be completely opposite, which can also achieve the above-mentioned beneficial effects.

[0108] Figure 11 This is a schematic diagram illustrating the connection relationship between another scanning driving unit and pixel circuit provided in an embodiment of the present invention; Figure 12 It is applicable Figure 11 A schematic diagram of a pixel circuit structure. Combined with... Figure 11 and Figure 12 In one embodiment, a scanning driving unit 20 includes at least one light emission control signal generation circuit 210. The output terminal of the light emission control signal generation circuit 210 is connected to the light emission control terminal EM and the first control terminal S1 of the pixel circuit 10. The light emission control signal generation circuit 210 is used to simultaneously provide light emission control signals to the light emission control terminal EM and the first control terminal S1 of the pixel circuit 10. The light emission control signals are multiplexed into a first scan signal. The transistor type that receives the light emission control signal in the pixel circuit 10 is opposite to the transistor type that receives the first scan signal.

[0109] Both the light emission control module 130 and the first initialization module 140 include transistors. The gate of the transistor in the light emission control module 130 serves as the light emission control terminal EM, and the gate of the transistor in the first initialization module 140 serves as the first control terminal S1. One of the transistors in the light emission control module 130 and the transistor in the first initialization module 140 is an N-type transistor, and the other is a P-type transistor.

[0110] Specifically, the various light-emitting control signal generation circuits 210 are cascaded, and the output terminal O1 of each light-emitting control signal generation circuit 210 is connected to the light-emitting control terminal EM and the first control terminal S1 of at least two rows of pixel circuits 10. When each light-emitting control signal generation circuit 210 drives two rows of pixel circuits 10, as follows... Figure 11 As shown, the nth light-emitting control signal generation circuit 210 can be connected to the light-emitting control terminal EM and the first control terminal S1 of the (2n-1)th and 2nth row pixel circuits 10. Here, n is an integer greater than or equal to 1. When each light-emitting control signal generation circuit 210 drives three or more rows of pixel circuits 10, each light-emitting control signal generation circuit 210 is connected to the light-emitting control terminal EM and the first control terminal S1 of m adjacent rows of pixel circuits 10, and each light-emitting control signal generation circuit 210 is sequentially connected to the light-emitting control terminal EM and the first control terminal S1 of the corresponding m adjacent rows of pixel circuits 10. Here, m is an integer greater than 2.

[0111] For example, the transistors in the light-emitting control module 130 are the first transistor T1 and the second transistor T2, and the transistor in the first initialization module 140 is the third transistor T3. Figure 12 This illustrates a scenario where the first transistor T1 and the second transistor T2 are both P-type transistors, and the third transistor T3 is an N-type transistor. When the third transistor T3 is of a different type than the first transistor T1 and the second transistor T2, and the refresh rate of the display panel is lower than a preset frequency, the light emission control signal provided by the light emission control signal generation circuit 210 to the light emission control terminal EM and the first control terminal S1 of the pixel circuit 10 is... Figure 10 The signal of the EM control terminal shown is similar. See also Figure 10 During the non-light-emitting phase of write frame F1 and hold frame F2, a high-level signal is input to the light-emitting control signal. The first transistor T1 and the second transistor T2 turn off in response to the light-emitting control signal, disconnecting the first power line VDD and the second power line VSS. The third transistor T3 turns on in response to the light-emitting control signal, transmitting the initialization voltage on the initialization signal line Vref to the first terminal of the light-emitting device D1, initializing the voltage at the first terminal of D1, causing the current of D1 to drop rapidly, and stopping D1 from emitting light so that the display panel can fully display a black screen. During the light-emitting phase of write frame F1 and hold frame F2, a low-level signal is input to the light-emitting control terminal EM. The third transistor T3 turns off in response to the light-emitting control signal, and the first transistor T1 and the second transistor T2 turn on in response to the light-emitting control signal, forming a discharge path between the first power line VDD and the second power line VSS. The driving transistor DT generates a driving current according to its gate voltage, driving the light-emitting device D1 to emit light.

[0112] The technical solution of this embodiment, by setting one of the transistors in the light-emitting control module 130 and the first initialization module 140 to be an N-type transistor and the other to be a P-type transistor, allows the light-emitting control signal provided by the light-emitting control signal generation circuit 210 to the light-emitting control terminal EM of the pixel circuit 10 to be multiplexed as the signal of the first control terminal S1. This eliminates the need for an additional scanning circuit to provide a signal to the first control terminal S1, reducing the number of scanning circuits in the display panel and facilitating a narrow bezel design. Furthermore, by multiplexing the light-emitting control signal as the signal of the first control terminal S1, the third transistor T3 can respond to the light-emitting control signal and initialize the voltage of the first electrode of the light-emitting device D1 during the initialization stages of both the write frame F1 and the hold frame F2. This increases the voltage initialization frequency of the light-emitting device D1, making it difficult for the human eye to perceive the brightness changes of the light-emitting device D1 during the various initialization stages of the write frame F1 and the hold frame F2, thereby improving screen flicker and optimizing the display effect.

[0113] Figure 13This is a schematic diagram of another pixel circuit used in display panels; Figure 14 This is a schematic diagram of the driving timing of another pixel circuit provided in an embodiment of the present invention. This driving timing can be applied to driving... Figure 13 The pixel circuitry operates within this system. Combined with... Figure 8 , Figure 13 and Figure 14 Optionally, the threshold compensation module 180 includes a dual-gate transistor connected between the first terminal and the control terminal of the driving module 110. The pixel circuit 10 further includes a leakage current suppression module 190, which is connected between the initialization signal line Vref and the dual-gate node N of the dual-gate transistor. The control terminal of the leakage current suppression module 190 is a first control terminal S1. The leakage current suppression module 190 is used to write an initialization voltage to the dual-gate node N in response to the signal of the first control terminal S1 to suppress the leakage current of the control terminal G of the driving module 110. The time interval during which the first control terminal S1 is connected to the conduction level does not overlap with the time interval during which the third control terminal S3 is connected to the conduction level.

[0114] For example, the threshold compensation module 180 includes a first dual-gate transistor T6-1 and a second dual-gate transistor T6-2. The first terminal of the second dual-gate transistor T6-2 is connected to the second terminal of the driving transistor DT. The second terminal of the second dual-gate transistor T6-2 and the first terminal of the first dual-gate transistor T6-1 are connected to the dual-gate node N. The second terminal of the first dual-gate transistor T6-1 is connected to the gate of the driving transistor DT. Optionally, the transistors in the second initialization module 150 can also be dual-gate transistors. For example, the second initialization module 150 includes a third dual-gate transistor T4-1 and a fourth dual-gate transistor T4-2 connected between the initialization signal line Vref and the gate of the driving transistor DT. The leakage current suppression module 190 includes a seventh transistor T7. The gate of the seventh transistor T7 serves as the control terminal of the leakage current suppression module 190, i.e., the first control terminal S1. The first terminal of the seventh transistor T7 is connected to the initialization signal line Vref, and the second terminal of the seventh transistor T7 is connected to the dual-gate node N.

[0115] The time interval during which the first control terminal S1 is connected to the conduction level does not overlap with the time interval during which the third control terminal S3 is connected to the conduction level. For example, when the refresh rate of the display panel is lower than the preset frequency, the first scanning circuit 230 provides a first scanning signal to the first control terminal S1 of the pixel circuit 10. The first scanning signals in both the write frame F1 and the hold frame F2 include a conduction level (e.g., a low level). The time interval between adjacent conduction levels is the same, and the time interval of the conduction level in the write frame F1 coincides with the time interval of the first stage t1. In this way, the seventh transistor T7 can be turned on in response to the on-level of the first control terminal S1 in both write frame F1 and hold frame F2, writing the initialization voltage on the initialization signal line Vref to the dual-gate node N, so as to reset the voltage of the dual-gate node N to the initialization voltage. This allows the voltage of the dual-gate node N to be reset to a lower initialization voltage multiple times in the write frame F1 and each hold frame F2 of a display frame, so as to avoid the generation of leakage current from the first dual-gate transistor T6-1 to the gate of the driving transistor DT. This helps to maintain the stability of the gate voltage of the driving transistor DT, thereby improving the leakage current problem of the pixel circuit and enhancing the display effect.

[0116] The technical solution of this embodiment provides a first scan signal to the first control terminal S1 of the pixel circuit 10 through the first scan circuit 230, thereby driving the third transistor T3 to work. This increases the voltage initialization frequency of the light-emitting device D1, making it difficult for the human eye to perceive the brightness changes of the light-emitting device D1 during the initialization stages of the write frame F1 and the hold frame F2. It also drives the seventh transistor T7 to work, thereby improving the leakage problem of the pixel circuit 10. While achieving the above-mentioned beneficial effects, it eliminates the need for two sets of scan circuits to supply signals to the third transistor T3 and the seventh transistor T7 respectively, reducing the number of scan circuits in the display panel and facilitating a narrow bezel design.

[0117] In another implementation, when the refresh rate of the display panel is higher than the preset frequency, a display frame may only include a write frame F1 and not a hold frame F2. The signals of the first control terminal S1 and the second control terminal S2 may be the same. In this case, the first scanning circuit 230 can be multiplexed into a second scanning circuit 240 to multiplex the first scanning signal into a second scanning signal. The first scanning circuit 230 provides signals to the first control terminal S1 and the second control terminal S2 of the pixel circuit 10 at the same time. There is no need to set up an additional second scanning circuit 240 to provide signals to the second control terminal S2 of the pixel circuit 10, which is equivalent to reducing the number of a set of second scanning circuits 240, which is beneficial to achieving a narrow bezel design.

[0118] Based on the same inventive concept, the embodiments of the invention also provide a display device, including the display panel in any of the above embodiments, and thus possessing the corresponding functional structure and beneficial effects of the display panel, which will not be repeated here. The display device can be a mobile phone, or any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, in-vehicle display, medical equipment, industrial control equipment, touch interactive terminal, etc., and the embodiments of the present invention do not make any special limitations on this.

[0119] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0120] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area. A multi-row pixel circuit is located in the display area; Multiple scanning driving units are arranged in the same column in the non-display area. One of the scanning driving units is connected to the light emission control terminal and the first control terminal of at least two rows of the pixel circuits. The scanning driving unit is used to generate a light emission control signal and a first scanning signal to provide the light emission control signal to the light emission control terminal of the at least two rows of the pixel circuits, and at the same time provide the first scanning signal to the first control terminal of the at least two rows of the pixel circuits. The time interval during which the light emission control signal is at the cutoff level covers the time interval during which the first scan signal is at the on level. Alternatively, the scanning driving unit is used to simultaneously provide the light emission control signal to the light emission control terminal and the first control terminal of the at least two rows of the pixel circuit, the light emission control signal being multiplexed as the first scanning signal, and the conduction levels of the light emission control terminal and the first control terminal of the pixel circuit being opposite; One of the scanning driving units includes a light emission control signal generation circuit and an inverting module. The output terminal of the light emission control signal generation circuit is connected to the light emission control terminal of the pixel circuit and the input terminal of the inverting module. The output terminal of the inverting module is connected to the first control terminal of the pixel circuit. The light emission control signal generation circuit is used to generate the light emission control signal, and the inverting module is used to invert the light emission control signal to obtain the first scanning signal. The first scan signal is used to initialize and control the voltage of the first electrode of the light-emitting device during the initialization phases of both the write frame and the hold frame. One of the scanning driving units includes at least one light emission control signal generation circuit. The output terminal of the light emission control signal generation circuit is connected to the light emission control terminal and the first control terminal of the pixel circuit. The light emission control signal generation circuit is used to simultaneously provide light emission control signals to the light emission control terminal and the first control terminal of the pixel circuit. The light emission control signals are multiplexed into the first scanning signal. The transistor type in the pixel circuit that receives the light emission control signal is opposite to the transistor type that receives the first scanning signal. Each of the light emission control signal generation circuits is cascaded, and the output terminal of each of the light emission control signal generation circuits is connected to the light emission control terminal and the first control terminal of at least two rows of pixel circuits.

2. The display panel according to claim 1, characterized in that, One of the scanning driving units includes at least one light emission control signal generation circuit and at least one first scanning circuit. The number of light emission control signal generation circuits in each scanning driving unit is the same as the number of first scanning circuits. The output terminal of the light emission control signal generation circuit is connected to the light emission control terminal of the pixel circuit, and the output terminal of the first scanning circuit is connected to the first control terminal of the pixel circuit. The light emission control signal generation circuit is used to generate the light emission control signal, and the first scanning circuit is used to generate the first scanning signal.

3. The display panel according to claim 2, characterized in that, The display panel further includes a first clock signal line and a second clock signal line. The light emission control signal generation circuit and the first scanning circuit are located on the same side of the first clock signal line and the second clock signal line, and the light emission control signal generation circuit and the first scanning circuit are arranged in the same column.

4. The display panel according to claim 3, characterized in that, Each of the light emission control signal generation circuits is cascaded and connected, and each of the first scanning circuits is cascaded and connected; The output terminal of the nth light emission control signal generation circuit is connected to the light emission control terminal of the pixel circuit in rows 2n-1 and 2n, and the output terminal of the nth first scanning circuit is connected to the first control terminal of the pixel circuit in rows 2n-1 and 2n; where n is an integer greater than or equal to 1.

5. The display panel according to claim 4, characterized in that, The output of each of the light emission control signal generation circuits is connected to the light emission control terminals of m adjacent pixel circuits. Each of the light emission control signal generation circuits is sequentially connected to the light emission control terminals of the corresponding m adjacent pixel circuits. The output of each of the first scanning circuits is connected to the first control terminals of m adjacent pixel circuits. Each of the first scanning circuits is sequentially connected to the first control terminals of the corresponding m adjacent pixel circuits. Wherein, m is an integer greater than 2.

6. The display panel according to claim 4, characterized in that, The light emission control signal generation circuit and the first scanning circuit are both connected to the first clock signal line and the second clock signal line. The light emission control signal generation circuit generates the light emission control signal in response to the signals on the first clock signal line and the second clock signal line, and the first scanning circuit generates the first scanning signal in response to the signals on the first clock signal line and the second clock signal line.

7. The display panel according to claim 4, characterized in that, The light emission control signal generation circuit and the first scanning circuit are arranged alternately in the same column; or, every two cascaded light emission control signal generation circuits and every two cascaded first scanning circuits are arranged alternately in the same column.

8. The display panel according to claim 2, characterized in that, The display panel also includes multiple cascaded second scanning circuits located in the non-display area. The output of the second scanning circuit is connected to the second control terminals of at least two rows of pixel circuits to provide a second scanning signal to the second control terminals of the pixel circuits.

9. The display panel according to claim 8, characterized in that, The waveform and pulse timing of the second scan signal are the same as those of the first scan signal. The first scan circuit is multiplexed as the second scan circuit, and the first scan signal is multiplexed as the second scan signal.

10. The display panel according to claim 8, characterized in that, The signal waveforms of the third control terminal and the second control terminal of the pixel circuit are the same, and the pulse timing of the third control terminal is later than the pulse timing of the second control terminal. The second control terminal of the pixel circuit in the i-th row is connected to the output terminal of the i-th second scanning circuit, and the third control terminal of the pixel circuit in the i-th row is connected to the output terminal of the (i+1)-th second scanning circuit; where i is an integer greater than or equal to 1.

11. The display panel according to any one of claims 1-10, characterized in that, The pixel circuit includes: A driving module, a light-emitting module, and a light-emitting control module are connected between a first power line and a second power line. The driving module is used to drive the light-emitting module. The control terminal of the light-emitting control module is the light-emitting control terminal. The light-emitting control module is used to respond to the signal of the light-emitting control terminal to control the connection or disconnection between the first power line and the second power line. A first initialization module is connected to the first end of the light-emitting module. The control end of the first initialization module is the first control end. The first initialization module is used to respond to the signal of the first control end and write an initialization voltage to the first end of the light-emitting module. The second initialization module is connected to the control terminal of the drive module. The control terminal of the second initialization module is a second control terminal. The second initialization module is used to respond to the signal of the second control terminal and write the initialization voltage to the control terminal of the drive module. A data writing module is connected to the driving module. The control terminal of the data writing module is a third control terminal. The data writing module is used to respond to the signal of the third control terminal and write data voltage to the control terminal of the driving module.

12. The display panel according to claim 11, characterized in that, The pixel circuit also includes: A threshold compensation module is connected between the first end and the control end of the drive module. The control end of the threshold compensation module is the third control end. The threshold compensation module is used to compensate the threshold voltage of the drive module in response to the signal of the third control end.

13. The display panel according to claim 11, characterized in that, When the refresh rate of the display panel is lower than the preset frequency, a display frame includes a write frame and at least one hold frame; the light emission control module responds to the signal of the light emission control terminal and controls the first power line and the second power line to be connected or disconnected in the write frame and the hold frame; the first initialization module responds to the signal of the first control terminal and writes the initialization voltage to the first terminal of the light emission module in the write frame and the hold frame.

14. The display panel according to claim 11, characterized in that, Both the light emission control module and the first initialization module include transistors. The gate of the transistor in the light emission control module serves as the light emission control terminal, and the gate of the transistor in the first initialization module serves as the first control terminal. When the scan driving unit provides light emission control signals to the light emission control terminal and the first control terminal of the pixel circuit, one of the transistors in the light emission control module and the first initialization module is an N-type transistor, and the other is a P-type transistor.

15. The display panel according to claim 12, characterized in that, The threshold compensation module includes a dual-gate transistor, which is connected between the first end and the control end of the driving module; The pixel circuit also includes: A leakage current suppression module is connected between the initialization signal line and the dual-gate node of the dual-gate transistor. The initialization signal line is connected to an initialization voltage. The control terminal of the leakage current suppression module is the first control terminal. The leakage current suppression module is used to write the initialization voltage to the dual-gate node in response to the signal of the first control terminal to suppress leakage current at the control terminal of the drive module. The time interval during which the first control terminal is connected to the conduction level does not overlap with the time interval during which the third control terminal is connected to the conduction level.

16. A display device, characterized in that, Includes the display panel described in any one of claims 1-15.

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