Data driver, electroluminescent display device and driving method thereof

Abstract

The present disclosure relates to a data driver, an electroluminescent display apparatus, and a driving method thereof. An electroluminescent display apparatus can include a display panel including at least one pixel, and a data driver configured to output a first gray scale level of data voltage to the at least one pixel in a first refresh frame, output a flicker compensation data voltage to the at least one pixel in a second refresh frame, and output an anode reset voltage to the at least one pixel in at least one anode reset frame disposed between the first refresh frame and the second refresh frame, wherein the anode reset voltage is a voltage for turning off a light emitting device included in the at least one pixel, and the flicker compensation data voltage is generated based on applying a weight to a second gray scale level of data voltage.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0171978, filed in the Republic of Korea on December 3, 2021, and Korean Patent Application No. 10-2022-0143306, filed in the Republic of Korea on November 1, 2022, the entire contents of which are incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This disclosure relates to data drivers, electroluminescent display devices, and driving methods thereof. Background Technology

[0004] An electroluminescent display device includes multiple pixels arranged in a matrix, and supplies voltage to the pixels in sync with image data, thereby enabling the pixels to achieve brightness corresponding to the image data.

[0005] Variable refresh rate (VRR) technology can be used to change the refresh rate based on the properties of the image in an electroluminescent display device. In VRR technology, when the image does not change or remains more or less constant, the data refresh cycle is extended to reduce power consumption (e.g., when displaying static images or wallpapers).

[0006] In VRR technology, brightness deviations may occur at the time of refresh rate changes when the data refresh cycle changes. This brightness deviation is identified as flickering, and therefore, the display quality is degraded. Summary of the Invention

[0007] To overcome the aforementioned problems in related technologies, this disclosure provides a data driver, an electroluminescent display device, and a driving method thereof, which adjusts the level of the flicker compensation data voltage based on the data refresh cycle to prevent flickering at the time of refresh rate change.

[0008] To achieve these objectives and other advantages, and in accordance with the purposes of this disclosure, as embodied and broadly described herein, an electroluminescent display device includes: a display panel including at least one pixel; and a data driver configured to: output a data voltage of a first gray level to at least one pixel in a first refresh frame; output a flicker compensation data voltage to at least one pixel in a second refresh frame; and output an anode reset voltage to at least one pixel in at least one anode reset frame disposed between the first refresh frame and the second refresh frame, wherein the anode reset voltage is a voltage for turning off a light-emitting device included in the at least one pixel, and wherein the flicker compensation data voltage is generated based on weighting the data voltage of the second gray level. Specifically, the anode reset voltage is a voltage for turning off a light-emitting device included in the at least one pixel during a portion of the anode reset frame, the flicker compensation data voltage is a data voltage of a third gray level obtained by reflecting weights in the data voltage of the second gray level, and the level of the flicker compensation data voltage when the number of anode reset frames is N (where N is a natural number) is different from the level of the flicker compensation data voltage when the number of anode reset frames is M (where M is a natural number greater than N).

[0009] In another aspect of this disclosure, the data driver is characterized by: outputting a first grayscale data voltage to at least one pixel in a first refresh frame; outputting a flicker compensation data voltage to at least one pixel in a second refresh frame; and outputting an anode reset voltage to at least one pixel in at least one anode reset frame disposed between the first refresh frame and the second refresh frame, wherein the anode reset voltage is a voltage for turning off a light-emitting device included in the at least one pixel, and wherein the flicker compensation data voltage is generated based on weighting the second grayscale data voltage. Specifically, the anode reset voltage is a voltage for turning off a light-emitting device included in the pixel during a portion of the anode reset frame, the flicker compensation data voltage is a third grayscale data voltage obtained by reflecting weights in the second grayscale data voltage, and the level of the flicker compensation data voltage when the number of anode reset frames is N (where N is a natural number) is different from the level of the flicker compensation data voltage when the number of anode reset frames is M (where M is a natural number greater than N).

[0010] In another aspect of this disclosure, a driving method for an electroluminescent display device includes: outputting a first grayscale data voltage to a pixel of a display panel in a first refresh frame; outputting a flicker compensation data voltage to the pixel in a second refresh frame; and outputting an anode reset voltage to the pixel in at least one anode reset frame disposed between the first refresh frame and the second refresh frame, wherein the anode reset voltage is a voltage for turning off a light-emitting device included in the pixel, and wherein the flicker compensation data voltage is generated based on weighting the second grayscale data voltage. Specifically, the anode reset voltage is a voltage for turning off a light-emitting device included in the pixel during a portion of the anode reset frame, the flicker compensation data voltage is a third grayscale data voltage obtained by reflecting weights in the second grayscale data voltage, and the level of the flicker compensation data voltage when the number of anode reset frames is N (where N is a natural number) is different from the level of the flicker compensation data voltage when the number of anode reset frames is M (where M is a natural number greater than N). Attached Figure Description

[0011] The accompanying drawings—included to provide a further understanding of this disclosure and incorporated in and forming part of this application—illustrate embodiments of the disclosure and, together with the description, serve to illustrate the principles of the disclosure. In the drawings:

[0012] Figure 1 This is a diagram illustrating an electroluminescent display device according to an embodiment of the present disclosure;

[0013] Figure 2 This illustrates the configuration according to an embodiment of the present disclosure. Figure 1 A diagram showing the circuit configuration of the pixels in the display panel;

[0014] Figure 3 and Figure 4 This is a diagram illustrating a technique for changing the refresh rate based on the number of skip frames set between refresh frames, as shown in a comparative example of this disclosure.

[0015] Figure 5 and Figure 6 This is a diagram illustrating a technique for changing the refresh rate based on the number of anode reset frames set between refresh frames in an embodiment of this disclosure.

[0016] Figure 7 This illustrates an embodiment of the present disclosure. Figure 2 A graph showing the refresh operation performed on the pixels;

[0017] Figure 8 This illustrates an embodiment of the present disclosure. Figure 2 The graph showing the pixel holding operation performed;

[0018] Figure 9 This illustrates an embodiment of the present disclosure. Figure 2 A diagram showing the anode reset operation performed on the pixels;

[0019] Figure 10 This illustrates an embodiment according to the present disclosure. Figure 9 A diagram illustrating an implementation of the anode reset voltage supplied to the pixel during the anode reset operation;

[0020] Figures 11 to 14 This is a diagram illustrating the grayscale response delay phenomenon that occurs when the anode reset frame is changed to a reset frame according to an embodiment of the present disclosure;

[0021] Figures 15A to 15C This is a diagram illustrating an example of setting the level of the flicker compensation data voltage based on different refresh rates to compensate for flicker caused by differences in grayscale response delay, according to an embodiment of the present disclosure.

[0022] Figure 16 This is a table illustrating detailed examples of how, according to embodiments of the present disclosure, different weights reflected in the data voltage of the input grayscale level are set based on the refresh rate to adjust the level of the flicker compensation data voltage.

[0023] Figure 17 This is a diagram illustrating the configuration of a timing controller for weighted data modulation operations according to an embodiment of the present disclosure;

[0024] Figure 18 This is a flowchart illustrating an example where the data refresh cycle varies based on the peak brightness of the entire image;

[0025] Figure 19A and Figure 19B This is a diagram illustrating an example where the duration of the hold period arranged between adjacent refresh frames varies based on the peak brightness of the entire image;

[0026] Figure 20A and Figure 20B This is another flowchart illustrating how the length of the hold period arranged between adjacent refresh frames varies based on the peak brightness of the entire image;

[0027] Figure 21 This is a flowchart illustrating an example where the data refresh cycle varies based on the size of consecutive low-grayscale areas throughout the region; and

[0028] Figure 22 This is a flowchart illustrating an example where the data refresh cycle varies based on the viewing distance of a user viewing the display panel. Detailed Implementation

[0029] The advantages and features of this disclosure and its implementation methods will be illustrated by the embodiments described below with reference to the accompanying drawings. However, this disclosure may be implemented in different forms, and it should not be construed as limited to the embodiments set forth herein. In fact, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is defined only by the scope of the claims.

[0030] The shapes, dimensions, ratios, angles, numbers, etc., disclosed in the accompanying drawings used to describe various embodiments of this disclosure are merely exemplary, and this disclosure is not limited thereto. Throughout the document, similar reference numerals refer to similar elements. Throughout this specification, the same elements are represented by the same reference numerals. As used herein, the terms "comprising," "having," "including," etc., indicate that additional parts may be added, unless the term "only" is used. As used herein, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to also include the plural forms.

[0031] Even without an explicit statement, elements in various embodiments of this disclosure will be interpreted as including tolerance ranges.

[0032] When describing positional relationships, for example, when the positional relationship between two parts is described as "on top of", "above", "below", "above", and "immediately following", one or more other parts may be placed between the two parts, unless "exactly" or "directly" is used.

[0033] It should be understood that while the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Throughout the text, similar reference numerals refer to similar elements.

[0034] In the following description, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In these embodiments, as examples of electroluminescent display devices, organic light-emitting display devices comprising organic light-emitting materials will be primarily described. However, the inventive concept is not limited to organic light-emitting display devices, and can be applied to inorganic light-emitting display devices comprising inorganic light-emitting materials.

[0035] Figure 1 This is a diagram illustrating an electroluminescent display device according to an embodiment of the present disclosure.

[0036] Reference Figure 1 An electroluminescent display device may include a display panel 10, a timing controller 11, a data driver 12, a gate driver 13, and a power circuit.

[0037] Multiple pixels PXL included in the display panel 10 can be arranged in a matrix to construct a pixel array. In the pixel array, each pixel PXL can be connected to a data line 14, a gate line 15, an initialization power line, a high-level power line, and a low-level power line. Here, the gate line 15 connected to each pixel PXL can include two scan lines and two emitter lines. Each pixel PXL can be supplied with a data voltage via the data line 14, a scan signal via the two scan lines, an emitter signal via the two emitter lines, an initialization voltage Vinit via the initialization power line, a high-level drive voltage VDDEL via the high-level power line, and a low-level drive voltage VSSEL via the low-level power line.

[0038] Initialization power lines, high-level power lines, and low-level power lines can be connected to a power circuit. The power circuit can generate an initialization voltage Vinit, a high-level drive voltage VDDEL, and a low-level drive voltage VSSEL.

[0039] Each pixel PXL can perform programming and emission operations based on a scan signal and an emission signal to achieve a brightness corresponding to the image data DATA. To this end, each pixel PXL may include: a driving element that generates a driving current corresponding to the image data DATA; and a light-emitting device that emits light with a brightness proportional to the level of the driving current. The driving element included in each pixel PXL can be implemented using, but is not limited to, oxide transistors with good leakage current characteristics.

[0040] Each pixel PXL can be programmed at each refresh frame to set the drive current before emission. The programming operation according to this embodiment may include applying an initialization voltage Vinit to the anode electrode of the light-emitting device to disable the initialization operation of the light-emitting device, sampling the threshold voltage of the driving element to reflect the sampled threshold voltage in the gate-source voltage of the driving element, and setting the drive current to reflect the image data DATA in the gate-source voltage of the driving element. During such programming operations, the light-emitting device can remain in a non-emitting state.

[0041] The initialization voltage Vinit can be used to prevent the light-emitting device from emitting unwanted light during programming operations, and can be selected within a voltage range sufficiently below the operating point voltage of the light-emitting device, and for example, can be selected as a voltage at or near the low-level drive voltage VSSEL.

[0042] Each pixel PXL can be driven based on Variable Refresh Rate (VRR) technology. To implement VRR, one or more anode reset frames can be set between adjacent refresh frames. During an anode reset frame, no data refresh operation can be performed on the pixel PXL, and the brightness of the previous refresh frame can be maintained during the anode reset frame. However, during the anode reset interval within the anode reset frame, an anode reset voltage can be applied to the pixel PXL. The anode reset interval of the anode reset frames can correspond to the programming operation interval of the refresh frames, and the anode reset voltage can be a voltage used to stop emission from the light-emitting device during the anode reset interval. Therefore, the emission sustaining time between refresh frames and anode reset frames can be equal. This will be referred to below. Figure 5 and Figure 6 Describe it.

[0043] The timing controller 11 can receive digital video data DATA and refresh rate change information from the host system. Based on the refresh rate change information, the timing controller 11 can adjust the number of anode reset frames set between adjacent refresh frames, and thus change the refresh period of the digital video data DATA. The timing controller 11 can apply weights to the image data DATA corresponding to the refresh frames to modulate the image data DATA, thereby reducing flickering that occurs at the time when the anode reset frame changes to a refresh frame.

[0044] The timing controller 11 can adjust the level of weight to be applied to the image data DATA as a whole based on the number of anode reset frames. The timing controller 11 can also adjust the level of weight to be applied to the image data DATA as a whole and further based on the average amount of transition of the image data DATA between adjacent refresh frames. The timing controller 11 can further adjust the level of weight to be applied to the image data DATA on a per-pixel basis based on the distance between pixel rows and the output terminals of the data driver 12. Here, a pixel row can represent a group of pixels PXL that share the same gate line 15 instead of a physical signal line and are horizontally adjacent to each other.

[0045] The timing controller 11 can supply weighted image data DATA to the data driver 12. Furthermore, the timing controller 11 can generate a data control signal DDC for controlling the operating timing of the data driver 12 and a gate control signal GDC for controlling the operating timing of the gate driver 13 based on timing signals such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the dot clock signal DCLK, and the data enable signal DE.

[0046] The following will refer to Figure 17 Describe the detailed configuration and operation of the timing controller 11.

[0047] The data driver 12 can perform digital-to-analog conversion on the image data DATA input from the timing controller 11 based on the data control signal DDC in the refresh frame to generate a compensation data voltage. The compensation data voltage can be a flicker compensation data voltage generated by reflecting weights in the input grayscale data voltage. The data driver 12 can output the flicker compensation data voltage to the data line 14 of the display panel 10 via the output terminal during the programming operation interval of the refresh frame.

[0048] The data driver 12 can generate an anode reset voltage based on the data control signal DDC in the anode reset frame. The anode reset voltage can be a voltage independent of the image data DATA. The data driver 12 can output the anode reset voltage to the data line 14 of the display panel 10 via the output terminal during the anode reset interval of the anode reset frame.

[0049] The gate driver 13 can generate a first gate signal based on the gate control signal GDC in the refresh frame. The first gate signal may include a scan signal and an transmit signal. The gate driver 13 can output the first gate signal to the gate line 15 of the display panel 10 in the refresh frame.

[0050] The gate driver 13 can generate a second gate signal based on the gate control signal GDC in the anode reset frame. The second gate signal may include a scan signal and a transmit signal. The gate driver 13 can output the second gate signal to the gate line 15 of the display panel 10 in the anode reset frame.

[0051] Depending on the type of gate driver (GIP) in the panel, the gate driver 13 can be directly disposed in the bezel area of ​​the display panel 10. Here, the bezel area can correspond to a non-display area outside the screen area, including the pixel array. The bezel area may not display an image.

[0052] Figure 2 It shows the setting Figure 1 A diagram showing the circuit configuration of the pixels in the display panel. Figure 2 The pixel circuit may be merely an implementation method, and the technical spirit of this disclosure is not limited to the configuration of the pixel circuit.

[0053] Reference Figure 2 The diagram shows the first pixel PXL among a plurality of pixels arranged in the nth (where n is a natural number) pixel row.

[0054] The first pixel PXL may include a light-emitting device EL, a driving element DT, a first switching element T1 to a fifth switching element T5, and a storage capacitor Cst.

[0055] The light-emitting device (EL) can be implemented using an organic light-emitting diode (OLED), which emits light using a drive current supplied through a driving element DT. A multilayer organic compound layer can be disposed between the anode and cathode electrodes of the EL. The organic compound layer may include a hole injection layer (HIL), a hole transport layer (HTL), an emitter layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode electrode of the EL can be connected to node C, and the cathode electrode can be connected to the input terminal of a low-level drive voltage VSSEL.

[0056] The driving element DT can generate a drive current applied to the light-emitting device EL based on its gate-source voltage. The gate electrode of the driving element DT can be connected to node A, the drain electrode of the driving element DT can be connected to node B, and the source electrode of the driving element DT can be connected to node D. The driving element DT can be implemented using a MOSFET that includes an oxide semiconductor layer, but is not limited thereto.

[0057] The first switching element T1 can be connected between node A and node B, and can be turned on / off based on the first scan signal SCAN1 from the first scan line 151. The gate electrode of the first switching element T1 can be connected to the first scan line 151.

[0058] The second switching element T2 can be connected between the input terminal of the initialization voltage Vinit and node C, and can be turned on / off based on the first scan signal SCAN1 from the first scan line 151. The gate electrode of the second switching element T2 can be connected to the first scan line 151.

[0059] The third switching element T3 can be connected between the first data line 14 and node D, and can be turned on / off based on the second scan signal SCAN2 from the second scan line 152. The gate electrode of the third switching element T3 can be connected to the second scan line 152.

[0060] The fourth switching element T4 can be connected between the input terminal of the high-level drive voltage VDDEL and node B, and can be turned on / off based on the second transmit signal EM2 from the second transmit line 154. The gate electrode of the fourth switching element T4 can be connected to the second transmit line 154.

[0061] The fifth switching element T5 can be connected between node D and node C, and can be turned on / off based on the first transmit signal EM1 from the first transmit line 153. The gate electrode of the fifth switching element T5 can be connected to the first transmit line 153.

[0062] The storage capacitor Cst can be connected between node A and node C.

[0063] The first pixel PXL can automatically compensate (hereinafter referred to as internal compensation) for the threshold voltage deviation of the driving element DT through pixel operations based on the connection configuration. The internal compensation operation can be interpreted as the threshold voltage of the driving element DT being reflected in the gate-source voltage of the driving element DT during pixel programming operations, and therefore, performing compensation ensures that the drive current generated by the driving element DT is unaffected by changes in the threshold voltage of the driving element DT.

[0064] Figure 3 and Figure 4 This is a diagram illustrating a frequency conversion technique used in a comparative example of this disclosure to determine the refresh rate based on the number of skip frames set between refresh frames.

[0065] Reference Figure 3 and Figure 4 The data refresh cycle implemented in the pixels of the display panel can vary based on refresh rate change information input from the host system. The data refresh cycle can increase as the refresh rate decreases, and the number of skipped frames can increase as the refresh rate decreases. For example, the data refresh cycle can be 1 / 120th of a second at 120Hz, 1 / 60th of a second at 60Hz, 1 / 24th of a second at 24Hz, and 1 second at 1Hz. The number of skipped frames set between two adjacent refresh frames can be zero at 120Hz, one at 60Hz, four at 24Hz, and 119 at 1Hz.

[0066] The refresh frame may include a programming operation interval PP and an emission operation interval EP. As mentioned above, the light-emitting device may emit light only during the emission operation interval EP, and may not emit light during the programming operation interval PP.

[0067] Frame skipping may consist of only the transmit operation interval EP (e.g., no programmed operation interval PP during frame skipping). Within the transmit operation interval EP, the transmit brightness of the previous refresh frame can be fully preserved.

[0068] The transmission interval EP for frame skipping can be longer than the transmission interval EP for refresh frames. Therefore, when comparing the luminance integral at a specific time, the luminance integral can increase as the refresh rate decreases (e.g., as the number of frame skips increases). For example, the luminance integral at a specific time can be higher at 60Hz than at 120Hz, higher at 24Hz than at 60Hz, and higher at 1Hz than at 24Hz.

[0069] Based on the comparison example above, flicker can be identified at the time of refresh rate changes (e.g., when the display switches from a 120Hz refresh rate to a 24Hz refresh rate) due to the difference in brightness integral based on refresh rate.

[0070] Figure 5 and Figure 6 This is a diagram illustrating a frequency conversion technique used in embodiments of this disclosure to determine the refresh rate based on the number of anode reset frames set between refresh frames.

[0071] Reference Figure 5 and Figure 6 The data refresh cycle implemented in the pixels of the display panel can vary based on refresh rate change information input from the host system. The data refresh cycle can increase as the refresh rate decreases, and the number of anode reset frames can increase as the refresh rate decreases. For example, the data refresh cycle can be 1 / 120th of a second at 120Hz, 1 / 60th of a second at 60Hz, 1 / 24th of a second at 24Hz, and 1 second at 1Hz. The number of anode reset frames set between two adjacent refresh frames can be zero at 120Hz, one at 60Hz, four at 24Hz, and 119 at 1Hz.

[0072] The refresh frame may include a programming operation interval PP and an emission operation interval EP. As mentioned above, the light-emitting device may emit light only during the emission operation interval EP, or it may not emit light during the programming operation interval PP.

[0073] The anode reset frame may include an anode reset interval PP' arranged before the transmit operation interval EP. During the transmit operation interval EP, the emission brightness of the previous refresh frame can be fully maintained. The anode reset interval PP' may correspond to the programming operation interval PP of the refresh frame, and when the anode reset voltage Vrst is applied to the anode electrode of the light-emitting device during the anode reset interval PP', the light-emitting device may not emit light.

[0074] The length of the anode reset interval PP' can be equal to or approximately equal to the length of the programming operation interval PP, so that the luminance integral of the anode reset frame is equal to or approximately equal to the luminance integral of the refresh frame.

[0075] According to the above implementation method, the difference in luminance integral amount based on refresh rate may not occur, and therefore, flickering caused by the difference in luminance integral amount can be prevented.

[0076] Figure 7 It shows the... Figure 2 The image shows the pixels for which refresh operations are performed. These operations can be performed within the programmed interval (PP) of the refresh frame. Figure 7 The refresh operation.

[0077] Reference Figure 7 During the programming operation interval PP of the refresh frame, when the first scan signal SCAN1 and the second scan signal SCAN2 are input at an ON level, the first switching element T1 to the third switching element T3 can be turned on. When the first switching element T1 to the third switching element T3 are turned on, nodes A, B, and D can be refreshed to the new data voltage Vdata, and node C can be initialized to the initialization voltage Vini. Here, the new data voltage Vdata can be the flicker compensation data voltage.

[0078] This refresh operation can be performed with the fourth switch element T4 and the fifth switch element T5 turned off. During the refresh operation, the light-emitting device EL may not emit light.

[0079] Figure 8 It shows the... Figure 2 The graph shows the pixels that have undergone hold operations. These operations can be performed during the emit operation interval (EP) of the refresh frame. Figure 8 The operation is maintained.

[0080] Reference Figure 8 During the transmit operation interval EP of the refresh frame, the first scan signal SCAN1 and the second scan signal SCAN2 are input at an off level, and the first transmit signal EM1 and the second transmit signal EM2 can be input at an on level. When the first switching element T1 to the third switching element T3 are off and the fourth switching element T4 and the fifth switching element T5 are on, the light-emitting device EL can emit light using the drive current Iel. The drive current Iel can be determined based on the gate-source voltage of the drive element DT set in the programming operation interval PP.

[0081] Figure 9 It shows the... Figure 2 The diagram shows the anode reset operation performed on the pixels, which is performed between adjacent refresh frames. Figure 10 It is shown in Figure 9 A diagram illustrating an implementation of the anode reset voltage supplied to the pixel during the anode reset operation.

[0082] Figure 9 The anode reset operation can be performed within the anode reset interval PP' of the anode reset frame. (See reference...) Figure 9When the first scan signal SCAN1 and the second transmit signal EM2 are input at an on level while the second scan signal SCAN2 and the first transmit signal EM2 are input at an off level, an anode reset voltage Vrst can be supplied to node C through data line 14 and third switch element T3 and fifth switch element T5 during the anode reset interval PP'. The anode reset voltage Vrst supplied to node C can be applied to the anode electrode of the light-emitting device EL to turn off the light-emitting device EL. For this purpose, the anode reset voltage Vrst can be a voltage lower than the on-threshold voltage of the light-emitting device EL, such as... Figure 10 As shown.

[0083] Furthermore, during the anode reset operation, the first switching element T1, the second switching element T2, and the fourth switching element T4 remain in the off state.

[0084] In an anode reset frame, the transmit operation interval can be arranged next to or adjacent to the anode reset interval PP'. The transmit operation interval of the anode reset frame can be equal to or substantially the same as the transmit operation interval EP of the refresh frame.

[0085] Through the anode reset operation, the luminance waveform of the anode reset frame can be equal to the luminance waveform of the refresh frame. That is, through the anode reset operation, the luminance integral of the anode reset frame can be equal to the luminance integral of the refresh frame, and therefore, flickering caused by differences in luminance integral can be prevented.

[0086] According to the VRR technology of this disclosure, although flickering caused by differences in luminance integral quantity can be prevented as described above, grayscale response delay may occur when the anode reset frame changes to or is converted to a reset frame, and another problem may occur in which the grayscale response delay varies according to the data refresh cycle. Differences in the amount of grayscale response delay based on the data refresh cycle may be another cause of flickering.

[0087] The following section presents methods for compensating for grayscale response delay and the resulting flicker.

[0088] Figure 11 and Figure 12 This is a diagram illustrating the grayscale response delay phenomenon that occurs at time Tt when a refresh frame changes from an anode reset frame at the first grayscale level (e.g., black grayscale) to a second grayscale level (e.g., white grayscale). For example, a pixel transitions from black to a bright color, and a delayed step response corresponding to ΔLa and L1 can be observed.

[0089] Reference Figure 11In 60Hz refresh rate mode, based on a step-by-step scheme, the black grayscale level can first increase to a first grayscale level L1 (lower than the white grayscale level) at time change Tt, and then further increase from the first grayscale level L1 to the white grayscale level within the refresh frame. In other words, the black grayscale level can be increased via... Figure 11 The steps shown are increased.

[0090] Reference Figure 12 In 1Hz refresh rate mode, based on a step-by-step scheme, the black grayscale level can be increased to a second grayscale level L2 (below the white grayscale level) at time Tt, and then further increased from the second grayscale level L2 to the white grayscale level during the refresh frame. In other words, the black grayscale level can be increased via... Figure 12 The multiple steps shown are added. Here, the second gray level L2 can have a higher gray level than... Figure 11 The value of the first gray level L1 shown is a small value.

[0091] Therefore, grayscale response latency can increase and worsen as the refresh rate decreases. For example, in Figure 11 In the 60Hz refresh rate mode shown, the grayscale response latency can be ΔLa, and... Figure 12 In the 1Hz refresh rate mode shown, the grayscale response delay can be ΔLb. Here, ΔLb can be greater than ΔLa. The reason is that in the 60Hz refresh rate mode, the data refresh cycle is 1 / 60 of a second, and the time used to maintain the black-grayscale level through the anode reset frame is 1 / 120 of a second. In the 1Hz refresh rate mode, the data refresh cycle is 1 second, and the time used to maintain the black-grayscale level through the anode reset frame is 59 / 60 seconds. Compared to the 60Hz refresh rate mode, in the 1Hz refresh rate mode, because the time used to maintain the black-grayscale level through the anode reset frame is relatively longer, the grayscale response delay can be relatively larger. In other words, compared to the 60Hz refresh rate mode, in the 1Hz refresh rate mode, because the number of anode reset frames is relatively larger, the grayscale response delay can be relatively larger.

[0092] Such differences in grayscale response delay can cause brightness deviations in refreshed frames. Furthermore, this type of brightness deviation can lead to flickering in refreshed frames.

[0093] Figure 13 and Figure 14 This is a graph illustrating the grayscale response delay that occurs at time Tt when an anode reset frame at the first grayscale level (e.g., white grayscale) is changed to or converted to a refresh frame at the second grayscale level (e.g., black grayscale). For example, this is the case where a pixel transitions from a bright color to black.

[0094] Reference Figure 13In 60Hz refresh rate mode, based on a step-by-step scheme, the white grayscale level can be reduced to a third grayscale level L3, higher than the black grayscale level, at time Tt. Furthermore, within the refresh frame, it can be further reduced from the third grayscale level L3 to finally reach the black grayscale level. In other words, it can be achieved through... Figure 13 The steps shown are for reducing the white gray level.

[0095] Reference Figure 14 In 1Hz refresh rate mode, based on a step-by-step scheme, the white grayscale level can be reduced to a fourth grayscale level L4, much higher than the black grayscale level, at time Tt, and then further reduced from the fourth grayscale level L4 to the black grayscale level during the refresh frame. In other words, the white grayscale level can be reduced via... Figure 14 The process involves multiple steps to reduce gray levels. Here, the fourth gray level L4 can have a higher gray level than... Figure 13 The value of the third gray level L3 shown is the largest.

[0096] Therefore, the grayscale response latency can increase as the refresh rate decreases or the data refresh cycle becomes longer. For example, in Figure 13 In the 60Hz refresh rate mode shown, the grayscale response latency can be ΔLc, and... Figure 14 In the 1Hz refresh rate mode shown, the grayscale response delay can be ΔLd. Here, ΔLd can be greater than ΔLc. The reason is that in the 60Hz refresh rate mode, the data refresh cycle is 1 / 60 of a second, and the time used to maintain the white grayscale level through the anodized reset frame is 1 / 120 of a second. In the 1Hz refresh rate mode, the data refresh cycle is 1 second, and the time used to maintain the white grayscale level through the anodized reset frame is 59 / 60 seconds. Compared to the 60Hz refresh rate mode, in the 1Hz refresh rate mode, the grayscale response delay can be relatively larger because the time used to maintain the white grayscale level through the anodized reset frame is relatively longer. In other words, compared to the 60Hz refresh rate mode, in the 1Hz refresh rate mode, the grayscale response delay can be relatively larger because the number of anodized reset frames is relatively larger. In other words, a slower refresh rate may result in a poorer response time when transitioning from black to bright colors and from bright colors to black.

[0097] Such differences in grayscale response delay can cause brightness deviations in refreshed frames. Furthermore, these brightness deviations can lead to flickering in refreshed frames.

[0098] Figures 15A to 15CThis diagram illustrates examples of setting the level of the flicker compensation data voltage differently based on the refresh rate (or the number of anode reset frames) to compensate for flicker caused by differences in the amount of grayscale response delay. For example, the data voltage can be adjusted to have an underdamped waveform to provide optimal transition for pixels when changing from black to bright colors.

[0099] Figures 15A to 15C This paper presents a concept for compensating for grayscale response delay that occurs at time Tt when the anode reset frame of the first grayscale level (black grayscale level) is changed to the refresh frame of the second grayscale level (white grayscale level).

[0100] Reference Figure 15A In a low refresh rate mode with a grayscale response delay of ΔLx, the data driver can output a flicker compensation data voltage with a first level to the pixel in a refresh frame. The flicker compensation data voltage with the first level can be a compensation voltage used to minimize the grayscale response delay of ΔLx, and can be a data voltage of a third grayscale level obtained by reflecting a first weight WT1 in the data voltage of the second grayscale level.

[0101] Reference Figure 15B In a medium refresh rate mode with a grayscale response delay of ΔLy, the data driver can output a flicker compensation data voltage with a second level to the pixel in a refresh frame. The flicker compensation data voltage with the second level can be a compensation voltage used to minimize the grayscale response delay of ΔLy, and can be a data voltage of a fourth grayscale level obtained by reflecting a second weight WT2 in the data voltage of the second grayscale level.

[0102] Reference Figure 15C In a high refresh rate mode with a grayscale response delay of ΔLz, the data driver can output a flicker compensation data voltage with a third level to the pixel in a refresh frame. The flicker compensation data voltage with the third level can be a compensation voltage used to minimize the grayscale response delay of ΔLz, and can be a data voltage of a fifth grayscale level obtained by reflecting a third weight WT3 in the data voltage of the second grayscale level.

[0103] exist Figures 15A to 15CIn this context, ΔLx > ΔLy > ΔLz, and WT1 > WT2 > WT3. Furthermore, each of the first weight WT1 to the third weight WT3 can be an increasing weight, and each of the data voltages of the third to fifth gray levels can be higher than the data voltage of the target second gray level. Among the data voltages of the third to fifth gray levels, the data voltage of the third gray level can be the highest, the data voltage of the fourth gray level can be the second highest, and the data voltage of the fifth gray level can be the lowest. For example, when the refresh rate slows down or the data refresh cycle becomes longer, a larger weight can be applied for compensation, while a faster refresh rate uses less compensation.

[0104] also, Figures 15A to 15C The compensation concept shown can be applied to compensate for the grayscale response delay that occurs at time Tt when the white grayscale level anode reset frame is changed to a black grayscale level refresh frame.

[0105] In this case, △Lx > △Ly > △Lz, and WT1 > WT2 > WT3. Furthermore, each of the first weight WT1 to the third weight WT3 can be a decreasing weight, and each of the data voltages of the third to fifth gray levels can be lower than the data voltage of the target second gray level. Among the data voltages of the third to fifth gray levels, the data voltage of the third gray level can be the lowest, the data voltage of the fourth gray level can be the second lowest, and the data voltage of the fifth gray level can be the highest.

[0106] Furthermore, each of the aforementioned first weights WT1 to third weights WT3 can be a first global weight, which is applied as a whole to (e.g., by the screen unit) the data voltage of a screen at the corresponding refresh rate.

[0107] The first global weight can be further adjusted by the screen unit based on a second global weight that is proportional to the average amount of data voltage conversion applied to the screen of the display panel during the refresh frame, and thus, the grayscale response delay that occurs at time Tt when the anode reset frame changes to the refresh frame can be reduced more effectively.

[0108] Furthermore, the first global weight can be further adjusted through the pixel row unit based on the line weight, which is also proportional to the distance between the pixel row and the output terminal of the data driver, and thus, the grayscale response delay that occurs at time Tt when the anode reset frame changes to a refresh frame can be reduced more effectively.

[0109] Figure 16 This is a table showing detailed examples of how different weights are set based on the refresh rate to reflect in the data voltage of the input grayscale level in order to adjust the level of the flicker compensation data voltage.

[0110] Reference Figure 16 Low refresh rate mode corresponds to a refresh rate of less than 30Hz, medium refresh rate mode corresponds to a refresh rate of 30Hz to 60Hz, and high refresh rate mode corresponds to a refresh rate of 60Hz to 120Hz.

[0111] exist Figure 16 In this context, the case where a black-grayscale anode reset frame is changed or converted to a white-grayscale refresh frame can be represented as a case of grayscale increase or grayscale increase type. Furthermore, the case where a white-grayscale anode reset frame is changed or converted to a black-grayscale refresh frame can be represented as a case of grayscale decrease or grayscale decrease type.

[0112] exist Figure 16 In this context, the output can be flicker compensation data voltage, and the input can be the target data voltage for refreshing the frame. The target data voltage can be the data voltage for the white grayscale level when grayscale increases, and it can also be the data voltage for the black grayscale level when grayscale decreases. Figure 16 In this context, the numbers multiplied, added, or subtracted from the input can represent either an increase or decrease in weight.

[0113] In low refresh rate mode, the flicker compensation data voltage when grayscale increases can be "(data voltage of white grayscale level * 1.3) + 10", and the flicker compensation data voltage when grayscale decreases can be "(data voltage of black grayscale level * 0.9) - 5".

[0114] In medium refresh rate mode, the flicker compensation data voltage when grayscale increases can be "(data voltage of white grayscale level * 1.2) + 7", and the flicker compensation data voltage when grayscale decreases can be "(data voltage of black grayscale level * 0.95) - 3".

[0115] In high refresh rate mode, the flicker compensation data voltage when grayscale increases can be "(data voltage of white grayscale level * 1.1) + 5", and the flicker compensation data voltage when grayscale decreases can be "(data voltage of black grayscale level * 1.0) - 1".

[0116] As mentioned above, the flicker compensation data voltage during grayscale increase can be highest in low refresh rate mode, second highest in medium refresh rate mode, and lowest in high refresh rate mode. Furthermore, the flicker compensation data voltage during grayscale decrease can be lowest in low refresh rate mode, second lowest in medium refresh rate mode, and highest in high refresh rate mode.

[0117] The arithmetic operation to generate the above-mentioned flicker compensation data voltage can be performed by the timing controller 11 in digital mode.

[0118] Figure 17 It is shown that it is used for Figure 16 The diagram shows the configuration of the timing controller 11 for data adjustment operations.

[0119] Reference Figure 17 The timing controller 11 may include a data receiver 111, a refresh rate setting unit 112 (e.g., a refresh rate setting circuit), a refresh frame buffer 113, a data conversion extractor 114, an anode reset frame counter 115, a pixel row position extractor 116, a weight generator 117, a data modulator 118, a data transmitter 119, and a control signal generator 120.

[0120] The data receiver 111 can be connected to the host system via an internal interface and can receive video data DATA and timing signals DE, Vsync, and Hsync from the host system. Furthermore, the data receiver 111 can receive refresh rate change information from the host system.

[0121] The refresh rate setting unit 112 can adjust the number of anode reset frames set between adjacent refresh frames based on refresh rate change information, thereby changing the refresh period of digital video data DATA. As the refresh rate decreases or slows down, the number of anode reset frames set between adjacent refresh frames can be increased, and the data refresh period can be lengthened.

[0122] The refresh frame buffer 113 can store the image data of one screen (previous frame data) at each refresh frame.

[0123] The data conversion extractor 114 can calculate the average conversion amount of image data (current frame data) to be applied to the display panel for one screen during a refresh frame. The data conversion extractor 114 can compare the current frame data with the previous frame data stored in the refresh frame buffer 113 to calculate the average conversion amount of the current frame data.

[0124] The anode reset frame counter 115 can count the number of anode reset frames based on the refresh rate.

[0125] The pixel row position extractor 116 can analyze the position of the pixel row in the current frame data to which the corresponding image data has been applied, and thus can extract the pixel row position of the image data.

[0126] The weight generator 117 can generate weights corresponding to the current frame data through the screen unit based on the number of anode reset frames. The weights can increase as the number of anode reset frames increases.

[0127] The weight generator 117 can further adjust the generated weights via screen units based on a global weight proportional to the average conversion amount of the current frame data. The global weight can increase as the average conversion amount of the current frame data increases. The weight generator 117 can further adjust the generated weights via pixel row units based on line weights based on the pixel row positions of the image data. When the pixel row positions of the image data are located far from the data driver (e.g., to compensate for voltage drops due to long wiring lengths), the line weights can be increased.

[0128] The data modulator 118 can reflect the weights generated by the weight generator 117 in the current frame data to modulate the current frame data.

[0129] Data transmitter 119 can transmit modulated current frame data DATAm to data driver based on refresh frames.

[0130] The control signal generator 120 can generate and output control signals DDC and GDC for use in controlling the operation timing of the data driver and the gate driver based on timing signals DE, Vsync and Hsync.

[0131] Figure 18 This is a flowchart illustrating an example where the data refresh cycle varies based on the peak brightness of the entire image. Figure 19A and Figure 19B This is a diagram illustrating an example where the duration of the hold period arranged between adjacent refresh frames varies based on the peak brightness of the entire image. Figure 20A and Figure 20B This is another flowchart illustrating how the length of the hold period arranged between adjacent refresh frames varies based on the peak brightness of the entire image.

[0132] like Figure 18 As shown, when a frame of image data is input, the timing controller according to this embodiment can calculate the peak brightness of the image data (S181 and S182). The peak brightness can be the brightness value of the image data with the highest brightness in a frame of image data.

[0133] The timing controller can adjust the refresh rate when displaying one frame of image data based on the calculated peak brightness (S183). Since the user's eye is more likely to perceive flicker in a dark image than in a bright image, the timing controller can increase the refresh rate in a dark image (i.e., peak brightness < reference value) to improve flicker (S185). In addition, the timing controller can decrease the refresh rate in a bright image (i.e., peak brightness ≥ reference value) to reduce power consumption (S184).

[0134] The timing controller can output image data to the data driver based on the adjusted refresh rate (S186).

[0135] Reference Figures 19A to 20B The duration of image retention can vary based on the adjusted refresh rate.

[0136] As in Figure 19A and Figure 20A In the case of displaying a bright image A when the peak brightness of the entire image held in the display panel is greater than or equal to a reference value, the holding period between the first refresh frame and the second refresh frame can have a first time length. On the other hand, as in Figure 19B and Figure 20B In the case of displaying a dark image B when the peak brightness of the entire image held in the display panel is less than a reference value, the hold period between the first refresh frame and the second refresh frame can have a second time length shorter than the first time length. As the length of the hold period increases, the number of skip frames or anode reset frames included in the hold period can increase. During the hold period, the screen of the display panel is not updated with a new image.

[0137] The timing controller and the data driver can transmit image data between them via an interface circuit. The interface circuit may include a TX circuit in the timing controller and an RX circuit in the data driver. The TX circuit can transmit first image data corresponding to a data voltage having a first grayscale level to the RX circuit in a first refresh frame, and can transmit second image data corresponding to a data voltage having a second grayscale level to the RX circuit in a second refresh frame.

[0138] As in Figures 19A to 20B In the bright image A, where the hold period is relatively long, the power consumption reduction effect is greater because the interface circuit is turned off during the hold period. Furthermore, in the dark image B, power consumption is reduced because the interface circuit is turned off during the hold period.

[0139] Figure 21 This is a flowchart illustrating an example where the data refresh cycle varies based on the size of consecutive low-grayscale areas throughout the region.

[0140] As in Figure 21 In this embodiment, when a frame of image data is input, the timing controller can calculate the size of a continuous low grayscale region in the image data (S211 and S212). The continuous low grayscale region can represent a region with a brightness less than or equal to a predetermined brightness (e.g., black grayscale level).

[0141] The timing controller can adjust the refresh rate when displaying a frame of image data based on the calculated size of the low grayscale area (S213). Because the user's eye is more likely to perceive flicker in a dark image than in a bright image, the timing controller can increase the refresh rate in the dark image (i.e., the size of the low grayscale area < reference value) to improve flicker (S215). In addition, the timing controller can decrease the refresh rate in the bright image (i.e., the size of the low grayscale area ≥ reference value) to reduce power consumption (S214).

[0142] The timing controller can output image data to the data driver based on the adjusted refresh rate (S216).

[0143] As in Figure 19A and Figure 20A In the case of displaying a bright image A when the size of the low grayscale area of ​​the entire image held in the display panel is greater than or equal to a reference value, the holding period between the first refresh frame and the second refresh frame can have a first time length. On the other hand, as in Figure 19B and Figure 20B In the case of displaying a dark image B when the size of the low grayscale area of ​​the entire image held in the display panel is smaller than a reference value, the hold period between the first refresh frame and the second refresh frame can have a second time length that is shorter than the first time length. As the length of the hold period increases, the number of skip frames or anode reset frames included in the hold period can increase. During the hold period, the screen of the display panel is not updated with a new image.

[0144] The timing controller and the data driver can transmit image data between them via an interface circuit. The interface circuit may include a TX circuit in the timing controller and an RX circuit in the data driver. The TX circuit can transmit first image data corresponding to a data voltage having a first grayscale level to the RX circuit in a first refresh frame, and can transmit second image data corresponding to a data voltage having a second grayscale level to the RX circuit in a second refresh frame.

[0145] As in Figures 19A to 20B In the bright image A, where the hold period is relatively long, the power consumption reduction effect is greater because the interface circuit is turned off during the hold period. Furthermore, in the dark image B, power consumption is reduced because the interface circuit is turned off during the hold period.

[0146] Figure 22 This is a flowchart illustrating an example where the data refresh cycle varies based on the viewing distance of a user viewing the display panel.

[0147] As in Figure 22In this embodiment, when a frame of image data is input, the timing controller can calculate the viewing distance of the user viewing the display panel based on the user image obtained from the camera device (S221 and S222). The camera device can be pre-installed in the display panel.

[0148] The timing controller can adjust the refresh rate when displaying a frame of image data based on the calculated viewing distance to the user (S223). Since the user's eye perceives flicker more easily when viewing the image at a close distance than when viewing it at a far distance, the timing controller can increase the refresh rate at close viewing distances (i.e., viewing distance < reference value) to reduce flicker (S225). Furthermore, the timing controller can decrease the refresh rate at far viewing distances (i.e., viewing distance ≥ reference value) to reduce power consumption (S224).

[0149] The timing controller can output image data to the data driver based on the adjusted refresh rate (S226).

[0150] As in Figure 19A and Figure 20A In the context of viewing image A, when the viewing distance of the user viewing image A is greater than or equal to a reference value, the hold period between the first refresh frame and the second refresh frame can have a first time length. On the other hand, as in... Figure 19B and Figure 20B In this process, when the viewing distance of the user viewing image B is less than a reference value, the hold period between the first refresh frame and the second refresh frame can have a second time length that is shorter than the first time length. As the length of the hold period increases, the number of skip frames or anode reset frames included in the hold period can increase. During the hold period, the display panel screen is not updated with a new image.

[0151] The timing controller and the data driver can transmit image data between them via an interface circuit. The interface circuit may include a TX circuit in the timing controller and an RX circuit in the data driver. The TX circuit can transmit first image data corresponding to a data voltage having a first grayscale level to the RX circuit in a first refresh frame, and can transmit second image data corresponding to a data voltage having a second grayscale level to the RX circuit in a second refresh frame.

[0152] As in Figures 19A to 20B Because the interface circuitry is switched off during the hold-up period, the power consumption reduction effect is significantly amplified at relatively long viewing distances. Furthermore, at close viewing distances, power consumption is reduced because the interface circuitry is switched off during the hold-up period.

[0153] The electroluminescent display device according to this disclosure can be based on VRR technology, wherein the data refresh period varies based on the attributes of the input image. The electroluminescent display device according to this disclosure can adjust the level of the flicker compensation data voltage based on the data refresh period to prevent flickering at the time of refresh rate change in the anode reset frame, thereby improving display quality.

[0154] The electroluminescent display device according to this disclosure can change the data refresh cycle based on the peak brightness of a screen, the size of the low grayscale area, or the viewing distance to the user to reduce flicker, and can shut down the interface circuit between the timing controller and the data driver during the hold period between adjacent refresh frames, thereby reducing power consumption.

[0155] The effects of this disclosure are not limited to the examples above, and various other effects may be included in the specification.

[0156] While this disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as defined by the appended claims.

Claims

1. An electroluminescent display device, comprising: The display panel includes at least one pixel; as well as The data drive is configured as follows: In the first refresh frame, the data voltage of the first grayscale level is output to the at least one pixel. In the second refresh frame, flicker compensation data voltage is output to the at least one pixel, and In at least one anode reset frame arranged between the first refresh frame and the second refresh frame, an anode reset voltage is output to the anode electrode of the light-emitting device included in the at least one pixel. Wherein, the anode reset voltage is the voltage used to turn off the light-emitting device, and Specifically, the flicker compensation data voltage is generated by applying weights to the data voltage of the second gray level. Wherein, when the number of anode reset frames between the first refresh frame and the second refresh frame is N, the flicker compensation data voltage is generated based on the first weight, and Wherein, when the number of anode reset frames between the first refresh frame and the second refresh frame is M, the flicker compensation data voltage is generated based on a second weight that is different from the first weight, where N is a natural number and M is a natural number greater than N.

2. The electroluminescent display device according to claim 1, wherein, When the number of anode reset frames between the first refresh frame and the second refresh frame is N, the flicker compensation data voltage is different from the flicker compensation data voltage when the number of anode reset frames between the first refresh frame and the second refresh frame is M.

3. The electroluminescent display device according to claim 1, wherein, The anode reset voltage is supplied during a portion of the anode reset frame.

4. The electroluminescent display device according to claim 1, wherein, When the data voltage of the second gray level is higher than the data voltage of the first gray level The flicker compensation data voltage is higher than the data voltage of the second gray level, and The first weight and the second weight correspond to the first rising weight and the second rising weight, respectively.

5. The electroluminescent display device according to claim 4, wherein, The second upward weight is greater than the first upward weight.

6. The electroluminescent display device according to claim 5, wherein, The levels of the first and second upweights are adjusted based on global weights that are proportional to the average amount of data voltage to be supplied to the display panel in the second refresh frame.

7. The electroluminescent display device according to claim 5, wherein, The levels of the first and second upweights are adjusted based on line weights that are proportional to the distance between the pixel row including the at least one pixel and the output terminal of the data driver.

8. The electroluminescent display device according to claim 1, wherein, When the data voltage of the second gray level is lower than the data voltage of the first gray level The flicker compensation data voltage is lower than the data voltage of the second gray level, and The first weight and the second weight correspond to the first decreasing weight and the second decreasing weight, respectively.

9. The electroluminescent display device according to claim 8, wherein, The second decrease weight is less than the first decrease weight.

10. The electroluminescent display device according to claim 9, wherein, The levels of the first and second decrease weights are adjusted based on global weights that are proportional to the average amount of data voltage to be supplied to the display panel in the second refresh frame.

11. The electroluminescent display device according to claim 9, wherein, The levels of the first and second decrease weights are adjusted based on line weights that are proportional to the distance between the pixel row including the at least one pixel and the output terminal of the data driver.

12. The electroluminescent display device according to claim 1, wherein, When the peak brightness of the entire image held in the display panel is greater than or equal to a reference value, the holding period between the first refresh frame and the second refresh frame has a first time length, and When the peak brightness of the entire image is less than the reference value, the hold period between the first refresh frame and the second refresh frame has a second time length that is less than the first time length.

13. The electroluminescent display device according to claim 1, wherein, When the size of a low grayscale region with a predetermined brightness less than or equal to the total brightness of the image held in the display panel is greater than or equal to a reference value, the holding period between the first refresh frame and the second refresh frame has a first time length, and When the size of the low grayscale region is smaller than the reference value, the hold period between the first refresh frame and the second refresh frame has a second time length that is shorter than the first time length.

14. The electroluminescent display device according to claim 1, wherein, When the viewing distance of a user viewing the display panel is greater than or equal to a reference value, the holding period between the first refresh frame and the second refresh frame has a first time length, and When the viewing distance to the user is less than the reference value, the holding period between the first refresh frame and the second refresh frame has a second time length that is less than the first time length.

15. The electroluminescent display device according to any one of claims 12 to 14, further comprising an interface circuit configured to transmit first image data corresponding to a data voltage having the first gray level in the first refresh frame between a timing controller and the data driver, and to transmit second image data corresponding to a data voltage having the second gray level in the second refresh frame between the timing controller and the data driver, and The interface circuit is turned off during the hold period.

16. A data driver configured to: In the first refresh frame, the data voltage of the first grayscale level is output to at least one pixel. In the second refresh frame, flicker compensation data voltage is output to the at least one pixel, and In at least one anode reset frame arranged between the first refresh frame and the second refresh frame, an anode reset voltage is output to the anode electrode of the light-emitting device included in the at least one pixel. in, The anode reset voltage is the voltage used to turn off the light-emitting device, and Specifically, the flicker compensation data voltage is generated by applying weights to the data voltage of the second gray level. Wherein, when the number of anode reset frames between the first refresh frame and the second refresh frame is N, the flicker compensation data voltage is generated based on the first weight, and Wherein, when the number of anode reset frames between the first refresh frame and the second refresh frame is M, the flicker compensation data voltage is generated based on a second weight that is different from the first weight, where N is a natural number and M is a natural number greater than N.

17. The data driver of claim 16, wherein, The anode reset voltage is supplied during a portion of the anode reset frame, and Specifically, when the number of anode reset frames between the first refresh frame and the second refresh frame is N, the flicker compensation data voltage is different from the flicker compensation data voltage when the number of anode reset frames between the first refresh frame and the second refresh frame is M.

18. The data driver of claim 16, wherein, When the data voltage of the second gray level is higher than the data voltage of the first gray level The flicker compensation data voltage is higher than the data voltage of the second gray level, and The first weight and the second weight correspond to the first rising weight and the second rising weight, respectively.

19. The data driver according to claim 18, wherein, The second upward weight is greater than the first upward weight.

20. The data driver of claim 16, wherein, When the data voltage of the second gray level is lower than the data voltage of the first gray level The flicker compensation data voltage is lower than the data voltage of the second gray level, and The first weight and the second weight correspond to the first decreasing weight and the second decreasing weight, respectively.

21. The data driver according to claim 20, wherein, The second decrease weight is less than the first decrease weight.

22. A method for driving an electroluminescent display device, the method comprising: In the first refresh frame, the data voltage of the first grayscale level is output to the pixels of the display panel; In the second refresh frame, flicker compensation data voltage is output to the pixel; as well as In one or more anode reset frames arranged between the first refresh frame and the second refresh frame, an anode reset voltage is output to the anode electrode of the light-emitting device included in the pixel. Wherein, the anode reset voltage is the voltage used to turn off the light-emitting device, and Specifically, the flicker compensation data voltage is generated by applying weights to the data voltage of the second gray level. Wherein, when the number of anode reset frames between the first refresh frame and the second refresh frame is N, the flicker compensation data voltage is generated based on the first weight, and Wherein, when the number of anode reset frames between the first refresh frame and the second refresh frame is M, the flicker compensation data voltage is generated based on a second weight that is different from the first weight, where N is a natural number and M is a natural number greater than N.

23. The method according to claim 22, wherein, The first refresh frame and the second refresh frame are supplied based on the set refresh rate, and the number of the one or more anode reset frames arranged between the first refresh frame and the second refresh frame increases as the period of the refresh rate increases.

Images