Chip Fault Injection Robustness Evaluation Method and System
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TIANJIN UNIV
- Filing Date
- 2023-02-21
- Publication Date
- 2026-07-17
Smart Images
Figure CN116312712B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit security assessment technology, specifically to a method and system for evaluating the robustness of chip anti-fault injection security. Background Technology
[0002] With the rapid development of electronic design automation technology and semiconductor manufacturing processes, monolithic digital integrated circuit chips are becoming increasingly complex in function, larger in scale, and higher in integration, leading to their widespread application in various fields of modern technology, particularly in financial equipment, mobile communications, transportation, and energy. Consequently, information security issues are becoming increasingly prominent, making the security of memory chips—that is, their ability to resist malicious attacks—a paramount concern. Therefore, testing and evaluating the security of secure memory chips before their actual deployment is of utmost importance.
[0003] Attack techniques on integrated circuits can be divided into two categories: side-channel attacks, which mainly include power analysis attacks, electromagnetic analysis attacks, and time analysis attacks; and fault injection attacks. Fault injection attacks, as a type of physical attack, maliciously inject faults, posing a serious threat to hardware security. The basic principle of fault injection attacks is that attackers use clock glitches, lasers, or electromagnetic methods to intentionally inject faults into specific parts of the chip during the operation of the cryptographic device, causing the chip to malfunction. By analyzing and comparing the faulty ciphertext with the correct ciphertext, attackers can obtain part or all of the key stored within the secure chip. Compared to side-channel attacks, fault injection attacks can significantly reduce the number of samples required for analysis, increasing attack efficiency and seriously threatening integrated circuit security.
[0004] Fault injection attacks aim to inject faults into circuits through artificial means, altering internal control flow or state data to achieve purposes such as disrupting functionality, bypassing authorization, and stealing critical information. Common fault injection methods include clock fault injection, voltage fault injection, and electromagnetic fault injection. After fault injection, attackers can directly use the injected fault to bypass access conditions or modify critical bits to carry out their attacks, or they can indirectly use the injected fault to extract critical information from the circuit through Differential Fault Analysis (DFA). For secure storage chips, the confidentiality and integrity of sensitive data are paramount. The leakage of sensitive information such as passwords and encryption keys can cause irreparable damage and consequences to the chip and even the entire system.
[0005] Fault injection attacks pose a significant threat to integrated circuits. To protect the information in memory chips, designers typically employ techniques to resist fault injection attacks, such as metal layer shielding against electromagnetic radiation fault injection attacks, asynchronous processors with random clock signals against clock glitch fault injection attacks, and adding redundant computing circuits against voltage glitch fault injection attacks. These techniques can effectively resist fault injection attacks to a certain extent.
[0006] In related technologies, Chinese invention patent application CN110598398A discloses a chip security assessment method based on steady-state faults. This method assesses chip security by statistically analyzing the proportion of points that can cause steady-state faults out of all scan points. The chip's SRAM cells store critical sensitive information for cryptographic algorithms (such as S-box data in symmetric encryption algorithms) in consecutive bytes, and the SRAM cell array is arranged in a matrix, meaning these consecutive bytes are stored in one or more areas of the SRAM. However, when injecting faults using laser scanning, the number of scan points has limited coverage over a planar area, making it impossible to exhaustively identify all points that might leak sensitive information by scanning fault points. Therefore, this method, which assesses chip security based on the proportion of points that can cause steady-state faults out of all scan points, has limitations in accuracy.
[0007] The Chinese invention patent application with publication number CN107818271A discloses a fault injection analysis method based on chip layout. It distinguishes and marks different chip regions on the layout according to their different sensitivities to fault injection, and quickly locates sensitive areas; instead of assessing chip security. Summary of the Invention
[0008] The technical problem to be solved by this invention is how to achieve accurate evaluation of chip security.
[0009] The present invention solves the above-mentioned technical problems through the following technical means:
[0010] In a first aspect, the present invention proposes a method for evaluating the robustness of chip anti-fault injection security, the method comprising:
[0011] The fault injection technique is used to scan and inject faults point by point in the SRAM region of the chip under test, and the effective fault injection points are counted.
[0012] Dilate the pixels of all valid fault injection points to generate connected components;
[0013] The ratio of the area of the connected region to the area of the SRAM region is used as the effective fault injection success rate of the chip under test.
[0014] Furthermore, the fault injection technique is used to scan and inject faults point-by-point into the SRAM region of the chip under test, and the effective fault injection points are counted, including:
[0015] The SRAM region of the chip to be tested is meshed to obtain a mesh matrix;
[0016] Fault injection technology is used to inject faults at each grid intersection in the primary grid.
[0017] The chip encryption algorithm is triggered at each fault injection point, and the algorithm execution result at each fault injection point is recorded.
[0018] All fault injection points that cause errors in chip operation results are selected as valid fault injection points.
[0019] Furthermore, the process of dilating the pixels of all valid fault injection points to generate connected components includes:
[0020] Mark all valid fault injection points in the infrared image of the SRAM region;
[0021] Dilation is performed on the pixels corresponding to all valid fault injection points in the infrared image of the SRAM region to generate connected components.
[0022] Furthermore, the step of performing dilation processing on the pixels corresponding to all valid fault injection points in the infrared image of the SRAM region to generate connected components specifically includes:
[0023] An image enhancement algorithm is used to enhance the infrared image of the SRAM region in order to highlight the SRAM region in the chip layout.
[0024] A Gaussian filtering algorithm is used to smooth and reduce noise in the infrared image of the SRAM region, thereby suppressing background noise and improving the image signal-to-noise ratio.
[0025] An image binarization algorithm is used to set the grayscale value of the valid fault injection points marked in the infrared image of the SRAM region to 255, thereby obtaining a binary image;
[0026] A morphological processing algorithm is used to set the structuring element as a circle of a specified size, and to dilate the pixels of the effective fault injection points in the binary image.
[0027] A connected component labeling algorithm is used to process the dilated effective fault injection points in the binary image into various connected components.
[0028] Furthermore, after identifying all fault injection points that cause erroneous chip operation results as valid fault injection points, the method further includes:
[0029] The secondary scanning area is determined by taking at least m effective fault injection points on the outermost side of the first grid in both the vertical and horizontal directions as boundaries;
[0030] The secondary scanning area is meshed to obtain a secondary mesh array, wherein the mesh spacing in the secondary mesh array is smaller than the mesh spacing in the primary mesh array.
[0031] Fault injection technology is used to inject faults at each grid intersection in the secondary grid, and the effective fault injection points are counted as secondary effective fault injection points.
[0032] Accordingly, the process of dilating the pixels of all valid fault injection points to generate connected components specifically involves:
[0033] Dilate the pixels of all secondary valid fault injection points to generate connected components.
[0034] Furthermore, before scanning and injecting faults point-by-point in the SRAM region of the chip under test using fault injection technology and counting the effective fault injection points, the method further includes:
[0035] Remove the package from the chip to be tested and perform a mold removal process using chemical agents;
[0036] After cleaning the chip under test using an ultrasonic cleaning tank, the location of the SRAM cell of the chip under test is determined.
[0037] The chip to be tested is fixed on the three-dimensional moving platform of the laser fault injection device.
[0038] Furthermore, after using the ratio of the area of the connected region to the area of the SRAM region as the effective fault injection success rate of the chip under test, the method further includes:
[0039] The robustness of the chip under test against fault injection is evaluated based on the quantification level of the effective fault injection success rate.
[0040] Secondly, the present invention also proposes a chip fault injection security robustness evaluation system, the system comprising:
[0041] The statistics module is used to scan and inject faults point by point in the SRAM region of the chip under test using fault injection technology, and to count the effective fault injection points.
[0042] The connected component generation module is used to dilate the pixels of all valid fault injection points to generate connected components.
[0043] The effective fault injection success rate calculation module is used to take the ratio of the area of the connected domain to the area of the SRAM region as the effective fault injection success rate of the chip under test.
[0044] Furthermore, the statistics module includes:
[0045] Mesh cells are used to perform meshing operations on the SRAM region of the chip under test to obtain a single mesh dot matrix;
[0046] The fault injection unit is used to inject a fault at each grid intersection in the primary grid using fault injection technology.
[0047] The encryption operation unit is used to trigger the chip encryption algorithm for each fault injection point and record the algorithm execution result at each fault injection point.
[0048] The filtering unit is used to filter out all fault injection points that cause errors in chip operation results, and then use them as valid fault injection points.
[0049] Furthermore, the connected component generation module includes:
[0050] An annotation unit is used to annotate all valid fault injection points in the infrared image of the SRAM region;
[0051] The connected component generation unit is used to perform dilation processing on the pixels corresponding to all valid fault injection points in the infrared image of the SRAM region to generate connected components.
[0052] Furthermore, the system also includes:
[0053] The region determination module is used to determine the secondary scanning region by taking at least m effective fault injection points on the outermost side of the longitudinal and transverse directions of the primary grid as boundaries.
[0054] A secondary grid point matrix generation module is used to perform a gridding operation on the secondary scanning area to obtain a secondary grid point matrix, wherein the grid spacing in the secondary grid point matrix is smaller than the grid spacing in the primary grid point matrix.
[0055] The fault secondary injection module is used to inject faults at each grid intersection in the secondary grid using fault injection technology, and count the effective fault injection points as secondary effective fault injection points.
[0056] Accordingly, the connected component generation module is specifically used for:
[0057] Dilate the pixels of all secondary valid fault injection points to generate connected components.
[0058] The advantages of this invention are:
[0059] (1) This invention considers the correctness of the calculation results of the chip under test under laser scanning fault injection, and selects a set of effective fault injection points. At the same time, it uses related digital image processing technology to expand the pixels of all effective fault injection points to generate connected components, that is, to locate all low robust connected components. The proportion of the area of the low robust connected components in the area of the SRAM cell of the chip is defined as the effective fault injection success rate. Compared with the traditional marker point distribution, this invention adopts a more intuitive and accurate area "surface" distribution, which has higher positioning accuracy and more comprehensive coverage. It can make a more accurate quantitative assessment of the security robustness of the security memory chip against fault injection, and help the security memory chip clarify the level of protection against fault injection.
[0060] (2) This invention performs two scanning meshing operations on the SRAM area of the chip to be tested. The step size of the first meshing operation is larger than that of the second meshing operation. The purpose of the first meshing operation is to quickly narrow down and locate sensitive areas by scanning fault points while ensuring the accuracy of the evaluation and improving the testing efficiency. The second meshing operation is a fine scan, which aims to count as many fault points as possible for subsequent image processing. By performing two scans to inject faults, the evaluation efficiency is improved while ensuring accuracy.
[0061] (3) Based on the quantitative level of the effective fault injection success rate, the present invention provides a relatively accurate evaluation report. At the same time, this technology can be combined with the detection technology based on side channel analysis to further improve the evaluation of the anti-attack capability of secure storage chips. It has certain practical significance and reference value for helping secure storage chips resist the threat of different types of fault injection, as well as for screening and locating the location of effective fault injection points.
[0062] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description
[0063] Figure 1 This is a flowchart illustrating a chip fault injection robustness evaluation method proposed in an embodiment of the present invention.
[0064] Figure 2 This is a complete flowchart of a chip fault injection robustness evaluation method proposed in an embodiment of the present invention;
[0065] Figure 3 This is a schematic diagram of the chip fault injection safety robustness evaluation system proposed in an embodiment of the present invention. Detailed Implementation
[0066] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0067] like Figure 1 As shown, the first embodiment of the present invention proposes a method for evaluating the robustness of chip fault injection resistance, the method comprising the following steps:
[0068] S10. Use fault injection technology to scan and inject faults point by point in the SRAM area of the chip under test, and count the effective fault injection points.
[0069] S20. Dilate the pixels of all valid fault injection points to generate connected components;
[0070] S30. The ratio of the area of the connected region to the area of the SRAM region is taken as the effective fault injection success rate of the chip under test.
[0071] This embodiment considers the correctness of the computational results of the chip under test under laser scanning fault injection, and selects a set of effective fault injection points. At the same time, it uses relevant digital image processing techniques to dilate the pixels of all effective fault injection points to generate connected components. The proportion of the area of the low robustness connected component in the area of the SRAM cell of the chip is defined as the effective fault injection success rate. Compared with traditional point statistics, it can more accurately quantify and evaluate the security robustness of the secure storage chip against fault injection, and help the secure storage chip clarify its protection level against fault injection.
[0072] In one embodiment, step S10: using fault injection technology to scan and inject faults point by point in the SRAM region of the chip under test, and counting the effective fault injection points, specifically includes the following steps:
[0073] S11. Perform a meshing operation on the SRAM region of the chip to be tested to obtain a mesh matrix;
[0074] It should be noted that, based on the characteristic that the SRAM memory cell array is arranged in a matrix, the SRAM area of the chip to be evaluated is meshed to obtain a mesh matrix, and a fault is injected at each mesh intersection using laser scanning injection technology.
[0075] S12. Fault injection technology is used to inject faults at each grid intersection in the primary grid.
[0076] S13. Trigger the chip encryption algorithm for each fault injection point and record the algorithm execution result at each fault injection point;
[0077] S14. Filter out all fault injection points that cause errors in chip operation results and use them as valid fault injection points.
[0078] Specifically, by recording the algorithm execution results of each grid point at each fault injection point, under different injection scan points, laser fault injection may cause SRAM bit reversal, leading to errors in the output of the memory chip algorithm, or it may be masked during propagation and have no impact on the result. An impact on the output result indicates that the memory chip cannot resist fault injection attacks at that injection point. This embodiment filters out points that cause errors in the chip's execution results and differ from the previous output, recording them as valid fault injection points.
[0079] It should be noted that this embodiment can select a set of effective fault injection points based on the principles of fault injection and fault occurrence, considering the correctness of the encryption algorithm calculation results of the chip under test under laser scanning fault injection, according to various attack scenarios that may occur in reality, such as voltage glitches, clock glitches, electromagnetic radiation, and laser irradiation.
[0080] In one embodiment, step S20: dilating the pixels of all valid fault injection points to generate connected components specifically includes the following steps:
[0081] S21. Mark all valid fault injection points in the infrared image of the SRAM region;
[0082] S22. Dilate the pixels corresponding to all valid fault injection points in the infrared image of the SRAM region to generate connected components.
[0083] It should be noted that the imaging image of the SRAM cell is processed by applying differential processing, binarization, and morphological processing techniques in digital image processing. The pixels of the effective fault injection point set are dilated to generate a connected component, which is denoted as a low robustness connected component.
[0084] Further, step S22: performing dilation processing on the pixels corresponding to all valid fault injection points in the infrared image of the SRAM region to generate connected components, specifically including:
[0085] S221. Use image enhancement algorithms to enhance the image, reduce the background grayscale, improve the image contrast, and highlight the SRAM area in the chip layout.
[0086] S222. Apply Gaussian filtering algorithm to smooth and reduce noise in the image, suppress background noise, and improve the image signal-to-noise ratio;
[0087] S223. Using an image binarization algorithm, set the grayscale value of all the counted and marked fault points to 255 to obtain a binary image;
[0088] S224. Using morphological processing algorithms as a preferred reference, the structural element can be set as a circle of a specified size to dilate the fault point pixels in the binary image.
[0089] S225. Using the connected component labeling algorithm, the dilated fault points in the binary image are processed into various connected components, which are low-security robust connected components.
[0090] This embodiment introduces digital image processing technology to further process the infrared imaging map marked with valid fault injection points. All valid fault injection points counted after scanning are generated into different connected domains, that is, all low robustness connected domains are located. By adopting a more intuitive and accurate regional "surface" distribution, the positioning accuracy is higher and the coverage is more comprehensive.
[0091] In one embodiment, after step S20: using fault injection technology to scan and inject faults point by point in the SRAM region of the chip under test and counting the effective fault injection points, the method further includes the following steps:
[0092] The secondary scanning area is determined by taking at least m effective fault injection points on the outermost side of the first grid in both the vertical and horizontal directions as boundaries;
[0093] The secondary scanning area is meshed to obtain a secondary mesh array, wherein the mesh spacing in the secondary mesh array is smaller than the mesh spacing in the primary mesh array.
[0094] Fault injection technology is used to inject faults at each grid intersection in the secondary grid, and the effective fault injection points are counted as secondary effective fault injection points.
[0095] Accordingly, the process of dilating the pixels of all valid fault injection points to generate connected components specifically involves:
[0096] Dilate the pixels of all secondary valid fault injection points to generate connected components.
[0097] It should be noted that after selecting the set of valid injection points in the first grid, the outermost four valid fault injection points along the X and Y axes of the first grid are used as boundaries to determine the rectangular area for the second scan. This area is then subjected to a second gridding operation. For reference, the grid spacing for the second grid can be set to half the grid spacing of the first grid.
[0098] This embodiment performs two meshing operations on the SRAM region of the chip under test and injects faults twice. The step size of the first meshing operation is larger than that of the second meshing operation. The purpose of the first meshing operation is to quickly narrow down and locate sensitive areas by scanning fault points while ensuring the accuracy of the evaluation and improving the testing efficiency. The second meshing operation is a fine scan, aiming to count as many fault points as possible for subsequent image processing. By performing two scans to inject faults, the evaluation efficiency is improved while ensuring accuracy.
[0099] In one embodiment, before step S10: scanning and injecting faults point by point in the SRAM region of the chip under test using fault injection technology and counting the effective fault injection points, the method further includes the following steps:
[0100] Remove the package from the chip to be tested and perform a mold removal process using chemical agents;
[0101] After cleaning the chip under test using an ultrasonic cleaning tank, the location of the SRAM cell of the chip under test is determined.
[0102] The chip to be tested is fixed on the three-dimensional moving platform of the laser fault injection device.
[0103] In this embodiment, the chip under test is fixed with its back side facing up on a three-dimensional moving platform within the laser fault injection device. An infrared imaging device is used to photograph the back of the chip to locate its SRAM cells. Then, the parameters of the laser fault injection device are set, such as the laser pulse frequency, the moving stage step speed, and the X-axis and Y-axis movement step sizes, and the position of the laser spot is adjusted. The chip under test is controlled to move on the three-dimensional moving platform, and laser fault injection is performed simultaneously during the movement.
[0104] This embodiment only performs fault injection on the SRAM region, and by setting the device to perform two scans with a step size from coarse to fine, it can quickly and accurately locate the low robustness safe region of the chip under test, resulting in higher evaluation efficiency.
[0105] In one embodiment, after step S30: using the ratio of the area of the connected region to the area of the SRAM region as the effective fault injection success rate of the chip under test, the method further includes:
[0106] The robustness of the chip under test against fault injection is evaluated based on the quantification level of the effective fault injection success rate.
[0107] Specifically, in this embodiment, the area S of all low-robustness connected domains is... (LRC) The area S of the SRAM cell in this chip (SRAM)The proportion of this percentage is defined as the effective fault injection success rate (ISR(f)) of the chip:
[0108]
[0109] The higher the effective fault injection success rate (ISR(f)), the lower the chip's robustness against fault injection, and vice versa.
[0110] Therefore, using the quantification level of ISR(f) as an evaluation standard for memory chip security can provide a quantitative and graded assessment of memory chip security, resulting in a more accurate evaluation report. This helps security chip designers to promptly improve protective measures for different application scenarios and enhance chip security. Furthermore, this technology can be combined with side-channel analysis-based detection techniques to comprehensively strengthen the security protection of memory chips.
[0111] like Figure 2 As shown, the second embodiment of the present invention proposes a chip fault injection security robustness evaluation system, the system comprising:
[0112] The statistics module 10 is used to scan and inject faults point by point in the SRAM region of the chip under test using fault injection technology, and to count the effective fault injection points.
[0113] The connected component generation module 20 is used to dilate the pixels of all valid fault injection points to generate connected components.
[0114] The effective fault injection success rate calculation module 30 is used to take the ratio of the area of the connected domain to the area of the SRAM region as the effective fault injection success rate of the chip under test.
[0115] In one embodiment, the statistics module 10 specifically includes:
[0116] Mesh cells are used to perform meshing operations on the SRAM region of the chip under test to obtain a single mesh dot matrix;
[0117] The fault injection unit is used to inject a fault at each grid intersection in the primary grid using fault injection technology.
[0118] The encryption operation unit is used to trigger the chip encryption algorithm for each fault injection point and record the algorithm execution result at each fault injection point.
[0119] The filtering unit is used to filter out all fault injection points that cause errors in chip operation results, and then use them as valid fault injection points.
[0120] In one embodiment, the connected component generation module 20 specifically includes:
[0121] An annotation unit is used to annotate all valid fault injection points in the infrared image of the SRAM region;
[0122] The connected component generation unit is used to perform dilation processing on the pixels corresponding to all valid fault injection points in the infrared image of the SRAM region to generate connected components.
[0123] In one embodiment, the connected component generation unit is specifically used to perform the following steps:
[0124] An image enhancement algorithm is used to enhance the infrared image of the SRAM region in order to highlight the SRAM region in the chip layout.
[0125] A Gaussian filtering algorithm is used to smooth and reduce noise in the infrared image of the SRAM region, thereby suppressing background noise and improving the image signal-to-noise ratio.
[0126] An image binarization algorithm is used to set the grayscale value of the valid fault injection points marked in the infrared image of the SRAM region to 255, thereby obtaining a binary image;
[0127] A morphological processing algorithm is used to set the structuring element as a circle of a specified size, and to dilate the pixels of the effective fault injection points in the binary image.
[0128] A connected component labeling algorithm is used to process the dilated effective fault injection points in the binary image into various connected components.
[0129] In one embodiment, the system further includes:
[0130] The region determination module is used to determine the secondary scanning region by taking at least m effective fault injection points on the outermost side of the longitudinal and transverse directions of the primary grid as boundaries.
[0131] A secondary grid point matrix generation module is used to perform a gridding operation on the secondary scanning area to obtain a secondary grid point matrix, wherein the grid spacing in the secondary grid point matrix is smaller than the grid spacing in the primary grid point matrix.
[0132] The fault secondary injection module is used to inject faults at each grid intersection in the secondary grid using fault injection technology, and count the effective fault injection points as secondary effective fault injection points.
[0133] Accordingly, the connected component generation module is specifically used for:
[0134] Dilate the pixels of all secondary valid fault injection points to generate connected components.
[0135] In one embodiment, the effective fault injection success rate (ISR) of the chip is:
[0136]
[0137] The higher the effective fault injection success rate (ISR(f)), the lower the chip's robustness against fault injection, and vice versa.
[0138] Therefore, using the quantification level of ISR(f) as an evaluation standard for memory chip security can provide a quantitative and graded assessment of memory chip security, resulting in a more accurate evaluation report. This helps security chip designers to promptly improve protective measures for different application scenarios and enhance chip security. Furthermore, this technology can be combined with side-channel analysis-based detection techniques to comprehensively strengthen the security protection of memory chips.
[0139] It should be noted that other embodiments or implementation methods of the chip fault injection security robustness evaluation system described in this invention can refer to the above-described method embodiments, and will not be repeated here.
[0140] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0141] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0142] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.
Claims
1. A method for evaluating the robustness of a chip against fault injection, characterized in that, The method includes: The fault injection technique is used to scan and inject faults point by point in the SRAM region of the chip under test, and the effective fault injection points are counted. Dilate the pixels of all valid fault injection points to generate connected components; The ratio of the area of the connected region to the area of the SRAM region is used as the effective fault injection success rate of the chip under test.
2. The chip fault injection robustness evaluation method as described in claim 1, characterized in that, The method employs fault injection technology to scan and inject faults point-by-point into the SRAM region of the chip under test, and counts the effective fault injection points, including: The SRAM region of the chip to be tested is meshed to obtain a mesh matrix; Fault injection technology is used to inject faults at each grid intersection in the primary grid. The chip encryption algorithm is triggered at each fault injection point, and the algorithm execution result at each fault injection point is recorded. All fault injection points that cause errors in chip operation results are selected as valid fault injection points.
3. The chip fault injection robustness evaluation method as described in claim 1, characterized in that, The step of dilating the pixels of all valid fault injection points to generate connected components includes: Mark all valid fault injection points in the infrared image of the SRAM region; Dilation is performed on the pixels corresponding to all valid fault injection points in the infrared image of the SRAM region to generate connected components.
4. The chip fault injection robustness evaluation method as described in claim 2, characterized in that, After identifying all fault injection points that cause errors in chip operation as valid fault injection points, the method further includes: The secondary scanning area is determined by taking at least m effective fault injection points on the outermost side of the first grid in both the vertical and horizontal directions as boundaries; The secondary scanning area is meshed to obtain a secondary mesh array, wherein the mesh spacing in the secondary mesh array is smaller than the mesh spacing in the primary mesh array. Fault injection technology is used to inject faults at each grid intersection in the secondary grid, and the effective fault injection points are counted as secondary effective fault injection points. Accordingly, the process of dilating the pixels of all valid fault injection points to generate connected components specifically involves: Dilate the pixels of all secondary valid fault injection points to generate connected components.
5. The chip fault injection robustness evaluation method as described in claim 1, characterized in that, Before employing fault injection technology to scan and inject faults point-by-point in the SRAM region of the chip under test and to count the effective fault injection points, the method further includes: Remove the package from the chip to be tested and perform a mold removal process using chemical agents; After cleaning the chip under test using an ultrasonic cleaning tank, the location of the SRAM cell of the chip under test is determined. The chip to be tested is fixed on the three-dimensional moving platform of the laser fault injection device.
6. The chip fault injection robustness evaluation method as described in claim 1, characterized in that, After using the ratio of the area of the connected region to the area of the SRAM region as the effective fault injection success rate of the chip under test, the method further includes: The robustness of the chip under test against fault injection is evaluated based on the quantification level of the effective fault injection success rate.
7. A chip fault injection robustness evaluation system, characterized in that, The system includes: The statistics module is used to scan and inject faults point by point in the SRAM region of the chip under test using fault injection technology, and to count the effective fault injection points. The connected component generation module is used to dilate the pixels of all valid fault injection points to generate connected components. The effective fault injection success rate calculation module is used to take the ratio of the area of the connected domain to the area of the SRAM region as the effective fault injection success rate of the chip under test.
8. The chip fault injection robustness evaluation system as described in claim 7, characterized in that, The statistics module includes: Mesh cells are used to perform meshing operations on the SRAM region of the chip under test to obtain a single mesh dot matrix; The fault injection unit is used to inject a fault at each grid intersection in the primary grid using fault injection technology. The encryption operation unit is used to trigger the chip encryption algorithm for each fault injection point and record the algorithm execution result at each fault injection point. The filtering unit is used to filter out all fault injection points that cause errors in chip operation results, and then use them as valid fault injection points.
9. The chip fault injection robustness evaluation system as described in claim 7, characterized in that, The connected component generation module includes: An annotation unit is used to annotate all valid fault injection points in the infrared image of the SRAM region; The connected component generation unit is used to perform dilation processing on the pixels corresponding to all valid fault injection points in the infrared image of the SRAM region to generate connected components.
10. The chip fault injection robustness evaluation system as described in claim 7, characterized in that, The system also includes: The region determination module is used to determine the secondary scanning region by taking at least m effective fault injection points on the outermost side of the longitudinal and transverse directions of the primary grid as boundaries. A secondary grid point matrix generation module is used to perform a gridding operation on the secondary scanning area to obtain a secondary grid point matrix, wherein the grid spacing in the secondary grid point matrix is smaller than the grid spacing in the primary grid point matrix. The fault secondary injection module is used to inject faults at each grid intersection in the secondary grid using fault injection technology, and count the effective fault injection points as secondary effective fault injection points. Accordingly, the connected component generation module is specifically used for: Dilate the pixels of all secondary valid fault injection points to generate connected components.