A short-term bias-temperature instability analysis method applied to a dram peripheral transistor

Abstract

The application discloses a short-term bias temperature instability analysis method applied to a DRAM peripheral transistor and belongs to the field of DRAM peripheral device reliability problem analysis. The application carries out experiments on the transistor to be analyzed, distinguishes different trap types, and calculates aging amounts of different traps under any voltage, temperature and time by simulation. The application solves the short board of traditional defect analysis technology, can measure and separate traps that capture or release carriers in the order of ns, and has great significance for developing a reliability model of a DRAM working at GHz and a reliability simulation circuit. In addition, the test scheme of the application is strong in operability and easy to implement, and can complete final BTI degradation prediction based on underlying defect parameters and corresponding physical theories, so that the result is more accurate and reliable.

Description

Technical Field

[0001] This invention relates to the field of reliability problem analysis of DRAM peripheral devices, and specifically to a method for analyzing short-term bias temperature instability of DRAM peripheral transistors. Background Technology

[0002] With the development of technologies such as the Internet of Things and artificial intelligence, the amount of data is increasing explosively, placing higher demands on memory. DRAM, as one of the most widely used memory technologies, faces increasingly stringent reliability requirements. To meet the demands of current sub-20nm DRAM processes, major DRAM manufacturers are introducing high-k dielectric materials into the transistor gate oxide layer to suppress leakage current. However, this also introduces a large number of native traps into the gate oxide layer, which exacerbates bias temperature instability (BTI). Furthermore, to improve DRAM retention time, high-temperature hydrogen annealing is typically used to passivate defects in the cell device. This forms numerous Si-H bonds at the oxide-substrate interface, reducing BTI reliability. Since DRAM operating speeds have now reached Gbps, considering only long-term BTI is insufficient; it is necessary to analyze the short-term BTI effect under high-speed DRAM operation.

[0003] refer to Figure 1 Currently used capacitance-voltage (CVU) testing methods and source test units (SMUs), while offering high accuracy, only achieve millisecond (ms) timescales. Even pulsed IV (PIV) testing only reaches microsecond (μs) levels, and this is done at the expense of accuracy. Charge pumping (CP) technology, by testing the average current generated during the defect capture and release process, can simultaneously meet the conflicting requirements of high speed and high accuracy. Furthermore, recent evidence suggests the presence of multiple types of defects (electron traps and hole traps) in BTI, making it challenging to separate different types of traps and extract their spatial distribution and energy level positions. Traditional CP techniques provide relatively coarse trap energy level positions and cannot calculate oxide layer traps. The improved "variable charge-discharge time and amplitude charge pumping technology" (VT) addresses this challenge. 2 Although ACP can obtain the spatial location and energy level distribution of oxide traps, it is only a rough estimate and not accurate enough.

[0004] In summary, existing technical solutions are unable to achieve high-speed, short-time BTI testing and analysis on DRAM peripheral devices. A reliable technical solution is needed to accurately predict the degradation caused by BTI on DRAM peripheral devices under GHz high-speed operating conditions. Summary of the Invention

[0005] To address the problems existing in the prior art, this invention proposes a method for analyzing short-term bias temperature instability of DRAM peripheral transistors.

[0006] The technical solution provided by this invention is as follows:

[0007] A method for analyzing short-term bias temperature instability of DRAM peripheral transistors, comprising the following steps:

[0008] 1) Using VT 2 The principle of ACP technology involves conducting experiments on the transistor under analysis to obtain the trap density Nt as a function of t. charge t discharge and V charge The changing relationship;

[0009] 2) Differentiate fast traps N near the channel based on the magnitude of charge and discharge time. t-fast With slow traps N distributed in the dielectric layer t-slow And obtain the fast trap N t-fast Follow t charge t discharge and V charge The changing relationship; and the slow trap N t-slow Follow t discharge t discharge and V charge The changing relationship;

[0010] 3) Set the parameters for various traps, including the trap energy level E. T Traps relaxation energy S, trap distance from trench x t The total density N of the traps T The time dynamics of different types of traps were simulated using nonradiative multiphonon theory, resulting in N... t-fast Follow t charge t discharge and V charge The relationship of change, N t-slow Follow t discharge t discharge and V charge The relationship between the changes matches the experimental data;

[0011] 4) Using the parameters of various traps obtained in step 3), calculate the BTI aging amount of different traps of the transistor to be analyzed under any voltage, temperature and time. By superimposing the contributions of different types of traps, the total BTI aging amount can be obtained.

[0012] Furthermore, in step 1), the experiment specifically involves applying a corresponding voltage signal to the transistor gate, based on the transistor's normal operating voltage conditions. This causes the transistor to continuously switch between trapping carriers in the inversion state and releasing carriers from the accumulation state, thereby allowing the traps to contribute to the substrate current I. bulk middle.

[0013] Furthermore, by changing t charge From 1μs to 500μs and t discharge To achieve a reduction from 100ns to 10ms, traps deeper within the oxide layer can participate in the charging and discharging process by changing the charging voltage V. charge The voltage ranges from -1V to -1.8V to allow traps at different energy levels to participate in the charging and discharging process.

[0014] Furthermore, in step 2), if the charging or discharging time is less than the order of μs, then this part of the trap is a fast trap; if the charging or discharging time is greater than 1 μs, then this part of the trap is a slow trap.

[0015] Furthermore, the method for determining whether a slow trap is located in a multilayer medium or exists in a single medium layer in step 2) is to analyze N. t-slow The relationship between the discharge time and the slope of the curves indicates that the slow traps are distributed in different dielectric layers, and the inflection point is the contact point between the different dielectric layers; if N t-slow If the relationship between the discharge time and the discharge time is a linear function with a single slope, then the traps are only distributed in one type of dielectric layer.

[0016] Furthermore, in step 3), the parameters of various traps are continuously optimized iteratively using a nonlinear optimization algorithm until an optimal set of parameters is found.

[0017] The beneficial effects of this invention are as follows: This invention solves the shortcomings of traditional defect analysis techniques, and can measure and separate the shortest traps that capture or release carriers on the order of nanoseconds. This is of great significance for developing reliability models and reliability simulation circuits for DRAMs operating at GHz. In addition, the test scheme of this invention is highly operable and easy to implement, and it completes the prediction of the final BTI degradation based on the underlying defect parameters and corresponding physical theories, resulting in more accurate and reliable results. Attached Figure Description

[0018] Figure 1 A schematic diagram illustrating the time accuracy of existing technologies capable of performing BTI analysis;

[0019] Figure 2 This is a schematic diagram illustrating the specific implementation process of the present invention;

[0020] Figure 3 A schematic diagram of the test signal waveform applied in a specific embodiment;

[0021] Figure 4 This is a schematic diagram showing the variation of trap density with charging voltage and charge / discharge time for a specific embodiment.

[0022] Figure 5 This is a schematic diagram showing the variation of trap density of slow traps with charging voltage and charge / discharge time in a specific embodiment.

[0023] Figure 6 The data and simulation comparison of the trap density of the fast trap as a function of charging time provided for a specific embodiment are shown in the figure.

[0024] Figure 7 The data and simulation comparison of the trap density of the slow trap as a function of discharge time provided for a specific embodiment are shown in the figure.

[0025] Figure 8 A comparison chart of BTI prediction results and measured data provided for a specific embodiment. Detailed Implementation

[0026] The present invention will be further illustrated below with reference to the accompanying drawings and specific embodiments, but the scope of the invention is not limited in any way.

[0027] This invention provides a technique for analyzing short-term bias temperature instability of DRAM peripheral transistors. Figure 2 The diagram shows the flow of the method of the present invention, and its specific implementation includes the following steps:

[0028] Step 1. Use VT 2 ACP technology extracts trap density information: trap density N t =I bulk / qAf, where q is the amount of electron charge, A is the area of ​​the gate dielectric layer, and f is the frequency of the applied voltage signal;

[0029] Apply such as on the gate Figure 3 The waveform shown. t charge The time period represents the charging phase, allowing the traps to capture charge carriers; t discharge The time period represents the discharge phase, allowing the traps that captured charge carriers to release. By changing t... charge From 1μs to 500μs and t discharge To achieve a reduction from 100ns to 10ms, traps deeper within the oxide layer can participate in the charging and discharging process by changing the charging voltage V. charge The voltage range is from -1V to -1.8V to allow traps at different energy levels to participate in the charging and discharging process. This results in... Figure 4 The trap density Nt shown varies with t charge t discharge and V charge The changing relationship.

[0030] Step 2. Separate different types of traps and extract the trap density of different types of traps:

[0031] refer to Figure 4 , fixed t charge Looking only at the relationship of any single data point, such as t charge =300μs. It's not hard to see that at t discharge When <1μs, the trap density N t The value is already relatively large, and remains constant between 100 ns and 1 μs. This indicates that some traps complete their discharge within 100 ns, i.e., fast traps. And at t... discharge After >1μs, the trap density N t It increases slowly with increasing discharge time; meanwhile, at t charge After >1μs, the second half of N t The increase in [something] becomes more and more obvious. This indicates that this part of the trap is a slow trap, requiring a longer charging and discharging time.

[0032] Based on the above discussion, it can be concluded that... Figure 4 The first point of each line, i.e., the fast trap N t-fast Follow t charge t discharge and V charge The relationship of change; subtract the data of the first point from each line, i.e., N. t -N t-fast This is the slow trap N t-slow Follow t charge t discharge and V charge The changing relationship.

[0033] refer to Figure 5 That is, the N of the slow trap provided in this example. t-slow Follow t discharge A diagram illustrating the changing data. The diagram shows that regardless of the value of t... charge Under the condition, N t-slow With t discharge The relationships all conform to a broken line relationship with two slopes. Considering the fact that the device used in this example has a 1.4nm thick SiO2 (interface layer, IL) and a 2.4nm thick High-k (HK) dual-dielectric gate structure, this confirms the conclusion that the trap exists in both dielectric layers. That is, N t-slow Actually, it's caused by the IL layer trap N. IL-h and HK layer trap N HK-h The result of a combination of factors.

[0034] Based on the above analysis, the following three types of traps exist in this example: N-type fast traps near the interface in the IL layer.IL-e Slow traps in the IL layer N IL-h Slow trap N in HK layer HK-h .

[0035] Step 3. Calculate accurate parameters for each type of trap: The defect information required for each trap is shown in formula (1):

[0036] Ρ=( <E T >,σ ET , <s>,σ S ,x t N T (1)

[0037] Based on the results of step 2 in this example, the initial values ​​of the corresponding trap parameters are defined as follows.

[0038] Table 1 Initial values ​​of various trap parameters

[0039] <![CDATA[<E T >]]> -0.2eV -2eV -2eV <![CDATA[σ ET ]]> 0.5eV 1eV 1eV <s> < / s> 1eV 2eV 2.5eV <![CDATA[σ S ]]> 0.5eV 1eV 1eV <![CDATA[x t ]]> 0~0.2nm 0~1.4nm 1.4~3.8nm <![CDATA[N T ]]> <![CDATA[1e20cm -3 ]]> <![CDATA[1e19cm -3 ]]> <![CDATA[1e19cm -3 ]]>

[0040] according to Figure 4 By analyzing the voltage signal waveform applied in the experiment and using the nonradiative multiphonon theory model, the waveforms of different types of traps at different t values ​​can be simulated and calculated. charge t discharge and V charge Participating in VT under certain conditions 2 Trap density during the ACP process. If the simulation results differ significantly from the trap data extracted in step 2, a nonlinear optimization algorithm will iteratively optimize the trap parameters until an optimal set of trap parameters is found that matches the simulation results with the experimental data. The final trap parameters determined in this example are shown in the table below, with fast trap N... t-fast With slow trap N t-slow The simulation results are as follows Figure 6 and Figure 7 As shown. The parameters for various traps are as follows:

[0041] Table 2 Final values ​​of various trap parameters

[0042] <![CDATA[<E T >]]> -0.1eV -1.6eV -1.71eV <![CDATA[σ ET ]]> 0.0016eV 0.37eV 0.24eV <s> < / s> 0.5eV 3.4eV 2.5eV <![CDATA[σ S ]]> 0.1eV 1.08eV 1.4eV <![CDATA[x t ]]> 0~0.24nm 0~1.4nm 1.4~3.8nm <![CDATA[N T ]]> <![CDATA[4.5e19cm -3 ]]> <![CDATA[9.2e18cm -3 ]]> <![CDATA[1.6e18cm -3 ]]>

[0043] Step 4. Calculate the BTI aging amount under any conditions:

[0044] Based on the parameters of various traps determined in step three, the aging amount ΔV of different traps under arbitrary voltage, temperature, and time can be calculated and output. th (N IL-e ), ΔV th (N IL-h ), ΔV th (N IL-h By summing the contributions of different types of traps, the total BTI aging amount can be obtained:

[0045] ΔV th (total)=ΔV th (N IL-e )+ΔV th (N IL-h )+ΔV th (N IL-h )

[0046] refer to Figure 8 When a BTI stress of -1.8V is applied to the device at room temperature, the measured data results show excellent agreement with the simulation results.

[0047] Finally, it should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the claims.< / s>

Claims

1. A method for analyzing short-term bias temperature instability of DRAM peripheral transistors, comprising the following steps: 1) Charge pump technology VT with variable charging and discharging time and amplitude 2 The principle of ACP technology, experiments on the transistor to be analyzed, the relationship between trap density Nt and charging time t charge , discharging time t discharge and charging voltage V charge ; 2) Differentiate fast traps N near the channel based on the magnitude of charge and discharge time. t-fast With slow traps N distributed in the dielectric layer t-slow And obtain the fast trap N t-fast Follow t charge t discharge and V charge The changing relationship; and the slow trap N t-slow Follow t charge t discharge and V charge The changing relationship; 3) Set the parameters for various traps, including the trap energy level E. T Traps relaxation energy S, trap distance from trench x t The total density N of the traps T The time dynamics of different types of traps were simulated using nonradiative multiphonon theory, resulting in N... t-fast Follow t charge t discharge and V charge The relationship of change, N t-slow Follow t charge t discharge and V charge The relationship between the changes matches the experimental data; 4) Using the parameters of various traps obtained in step 3), calculate the BTI aging amount of different traps of the transistor to be analyzed under any voltage, temperature and time. By superimposing the contributions of different types of traps, the total BTI aging amount can be obtained.

2. The method for analyzing short-term bias temperature instability of DRAM peripheral transistors as described in claim 1, characterized in that, The experiment in step 1) specifically involves applying a corresponding voltage signal to the transistor gate, based on the transistor's normal operating voltage conditions. This causes the transistor to continuously switch between trapping carriers in the inversion state and releasing carriers from the accumulation state, thereby allowing the traps to contribute to the substrate current I. bulk middle.

3. The method for analyzing short-term bias temperature instability of DRAM peripheral transistors as described in claim 2, characterized in that, By changing t charge From 1μs to 500μs and t discharge To achieve a reduction from 100ns to 10ms, traps deeper within the oxide layer can be incorporated into the charging and discharging process by changing the charging voltage V. charge The voltage ranges from -1V to -1.8V to allow traps at different energy levels to participate in the charging and discharging process.

4. The method for analyzing short-term bias temperature instability of DRAM peripheral transistors as described in claim 1, characterized in that, In step 2), if the charging or discharging time is less than μs, the trap is a fast trap; if the charging or discharging time is greater than 1 μs, the trap is a slow trap.

5. The method for analyzing short-term bias temperature instability of DRAM peripheral transistors as described in claim 1, characterized in that, Step 2) determines whether a slow trap is located in a multilayer medium or exists in a single medium layer by analyzing N. t-slow The relationship between the discharge time and the slope of the curves indicates that the slow traps are distributed in different dielectric layers, and the inflection point is the contact point between the different dielectric layers; if N t-slow If the relationship between the discharge time and the time is a linear function with a single slope, then the traps are distributed only in one type of dielectric layer.

6. The method for analyzing short-term bias temperature instability of DRAM peripheral transistors as described in claim 1, characterized in that, In step 3), the parameters of various traps are continuously optimized iteratively using a nonlinear optimization algorithm until an optimal set of parameters is found.

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