A semiconductor structure and a method of manufacturing the same

Abstract

The embodiments of the present disclosure disclose a semiconductor structure and a manufacturing method thereof. The manufacturing method comprises: providing a substrate, the substrate comprising a first surface and a second surface opposite to the first surface; etching from the first surface of the substrate to the inside to form a first initial groove; filling a first blocking layer at the lower part of the first initial groove; filling a first dielectric layer at the upper part of the first initial groove; etching the substrate and the first dielectric layer to form a second groove at the top position of the first initial groove, the part of the first initial groove below the second groove constituting a first groove, and part of the first dielectric layer remaining in the first groove; forming a second blocking layer in the second groove; performing a first thinning process on the substrate from the second surface of the substrate to expose the first blocking layer; and performing a second thinning process on the substrate from the exposed first blocking layer to expose the second blocking layer, wherein the thinning rate of the second thinning process is less than the thinning rate of the first thinning process.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] Semiconductor structures, such as dynamic random access memory (DRAM), typically include a substrate and an array region on the substrate, within which a memory array for storing data is formed. In the manufacturing process of semiconductor structures, the substrate is typically thinned from the back side to remove a predetermined thickness, followed by bonding different semiconductor structures together.

[0003] However, in the thinning process, it is often difficult to determine the precision of thinning, which can easily lead to excessive thinning that damages the memory array or insufficient thinning that fails to reach the preset thickness, thereby affecting the performance of the semiconductor structure. Summary of the Invention

[0004] This disclosure provides a method for manufacturing a semiconductor structure, including:

[0005] A substrate is provided, the substrate including a first surface and a second surface opposite to the first surface;

[0006] Etching from the first surface of the substrate inwards forms a first initial trench;

[0007] A first barrier layer is filled in the lower part of the first initial trench;

[0008] A first dielectric layer is filled in the upper part of the first initial trench;

[0009] The substrate and the first dielectric layer are etched to form a second trench at the top of the first initial trench. The first initial trench located below the second trench constitutes a first trench, and a portion of the first dielectric layer is retained in the first trench.

[0010] A second barrier layer is formed within the second trench;

[0011] Starting from the second surface of the substrate, a first thinning process is performed on the substrate until the first barrier layer is exposed;

[0012] Starting from the exposed first barrier layer, a second thinning process is performed on the substrate until the second barrier layer is exposed, wherein the thinning rate of the second thinning process is less than the thinning rate of the first thinning process.

[0013] In some embodiments, starting from a second surface of the substrate, performing a first thinning process on the substrate until the first barrier layer is exposed includes:

[0014] A rough grinding process is performed on the second surface of the substrate to reduce the substrate to a first preset thickness;

[0015] A fine grinding process is performed on the second surface of the substrate to reduce the substrate to a second predetermined thickness;

[0016] A first chemical mechanical polishing process is performed on the second surface of the substrate to expose the first barrier layer, thereby thinning the substrate to a third predetermined thickness; wherein the thinning rate of the fine polishing process is less than the thinning rate of the coarse polishing process, and the thinning rate of the first chemical mechanical polishing process is less than the thinning rate of the fine polishing process.

[0017] In some embodiments, the thinning rate of the coarse grinding process ranges from 3 μm / s to 7 μm / s, the thinning rate of the fine grinding process is less than 1 μm / s, and the thinning rate of the first chemical mechanical polishing process ranges from 1 to 50 nm / s.

[0018] In some embodiments, starting from the exposed first barrier layer, a second thinning process is performed on the substrate until the second barrier layer is exposed, including:

[0019] Starting from the exposed first barrier layer, a second chemical mechanical polishing process is performed on the substrate until the first dielectric layer is exposed;

[0020] Starting from the exposed first dielectric layer, a third chemical mechanical polishing process is performed on the substrate until the second barrier layer is exposed; wherein the thinning rate of the third chemical mechanical polishing process is equal to or less than the thinning rate of the second chemical mechanical polishing process.

[0021] In some embodiments, the thinning rate of the second chemical mechanical polishing process is in the range of 1-50 nm / s, and the thinning rate of the third chemical mechanical polishing process is in the range of 1-50 nm / s.

[0022] In some embodiments, the substrate includes an array region, a peripheral region, and a spacer region between the array region and the peripheral region, wherein the first initial trench and the second trench are formed in the spacer region; and while etching the substrate and the first dielectric layer to form the second trench at the top position of the first initial trench, the substrate further includes:

[0023] The substrate located in the array region and the peripheral region is etched to form a plurality of third trenches extending along a first direction and a plurality of fourth trenches extending along a second direction in the array region. The third trenches and the fourth trenches intersect each other to define a plurality of first active pillars in the substrate. A fifth trench is formed in the peripheral region to define a plurality of discrete second active pillars in the substrate.

[0024] In some embodiments, the second trench includes opposing first and second sidewalls, the first sidewall being adjacent to the array region and the second sidewall being adjacent to the peripheral region; prior to forming the second barrier layer, it further includes:

[0025] A second dielectric layer is formed, which fills the third trench, the fourth trench and the fifth trench, and covers the first sidewall, the second sidewall and the bottom surface of the second trench.

[0026] In some embodiments, forming a second barrier layer within the second trench includes:

[0027] A second barrier layer is formed, which covers the second dielectric layer;

[0028] A third dielectric layer is formed, which covers the second barrier layer and fills the second trench;

[0029] A portion of the second dielectric layer, a portion of the second barrier layer, and a portion of the third dielectric layer are removed, causing the upper surfaces of the second dielectric layer, the second barrier layer, and the third dielectric layer located in the array region and in the second trench and close to the array region to drop by a predetermined height, thereby exposing a portion of the sidewall of the first active pillar and a portion of the first sidewall of the second trench. The remaining second dielectric layer fills the lower part of the third trench and the fourth trench, and covers the bottom surface of the second trench, the lower part of the first sidewall, and the second sidewall. The remaining second barrier layer covers the inner wall of the second dielectric layer located in the second trench, and the remaining third dielectric layer fills a portion of the second trench and covers the second barrier layer.

[0030] In some embodiments, after removing a portion of the second dielectric layer, a portion of the second barrier layer, and a portion of the third dielectric layer, the method further includes:

[0031] Multiple word line structures are formed on the second dielectric layer, each word line structure extending along the first direction and covering part of the sidewall of multiple first active pillars;

[0032] A fourth dielectric layer is formed, which covers the substrate and fills the second trench, the third trench, and the remaining space within the fourth trench;

[0033] The fourth dielectric layer is etched to form a plurality of openings, each of which extends along the second direction and exposes the upper surface of a plurality of the first active pillars;

[0034] A bitline structure is formed within the opening.

[0035] This disclosure also provides a semiconductor structure comprising:

[0036] A substrate, the substrate comprising a first surface and a second surface opposite to the first surface;

[0037] A second trench extending from the first surface of the substrate into the interior, and a first trench located below the second trench and communicating with the second trench;

[0038] A first barrier layer fills the lower part of the first trench;

[0039] A first dielectric layer fills the upper part of the first trench;

[0040] The second barrier layer is located within the second trench.

[0041] In some embodiments, the depth of the second trench ranges from 100 nm to 200 nm, and the depth of the first trench ranges from 150 nm to 300 nm.

[0042] In some embodiments, the thickness of the first dielectric layer ranges from 100 nm to 200 nm, and the thickness of the first barrier layer ranges from 50 nm to 100 nm.

[0043] In some embodiments, the substrate includes an array region, a peripheral region, and a spacer region between the array region and the peripheral region, wherein the first trench and the second trench are located in the spacer region; the semiconductor structure further includes: a plurality of third trenches extending in a first direction, a plurality of fourth trenches extending in a second direction, and a fifth trench located within the substrate, wherein the third trenches and the fourth trenches are located in the array region and intersect each other to define a plurality of discrete first active pillars within the array region, and the fifth trench is located in the peripheral region and defines a plurality of discrete second active pillars within the peripheral region.

[0044] In some embodiments, the second trench includes opposing first and second sidewalls, the first sidewall being close to the array region and the second sidewall being close to the peripheral region; the semiconductor structure further includes: a second dielectric layer, the second dielectric layer filling the lower portions of the third and fourth trenches and the fifth trench, and covering the bottom surface of the second trench, the lower portion of the first sidewall, and the second sidewall; a second barrier layer covering the inner wall of the second dielectric layer located within the second trench; and a third dielectric layer filling a portion of the second trench and covering the second barrier layer.

[0045] In some embodiments, the semiconductor structure further includes:

[0046] A word line structure is located on the second dielectric layer, and each of the word line structures extends along the first direction and covers part of the sidewall of a plurality of first active pillars.

[0047] A fourth dielectric layer covers the substrate and fills the remaining space in the third trench, the fourth trench, and the second trench;

[0048] A plurality of openings located on the fourth medium, each of the openings extending along the second direction and exposing the upper surfaces of a plurality of the first active pillars; a bitline structure located within the openings.

[0049] The semiconductor structure and manufacturing method disclosed herein include the following steps: providing a substrate, the substrate including a first surface and a second surface opposite to the first surface; etching from the first surface of the substrate inward to form a first initial trench; filling the lower portion of the first initial trench with a first barrier layer; filling the upper portion of the first initial trench with a first dielectric layer; etching the substrate and the first dielectric layer to form a second trench at the top of the first initial trench, the first initial trench located below the second trench constituting a first trench, a portion of the first dielectric layer remaining in the first trench; forming a second barrier layer in the second trench; performing a first thinning process on the substrate starting from the second surface of the substrate until the first barrier layer is exposed; and performing a second thinning process on the substrate starting from the exposed first barrier layer until the second barrier layer is exposed, wherein the thinning rate of the second thinning process is less than the thinning rate of the first thinning process. In this embodiment, a first barrier layer is disposed below the second barrier layer. The first barrier layer serves as a stop layer for the first thinning process, and the second barrier layer serves as a stop layer for the second thinning process. By setting up a double-layer thinning stop layer, the accuracy of the thinning process is improved, avoiding damage to other structures located within the substrate due to excessive thinning or insufficient thinning thickness. Furthermore, in this embodiment, the first thinning process has a larger thinning rate, which improves the thinning efficiency, while the second thinning process has a smaller thinning rate, which further improves the thinning accuracy and reduces the damage caused by the first thinning process. This results in the second surface of the thinned substrate having better flatness and less damage.

[0050] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description

[0051] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure;

[0053] Figures 2a to 16b A process flow diagram of a method for manufacturing a semiconductor structure provided in an embodiment of this disclosure. Detailed Implementation

[0054] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0055] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0056] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0057] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0058] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0059] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0060] Semiconductor structures, such as dynamic random access memory (DRAM), typically include a substrate and an array region on the substrate, within which a memory array for storing data is formed. In the manufacturing process of semiconductor structures, the substrate is typically thinned from the back side to remove a predetermined thickness, followed by bonding different semiconductor structures together.

[0061] However, in the thinning process, it is often difficult to determine the precision of thinning, which can easily lead to excessive thinning that damages the memory array or insufficient thinning that fails to reach the preset thickness, thereby affecting the performance of the semiconductor structure.

[0062] Based on this, the following technical solutions are proposed for embodiments of this disclosure:

[0063] Based on this, the present disclosure provides a method for manufacturing a semiconductor structure, for details please refer to [link to relevant documentation]. Figure 1 As shown in the figure, the method includes the following steps:

[0064] Step 101: Provide a substrate, the substrate including a first surface and a second surface opposite to the first surface;

[0065] Step 102: Etch from the first surface of the substrate inward to form the first initial trench;

[0066] Step 103: Fill the lower part of the first initial trench with a first barrier layer;

[0067] Step 104: Fill the upper part of the first initial trench with a first dielectric layer;

[0068] Step 105: Etch the substrate and the first dielectric layer, form a second trench at the top of the first initial trench, and the first initial trench located below the second trench constitutes the first trench, with a portion of the first dielectric layer remaining in the first trench;

[0069] Step 106: Form a second barrier layer in the second trench;

[0070] Step 107: Starting from the second surface of the substrate, perform a first thinning process on the substrate until the first barrier layer is exposed;

[0071] Step 108: Starting from the exposed first barrier layer, perform a second thinning process on the substrate until the second barrier layer is exposed, wherein the thinning rate of the second thinning process is less than the thinning rate of the first thinning process.

[0072] The semiconductor structure manufacturing method provided in this disclosure can be used to manufacture dynamic random access memory (DRAM), particularly DRAM with vertical transistors. However, it is not limited to this; any semiconductor structure that requires thinning can be manufactured using the method provided in this disclosure.

[0073] Figures 2a to 16b A process flow diagram of a method for manufacturing a semiconductor structure provided in this disclosure embodiment, wherein, Figure 1 a, Figure 2a , Figure 3a , Figure 4a , Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a , Figure 10a , Figure 11a , Figure 12a , Figure 13a , Figure 14a , Figure 15a , Figure 16a Perspective views of different process steps in the method for manufacturing a semiconductor structure according to embodiments of this disclosure. Figure 1 b、 Figure 2b , Figure 3b , Figure 4b , Figure 5b , Figure 6b , Figure 7b , Figure 8b , Figure 9b , Figure 10b , Figure 11b , Figure 12b , Figure 13b , Figure 14b , Figure 15b , Figure 16b respectively along Figure 1 a, Figure 2a , Figure 3a , Figure 4a , Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a , Figure 10a , Figure 11a , Figure 12a , Figure 13a , Figure 14a , Figure 15a , Figure 16a A schematic diagram of the cross-sectional structure taken by line A-A'. The following is combined with... Figures 2a to 16b The method for manufacturing the semiconductor structure provided in the embodiments of this disclosure will be further described.

[0074] First, perform step 101, as follows: Figures 2a to 2b As shown, a substrate 20 is provided, which includes a first surface S1 and a second surface S2 opposite to the first surface S1.

[0075] The substrate 20 may be a semiconductor substrate and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate 20 is a silicon substrate, which may be doped or undoped. In one embodiment, the substrate 20 includes an array region 201, a peripheral region 203, and a spacer region 202 located between the array region 201 and the peripheral region 203, the peripheral region 203 surrounding the array region 201, and the spacer region 202 separating the peripheral region 203 from the array region 201.

[0076] Next, proceed to step 102, as follows: Figures 3a to 3b As shown, a first initial trench T1' is formed by etching from the first surface S1 of the substrate 20 inward.

[0077] In practice, the first initial trench T1' can be formed using the following method: First, a first mask layer 21 is formed on the substrate 20, covering the first surface S1 of the substrate 20; then, a first mask pattern (not shown) is formed on the first mask layer 21; next, the first mask layer 21 and the substrate 20 are etched using the first mask pattern (not shown) as a mask to form the first initial trench T1' within the substrate 20. Here, the first mask layer 21 can have a single-layer or multi-layer structure, for example, including one or a combination of an oxide layer, a polysilicon layer, and a hard mask layer. In a specific embodiment, the first mask layer 21 includes a silicon oxide layer and a polysilicon layer located on the silicon oxide layer.

[0078] In one embodiment, a first initial trench T1' is formed in the spacer region 202 and is disposed around the array region 201. In some embodiments, the depth of the first initial trench T1' is between 300nm and 500nm, for example, 300nm, 350nm, 400nm, 450nm, and 500nm.

[0079] Next, proceed to step 103, as follows: Figures 4a to 5b As shown, a first barrier layer 23 is filled in the lower part of the first initial trench T1'.

[0080] Specifically, forming the first barrier layer 23 includes: forming a first barrier material layer 23', the first barrier material layer 23' filling the first initial trench T1' and covering the first mask layer 21; and removing a portion of the first barrier material layer 23' to form the first barrier layer 23.

[0081] Here, the first barrier material layer 23' can be formed using processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). The first barrier layer 23 can subsequently serve as a stop layer for thinning processes. In one embodiment, the material of the first barrier layer 23 includes one or more of nitrides, oxides of nitrides, and carbides of nitrides, for example, silicon nitride.

[0082] In one embodiment, prior to forming the first barrier material layer 23', the method further includes forming an insulating layer (not shown) that covers the inner wall of the first initial trench T1' to protect the substrate 20 exposed by the first initial trench T1' from damage or contamination by subsequent processes. The insulating layer (not shown) may be made of an oxide, such as silicon oxide.

[0083] Next, proceed to step 104, as follows: Figures 6a to 6b As shown, the upper part of the first initial trench T1' is filled with a first dielectric layer 24.

[0084] Here, the first dielectric layer 24 can be formed using processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). The first dielectric layer 24 and the first barrier layer 23 are made of different materials. In one embodiment, the material of the first dielectric layer 24 includes oxides, such as silicon oxide.

[0085] See you again Figures 6a to 6b Before or after the formation of the first dielectric layer 24, the method further includes: removing the first mask layer 21.

[0086] Next, proceed to step 105, as follows: Figures 7a to 7b As shown, the substrate 20 and the first dielectric layer 24 are etched, and a second trench T2 is formed at the top position of the first initial trench T1'. The first initial trench T1' located below the second trench T2 constitutes the first trench T1, and a portion of the first dielectric layer 24 is retained in the first trench T1.

[0087] A second barrier layer 27 will subsequently be formed within the second trench T2 (see...). Figures 11a to 11b The substrate 20's second surface S2 is thinned using a first thinning process and a second thinning process, wherein the thinning rate of the second thinning process is less than that of the first thinning process. The first barrier layer 23 serves as a stop layer for the first thinning process, and the second barrier layer 27 (see...) Figures 11a to 11bAs a stop layer in the second thinning process, when the depth of the second trench T2 is large and the depth of the first trench T1 is small, the remaining thickness of the first dielectric layer 24 and the first barrier layer 23 is small, affecting the accuracy of the thinning process. When the depth of the second trench T2 is small and the depth of the first trench T1 is large, the remaining thickness of the first dielectric layer 24 and the first barrier layer 23 is large, increasing the overall thinning process time due to the low rate of the second thinning process. Therefore, in one embodiment, the depth of the second trench T2 is between 100nm and 200nm, for example, 100nm, 120nm, 140nm, 160nm, 180nm, 200nm; the depth of the first trench T1 is between 150nm and 300nm, for example, 150nm, 170nm, 200nm, 220nm, 250nm, 270nm, 300nm.

[0088] See you again Figures 7a to 7b In one embodiment, while etching the substrate 20 and the first dielectric layer 24, forming the second trench T2 at the top position of the first initial trench T1', the method further includes:

[0089] The substrate 20 located in the array region 201 and the peripheral region 203 is etched. Multiple third trenches T3 extending along the first direction and multiple fourth trenches T4 extending along the second direction are formed in the array region 201. The third trenches T3 and the fourth trenches T4 intersect each other to define multiple first active pillars AA1 in the substrate 20. A fifth trench T5 is formed in the peripheral region 203. The fifth trench T5 defines multiple discrete second active pillars AA2 in the substrate 20.

[0090] Multiple first active pillars AA1 are arranged in an array in array region 201 along a first direction and a second direction. In one embodiment, the first direction and the second direction are perpendicular to each other. However, this is not a limitation; the first direction and the second direction can also intersect obliquely.

[0091] In practice, before forming the second trench T2, the third trench T3, the fourth trench T4, and the fifth trench T5, a second mask layer 25 can be formed on the substrate 20. A second mask pattern (not shown) is formed on the second mask layer 25. Then, the second mask layer 25 and the substrate 20 are etched using the second mask pattern (not shown) as a mask to form multiple trenches within the substrate 20. However, this is not a limitation; the second trench T2, the third trench T3, the fourth trench T4, and the fifth trench T5 can also be formed in different process steps. Here, the second mask layer 25 can have a single-layer or multi-layer structure, for example, including one or a combination of an oxide layer, a polysilicon layer, and a hard mask layer. In a specific embodiment, the second mask layer 25 includes a silicon oxide layer and a polysilicon layer located on the silicon oxide layer.

[0092] In one embodiment, the second trench T2 includes a first sidewall W1 and a second sidewall W2 opposite to each other, the first sidewall W1 being close to the array region 201 and the second sidewall W2 being close to the peripheral region 203.

[0093] Figures 7a to 7b The width of the second trench T2 shown is greater than the width of the first initial trench T1', but it is not limited thereto; the width of the second trench T2 may also be less than or equal to the width of the first initial trench T1'. In one embodiment, the width of the second trench T2 is the same as the width of the spacer region 202, and the second trench T2, the third trench T3, the fourth trench T4, and the fifth trench T5 are interconnected. However, it is not limited thereto; in some other embodiments, the width of the second trench T2 is less than the width of the spacer region 202, and the second trench T2 and the array region 201 and the peripheral region 203 may also be separated by an unetched substrate 20 and / or an unetched first dielectric layer 24 located within the spacer region 202.

[0094] Next, proceed to step 106, as follows: Figures 9a to 11b As shown, a second barrier layer 27 is formed within the second trench T2.

[0095] like Figures 8a to 8b As shown, in one embodiment, before forming the second barrier layer 27, the method further includes forming a second dielectric layer 26, which fills the third trench T3, the fourth trench T4 and the fifth trench T5, and covers the first sidewall W1, the second sidewall W2 and the bottom surface of the second trench T2.

[0096] Understandably, the second trench T2 has a larger width. When forming the second dielectric layer 26, it is easier for the second dielectric layer 26 to fill the third trench T3, the fourth trench T4, and the fifth trench T5, but it is difficult to fill the second trench T2, thus only covering the inner wall of the second trench T2. In actual operation, the second dielectric layer 26 can be formed using processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). The second dielectric layer 26 also covers the second mask layer 25 located on the substrate 20. The material of the second dielectric layer 26 can be an oxide, such as silicon oxide.

[0097] Next, a second barrier layer 27 is formed within the second trench T2, comprising:

[0098] A second barrier layer 27 is formed, and the second barrier layer 27 covers the second dielectric layer 26;

[0099] A third dielectric layer 28 is formed, which covers the second barrier layer 27 and fills the second trench T2;

[0100] Part of the second dielectric layer 26, part of the second barrier layer 27, and part of the third dielectric layer 28 are removed, causing the upper surfaces of the second dielectric layer 26, the second barrier layer 27, and the third dielectric layer 28 located in the array region 201 and in the second trench T2 and close to the array region 201 to drop by a predetermined height, thereby exposing part of the sidewall of the first active pillar AA1 and part of the first sidewall W1 of the second trench T2. The remaining second dielectric layer 26 fills the lower part of the third trench T3 and the fourth trench T4, and covers the bottom surface of the second trench T2, the lower part of the first sidewall W1, and the second sidewall W2. The remaining second barrier layer 27 covers the inner wall of the second dielectric layer 26 located in the second trench T2. The remaining third dielectric layer 28 fills part of the second trench T2 and covers the second barrier layer 27.

[0101] In practical operation, processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD) can be used to form the second barrier layer 27 and the third dielectric layer 28. The material of the second barrier layer 27 can be the same as that of the first barrier layer 23, such as silicon nitride. The material of the third dielectric layer 28 can be the same as that of the second dielectric layer 26, such as silicon oxide. In this way, the etching is more uniform when removing a portion of the second dielectric layer 26, a portion of the second barrier layer 27, and a portion of the third dielectric layer 28. However, this is not a limitation. In some embodiments, the third dielectric layer 28 may not be formed. Instead, the second barrier layer 27 may be directly filled into the second trench T2 after the second dielectric layer 26 is formed.

[0102] The remaining portion of the second barrier layer 27 covering the bottom surface of the second trench T2 can serve as a stop layer for subsequent thinning processes. The remaining second dielectric layer 26 also fills the fifth trench T5 and covers the peripheral region 203, preventing the structure located in the peripheral region 203 from being damaged or contaminated in subsequent processes.

[0103] like Figures 12a to 13b As shown, after removing a portion of the second dielectric layer 26, the second barrier layer 27, and a portion of the third dielectric layer 28, the following is also included:

[0104] Multiple word line structures 29 are formed on the second dielectric layer 26, each word line structure 29 extending along the first direction and covering part of the sidewall of multiple first active pillars AA1.

[0105] A fourth dielectric layer 31 is formed, which covers the substrate 20 and fills the remaining space in the second trench T2, the third trench T3 and the fourth trench T4;

[0106] The fourth dielectric layer 31 is etched to form a plurality of openings S, each opening S extending along the second direction and exposing the upper surface of a plurality of first active pillars AA1.

[0107] A bitline structure 32 is formed within the opening S.

[0108] Here, the fourth dielectric layer 31 can be formed using processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). The word line structure 29 and bit line structure 32 can be formed using processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, and sputtering. The material of the fourth dielectric layer 31 includes oxides, such as silicon oxide. The materials of the word line structure 29 and the bit line structure 32 include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, and metal alloys, such as titanium nitride.

[0109] In one embodiment, each word line structure 29 surrounds a plurality of first active pillars AA1 arranged along a first direction. However, it is not limited to this, each word line structure 29 may also partially surround the plurality of first active pillars AA1 arranged along the first direction.

[0110] In one embodiment, prior to forming the word line structure 29, the method further includes forming a gate dielectric layer (not shown), which covers a portion of the sidewall of the first active pillar AA1 and is at least partially sandwiched between the first active pillar AA1 and the word line structure 29. The material of the gate dielectric layer (not shown) includes oxides, such as silicon oxide, which can be formed by thermally oxidizing the sidewall of the first active pillar AA1.

[0111] In one embodiment, before forming the fourth dielectric layer 31, the second mask layer 25 and a portion of the third dielectric layer 28, the second barrier layer 27 and the second dielectric layer 26 are removed, so that the upper surfaces of the second dielectric layer 26, the second barrier layer 27 and the third dielectric layer 28 located in the peripheral region 203 and located in the second trench T2 and close to the peripheral region 203 are flush with the upper surface of the substrate 20.

[0112] Next, proceed to step 107, as follows: Figures 15a to 15b As shown, starting from the second surface S2 of the substrate 20, a first thinning process is performed on the substrate 20 until the first barrier layer 23 is exposed.

[0113] Specifically, starting from the second surface S2 of the substrate 20, a first thinning process is performed on the substrate 20 until the first barrier layer 23 is exposed, including:

[0114] A rough grinding process is performed on the second surface S2 of the substrate 20 to reduce the substrate 20 to a first preset thickness;

[0115] A fine grinding process is performed on the second surface S2 of the substrate 20 to reduce the substrate 20 to a second preset thickness;

[0116] A first chemical mechanical polishing process is performed on the second surface S2 of the substrate 20 to expose the first barrier layer 23, thereby thinning the substrate 20 to a third preset thickness; wherein the thinning rate of the fine grinding process is less than the thinning rate of the coarse grinding process, and the thinning rate of the first chemical mechanical polishing process is less than the thinning rate of the fine grinding process.

[0117] like Figures 14a to 14b As shown, more specifically, before performing the first thinning process on the substrate 20, the method further includes: providing a carrier 34; and fixing the carrier 34 to the first surface S1 of the substrate 20 via an adhesive layer 33. Subsequently, the semiconductor structure composed of the substrate 20, the adhesive layer 33, and the carrier 34 can be inverted so that the second surface S2 of the substrate 20 faces upwards. Then, a thinning process is performed on the second surface S2 of the substrate 20, with the carrier 34 used to support the substrate 20 during the thinning process. The material of the carrier 34 includes semiconductor materials, such as silicon.

[0118] In one embodiment, the ratio of the first preset thickness to the sum of the first preset thickness, the second preset thickness, and the third preset thickness (i.e., the thinning thickness of the first thinning process) ranges from 0.7 to 0.9, and the third preset thickness ranges from 1 μm to 10 μm. In some embodiments, the coarse grinding process uses a diamond wheel abrasive to cut the substrate 20. The diamond wheel abrasive has a large particle size and a fast cutting speed. In this embodiment, the second surface S2 of the substrate 20 is first thinned using a coarse grinding process, and a thicker portion of the substrate 20 is removed, shortening the time of the first thinning process and improving the overall efficiency of the first thinning process. Then, a fine grinding process with a lower thinning rate is used for thinning, which increases the thinning accuracy of the first thinning process on the one hand, and reduces the damage caused by the coarse grinding process on the other hand, making the second surface S2 of the substrate 20 smoother and less damaged. Then, a first chemical mechanical polishing process with an even lower thinning rate is used to continue thinning the substrate 20 until the first barrier layer 23 is exposed, further improving the thinning accuracy and avoiding over-thinning. In one embodiment, the thinning rate of the coarse grinding process ranges from 3 μm / s to 7 μm / s, for example, 3 μm / s, 4 μm / s, 5 μm / s, 6 μm / s, 7 μm / s; the thinning rate of the fine grinding process is less than 1 μm / s, for example, 0.1 μm / s, 0.3 μm / s, 0.5 μm / s, 0.7 μm / s, 0.9 μm / s; and the thinning rate of the first chemical mechanical polishing process ranges from 1 to 50 nm / s, for example, 1 nm / s, 10 nm / s, 20 nm / s, 30 nm / s, 40 nm / s, 50 nm / s.

[0119] Next, proceed to step 108, as follows: Figures 16a to 16bAs shown, starting from the exposed first barrier layer 23, a second thinning process is performed on the substrate 20 until the second barrier layer 27 is exposed, wherein the thinning rate of the second thinning process is less than the thinning rate of the first thinning process.

[0120] Specifically, starting from the exposed first barrier layer 23, a second thinning process is performed on the substrate 20 until the second barrier layer 27 is exposed, including:

[0121] Starting from the exposed first barrier layer 23, a second chemical mechanical polishing process is performed on the substrate 20 until the first dielectric layer 24 is exposed;

[0122] Starting from the exposed first dielectric layer 24, a third chemical mechanical polishing process is performed on the substrate 20 until the second barrier layer 27 is exposed; wherein the thinning rate of the third chemical mechanical polishing process is equal to or less than the thinning rate of the second chemical mechanical polishing process.

[0123] The second chemical mechanical polishing (CMP) process polishes the substrate 20 and the first barrier layer 23. The third CMP process polishes the substrate 20, the first dielectric layer 24, and part of the second dielectric layer 26. Since the materials to be polished in the two polishing processes are different, the parameters of the polishing slurry used in the two polishing processes are different in order to ensure the planarization of the polishing. This is so that the thinning rate of different materials is the same or similar in each CMP process. That is, in the second CMP process, the thinning rate of the substrate 20 and the first barrier layer 23 is the same or similar, and in the third CMP process, the thinning rate of the substrate 20, the first dielectric layer 24, and the second dielectric layer 26 is the same or similar.

[0124] The thinning rates of the third chemical mechanical polishing (CMP) process and the second CMP process can be the same or close. However, this is not the case. The second CMP process can also have a larger thinning rate than the third CMP process. This can improve the overall thinning efficiency of the second thinning process, while the smaller thinning rate of the third CMP process can improve the thinning accuracy of the second thinning process and avoid over-thinning. In one embodiment, the thinning rate of the second CMP process is in the range of 1-50 nm / s, for example, 1 nm / s, 10 nm / s, 20 nm / s, 30 nm / s, 40 nm / s, and 50 nm / s; the thinning rate of the third CMP process is in the range of 1-50 nm / s, for example, 1 nm / s, 10 nm / s, 20 nm / s, 30 nm / s, 40 nm / s, and 50 nm / s.

[0125] The first barrier layer 23 serves as the stop layer for the first thinning process, and the second barrier layer 27 serves as the stop layer for the second thinning process. When the thickness of the first barrier layer 23 is small, the effect of stopping the first thinning process is not good. When the thickness of the first barrier layer 23 is large, the thickness of the first dielectric layer 24 is small, which reduces the accuracy of the third chemical mechanical polishing process, thereby reducing the accuracy of the second thinning process. Therefore, in some embodiments, the thickness of the first barrier layer 23 is between 50nm and 100nm, for example, 50nm, 60nm, 70nm, 80nm, 90nm, and 100nm, and the thickness of the first dielectric layer 24 is between 100nm and 200nm, for example, 100nm, 120nm, 140nm, 160nm, 180nm, and 200nm.

[0126] like Figure 16b As shown, in this embodiment of the present disclosure, a second dielectric layer 26 is formed in the second trench T2 before the second barrier layer 27 is formed, such that the bottom surface of the second barrier layer 27 is higher than the bottom surfaces of the first active pillar AA1 and the second active pillar AA2. Thus, after the first thinning process and the second thinning process are performed to expose the second barrier layer 27, the bottoms of the first active pillar AA1 and the second active pillar AA2 are also removed, so that the multiple first active pillars AA1 and the multiple second active pillars AA2 are separated from each other, avoiding electrical connection between different active pillars.

[0127] As can be seen, in this embodiment of the present disclosure, a first barrier layer 23 is provided below the second barrier layer 27. The first barrier layer 23 serves as a stop layer for the first thinning process, and the second barrier layer 27 serves as a stop layer for the second thinning process. By setting up a double-layer thinning stop layer, the accuracy of the thinning process is improved, avoiding damage to other structures located within the substrate 20 due to excessive thinning thickness, or insufficient thinning thickness that fails to reach the target thinning thickness. In addition, in this embodiment of the present disclosure, the thinning rate of the first thinning process is relatively large, which improves the thinning efficiency, while the thinning rate of the second thinning process is relatively small, which further improves the thinning accuracy and reduces the damage caused by the first thinning process, so that the second surface S2 of the thinned substrate 20 has better flatness and less damage.

[0128] It should be noted that those skilled in the art can make possible changes to the order of the above steps without departing from the scope of protection of this disclosure.

[0129] This disclosure also provides a semiconductor structure, such as Figures 13a to 13bAs shown, the semiconductor structure includes: a substrate 20, which includes a first surface S1 and a second surface S2 opposite to the first surface S1; a second trench T2 extending from the first surface S1 of the substrate 20 into the interior, and a first trench T1 located below the second trench T2 and communicating with the second trench T2; a first barrier layer 23 filling the lower part of the first trench T1; a first dielectric layer 24 filling the upper part of the first trench T1; and a second barrier layer 27 located in the second trench T2.

[0130] The substrate 20 may be a semiconductor substrate and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate 20 is a silicon substrate, which may be doped or undoped.

[0131] In one embodiment, the substrate 20 includes an array region 201, a peripheral region 203, and a spacer region 202 located between the array region 201 and the peripheral region 203. The peripheral region 203 surrounds the array region 201 and is separated from the array region 201 by the spacer region 202.

[0132] In one embodiment, the first trench T1 and the second trench T2 are located in the spacer region 202; see also Figures 7a to 7b The semiconductor structure also includes: multiple third trenches T3 extending along a first direction, multiple fourth trenches T4 extending along a second direction, and a fifth trench T5 located within the substrate 20. The third trenches T3 and the fourth trenches T4 are located in the array region 201 and intersect each other to define multiple discrete first active pillars AA1 within the array region 201. The fifth trench T5 is located in the peripheral region 203 and defines multiple discrete second active pillars AA2 within the peripheral region 203.

[0133] Multiple first active pillars AA1 are arranged in an array within the array region 201 along a first direction and a second direction. In some embodiments, the first direction and the second direction are perpendicular to each other. However, this is not a limitation; the first direction and the second direction may also intersect obliquely.

[0134] In actual operation, the first trench T1, the second trench T2, the first barrier layer 23, and the first dielectric layer 24 can be formed in the following manner: First, etching is performed from the first surface S1 of the substrate 20 inward to form a first initial trench (not shown); then, the lower part of the first initial trench (not shown) is filled with the first barrier layer 23; then, the upper part of the first initial trench (not shown) is filled with the first dielectric layer 24; then, the substrate 20 and the first dielectric layer 24 are etched to form the second trench T2 at the top position of the first initial trench (not shown), and the portion of the first initial trench (not shown) located below the second trench T2 constitutes the first trench T1, with a portion of the first dielectric layer 24 remaining in the first trench T1. In some embodiments, the second trench T2, the third trench T3, the fourth trench T4, and the fifth trench T5 are formed in the same step.

[0135] Figures 13a to 13b The width of the second trench T2 shown is greater than the width of the first trench T1, but it is not limited thereto; the width of the second trench T2 may also be less than or equal to the width of the first trench T1. In some embodiments, the width of the second trench T2 is the same as the width of the spacer region 202, and the second trench T2, the third trench T3, the fourth trench T4, and the fifth trench T5 are interconnected. However, it is not limited thereto; in some other embodiments, the width of the second trench T2 is less than the width of the spacer region 202, and the second trench T2 and the array region 201 and the peripheral region 203 may also be separated by an unetched substrate 20 and / or an unetched first dielectric layer 24 located within the spacer region 202.

[0136] In one embodiment, the material of the first barrier layer 23 includes one or more of nitrides, oxynitrides, and carbides, such as silicon nitride. The materials of the first dielectric layer 24 and the first barrier layer 23 are different. In some embodiments, the material of the first dielectric layer 24 includes oxides, such as silicon oxide.

[0137] In one embodiment, the semiconductor structure further includes an insulating layer (not shown) covering the inner wall of the first trench T1 to protect the substrate 20 exposed by the first trench T1 from damage or contamination during the fabrication of the semiconductor structure. The insulating layer (not shown) may be made of an oxide, such as silicon oxide.

[0138] In one embodiment, the second trench T2 includes opposing first sidewalls W1 and second sidewalls W2, with the first sidewall W1 near the array region 201 and the second sidewall W2 near the peripheral region 203. The semiconductor structure further includes: a second dielectric layer 26, which fills the lower portions of the third trench T3 and the fourth trench T4, and covers the bottom surface of the second trench T2, the lower portion of the first sidewall W1, and the second sidewall W2; a second barrier layer 27, which covers the inner wall of the second dielectric layer 26 located within the second trench T2; and a third dielectric layer 28, which fills a portion of the second trench T2 and covers the second barrier layer 27. In some embodiments, the second dielectric layer 26 further fills a fifth trench T5. The material of the second barrier layer 27 may be the same as the material of the first barrier layer 23, such as silicon nitride. The material of the third dielectric layer 28 includes oxides, such as silicon oxide.

[0139] Subsequently, a thinning process can be performed on the second surface S2 of the substrate 20, and the first barrier layer 23 and the second barrier layer 27 can serve as stop layers for the thinning process. Specifically, firstly, starting from the second surface S2 of the substrate 20, a first thinning process is performed on the substrate 20 until the first barrier layer 23 is exposed; then, starting from the exposed first barrier layer 23, a second thinning process is performed on the substrate 20 until the second barrier layer 27 is exposed, wherein the thinning rate of the second thinning process is less than the thinning rate of the first thinning process. In this embodiment, a first barrier layer 23 is provided below the second barrier layer 27. The first barrier layer 23 serves as a stop layer for the first thinning process, and the second barrier layer 27 serves as a stop layer for the second thinning process. By setting up a double-layer thinning stop layer, the accuracy of the thinning process is improved, avoiding damage to other structures located within the substrate 20 due to excessive thinning thickness, or insufficient thinning thickness that fails to reach the target thinning thickness. Furthermore, in this embodiment, the first thinning process has a larger thinning rate, which improves the thinning efficiency, while the second thinning process has a smaller thinning rate, which further improves the thinning accuracy and reduces the damage caused by the first thinning process, resulting in better flatness and less damage on the second surface S2 of the thinned substrate 20.

[0140] In this embodiment, the thinning rate of the second thinning process is less than that of the first thinning process. The first barrier layer 23 serves as the stop layer of the first thinning process, and the second barrier layer 27 serves as the stop layer of the second thinning process. When the depth of the second trench T2 is large and the depth of the first trench T1 is small, the thickness of the first dielectric layer 24 and the first barrier layer 23 is small, which affects the accuracy of the thinning process. When the depth of the second trench T2 is small and the depth of the first trench T1 is large, the thickness of the second dielectric layer 26 and the first barrier layer 23 is large. Since the second thinning process has a smaller rate, the overall time of the thinning process is increased. Therefore, in one embodiment, the depth of the second trench T2 is between 100nm and 200nm, for example, 100nm, 120nm, 140nm, 160nm, 180nm, or 200nm; and the depth of the first trench T1 is between 150nm and 300nm, for example, 150nm, 170nm, 200nm, 220nm, 250nm, 270nm, or 300nm.

[0141] More specifically, in actual operation, the first thinning process of substrate 20 can be performed in the following manner: First, a coarse grinding process is performed on the second surface S2 of substrate 20 to reduce substrate 20 to a first preset thickness; then, a fine grinding process is performed on the second surface S2 of substrate 20 to reduce substrate 20 to a second preset thickness; then, a first chemical mechanical polishing process is performed on the second surface S2 of substrate 20 until the first barrier layer 23 is exposed to reduce substrate 20 to a third preset thickness; wherein, the thinning rate of the fine grinding process is less than the thinning rate of the coarse grinding process, and the thinning rate of the first chemical mechanical polishing process is less than the thinning rate of the fine grinding process.

[0142] In one embodiment, the ratio of the first preset thickness to the sum of the first preset thickness, the second preset thickness, and the third preset thickness (i.e., the thinning thickness of the first thinning process) ranges from 0.7 to 0.9, and the third preset thickness ranges from 1 μm to 10 μm. In some embodiments, the coarse grinding process uses a diamond wheel abrasive to cut the substrate 20. The diamond wheel abrasive has a large particle size and a fast cutting speed. In this embodiment, the second surface S2 of the substrate 20 is first thinned using a coarse grinding process, and a thicker portion of the substrate 20 is removed, shortening the time of the first thinning process and improving the overall efficiency of the first thinning process. Then, a fine grinding process with a lower thinning rate is used for thinning, which increases the thinning accuracy of the first thinning process on the one hand, and reduces the damage caused by the coarse grinding process on the other hand, making the second surface S2 of the substrate 20 smoother and less damaged. Then, a first chemical mechanical polishing process with an even lower thinning rate is used to continue thinning the substrate 20 until the first barrier layer 23 is exposed, further improving the thinning accuracy and avoiding over-thinning. In one embodiment, the thinning rate of the coarse grinding process ranges from 3 μm / s to 7 μm / s, for example, 3 μm / s, 4 μm / s, 5 μm / s, 6 μm / s, 7 μm / s; the thinning rate of the fine grinding process is less than 1 μm / s, for example, 0.1 μm / s, 0.3 μm / s, 0.5 μm / s, 0.7 μm / s, 0.9 μm / s; and the thinning rate of the first chemical mechanical polishing process ranges from 1 to 50 nm / s, for example, 1 nm / s, 10 nm / s, 20 nm / s, 30 nm / s, 40 nm / s, 50 nm / s.

[0143] In practice, the second thinning process can be performed on the substrate 20 as follows: starting from the exposed first barrier layer 23, the substrate 20 is subjected to a second chemical mechanical polishing process until the first dielectric layer 24 is exposed; continuing from the exposed first dielectric layer 24, the substrate 20 is subjected to a third chemical mechanical polishing process until the second barrier layer 27 is exposed; wherein, the thinning rate of the third chemical mechanical polishing process is equal to or less than the thinning rate of the second chemical mechanical polishing process.

[0144] The second chemical mechanical polishing (CMP) process polishes the substrate 20 and the first barrier layer 23. The third CMP process polishes the substrate 20, the first dielectric layer 24, and part of the second dielectric layer 26. Since the materials to be polished in the two polishing processes are different, the parameters of the polishing slurry used in the two polishing processes are different in order to ensure the planarization of the polishing. This is so that the thinning rate of different materials is the same or similar in each CMP process. That is, in the second CMP process, the thinning rate of the substrate 20 and the first barrier layer 23 is the same or similar, and in the third CMP process, the thinning rate of the substrate 20, the first dielectric layer 24, and the second dielectric layer 26 is the same or similar.

[0145] The thinning rates of the third chemical mechanical polishing (CMP) process and the second CMP process can be the same or close. However, this is not the case. The second CMP process can also have a larger thinning rate than the third CMP process. This can improve the overall thinning efficiency of the second thinning process. The smaller thinning rate of the third CMP process can improve the thinning accuracy of the second thinning process and avoid over-thinning. In one embodiment, the thinning rate of the second CMP process is in the range of 1-50 nm / s, for example, 1 nm / s, 10 nm / s, 20 nm / s, 30 nm / s, 40 nm / s, and 50 nm / s; the thinning rate of the third CMP process is in the range of 1-50 nm / s, for example, 1 nm / s, 10 nm / s, 20 nm / s, 30 nm / s, 40 nm / s, and 50 nm / s.

[0146] The first barrier layer 23 serves as the stop layer for the first thinning process, and the second barrier layer 27 serves as the stop layer for the second thinning process. When the thickness of the first barrier layer 23 is small, the effect of stopping the first thinning process is not good. When the thickness of the first barrier layer 23 is large, the thickness of the first dielectric layer 24 is small, which reduces the accuracy of the third chemical mechanical polishing process, thereby reducing the accuracy of the second thinning process. Therefore, in some embodiments, the thickness of the first barrier layer 23 is between 50nm and 100nm, for example, 50nm, 60nm, 70nm, 80nm, 90nm, and 100nm, and the thickness of the first dielectric layer 24 is between 100nm and 200nm, for example, 100nm, 120nm, 140nm, 160nm, 180nm, and 200nm.

[0147] like Figures 13a to 13b As shown, the second dielectric layer 26 is located below the second barrier layer 27, such that the bottom surface of the second barrier layer 27 is higher than the bottom surfaces of the first active pillar AA1 and the second active pillar AA2. Thus, in actual operation, after the first thinning process and the second thinning process are performed to expose the second barrier layer 27, the bottom surfaces of the first active pillar AA1 and the second active pillar AA2 are also removed, so that the multiple first active pillars AA1 and the multiple second active pillars AA2 are separated from each other, avoiding electrical connection between different active pillars.

[0148] In one embodiment, the semiconductor structure further includes: word line structures 29 located on the second dielectric layer 26, each word line structure 29 extending along a first direction and covering a portion of the sidewalls of a plurality of first active pillars AA1; a fourth dielectric layer 31 covering the substrate 20 and filling the remaining space in the third trench T3, the fourth trench T4, and the second trench T2; a plurality of openings S located on the fourth dielectric layer 31, each opening S extending along a second direction and exposing the upper surface of the plurality of first active pillars AA1; and bit line structures 32 located within the openings S.

[0149] In one embodiment, each word line structure 29 surrounds a plurality of first active pillars AA1 arranged along a first direction. However, this is not a limitation; each word line structure 29 may also partially surround the plurality of first active pillars AA1 arranged along the first direction. In some embodiments, the semiconductor structure further includes a gate dielectric layer (not shown) that covers a portion of the sidewalls of the first active pillars AA1 and is at least partially sandwiched between the first active pillars AA1 and the word line structure 29. The material of the gate dielectric layer (not shown) includes oxides, such as silicon oxide, which can be formed by thermally oxidizing the sidewalls of the first active pillars AA1.

[0150] The material of the fourth dielectric layer 31 includes oxides, such as silicon oxide. The materials of the word line structure 29 and the bit line structure 32 include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, and metal alloys, such as titanium nitride.

[0151] It should be noted that the above description is only a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first surface and a second surface opposite to the first surface; Etching from the first surface of the substrate inwards forms a first initial trench; A first barrier layer is filled in the lower part of the first initial trench; A first dielectric layer is filled in the upper part of the first initial trench; The substrate and the first dielectric layer are etched to form a second trench at the top of the first initial trench. The first initial trench located below the second trench constitutes a first trench, and a portion of the first dielectric layer is retained in the first trench. A second barrier layer is formed within the second trench; Starting from the second surface of the substrate, a first thinning process is performed on the substrate until the first barrier layer is exposed; Starting from the exposed first barrier layer, a second thinning process is performed on the substrate until the second barrier layer is exposed, wherein the thinning rate of the second thinning process is less than the thinning rate of the first thinning process.

2. The manufacturing method according to claim 1, characterized in that, Starting from the second surface of the substrate, a first thinning process is performed on the substrate until the first barrier layer is exposed, including: A rough grinding process is performed on the second surface of the substrate to reduce the substrate to a first preset thickness; A fine grinding process is performed on the second surface of the substrate to reduce the substrate to a second predetermined thickness; A first chemical mechanical polishing process is performed on the second surface of the substrate to expose the first barrier layer, thereby thinning the substrate to a third predetermined thickness; wherein the thinning rate of the fine polishing process is less than the thinning rate of the coarse polishing process, and the thinning rate of the first chemical mechanical polishing process is less than the thinning rate of the fine polishing process.

3. The manufacturing method according to claim 2, characterized in that, The thinning rate of the coarse grinding process ranges from 3 μm / s to 7 μm / s, the thinning rate of the fine grinding process is less than 1 μm / s, and the thinning rate of the first chemical mechanical polishing process ranges from 1 to 50 nm / s.

4. The manufacturing method according to claim 2, characterized in that, Starting from the exposed first barrier layer, a second thinning process is performed on the substrate until the second barrier layer is exposed, including: Starting from the exposed first barrier layer, a second chemical mechanical polishing process is performed on the substrate until the first dielectric layer is exposed; Starting from the exposed first dielectric layer, a third chemical mechanical polishing process is performed on the substrate until the second barrier layer is exposed; wherein the thinning rate of the third chemical mechanical polishing process is equal to or less than the thinning rate of the second chemical mechanical polishing process.

5. The manufacturing method according to claim 4, characterized in that, The thinning rate of the second chemical mechanical polishing process is in the range of 1-50 nm / s, and the thinning rate of the third chemical mechanical polishing process is in the range of 1-50 nm / s.

6. The manufacturing method according to claim 1, characterized in that, The substrate includes an array region, a peripheral region, and a spacer region located between the array region and the peripheral region, wherein the first initial trench and the second trench are formed in the spacer region; While etching the substrate and the first dielectric layer, and forming a second trench at the top position of the first initial trench, the process also includes: The substrate located in the array region and the peripheral region is etched to form a plurality of third trenches extending along a first direction and a plurality of fourth trenches extending along a second direction in the array region. The third trenches and the fourth trenches intersect each other to define a plurality of first active pillars in the substrate. A fifth trench is formed in the peripheral region to define a plurality of discrete second active pillars in the substrate.

7. The manufacturing method according to claim 6, characterized in that, The second trench includes opposing first and second sidewalls, the first sidewall being close to the array region and the second sidewall being close to the peripheral region; Before the formation of the second barrier layer, the following are also included: A second dielectric layer is formed, which fills the third trench, the fourth trench and the fifth trench, and covers the first sidewall, the second sidewall and the bottom surface of the second trench.

8. The manufacturing method according to claim 7, characterized in that, A second barrier layer is formed within the second trench, comprising: A second barrier layer is formed, which covers the second dielectric layer; A third dielectric layer is formed, which covers the second barrier layer and fills the second trench; A portion of the second dielectric layer, a portion of the second barrier layer, and a portion of the third dielectric layer are removed, causing the upper surfaces of the second dielectric layer, the second barrier layer, and the third dielectric layer located in the array region and in the second trench and close to the array region to drop by a predetermined height, thereby exposing a portion of the sidewall of the first active pillar and a portion of the first sidewall of the second trench; the remaining second dielectric layer fills the lower part of the third trench and the fourth trench, and covers the bottom surface of the second trench, the lower part of the first sidewall, and the second sidewall; the remaining second barrier layer covers the inner wall of the second dielectric layer located in the second trench; and the remaining third dielectric layer fills a portion of the second trench and covers the second barrier layer.

9. The manufacturing method according to claim 8, characterized in that, After removing a portion of the second dielectric layer, a portion of the second barrier layer, and a portion of the third dielectric layer, the method further includes: Multiple word line structures are formed on the second dielectric layer, each word line structure extending along the first direction and covering part of the sidewall of multiple first active pillars; A fourth dielectric layer is formed, which covers the substrate and fills the second trench, the third trench, and the remaining space within the fourth trench; The fourth dielectric layer is etched to form a plurality of openings, each of which extends along the second direction and exposes the upper surface of a plurality of the first active pillars; A bitline structure is formed within the opening.

10. A semiconductor structure, characterized in that, include: A substrate, the substrate including a first surface and a second surface opposite to the first surface; the substrate including an array region, a peripheral region and a spacing region located between the array region and the peripheral region; A second trench extending from the first surface of the substrate into the interior and a first trench located below and communicating with the second trench, the first trench and the second trench being located in the spacer region; A first barrier layer fills the lower part of the first trench; A first dielectric layer fills the upper part of the first trench; The second barrier layer is located within the second trench; The thickness of the first dielectric layer is greater than or equal to the thickness of the first barrier layer.

11. The semiconductor structure according to claim 10, characterized in that, The depth of the second trench ranges from 100nm to 200nm, and the depth of the first trench ranges from 150nm to 300nm.

12. The semiconductor structure according to claim 10, characterized in that, The thickness of the first dielectric layer is between 100 nm and 200 nm, and the thickness of the first barrier layer is between 50 nm and 100 nm.

13. The semiconductor structure according to claim 10, characterized in that, The semiconductor structure further includes: a plurality of third trenches extending along a first direction, a plurality of fourth trenches extending along a second direction, and a fifth trench located within the substrate, wherein the third trenches and the fourth trenches are located in the array region and intersect each other to define a plurality of discrete first active pillars within the array region, and the fifth trench is located in the peripheral region and defines a plurality of discrete second active pillars within the peripheral region.

14. The semiconductor structure according to claim 13, characterized in that, The second trench includes opposing first and second sidewalls, the first sidewall being close to the array region and the second sidewall being close to the peripheral region; The semiconductor structure further includes: a second dielectric layer, which fills the lower part of the third trench and the fourth trench and the fifth trench, and covers the bottom surface of the second trench, the lower part of the first sidewall and the second sidewall, and the second barrier layer covers the inner wall of the second dielectric layer located in the second trench; and a third dielectric layer, which fills part of the second trench and covers the second barrier layer.

15. The semiconductor structure according to claim 14, characterized in that, The semiconductor structure also includes: A word line structure is located on the second dielectric layer, and each of the word line structures extends along the first direction and covers part of the sidewall of a plurality of first active pillars. A fourth dielectric layer covers the substrate and fills the remaining space in the third trench, the fourth trench, and the second trench; A plurality of openings located on the fourth medium, each of the openings extending along the second direction and exposing the upper surfaces of a plurality of the first active pillars; a bitline structure located within the openings.

Images