一种芯片堆叠封装的方法及芯片封装件
By laying encapsulating adhesive layers around the chip and using additive manufacturing technology to extend the hollow conductive path, the problems of high welding difficulty and high cost in existing 3D packaging are solved, and efficient and reliable chip stacking packaging is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN REWO MICRO SEMICON TECH CO LTD
- Filing Date
- 2023-01-06
- Publication Date
- 2026-07-17
AI Technical Summary
Existing 3D packaging technologies are difficult to weld, costly, and have poor reliability, with multi-point welding processes being complex.
An additive manufacturing method is used to lay an encapsulating adhesive layer around the chip. The encapsulating adhesive layer has longitudinal through holes. The chip electrodes are extended to the bottom through additive manufacturing, and a hollow conductive path is extended along the inner wall of the through hole for encapsulation. The multi-layer chips are connected and conductive through the hollow conductive path, avoiding the hot soldering process of solder balls.
It improved production efficiency and process quality, reduced process difficulty and manufacturing costs, and ensured product reliability.
Smart Images
Figure CN116313824B_ABST