Electronic device and packaging method thereof

Abstract

The present disclosure provides a packaging method of an electronic device, comprising: providing a first substrate, forming a first bonding layer on the first substrate, the first bonding layer being composed of a material having a liquidus line between 300-450℃; providing a second substrate, forming a second bonding layer on the second substrate, the second bonding layer being composed of a material capable of eutectic bonding with the material of the first bonding layer; forming a first region capable of eutectic bonding and a second region of eutectic blocking in the second bonding layer; and packaging the first substrate and the second substrate together by eutectic bonding the first bonding layer and the second bonding layer.

Description

Technical Field

[0001] This disclosure relates to the field of electronics, and more specifically, to an electronic device and a method for packaging the same. Background Technology

[0002] A wide variety of electronic devices can be fabricated on substrates. As the physical structure of electronic devices becomes increasingly complex, they often include different types of components, such as thin-film acoustic wave resonators, bulk acoustic wave filters, and transistors. However, different types of components have different requirements for the performance parameters of the substrate. For example, substrates used to fabricate bulk acoustic wave filters typically require high resistivity, while substrates used to fabricate transistors typically require low resistivity. Therefore, when fabricating electronic devices with different types of components, it is usually necessary to fabricate the different components separately on substrates with different performance parameters, and then package them together using wafer-level packaging technology.

[0003] Please see Figure 1 , Figure 1 A schematic diagram of a wafer-level packaging structure in the prior art is shown. For example... Figure 1 As shown, traditional wafer-level packaging structures currently mainly use gold-gold (Au-Au) bonding technology to achieve hermetical packaging between different substrates. Taking a thin-film bulk acoustic wave resonator as an example, a high-resistivity single-crystal silicon (Si) substrate 11 is provided. A cavity 12 is first processed on the substrate 11. A resonator 13, a gold pad array 14 electrically connected to the resonator 13, and a continuous or discontinuous annular gold layer serving as a protective barrier around the gold pads 14 are formed on the top surface of the high-resistivity single-crystal silicon substrate 11. Then, corresponding gold bonding points / lines 15 and 17 are formed below a low-resistivity single-crystal silicon substrate 16 on which semiconductor elements (not shown) are formed. The low-resistivity single-crystal silicon substrate and the high-resistivity single-crystal silicon substrate are pressed together by a gold-gold bonding process. The top surface of the low-resistivity silicon substrate 16 is thinned by a diamond grinding wheel process. Finally, a contact plug 18 is formed using a through-silicon via (TSV) process to electrically connect the gold pads 14. Then, a redistribution line (RDL) 19 is formed on top of the thinned low-resistivity silicon substrate 16, and then balls are placed on the redistribution line 19 to form a wafer-level package of the electronic device.

[0004] Gold-gold thermocompression bonding is a crucial step in wafer-level packaging. The principle of gold-gold thermocompression bonding is that when gold-gold interfaces come into contact, under high temperature and pressure, gold atoms diffuse into each other, forming a diffusion layer. This diffusion layer bonds the two original gold layers together, forming a unified whole, thus achieving bonding and sealing.

[0005] However, for the packaging structure of the aforementioned electronic devices, on the one hand, the use of gold-to-metal bonding leads to persistently high packaging costs. On the other hand, gold-to-metal bonding requires the bonding surfaces of the electronic device's packaging structure to be highly flat and free of contamination, and to ensure high adhesion of the bonding layer metals during the process. Therefore, the flatness requirements for the bonding surfaces are high when using gold-to-metal bonding. Furthermore, during wafer bonding, voids may form at the bonding interface, which reduces the reliability of the electrical connection between components mounted on the two wafers. Therefore, providing a new wafer-level packaging structure and process to solve the above-mentioned technical problems is desirable for the art. Summary of the Invention

[0006] This disclosure addresses the aforementioned technical problems by designing a novel packaging structure for an electronic device and its fabrication method. The aim is to overcome the technical problems existing in the prior art, thereby reducing manufacturing costs, improving process stability, ensuring the reliability of electrical connections, and increasing product yield.

[0007] A brief overview of this disclosure will be given below to provide a basic understanding of certain aspects of it. It should be understood that this overview is not an exhaustive summary of this disclosure. It is not intended to identify key or essential parts of this disclosure, nor is it intended to limit the scope of this disclosure. Its purpose is merely to present certain concepts in a simplified form as a prelude to the more detailed description that follows.

[0008] According to one aspect of this disclosure, a method for manufacturing an electronic device is provided, comprising: providing a first substrate; forming a first bonding layer on the first substrate, the first bonding layer being composed of a material with a liquidus line between 300-450°C; providing a second substrate; forming a second bonding layer on the second substrate, the second bonding layer being composed of a material capable of eutectic bonding with the material of the first bonding layer; forming a first region capable of eutectic bonding and a second region capable of eutectic blocking in the second bonding layer; and encapsulating the first substrate and the second substrate together by eutectic bonding of the first bonding layer and the second bonding layer.

[0009] According to another aspect of this disclosure, an electronic device is provided, comprising: a first substrate, a first bonding layer formed on a first surface of the first substrate, a second substrate, a second bonding layer formed on a first surface of the second substrate, the second bonding layer being composed of a material capable of eutectic bonding with the material of the first bonding layer; the second bonding layer including a first region capable of eutectic bonding and a second region capable of eutectic blocking; and a eutectic bonding layer formed between the first surface of the first substrate and the first surface of the second substrate through eutectic bonding of the first bonding layer and the second bonding layer. Attached Figure Description

[0010] The specific details of this disclosure are described below with reference to the accompanying drawings, which will facilitate a more readily understanding of the above and other objects, features, and advantages of this disclosure. The drawings are merely for illustrating the principles of this disclosure. The dimensions and relative positions of the elements are not necessarily drawn to scale in the drawings.

[0011] Figure 1 A schematic diagram of the structure of an existing electronic device is shown;

[0012] Figure 2 A schematic diagram of the filter structure is shown in a specific embodiment of the present disclosure;

[0013] Figure 3-4 A schematic diagram of the pattern of the second bonding layer is shown.

[0014] Figure 5-6 This invention illustrates a modified embodiment of the filter structure provided in this disclosure;

[0015] Figure 7-16 A schematic diagram of the fabrication process based on the filter structure provided in this disclosure is shown. Detailed Implementation

[0016] Exemplary disclosures of this disclosure will be described below with reference to the accompanying drawings. For clarity and brevity, not all features implementing this disclosure are described in the specification. However, it should be understood that many disclosure-specific decisions can be made in developing any such implementation of this disclosure to achieve the developer’s specific goals, and these decisions may vary depending on the specific disclosure.

[0017] It should also be noted that, in order to avoid obscuring this disclosure with unnecessary details, only the device structure closely related to the scheme according to this disclosure is shown in the accompanying drawings, while other details that are not closely related to this disclosure are omitted.

[0018] Generally, it should be understood that the drawings and the various elements depicted therein are not drawn to scale. Furthermore, the use of relative terms (such as "above", "below", "top", "bottom", "upper", and "lower") to describe the relationships between the various elements should be understood to cover different orientations of the device and / or element in addition to the orientations depicted in the drawings.

[0019] It should be understood that this disclosure is not limited to the described embodiments by virtue of the following description with reference to the accompanying drawings. Throughout this document, features may be substituted or borrowed between different embodiments where feasible, and one or more features may be omitted in one embodiment, wherein the same reference numerals denote the same parts. It should be understood that the manufacturing steps of this disclosure are exemplary in the embodiments, and the order of the steps may be adjusted.

[0020] The electronic device described in this embodiment is an example of a filter, but those skilled in the art will understand that the solutions disclosed herein are not limited to filters.

[0021] See Figure 2 , Figure 2 A schematic diagram of a filter structure according to a specific embodiment provided in this disclosure is shown. The filter has a first substrate 100, which may be, for example, high-resistivity silicon, gallium arsenide, indium phosphide, glass, sapphire, or aluminum oxide. 、 Materials used in SiC and other adaptive filters to fabricate resonator components and to form materials compatible with semiconductor processes. It should be particularly noted that when the first substrate 100 is made of glass, its low dielectric constant and high resistive efficiency offer significant advantages in high-frequency performance.

[0022] An acoustic wave reflecting region 110, consisting of a structure such as an air cavity or a Bragg reflector layer, can be formed in the first substrate 100. The Bragg reflector layer can be formed by stacking thin films with different acoustic impedances.

[0023] At least one resonator assembly is formed on the first substrate 100. The resonator assembly may include at least one resonator 200, which includes a structural functional layer, which includes at least an upper electrode, a lower electrode and a piezoelectric layer.

[0024] In one embodiment, the lower electrode can be a single layer or multiple layers, and the lower electrode can completely or partially cover the first substrate. The lower electrode can be formed of one or more conductive materials, such as various metals compatible with semiconductor processes, including tungsten, molybdenum, iridium, aluminum, platinum, ruthenium, niobium, or hafnium.

[0025] A piezoelectric layer is formed on the lower electrode. The piezoelectric layer can be formed from any piezoelectric material compatible with semiconductor processes, such as aluminum nitride, doped aluminum nitride, or zirconate titanate (PZT).

[0026] An upper electrode is formed on the piezoelectric layer. The upper electrode can be formed of one or more conductive materials, such as various semiconductor-compatible metals including tungsten, molybdenum, iridium, aluminum, platinum, ruthenium, niobium, or hafnium. The materials of the upper electrode and the lower electrode can be the same or different.

[0027] It is understood that the structural functional layer of the resonator may further include structural layers such as a mass load layer and a frame layer. This mass load layer and frame layer structure can be formed above the lower electrode, or it can be further formed on the upper electrode. The location where the upper electrode, piezoelectric layer, lower electrode, and acoustic wave reflecting region project onto the surface of the first substrate 100 is defined as the active region of the resonator assembly.

[0028] A first bonding layer 300 is further formed on the first surface of the first substrate 100 outside the active region. The location of the first bonding layer 300 is defined as the bonding region of the first substrate 100. The first bonding layer 300 can be a bonding metal with a low melting temperature, such as solder with a liquidus line between 300°C and 450°C. Typical examples include gold, aluminum, or copper.

[0029] The filter also includes a second substrate 400, which can be a substrate material adapted for semiconductor device fabrication, such as low-resistivity silicon, SOI, gallium arsenide, or gallium nitride. It is understood that the second substrate 400 can also be a substrate material adapted for use as a cover plate, such as high-resistivity silicon or glass. A first oxide layer 500 can be formed on the first surface of the second substrate 400 opposite to the first substrate 100 through a thin film deposition process such as epitaxial growth, chemical vapor deposition, or an oxidation process.

[0030] A non-gold second bonding layer 600 is further formed on the first oxide layer 500. The material of the second bonding layer 600 can be selected from materials that can undergo eutectic bonding with the material of the first bonding layer 300. For example, when the material of the first bonding layer 300 is gold, the material of the second bonding layer 600 is silicon or tin; when the material of the first bonding layer 300 is aluminum, the material of the second bonding layer 600 is germanium; when the material of the first bonding layer 300 is copper, the material of the second bonding layer 600 is tin. In this disclosure, the material of the first bonding layer is preferably gold, and the material of the second bonding layer is silicon.

[0031] The second bonding layer 600 is formed by patterning the material of the second bonding layer 600. (See also...) Figure 3 , Figure 3 A specific example of the second bonding layer 600 is shown. For example... Figure 3As shown, the second bonding layer 600 can form a U-shaped bonding pattern. Specifically, the U-shaped bonding pattern includes a first closed loop 601, a second closed loop 602, a plurality of first pillars 603 between the first closed loop 601 and the second closed loop 602, and a plurality of second pillars 604 within the second closed silicon ring 602. The first closed loop 601 forms the outer periphery of the bonding pattern, and the first pillars 603 between the first closed loop 601 and the second closed loop 602 form a pillar array; the second pillars 604 within the area defined by the second closed loop 602 form a pillar array. The second closed loop 602 defines a eutectic blocking region of the bonding pattern. The materials of the second bonding layer 600 and the first bonding layer 300 can form a eutectic alloy 605 when heated to the eutectic temperature to achieve eutectic bonding. By adjusting the bonding pressure and the material thicknesses of the first and second bonding layers, the thickness of the eutectic alloy 605 formed can be easily controlled. It is understood that a second oxide layer 700 may be selectively applied to the surface of the bonding pattern and its sidewalls to facilitate control over the formation position of the eutectic alloy pillars, thereby forming a first region capable of eutectic bonding and a second region capable of eutectic blocking on the second bonding layer 600.

[0032] In this disclosure, the eutectic bonding of the first bonding layer and the non-gold second bonding layer replaces the gold-to-gold bonding in the prior art, which makes it less likely for voids to appear at the interface of the bonding layer, reduces the flatness requirement of the bonding surface, and lowers the packaging cost.

[0033] Furthermore, this disclosure employs meticulous design of the bonding pattern. Taking the first bonding layer 300 as an example (material is gold) and the second bonding layer 600 as silicon), the design of the silicon pillars, in particular, ensures a thorough eutectic bonding reaction and strengthens the bonding strength. The dense arrangement of the silicon pillars effectively disperses the gold material, allowing it to embed within the second substrate, increasing the shear force of the packaging structure, forming a multi-point pad-like structure, and guaranteeing the stability of the electrical connection.

[0034] The design of the second closed ring 602 makes the area defined by the second closed ring 602 in the bonding pattern become the eutectic blocking region of the first bonding layer 300 and the second bonding layer 600. This can prevent the eutectic alloy generated by the reaction of gold and silicon around the second closed ring 602 from spreading into the eutectic blocking region, thereby avoiding affecting the electrical connection effect of the through-hole (TSV) in the subsequent electronic device.

[0035] See Figure 4 , Figure 4 Another specific example of the second bonding layer 600 is shown. For example... Figure 4As shown, in a variation of this disclosure, the region defined by the second closed silicon ring may further have a second oxide layer 700. The provision of the second oxide layer 700 can further ensure that the eutectic reaction of the first bonding layer 300 and the second bonding layer 600 is avoided in the region defined by the second closed ring 602, thereby avoiding affecting the electrical connection effect of the subsequent through-hole.

[0036] Continue reading Figure 2 In the second substrate 400, a via 401 is further formed in the portion corresponding to the eutectic blocking region defined by the second closed ring 602. The projected area of ​​the via 401 on the surface of the second substrate 400 is less than or equal to the projected area of ​​the second region on the second substrate 400. A metal liner 402 or a conductive pillar (not shown) may be disposed in the via 401. A redistribution layer 403 is also disposed on the surface of the second substrate 400 opposite to the second bonding layer 600, and the redistribution layer 403 is electrically connected to the via 401. Furthermore, a semiconductor element (not shown) and a second air cavity 410 may also be disposed on the second substrate 400 to provide working space for the filter on the first substrate 100 after the first substrate 100 and the second substrate 400 are eutectic bonded.

[0037] Furthermore, a passivation layer 800 is further provided on the surface of the second substrate 400 where the redistribution layer 403 is provided. The passivation layer 800 may be, for example, a dry film, polyimide, etc. Electrical connection structures such as bumps 801, spacers 802, and solder balls 803 may be further provided in the passivation layer 800.

[0038] In the filter structure provided in this disclosure, the heights of the first pillar 603 and the second pillar 604 can be as follows: Figure 2-3 The depth shown is less than that of the second air cavity 410.

[0039] See Figure 5 , Figure 5 Another modified embodiment of the filter structure provided in this disclosure is shown. In one modified embodiment, combined with Figure 3-5 As shown, the height of the first column 603 and the second column 604 can be equal to the depth of the second air cavity 410.

[0040] See Figure 6 , Figure 6 This illustrates another modified embodiment of the filter structure provided in this disclosure. It is similar to... Figure 2The difference in the filter structure shown is that the through-hole 101 is formed in the first substrate 100 and located in the portion corresponding to the eutectic blocking region defined by the second closed loop 602. The projected area of ​​the through-hole 101 on the surface of the first substrate 100 is less than or equal to the projected area of ​​the second region on the second substrate 400. A metal liner 102 may be disposed in the through-hole 101 or a conductive pillar (not shown) may be formed in the through-hole 101. A redistribution layer 103 is also disposed on the surface of the first substrate 100 opposite to the first bonding layer 300, and the redistribution layer 103 is electrically connected to the through-hole 101.

[0041] Furthermore, a passivation layer 800 is further provided on the surface of the first substrate 100 where the redistribution layer 103 is provided. The passivation layer 800 may be, for example, a dry film, polyimide, etc. Electrical connection structures such as bumps 801, spacers 802, and solder balls 803 may be further provided in the passivation layer 800.

[0042] It should be noted that, in this modified embodiment, since the through hole 101 is formed in the first substrate 100, and the bottom of the through hole 101 is opposite to the surface of the first bonding layer 300 forming the eutectic alloy, when the thickness of the first bonding layer 300 does not affect the electrical connection effect of the through hole 101, it is not necessary to provide the first oxide layer 500 and the second oxide layer 700 on the second substrate 400.

[0043] Please see Figure 7-16 , Figure 7-16 A schematic diagram of the fabrication process based on the filter structure provided in this disclosure is shown.

[0044] Step 1: Provide a first substrate.

[0045] See Figure 7 A first substrate 100 is provided, and the material of the first substrate 100 may be, for example, high-resistivity silicon, gallium arsenide, indium phosphide, glass, sapphire, or aluminum oxide. 、 Materials such as SiC, which are suitable for resonator fabrication and compatible with semiconductor processes, are formed. The first substrate 100 mainly serves as a support carrier for the filter device, ensuring that the filter is robust and reliable during processing and packaging.

[0046] Step 2: Creating the sound wave reflection area.

[0047] See Figure 7 An acoustic wave reflecting region 110, consisting of a structure such as an air cavity or a Bragg reflector layer, is formed in the first substrate 100.

[0048] In one embodiment, the fabrication of the acoustic wave reflection region 110 formed by the air cavity includes: forming a cavity in the first substrate 100 by photolithography etching process, and then filling the cavity with a sacrificial layer (not shown in the figure), which is used to support the deposition of subsequent device films on the first substrate 100.

[0049] Alternatively, a support layer can be formed in the first substrate 100, and a groove can be formed by etching the support layer, with the sacrificial layer filled in the groove. The sacrificial layer can be selected from thin film materials such as phosphosilicate glass, silicon dioxide, and amorphous silicon, which are compatible with the deposition temperature of subsequent thin films, do not contaminate the process system, and have good etching selectivity and chemical polishing properties.

[0050] In an alternative embodiment, the fabrication of the acoustic wave reflecting region 110 composed of the Bragg reflector layer includes: forming a multilayer of thin films with different acoustic impedances stacked along the thickness direction of the first substrate 100 on the first substrate 100 using thin film deposition and chemical mechanical polishing processes. The materials of the different acoustic impedance films can be, for example, SiO2 and tungsten (W).

[0051] Step 3: Creating the structural functional layers.

[0052] See Figure 8 A lower electrode material completely covering the acoustic wave reflection region 110 is deposited on a first substrate 100, and the lower electrode material is etched to form a lower electrode 201. A piezoelectric layer 202 is formed on the lower electrode, and an upper electrode material is formed on the piezoelectric layer, and the upper electrode material is etched to form an upper electrode. The position where the projections of the upper electrode 203, the piezoelectric layer 2020, the lower electrode 201, and the acoustic wave reflection region 110 overlap on the upper surface of the first substrate 100 is defined as the active region. The lower electrode 201, the piezoelectric layer 202, and the upper electrode 203 constitute the structural functional layer of the resonator.

[0053] Alternatively, a support layer (not shown) can be formed on the first substrate 100, a groove can be formed by etching the support layer, a lower electrode material can be conformally deposited on the support layer, and a lower electrode 201 can be formed in the groove by chemical mechanical polishing.

[0054] Understandably, a mass load layer, a framework layer, or other structures can be further formed on the lower electrode 201. Then, a piezoelectric layer 202 and an upper electrode 203 can be formed on it.

[0055] Understandably, after forming the upper electrode 203, structures such as a mass loading layer, a frame layer, and a protective layer can be further formed. In this case, the lower electrode 201, piezoelectric layer 202, upper electrode 203, and the mass loading layer, frame layer, and protective layer constitute the structural functional layer. When the acoustic wave reflecting region 110 formed in the first substrate 100 is composed of an air cavity, the sacrificial layer material needs to be removed after forming the structural functional layer to release the cavity. Since the structural functional layer is closely related to the specific device, and other related components of the filter are not shown in the accompanying drawings, for simplicity, the filter 200 will be used for illustration in the other drawings.

[0056] Step 4: Creation of the first bonding layer 300.

[0057] See Figure 9 A photoresist layer is deposited on a first substrate, and the photoresist layer is patterned. Then, a first bonding layer 300 is formed on the bonding region outside the active region on the upper surface of the first substrate. Exemplarily, the patterned photoresist can be formed at the bonding region of the first substrate 100 using methods such as electron beam evaporation or magnetron sputtering, a bonding material with good ohmic contact can be deposited, and then the first bonding layer 300 can be formed at the bonding region of the first substrate 100 through a lift-off process. An electrical connection (not shown in the figure) may exist between the first bonding layer 300 and the filter 200.

[0058] Step 5: Second substrate

[0059] See Figure 10 A second substrate 400 is provided, the material of which is as described above and will not be repeated here.

[0060] Step 6: Fabrication of the second bonding layer

[0061] Continue reading Figure 10 The first oxide layer 500 can be formed on the second substrate 400 by thin film deposition processes such as epitaxial process, chemical vapor deposition process or oxidation process.

[0062] See Figure 10-11 A second bonding layer material is further deposited on the first oxide layer 500 by thin film deposition, and then the second bonding layer 600 as described above is formed by patterning processes such as etching.

[0063] Then, a second oxide layer material is conformally formed on the second bonding layer 600 using a thin film deposition process. This second oxide layer material is patterned, and according to the design of the eutectic blocking region, a portion of the second oxide layer material on the upper surface of the second bonding layer 600 is removed to form a patterned second oxide layer 700. The patterned second oxide layer 700 can be exemplarily as follows: Figure 12AAs shown, a pillar is formed at the location corresponding to the subsequent conductive via, and a second oxide layer 700 is formed on both the upper and side surfaces of the pillar. Alternatively, the patterned second oxide layer 700 can be exemplarily as shown in... Figure 12B As shown, no pillar was formed at the location corresponding to the subsequent conductive via.

[0064] Step 7: Construction of the second air cavity

[0065] See Figure 13 A second air cavity 410 is further formed by etching on the second substrate 400.

[0066] It is understood that although steps 6 and 7 form the second bonding layer 600 and the second air cavity 410 respectively through step-by-step etching, in a modified embodiment of this disclosure, the second bonding layer 600 and the second air cavity 410 can also be formed simultaneously in a single etching step. In this case, the height of the first pillar 603 and the second pillar 604 in the second bonding layer 600 is greater than the height of the first pillar 603 and the second pillar 604 during step-by-step etching. Specifically, the height can be set to be equal to the set height of the second air cavity 410. Then, as described above, a second oxide layer material is deposited on the second bonding layer 600, and selective etching is performed to form the second oxide layer 700 at locations requiring eutectic blocking.

[0067] Step 8: Forming a eutectic bonding layer

[0068] See Figure 14 The first substrate 100 and the second substrate 400 are chemically cleaned to remove the native oxide layer. Then, the first bonding pattern of the first substrate 100 and the second bonding pattern of the second substrate 400 are placed opposite each other and bonded. The applied bonding temperature is set to the eutectic bonding reaction temperature of the first bonding layer 300 and the second bonding layer 600, causing a eutectic alloy 405 to continuously form at the contact area between the first and second bonding materials. The thickness of this alloy 405 can be adjusted by adjusting the bonding pressure and the thickness of the first and second bonding materials. The first substrate 100 and the second substrate 400 are then cooled, forming a bond between them as shown in the image. Figure 14 The eutectic bonding layer, shown by the dashed line, securely encapsulates and connects the first substrate 100 and the second substrate 400. Those skilled in the art will understand that any material capable of eutectic bonding is included within the scope of this disclosure.

[0069] Step 9: Grind the second substrate

[0070] Starting with the unbonded surface of the second substrate 400, a portion of the second substrate 400 is removed by setting the grinding amount through mechanical grinding.

[0071] Step 10: Form an electrical connection structure in the second substrate

[0072] refer to Figure 15 The second substrate 400 is patterned using photolithography and etching processes to form a through-hole 401 in the second substrate 400 to expose the central region of the eutectic bonding layer. A conductive liner 402 or a conductive pillar (not shown in the figure) can be formed in the through-hole 401 by a thin film deposition process. Then, a redistribution layer 403 electrically connected to the conductive liner 402 or the conductive pillar (not shown in the figure) is formed on the surface of the second substrate away from the second bonding pattern.

[0073] refer to Figure 16 A passivation layer 800 is formed on the redistribution layer 403. The material of the passivation layer 800 can be selected from a dry film layer, a polyimide layer, or a combination of the two.

[0074] Furthermore, through-holes are formed in the passivation layer 800. Bumps 801 and solder balls 803, electrically connected to the redistribution layer, are formed in and above the openings. A spacer layer 802 can be formed between the bumps 801 and solder balls 803. The bumps 801 are preferably made of a metal with excellent electrical conductivity, such as copper, for better electrical signal transmission. The bumps 801 can also be made of a metal with a low melting point, such as tin, lead (Pb), or aluminum, for easy melting and forming. The spacer layer 802 is selected from metals that provide spacing and protection, such as nickel, depending on the conductive pillar material and the bump material. The bumps 801, spacer layer 802, and solder balls 803 constitute the electrical connection structure for leading out the input and output signals of the filter.

[0075] In another embodiment of this disclosure, the electrical connection structure may not be formed in the second substrate 400, but may be formed in the first substrate 100.

[0076] Similarly, a patterning process is used to pattern the first substrate 100 using photolithography and etching to form through-holes, exposing the central region of the eutectic bonding layer. A conductive substrate or conductive pillar can be formed in the through-hole using thin film deposition. Then, a redistribution layer electrically connected to the conductive substrate or conductive pillar is formed on the surface of the first substrate opposite to the first bonding pattern. A passivation layer is then formed on the redistribution layer; the material of the passivation layer can be selected from a dry film layer, a polyimide layer, or a combination of both.

[0077] Furthermore, through-holes are formed in the passivation layer, and bumps and solder balls electrically connected to the redistribution layer are formed in and above the openings, with spacer layers formed between the solder balls and bumps.

[0078] It should be noted that when the electrical connection structure is formed in the first substrate, a second oxide layer is not required after the second bonding pattern is fabricated.

[0079] This disclosure, through the design of the structure and manufacturing process of an electronic device, taking a filter as an example, can achieve the goals of reducing manufacturing costs, strengthening bonding strength, increasing the shear force of the packaging structure, ensuring the reliability of electrical connections, and improving product yield.

[0080] The present disclosure has been described above with reference to specific implementation schemes. However, those skilled in the art should understand that these descriptions are exemplary and not intended to limit the scope of protection of the present disclosure. Those skilled in the art can make various modifications and variations to the present disclosure based on its spirit and principles, and such modifications and variations are also within the scope of the present disclosure.

Claims

1. A packaging method for an electronic device, characterized in that, include: A first substrate is provided, and a first bonding layer is formed on the first substrate; A second substrate is provided, and a second bonding layer is formed on the second substrate, the second bonding layer being composed of a material capable of eutectic bonding with the material of the first bonding layer; The second bonding layer forms a first region capable of eutectic bonding and a second region that blocks eutectic bonding, wherein the second region is used to prevent the eutectic alloy from spreading to the second region; The first bonding layer and the second bonding layer are eutectic bonded to encapsulate the first substrate and the second substrate together; A through-hole is further formed on the second substrate or the first substrate, wherein the projected area of ​​the through-hole on the surface of the second substrate or the first substrate is less than or equal to the projected area of ​​the second region on the second substrate.

2. The packaging method as described in claim 1, characterized in that: The first bonding layer is made of a material with a liquidus temperature between 300-450°C.

3. The packaging method as described in claim 1, characterized in that: The first bonding layer is selected from gold, aluminum, or copper; the second bonding layer is selected from silicon, germanium, or tin.

4. The packaging method as described in claim 1, characterized in that: The second bonding layer is graphically processed to form the first region and the second region.

5. The packaging method as described in claim 4, characterized in that: The patterned second bonding layer is formed into a U-shaped bonding pattern, which includes a first closed loop, a second closed loop, a plurality of first pillars arrayed between the first and second closed loops, and a plurality of second pillars arrayed within the second closed silicon ring. Alternatively, the second bonding layer is formed as a U-shaped bonding pattern, the bonding pattern including a first closed loop, a second closed loop, a plurality of first pillars arrayed between the first and second closed loops, and a plurality of second pillars not present within the second closed silicon ring.

6. The packaging method as described in claim 5, characterized in that: The second region is formed within the area defined by the second closed loop, and the region between the first closed loop and the second closed loop is the first region.

7. The packaging method as described in claim 6, characterized in that: A first air cavity is further formed in the first substrate, and a second air cavity is further formed in the second substrate, the first air cavity and the second air cavity defining the working space of the electronic device.

8. The packaging method as described in claim 7, characterized in that: The quasi-return-shaped bonding pattern is formed simultaneously with the second air cavity, or the quasi-return-shaped bonding pattern is formed before the second air cavity.

9. The packaging method as described in claim 7, characterized in that: When the through hole is disposed on the second substrate and the second region has a second pillar, a first oxide layer is formed on the first surface of the second substrate, a second oxide layer is formed on the sidewall of the first pillar of the second bonding layer, and a second oxide layer is formed on the sidewall and top surface of the second pillar of the second bonding layer. Alternatively, when the through hole is disposed on the second substrate and there is no second pillar in the second region, a first oxide layer is formed on the first surface of the second substrate, a second oxide layer is formed on the sidewall of the first pillar of the second bonding layer, and a second oxide layer is formed on the sidewall of the second region of the second bonding layer.

10. The packaging method as described in claim 1, characterized in that: When the through-hole is disposed on the first substrate, the second bonding layer having the first and second regions is replaced by the second bonding layer having only the first region.

11. An electronic device, characterized in that: include: A first substrate, and a first bonding layer formed on a first surface of the first substrate. A second substrate, and a second bonding layer formed on a first surface of the second substrate, wherein the second bonding layer is composed of a material capable of eutectic bonding with the material of the first bonding layer; The second bonding layer includes a first region capable of eutectic bonding and a second region capable of eutectic blocking, wherein the second region is used to prevent the eutectic alloy from spreading to the second region; A eutectic bonding layer is formed between a first surface of a first substrate and a first surface of a second substrate through eutectic bonding of a first bonding layer and a second bonding layer; A through-hole is further formed on the second substrate or the first substrate, wherein the projected area of ​​the through-hole on the surface of the second substrate or the first substrate is less than or equal to the projected area of ​​the second region on the surface of the second substrate.

12. The electronic device as claimed in claim 11, characterized in that: The first bonding layer is made of a material with a liquidus temperature between 300-450°C.

13. The electronic device as claimed in claim 11, characterized in that: The material of the first bonding layer is selected from gold, aluminum or copper; the material of the second bonding layer is selected from silicon, germanium or tin.

14. The electronic device as claimed in claim 11, characterized in that: The second bonding layer is formed as a U-shaped bonding pattern, the bonding pattern including a first closed loop, a second closed loop, a plurality of first pillars arrayed between the first closed loop and the second closed loop, and a plurality of second pillars arrayed within the second closed silicon ring; Alternatively, the second bonding layer is formed as a U-shaped bonding pattern, the bonding pattern including a first closed loop, a second closed loop, a plurality of first pillars forming an array between the first closed loop and the second closed loop, and a plurality of second pillars not forming an array within the second closed silicon ring.

15. The electronic device as claimed in claim 14, characterized in that: The second region is formed within the area defined by the second closed loop, and the region between the first closed loop and the second closed loop is the first region.

16. The electronic device as claimed in claim 14, characterized in that: A first air cavity is further formed in the first substrate, and a second air cavity is further formed in the second substrate, the first air cavity and the second air cavity defining the working space of the electronic device.

17. The electronic device as claimed in claim 16, characterized in that: The height of the column is less than or equal to the depth of the second air cavity.

18. The electronic device as claimed in claim 11, characterized in that: When the through hole is disposed on the second substrate and the second region has a second pillar, a first oxide layer is formed on the first surface of the second substrate, a second oxide layer is formed on the sidewall of the first pillar of the second bonding layer, and a second oxide layer is formed on the sidewall and top surface of the second pillar of the second bonding layer. Alternatively, when the through hole is disposed on the second substrate and there is no second pillar in the second region, a first oxide layer is formed on the first surface of the second substrate, a second oxide layer is formed on the sidewall of the first pillar of the second bonding layer, and a second oxide layer is formed on the sidewall of the second region of the second bonding layer.

19. The electronic device as claimed in claim 11, characterized in that: When the through-hole is disposed on the first substrate, the second bonding layer having the first and second regions is replaced by the second bonding layer having only the first region.

20. The electronic device as claimed in any one of claims 11-19, characterized in that: The electronic device is a filter.

21. The electronic device as claimed in claim 20, characterized in that: The filter includes a thin-film bulk acoustic resonator formed on the first substrate.

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