Method of manufacturing a semiconductor device having a bi-damascene structure

Abstract

The application provides a preparation method of a semiconductor device with a double damascene structure, comprising the following steps: providing a substrate, sequentially forming a bottom wiring layer, a hard mask layer, a first dielectric layer, an etching stop layer, a second dielectric layer and a photoresist layer; performing first exposure to define a via topography; performing second exposure to define a trench topography; developing to form a double damascene structure pattern in the exposed area; sequentially etching the obtained structure by using etching agents with a first etching selectivity and a second etching selectivity for the first dielectric layer and the etching stop layer, so as to sequentially transfer the double damascene structure pattern, wherein the first etching selectivity is less than the second etching selectivity; removing the residual photoresist layer; and performing metal filling to obtain the double damascene structure which is electrically connected with the bottom wiring layer. The application can effectively simplify the preparation process and reduce the preparation cost, can effectively avoid the etching product residue, and is helpful to improve the process yield.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for fabricating a semiconductor device with a double damask structure. Background Technology

[0002] TM (top metal) is the top layer of the multilayer metal interconnect structure of a chip. In existing technologies, a double damask structure including TV (Through Vias) and TM is usually formed by two exposures and etchings. Since the CD (Critical Dimension) of TM is larger and thicker than that of inter metal, the etching requirements are lower than those of inter metal.

[0003] Specifically, dual damascene structures with TVs and TMs are typically formed using a Via first Trench last process. In this process, the first exposure etching forms the via, followed by a second exposure etching above the via to form the trench. Due to the two exposures and two etching processes, the wafer needs to be transferred back and forth between the exposure and etching equipment, making the process complex and costly. Furthermore, during the TM pattern etching process, the via filling is difficult to control, and during the subsequent trench lithography process, the photoresist and anti-reflective layer fill the holes, potentially leaving organic residues inside the vias after trench etching, leading to issues such as… Figure 1 The micro trenches marked in the circle and such Figure 2 The circled area indicates a fence or other defect. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for fabricating a semiconductor device with a double damascene structure, which solves the problem that in the prior art, when forming a double damascene structure with TV and TM using the Via first Trench last process, two exposures and two etchings are required. The wafer needs to be transferred back and forth between the exposure station and the etching station, which is complicated and costly. In addition, the filling of vias is difficult to control during the etching of TM patterns, and etching products are easy to remain, resulting in defects such as microtrench and fence.

[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating a semiconductor device with a double damask structure, the method comprising the steps of:

[0006] A substrate is provided, on which a bottom wiring layer, a hard mask layer, a first dielectric layer, an etch barrier layer, a second dielectric layer and a photoresist layer are sequentially formed, wherein the first dielectric layer and the second dielectric layer are made of the same material;

[0007] The photoresist layer is subjected to a first exposure to define the via morphology in the photoresist layer;

[0008] The photoresist layer is exposed a second time to the area corresponding to the via, so as to define a trench morphology on the upper part of the via. The second exposure is a defocusing exposure.

[0009] The photoresist layer is developed to form a double damask structure pattern in the exposure area. The double damask structure pattern penetrates the photoresist layer and includes a via at the bottom and a trench at the top. The trench and the via are interconnected, and the opening size of the trench is larger than the opening size of the via.

[0010] The obtained structure is etched by etchants with first etch selectivity and second etch selectivity to the first dielectric layer and the etch barrier layer, so as to transfer the double damask structure pattern in the photoresist layer to the second dielectric layer, the etch barrier layer, the first dielectric layer and the hard mask layer until the bottom wiring layer is exposed. The first etch selectivity is less than the second etch selectivity.

[0011] Remove residual photoresist layer;

[0012] A double damask structure is obtained by metal filling in the double damask structure pattern transferred to the first dielectric layer, the etch barrier layer, the second dielectric layer and the hard mask layer, and the double damask structure is electrically connected to the bottom wiring layer.

[0013] Optionally, the first dielectric layer and the second dielectric layer are silicon oxide layers, and the etch barrier layer is a silicon nitride layer.

[0014] Optionally, the first etching selectivity ratio is 1:1, and the second etching selectivity ratio is 20:1.

[0015] Optionally, the etchants used in succession are all etching gases. The etchant with the first etching selectivity includes CF4 gas, and the etchant with the second etching selectivity includes C4F8 gas.

[0016] Optionally, the first exposure uses normal focusing exposure to form a through hole. During the second exposure, the optimal focal point is first found through focusing exposure, and then the exposure focal point is set above the optimal focal point so that the pattern formed in the second exposure presents an elliptical cross-section groove that is wider at the top and narrower at the bottom. After exposure, a double damask structure pattern is formed in the photoresist layer through a first development.

[0017] Optionally, the hard mask layer may be made of a doped silicon carbide thin film layer.

[0018] Optionally, the thickness of the photoresist layer is 1200nm ± 100nm.

[0019] Optionally, an anti-reflective coating is also formed between the photoresist layer and the second dielectric layer, and the anti-reflective coating is simultaneously etched during the etching process.

[0020] Optionally, the filler metal may include copper.

[0021] Alternatively, an electroplating process can be used for metal filling.

[0022] As described above, the method for fabricating a semiconductor device with a double damascene structure according to the present invention has the following beneficial effects: The method for fabricating a semiconductor device with a double damascene structure provided by the present invention first performs two consecutive exposures to define the pattern of the double damascene structure in the photoresist layer, and then transfers the pattern to the dielectric layer through a continuous etching process. After metal filling is completed, the double damascene structure is obtained. Compared with the existing Via first Trench last process of exposure-etching-exposure-etching, it can reduce the number of times the substrate (e.g., wafer) is transferred in different devices, which can effectively simplify the fabrication process and reduce the fabrication cost. Moreover, the continuous etching fully opens the vias and trenches, which facilitates subsequent metal filling and can effectively avoid etching product residue, avoid defects such as microtrenches and fences, and help improve the process yield. Attached Figure Description

[0023] Figure 1 This diagram illustrates the micropore defects that occur during the fabrication of double damask structures in the prior art.

[0024] Figure 2 This diagram illustrates a fence defect that occurs during the fabrication of a double damask structure in the prior art.

[0025] Figure 3 The flowchart shown is a method for fabricating a semiconductor device with a double damascene structure provided by the present invention.

[0026] Figure 4 Displayed as Figure 3 Schematic diagram of the cross-sectional structure obtained in step S11

[0027] Figure 5 Displayed as Figure 3 A schematic diagram of step S12, which involves the first exposure.

[0028] Figure 6 Displayed as Figure 3 A schematic diagram of step S13, which involves a second exposure.

[0029] Figure 7 Displayed as Figure 3 The schematic diagram of the cross-sectional structure obtained after development in step S14.

[0030] Figure 8 Displayed as Figure 3 A schematic diagram of the cross-sectional structure obtained after etching in step S15.

[0031] Figure 9 Displayed as Figure 3 A schematic diagram of the cross-sectional structure obtained after removing the residual photoresist layer in step S16.

[0032] Figure 10 Displayed as Figure 3 The schematic diagram of the cross-sectional structure obtained after metal filling in step S17.

[0033] Component designation explanation

[0034] 11 Bottom wiring layer

[0035] 12 Hard mask layers

[0036] 13 First dielectric layer

[0037] 14 Etching barrier layer

[0038] 15 Second dielectric layer

[0039] 16 photoresist layers

[0040] 17 Anti-reflective coating

[0041] 18. Double Damask knot leather construction pattern

[0042] 181 Through Hole

[0043] 182 trench

[0044] 19. Double Damascus Structure Detailed Implementation

[0045] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. For ease of explanation, when detailing the embodiments of the present invention, the cross-sectional views showing the device structure are partially enlarged, not according to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0046] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0047] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0048] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components related to the present invention and are not drawn according to the actual number, shape, and size of the components in the actual implementation. In the actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex. To keep the illustrations as concise as possible, not all structures are shown in the figures.

[0049] like Figure 3 As shown, the present invention provides a method for fabricating a semiconductor device with a double damask structure, the method comprising the following steps:

[0050] S11: Provide a substrate, on which a bottom wiring layer 11, a hard mask layer 12, a first dielectric layer 13, an etch stop layer 14, a second dielectric layer 15, and a photoresist layer 16 are sequentially formed. The first dielectric layer 13 and the second dielectric layer 15 are made of the same material (therefore, the etch selectivity ratio of the first dielectric layer and the etch stop layer is equal to the etch selectivity ratio of the second dielectric layer and the etch stop layer). Specifically, the substrate includes, but is not limited to, a silicon wafer. Other device structures, such as capacitors, may also be formed in the substrate. The hard mask layer 12, the first dielectric layer 13, the etch stop layer 14, and the second dielectric layer 15 can be sequentially formed on the bottom wiring layer 11 using a chemical vapor deposition process. The photoresist layer 16 is formed using, but is not limited to, spin coating. The resulting structure is as follows: Figure 4 As shown; the thickness of the first dielectric layer 13 and the second dielectric layer 15 can be the same or different. In this embodiment, the thickness of the second dielectric layer 15 is greater than the thickness of the first dielectric layer 13. For example, the first dielectric layer 13 is 2000nm-6000nm and the second dielectric layer 15 is 5000nm-8000nm.

[0051] S12: Perform a first exposure on the photoresist layer 16 to define the morphology of the via 181 within the photoresist layer 16; specifically, this exposure uses focused exposure, ensuring sufficient exposure energy to penetrate to the bottom of the photoresist layer 16, thereby more accurately defining the morphology of the via 181; a schematic diagram of this step is shown below. Figure 5 As shown;

[0052] S13: The photoresist layer 16 is subjected to a second exposure in the area corresponding to the via 181 to define the trench 182 morphology above the via 181. The second exposure is a defocus exposure. More specifically, the first exposure uses normal focusing exposure to form the via. In the second exposure, the optimal focus is first found through focusing exposure, and then the exposure focus is set to a position above the optimal focus. The offset value of this position from the optimal focus is preferably about 1 / 3 to 2 / 3 of the photoresist thickness. With this setting, the pattern formed in the second exposure is an elliptical cross-section trench that is wider at the top and narrower at the bottom. After exposure, a double damask structure pattern is formed in the photoresist layer after one development. Defocus exposure can make the exposure energy insufficient (insufficient to produce an image) in the position that is seriously off-focus, so that the exposure depth is limited and imaging is only performed in the upper area of ​​the photoresist layer 16 (the area corresponding to the area where the trench 182 needs to be formed). A schematic diagram of this step is shown in Figure 6.

[0053] S14: The photoresist layer 16 is developed (no development is performed after the first exposure, and development is performed once after the second exposure) to form a double damask structure pattern 18 in the exposed area. The double damask structure pattern 18 penetrates the photoresist layer 16 and includes a via 181 at the bottom and a trench 182 at the top. The trench 182 and the via 181 are interconnected, and the opening size of the trench 182 is larger than the opening size of the via 181 (or the upper opening size of the trench 182 is larger than the lower opening size). This structure facilitates subsequent metal filling. The structure obtained after this step is as follows: Figure 7 As shown;

[0054] S15: The obtained structure is etched sequentially using etchants with first and second etch selectivity ratios for the first dielectric layer 13 and the etch stop layer 14, to transfer the double damask structure pattern 18 in the photoresist layer 16 to the second dielectric layer 15, the etch stop layer 14, the first dielectric layer 13, and the hard mask layer 12 until the bottom wiring layer 11 is exposed. The first etch selectivity ratio is less than the second etch selectivity ratio. Specifically, an etch parameter (recipe) with a low etch selectivity ratio is first used... The double damascene pattern in the photoresist layer 16 is transferred. Simultaneously, a portion of the etch barrier layer 14 of the first dielectric layer 13 and the second dielectric layer 15 is opened to serve as a hard mask for the subsequent etching of the via 181. Then, etching continues using high etch selectivity parameters. The area where the etch barrier layer 14 has been opened will continue to be etched downwards to form the via 181. The remaining portion will remain on the etch barrier layer 14, forming a trench with an approximately vertical morphology, thus obtaining the prototype of the double damascene pattern 18. The structure obtained after this step is as follows: Figure 8 As shown;

[0055] S16: Remove residual photoresist layer 16; specifically, the residual photoresist layer 16 can be removed first using an asher process (ashing), followed by cleaning with a cleaning solution such as a stripping solution. During this process, the double damask structure pattern 18 will be further modified, resulting in a structural reference. Figure 9 As shown; it can be seen that in the double damask structure pattern 18, the via 181 penetrates the first dielectric layer 13 and the hard mask layer 12 to expose the bottom wiring layer 11, and the trench 182 is connected to the via 181 and passes upward through the etch barrier layer 14 and the second dielectric layer 15.

[0056] S17: Metal filling is performed on the double damascene pattern 18 transferred to the first dielectric layer 13, the etch barrier layer 14, the second dielectric layer 15, and the hard mask layer 12 to obtain a double damascene structure 19. The filling metal is preferably copper, which has advantages such as low conductivity. The double damascene structure is electrically connected to the bottom wiring layer 11. That is, the metal filled in the vias 181 and trenches 182 constitutes the double damascene structure 19, resulting in the structure shown below. Figure 10 As shown.

[0057] The present invention provides a method for fabricating a semiconductor device with a double damascene structure. First, two consecutive exposures are performed to define the double damascene structure pattern in a photoresist layer. Then, a continuous etching process transfers the pattern to a dielectric layer. After metal filling, the double damascene structure is obtained. Compared to the existing Via first Trench last process (exposure-etching-exposure-etching), this method reduces the number of substrate (e.g., wafer) transfers between different devices, effectively simplifying the fabrication process and reducing costs. Furthermore, the continuous etching fully opens vias and trenches, facilitating subsequent metal filling and effectively preventing etching product residue, thus avoiding defects such as microtrenching and fencing, and contributing to improved process yield.

[0058] In a preferred example, the first dielectric layer 13 and the second dielectric layer 15 are silicon oxide layers, and the etching barrier layer 14 is a silicon nitride layer. The preparation and etching processes of these two materials are relatively mature, and the etching parameters can be flexibly formulated as needed.

[0059] The first etching ratio and the second etching ratio can be determined based on the material and thickness of the first dielectric layer 13 and the second dielectric layer 15, as well as the pattern to be formed. In a preferred example, the first etching selectivity is 1:1 or close to 1:1, and the second etching selectivity is close to 20:1. A suitable etchant can be used to achieve this etching selectivity. Preferably, the etchant used in the two etching processes is either an etching liquid or an etching gas, so that the two etching processes can be performed continuously in the same etching equipment, which simplifies the etching process. In this embodiment, when the first dielectric layer 13 and the second dielectric layer 15 are made of silicon oxide and the etching barrier layer 14 is made of silicon nitride, the etchant with the first etching selectivity can be a mixed etching gas with CF4 gas as the main component and other gases such as oxygen and argon added, and the etchant with the second etching selectivity is a mixed etching gas with C4F8 gas as the main component and other gases such as oxygen and argon added.

[0060] During the second exposure, parameters such as exposure energy and exposure angle can be adjusted to make it difficult for the exposure energy to penetrate to the bottom of the photoresist layer 16. Preferably, the exposure angle during the second exposure is 45°-60°.

[0061] In a preferred example, the hard mask layer 12 is made of nitride-doped silicon carbide (NDC) thin film. The NDC layer not only provides good etching barrier function, but also forms good interfacial contact with the first dielectric layer 13 and the second dielectric layer 15, which helps to reduce interlayer stress.

[0062] In this embodiment, the thickness of the photoresist layer 16 has a very important influence on whether the double damask structure 19 can be formed. Through extensive experiments, the inventors found that the thickness of the photoresist layer 16 is preferably 1200nm ± 100nm.

[0063] In one example, an anti-reflective coating 17 is also formed between the photoresist layer 16 and the second dielectric layer 15. During the etching process, the anti-reflective coating 17 is simultaneously etched, and subsequently, during the removal of the remaining photoresist layer 16, the remaining anti-reflective coating 17 is also simultaneously removed. The main components of the anti-reflective coating 17 are crosslinkable resin, thermo-acid generator, surfactant, and solvent. The anti-reflective coating 17 reduces reflection and problems such as standing waves, thus helping to improve exposure accuracy. The thickness of the anti-reflective coating 17 can be determined as needed, preferably between 200 nm and 1000 nm.

[0064] In a preferred example, an electroplating process is used for metal filling, such as copper electroplating. Initially, a copper seed layer can be formed at the bottom of the via 181 using a chemical vapor deposition process, followed by an electroplating process to form the copper body layer. This helps to improve the filling quality and reduce device resistance.

[0065] In summary, this invention provides a method for fabricating a semiconductor device with a double damascene structure, comprising the steps of: providing a substrate; sequentially forming a bottom wiring layer, a hard mask layer, a first dielectric layer, an etch stop layer, a second dielectric layer, and a photoresist layer on the substrate, wherein the first dielectric layer and the second dielectric layer are made of the same material; performing a first exposure on the photoresist layer to define a via morphology in the photoresist layer; performing a second exposure on the region of the photoresist layer corresponding to the via to define a trench morphology above the via, wherein the second exposure is a defocusing exposure; and developing the photoresist layer to form a double damascene structure pattern in the exposed region, wherein the double damascene structure pattern penetrates the photoresist layer and includes a via located at the bottom and a via located at the top. The upper trench is interconnected with the via, and the opening size of the trench is larger than the opening size of the via. The obtained structure is etched sequentially using etchants with first and second etch selectivity ratios for the first dielectric layer and the etch stop layer, respectively, to transfer the double damascene structure pattern in the photoresist layer to the second dielectric layer, the etch stop layer, the first dielectric layer, and the hard mask layer until the bottom wiring layer is exposed. The first etch selectivity ratio is less than the second etch selectivity ratio. Residual photoresist is removed. Metal filling is performed on the double damascene structure pattern transferred to the first dielectric layer, the etch stop layer, the second dielectric layer, and the hard mask layer to obtain the double damascene structure, which is electrically connected to the bottom wiring layer. The method for fabricating a semiconductor device with a double damascene structure provided by this invention involves first performing two consecutive exposures to define the double damascene structure pattern in the photoresist layer, then transferring the pattern to the dielectric layer through a continuous etching process, and finally fabricating the double damascene structure after metal filling. Compared to the existing Via first Trench last process of exposure-etching-exposure-etching, this invention reduces the number of substrate (e.g., wafer) transfers between different devices, effectively simplifying the fabrication process and reducing costs. Furthermore, the continuous etching fully opens vias and trenches, facilitating subsequent metal filling and effectively preventing etching product residue, micro-trenches, and fences, thus improving process yield. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0066] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a semiconductor device with a double damask structure, characterized in that, The preparation method includes the following steps: A substrate is provided, on which a bottom wiring layer, a hard mask layer, a first dielectric layer, an etch barrier layer, a second dielectric layer, and a photoresist layer are sequentially formed. The first dielectric layer and the second dielectric layer are made of the same material. The first dielectric layer and the second dielectric layer are silicon oxide layers. The etch barrier layer is a silicon nitride layer. The thickness of the photoresist layer is 1200nm±100nm. The photoresist layer is subjected to a first exposure, which uses normal focused exposure to form vias, thereby defining the via morphology in the photoresist layer; The photoresist layer is subjected to a second exposure in the region corresponding to the via to define a trench morphology above the via. The second exposure is a defocused exposure. During the second exposure, the optimal focal point is first found through focused exposure, and then the exposure focal point is set to a position above the optimal focal point so that the pattern formed by the second exposure presents an elliptical cross-section trench that is wider at the top and narrower at the bottom. The offset of the position of the exposure focal point above the optimal focal point relative to the optimal focal point is 1 / 3 to 2 / 3 of the thickness of the photoresist layer. The photoresist layer is developed to form a double damask structure pattern in the exposure area. The double damask structure pattern penetrates the photoresist layer and includes a via at the bottom and a trench at the top. The trench and the via are interconnected, and the opening size of the trench is larger than the opening size of the via. The obtained structure is etched sequentially using etchants with a first etch selectivity ratio of 1:1 and a second etch selectivity ratio of 20:1 on the first dielectric layer and the etch barrier layer. Both etchants used are etching gases; the etchant with the first etch selectivity ratio includes CF4 gas, and the etchant with the second etch selectivity ratio includes C4F8 gas. The double damask structure pattern in the photoresist layer is sequentially transferred to the second dielectric layer, the etch barrier layer, the first dielectric layer, and the hard mask layer until the bottom wiring layer is exposed. The first etch selectivity ratio is less than the second etch selectivity ratio. Remove residual photoresist layer; A double damask structure is obtained by metal filling in the double damask structure pattern transferred to the first dielectric layer, the etch barrier layer, the second dielectric layer and the hard mask layer, and the double damask structure is electrically connected to the bottom wiring layer.

2. The preparation method according to claim 1, characterized in that, The material of the hard mask layer includes a doped silicon carbide thin film layer.

3. The preparation method according to claim 1, characterized in that, An anti-reflective coating is also formed between the photoresist layer and the second dielectric layer, and the anti-reflective coating is simultaneously etched during the etching process.

4. The preparation method according to claim 1, characterized in that, The filler metals include copper.

5. The preparation method according to claim 4, characterized in that, Metal filling is performed using an electroplating process.

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