Element substrate and method for manufacturing the same

Abstract

A component substrate and its manufacturing method are disclosed. The component substrate includes a circuit substrate and a side trace structure. The circuit substrate includes a substrate and a front circuit structure located on the front side of the substrate. The side trace structure is electrically connected to the front circuit structure and extends from the front circuit structure to the back side of the circuit substrate. The cross-sectional structure of the side trace structure includes a first portion located above the front side of the circuit substrate, a second portion located above the side of the circuit substrate, and a third portion located above the back side of the circuit substrate. The first portion, the second portion, and the third portion each include a plurality of strip-shaped traces. The ratio between the maximum thickness of the first portion and the maximum thickness of the second portion is A. The ratio between the maximum thickness of the third portion and the maximum thickness of the second portion is B. A and B are both between 0.25 and 0.6.

Description

Technical Field

[0001] This invention relates to a component substrate and its manufacturing method. Background Technology

[0002] To meet market demands, more and more manufacturers are focusing on developing narrow-bezel or even bezel-less display panels. Generally, to reduce the bezel area of ​​a display panel, chips or thin-film flip-chip packages are placed on the back or sides of the panel. For example, a flexible circuit board (PCB) is used to connect a pad located on the front of the display panel, and then the PCB is bent to the back of the panel. However, due to the thickness of the PCB itself and the difficulty in fully fitting it to the sides of the display panel, it is difficult to further reduce the bezel area. Summary of the Invention

[0003] This invention provides a component substrate and its manufacturing method, which can reduce the border size of the component substrate through side wiring structure and improve the production yield of side wiring structure by using oblique deposition process.

[0004] At least one embodiment of the present invention provides a method for manufacturing a component substrate, comprising the following steps: A circuit substrate is provided, the circuit substrate including a substrate and a front circuit structure located on the front side of the substrate. A side trace structure electrically connecting the front circuit structure is formed. The side trace structure extends from the front circuit structure to the back side of the circuit substrate, and the method for forming the side trace structure includes the following steps: A first oblique deposition process is performed on the front side and the side side of the circuit substrate using a first target, wherein a first angle is formed between the front side of the first target and the side side of the circuit substrate. A second oblique deposition process is performed on the back side and the side side of the circuit substrate using a second target, wherein a second angle is formed between the front side of the second target and the side side of the circuit substrate. The cross-sectional structure of the side trace structure includes a first portion located on the front side of the circuit substrate, a second portion located on the side side of the circuit substrate, and a third portion located on the back side of the circuit substrate. The first portion, the second portion, and the third portion each include a plurality of strip-shaped traces. The ratio between the maximum thickness of the first portion and the maximum thickness of the second portion is A. The ratio between the maximum thickness of the third portion and the maximum thickness of the second portion is B. A and B are each 0.25 to 0.6.

[0005] At least one embodiment of the present invention provides a component substrate. The component substrate includes a circuit substrate and a side trace structure. The circuit substrate includes a substrate and a front circuit structure located on the front side of the substrate. The side trace structure is electrically connected to the front circuit structure and extends from the front circuit structure to the back side of the circuit substrate. The cross-sectional structure of the side trace structure includes a first portion located above the front side of the circuit substrate, a second portion located above the side of the circuit substrate, and a third portion located above the back side of the circuit substrate. The first portion, the second portion, and the third portion each include a plurality of strip-shaped traces. The ratio between the maximum thickness of the first portion and the maximum thickness of the second portion is A. The ratio between the maximum thickness of the third portion and the maximum thickness of the second portion is B. A and B are each 0.25 to 0.6.

[0006] Based on the above, forming side trace structures using an oblique deposition process can reduce the bezel size of the component substrate. Furthermore, by adjusting the thickness of the first, second, and third portions of the side trace structure, the production yield of the side trace structure can be improved. Attached Figure Description

[0007] Figure 1A , Figure 2A , Figure 3A as well as Figure 4A This is a top view schematic diagram of a method for manufacturing a component substrate according to an embodiment of the present invention.

[0008] Figure 1B , Figure 2B , Figure 3B as well as Figure 4B This is a side view schematic diagram of a method for manufacturing a component substrate according to an embodiment of the present invention.

[0009] Figure 1C , Figure 2C , Figure 3C as well as Figure 4C This is a bottom view schematic diagram of a method for manufacturing a component substrate according to an embodiment of the present invention.

[0010] Figure 1D , Figure 2D , Figure 3D as well as Figure 4D They are along Figure 1A , Figure 2A , Figure 3A as well as Figure 4A A schematic cross-sectional view of line I-I'.

[0011] Figure 5A , Figure 6A , Figure 7A as well as Figure 8A This is a top view schematic diagram of a method for manufacturing a component substrate according to an embodiment of the present invention.

[0012] Figure 5B , Figure 6B , Figure 7B as well as Figure 8B This is a side view schematic diagram of a method for manufacturing a component substrate according to an embodiment of the present invention.

[0013] Figure 5C , Figure 6C , Figure 7C as well as Figure 8C This is a bottom view schematic diagram of a method for manufacturing a component substrate according to an embodiment of the present invention.

[0014] Figure 5D , Figure 6D , Figure 7D as well as Figure 8D They are along Figure 5A , Figure 6A , Figure 7A as well as Figure 8A A schematic cross-sectional view of line I-I'.

[0015] Figure 9 This is a cross-sectional schematic diagram of a component substrate according to an embodiment of the present invention.

[0016] Figure 10 This is a perspective view of a carrier box for a circuit board according to an embodiment of the present invention.

[0017] Figure 11 This is a data graph showing the ratio of the thickness of some conductive material layers at different locations according to the present invention.

[0018] Figure 12 This is a data graph showing the ratio of the thickness of some conductive material layers at different locations according to the present invention.

[0019] Explanation of reference numerals in the attached figures:

[0020] 100, 100A, 100B, 100C, 100D, 100E: Circuit boards

[0021] 100a, 102a: Front

[0022] 100b, 102b: Back side

[0023] 100c: Side view

[0024] 100c1: First inclined plane

[0025] 100c2: Second inclined plane

[0026] 102: Substrate

[0027] 110: Front Circuit Structure

[0028] 112: Connecting pad

[0029] 120: Rear Circuit Structure

[0030] 210: First target material

[0031] 220: Second target material

[0032] 230: Third target material

[0033] 240: Fourth target material

[0034] 300: Side wiring structure

[0035] 310': First conductive material layer

[0036] 310”, 320”: Conductive materials

[0037] 312, 322, P1: Part One

[0038] 314, 324, P2: Part Two

[0039] 316, 326, P3: Part Three

[0040] 320': Second conductive material layer

[0041] 400: Mask layer

[0042] 500: Thin-film flip-chip packaging

[0043] 510: Pin

[0044] 520: Flexible substrate

[0045] 530: Conductive connection structure

[0046] 600: Carrier box

[0047] C1: First conductive layer

[0048] C2: Second conductive layer

[0049] C3: Third conductive layer

[0050] C4: Fourth conductive layer

[0051] C5: Fifth conductive layer

[0052] E1~E3: Direction of extension

[0053] I1: First insulating layer

[0054] I2: Second insulating layer

[0055] I3: Third insulating layer

[0056] I4: Fourth insulating layer

[0057] I5: Fifth Insulation Layer

[0058] L: Left area

[0059] M: Middle area

[0060] PL: Protective layer

[0061] R: Right side area

[0062] ST1, ST2: Strip-shaped marks

[0063] T1~T9: Thickness

[0064] TS: Distance

[0065] α1, α2, α3: included angle

[0066] θ1: First included angle

[0067] θ2: Second included angle

[0068] θ3: Third included angle

[0069] θ4: Fourth included angle Detailed Implementation

[0070] Figure 1A , Figure 2A , Figure 3A as well as Figure 4A This is a top view schematic diagram of a method for manufacturing a component substrate according to an embodiment of the present invention. Figure 1B , Figure 2B , Figure 3B as well as Figure 4B This is a side view schematic diagram of a method for manufacturing a component substrate according to an embodiment of the present invention. Figure 1C , Figure 2C , Figure 3C as well as Figure 4C This is a bottom view schematic diagram of a method for manufacturing a component substrate according to an embodiment of the present invention. Figure 1D , Figure 2D , Figure 3D as well as Figure 4D They are along Figure 1A , Figure 2A , Figure 3A as well as Figure 4A A schematic cross-sectional view of line I-I'. For ease of explanation, Figure 1D as well as Figure 2D In addition to showing separately Figure 1A as well as Figure 2A In addition to the cross-sectional structure of line I-I', the cross-sectional structures of the first target 210 and the second target 220 are also shown.

[0071] Please refer to Figures 1A to 1D A circuit board 100 is provided. The circuit board 100 includes a substrate 102 and a front circuit structure 110 located on the front side 100a of the substrate 102. In this embodiment, the circuit board 100 may optionally also include a back circuit structure 120. The back circuit structure 120 is located on the back side 100b of the substrate 102.

[0072] The circuit board 100 includes a front surface 100a, a back surface 100b opposite to the front surface 100a, and a side surface 100c. In this embodiment, a first inclined surface 100c1 may optionally be included between the front surface 100a and the side surface 100c, and a second inclined surface 100c2 may optionally be included between the back surface 100b and the side surface 100c, but the invention is not limited thereto. In other embodiments, the front surface 100a and the side surface 100c have a right angle or a rounded corner, and the back surface 100b and the side surface 100c have a right angle or a rounded corner.

[0073] The substrate 102 may be a rigid substrate, for example, made of glass, quartz, organic polymer, or opaque / reflective materials (e.g., wafers, ceramics, or other suitable materials), but the invention is not limited thereto. In other embodiments, the substrate 102 may be a flexible substrate or a stretchable substrate.

[0074] A front-side circuit structure 110 is formed on the front side of the substrate 102. In this embodiment, the pads in the front-side circuit structure 110 are shown, and other structures other than the pads in the front-side circuit structure 110 are omitted. In practice, the front-side circuit structure 110 may include multiple conductive layers (not shown) and multiple insulating layers (not shown), and the pads of the front-side circuit structure 110 may be a single-layer structure or a multi-layer structure. In some embodiments, multiple active elements (not shown) and / or multiple passive elements (not shown) may be connected in the front-side circuit structure 110, and the active elements (not shown) may be thin-film transistors.

[0075] A back-side circuit structure 120 is formed on the back side of the substrate 102. In this embodiment, pads in the back-side circuit structure 120 are shown, and other structures besides the pads in the back-side circuit structure 120 are omitted. In practice, the back-side circuit structure 120 may include multiple conductive layers (not shown), and the pads of the back-side circuit structure 120 may be a single-layer structure or a multi-layer structure. In other embodiments, the back-side circuit structure 120 may be omitted.

[0076] In some embodiments, the roughness of the side surface 100c of the substrate 102 is greater than the roughness of the first inclined surface 100c1 and the second inclined surface 100c2 of the substrate 102. Specifically, due to the first conductive material layer 310' (see reference) Figure 2D Since the thickness T1 of the substrate 102 is greater than the thickness T2, the stress formed on the side surface 100c of the substrate 102 is relatively large, which can easily lead to film peeling. Therefore, a larger roughness needs to be designed on the side surface 100c of the substrate 102 to produce better film adhesion. The roughness of the first inclined surface 100c1 and the second inclined surface 100c2 to the front surface 100a and the back surface 100b is relatively small. In some embodiments, the roughness of the side surface 100c of the substrate 102 is 0.5 micrometers to 2 micrometers, and the roughness of the front surface 100a of the substrate 102 and the roughness of the first inclined surface 100c1 and the second inclined surface 100c2 of the substrate 102 is 0.1 micrometers to 0.5 micrometers.

[0077] A first oblique deposition process is performed on the front side 100a and side side 100c of the circuit substrate 100 using a first target 210 to deposit conductive material 310” on the front side 100a and side side 100c of the circuit substrate 100. In this embodiment, the conductive material 310” is also deposited on the first oblique surface 100c1. Although in Figure 1D In this embodiment, the conductive material 310” is not formed on the second inclined surface 100c2, but the present invention is not limited thereto. In some embodiments, some of the conductive material 310” may be deposited on the second inclined surface 100c2, or even a small amount may be deposited on the back surface 100b.

[0078] Please refer to Figures 2A to 2D A second oblique deposition process is performed on the back side 100b and side side 100c of the circuit substrate 100 using a second target 220. The first oblique deposition process and the second oblique deposition process form a first conductive material layer 310'. The first conductive material layer 310' extends from above the front side 100a of the circuit substrate 100, through the first oblique surface 100c1, the side side 100c, and the second oblique surface 100c2, and extends to above the back side 100b of the circuit substrate 100. The first conductive material layer 310' connects the front circuit structure 110 and the back circuit structure 120.

[0079] Please also refer to Figure 1D and Figure 2DIn this embodiment, the front surface of the first target 210 and the side surface 100 of the circuit substrate 100 have a first included angle θ1, and the front surface of the second target 220 and the side surface 100 of the circuit substrate 100 have a second included angle θ2. Both the first included angle θ1 and the second included angle θ2 are greater than 0 degrees. In a preferred embodiment, the first included angle θ1 and the second included angle θ2 are between 10 degrees and 40 degrees. When the first included angle θ1 and the second included angle θ2 are between 10 degrees and 40 degrees, the formed first conductive material layer 310' has appropriate uniformity and good adhesion to the circuit substrate 100. In some embodiments, the distance TS between the first target 210 and the circuit substrate 100 and the distance TS between the second target 220 and the circuit substrate 100 are between 8 cm and 14 cm.

[0080] In some embodiments, the first target 210 and the second target 220 comprise the same material, and the material of the first conductive material layer 310' formed by the first oblique deposition process and the second oblique deposition process includes tungsten, copper, titanium, molybdenum, silver, aluminum, thallium, nickel, chromium, or alloys of the aforementioned metals.

[0081] In this embodiment, the maximum thickness T1 of the first conductive material layer 310' on the side surface 100c of the circuit substrate 100 is greater than the maximum thickness T2 of the first conductive material layer 310' on the front surface 100a of the circuit substrate 100 and the maximum thickness T3 of the first conductive material layer 310' on the back surface 100b of the circuit substrate 100. Because the first conductive material layer 310' is thicker on the side surface 100c of the circuit substrate 100, the problem of breakage or peeling of the first conductive material layer 310' caused by the roughness of the side surface 100c of the circuit substrate 100 can be improved.

[0082] Furthermore, in this embodiment, since the first conductive material layer 310' is formed using an oblique deposition process, the cross-sectional structure of the first conductive material layer 310' includes multiple strip-shaped traces ST1. In some embodiments, the cross-sectional structure of the first conductive material layer 310' includes strip-shaped traces ST1 with different extension directions. For example, the cross-sectional structure of the first conductive material layer 310' includes strip-shaped traces ST1 with three or more extension directions.

[0083] Please refer to Figures 3A to 3DA masking layer 400 is formed on the first conductive material layer 310'. In some embodiments, the method of forming the masking layer 400 includes photolithography, screen printing, or inkjet printing, and the material of the masking layer 400 includes cured photoresist. The masking layer 400 shields at least a portion of the first conductive material layer 310', and extends from above the front side 100a of the circuit substrate 100, through the first inclined surface 100c1, the side surface 100c, and the second inclined surface 100c2, and extends above the back side 100b of the circuit substrate 100.

[0084] Please refer to Figures 4A to 4D An etching process is performed using a mask layer 400 as a mask to pattern the first conductive material layer 310' and obtain the side trace structure 300. The etching process is a wet etching process, wherein the etching solution can be selected according to the metal of the corresponding first conductive material layer 310'.

[0085] The side trace structure 300 extends from the front circuit structure 110 to the back circuit structure 120. The cross-sectional structure of the side trace structure 300 includes a first portion 312 located above the front surface 100a of the circuit board 100, a second portion 314 located above the side surface 100c of the circuit board 100, and a third portion 316 located above the back surface 100b of the circuit board 100. In this embodiment, the second portion 314 is also located above the first inclined surface 100c1 and the second inclined surface 100c2, and the second portion 314 connects the first portion 312 and the third portion 316.

[0086] In this embodiment, the ratio between the maximum thickness T2 of the first portion 312 and the maximum thickness T1 of the second portion 314 is A, and the ratio between the maximum thickness T3 of the third portion 316 and the maximum thickness T1 of the second portion 314 is B, with A and B each ranging from 0.25 to 0.6. Because the second portion 314 is thicker, the problem of breakage or peeling of the side trace structure 300 caused by the roughness of the side surface 100c of the circuit board 100 can be improved. In this embodiment, A and B are less than 0.6 to improve the problem of easy breakage or peeling of the side trace structure 300 on the side surface 100c; A and B are greater than 0.25 to avoid the problem of difficulty in controlling the etching process due to excessive thickness differences at different locations in the first conductive material layer 310'.

[0087] In this embodiment, since the method for forming the side trace structure 300 includes an oblique deposition process, the first portion 312, the second portion 314, and the third portion 316 each include a plurality of strip-shaped traces ST1. The first portion 312, the second portion 314, and the third portion 316 of the side trace structure 300 include strip-shaped traces ST1 with at least three different extension directions. For example, the angle α1 between the extension direction E1 of the strip-shaped trace ST1 in the first portion 312 and the front side 100a of the circuit board 100 is 10 to 80 degrees. The angle α3 between the extension direction E3 of the strip-shaped trace ST1 in the third portion 316 and the back side 100b of the circuit board 100 is 10 to 80 degrees. The angle α2 between the extension direction E2 of the strip-shaped trace ST1 in the second portion 314 and the side side 100c of the circuit board 100 is approximately 80 to 90 degrees. In some embodiments, the strip-shaped traces ST1 have a gradually changing extension direction. For example, as it gets closer to the second part 314, the direction of extension of the strip-shaped mark ST1 gradually changes from being inclined to the side 100c to being perpendicular to the side 100c.

[0088] Figure 5A , Figure 6A , Figure 7A as well as Figure 8A This is a top view schematic diagram of a method for manufacturing a component substrate according to an embodiment of the present invention. Figure 5B , Figure 6B , Figure 7B as well as Figure 8B This is a side view schematic diagram of a method for manufacturing a component substrate according to an embodiment of the present invention. Figure 5C , Figure 6C , Figure 7C as well as Figure 8C This is a bottom view schematic diagram of a method for manufacturing a component substrate according to an embodiment of the present invention. Figure 5D , Figure 6D , Figure 7D as well as Figure 8D They are along Figure 5A , Figure 6A , Figure 7A as well as Figure 8A A schematic cross-sectional view of line I-I'. For ease of explanation, Figure 5D as well as Figure 6D In addition to showing separately Figure 5A as well as Figure 5A In addition to the cross-sectional structure of line I-I', the cross-sectional structures of the third target 230 and the fourth target 240 are also shown.

[0089] Please refer to Figures 5A to 5D ,continue Figures 1A to 2DThe steps involve performing a third oblique deposition process on the front side 100a and side side 100c of the circuit substrate 100 using a third target 230 to deposit conductive material 320” on the front side 100a and side side 100c of the circuit substrate 100. In this embodiment, the conductive material 320” is also deposited on the first oblique surface 100c1. Although in Figure 5D In this embodiment, the conductive material 320” is not formed above the second inclined surface 100c2, but the present invention is not limited thereto. In some embodiments, a portion of the conductive material 320” may be deposited above the second inclined surface 100c2, or even a small amount may be deposited above the back surface 100b.

[0090] Please refer to Figures 6A to 6D A fourth oblique deposition process is performed on the back surface 100b and side surface 100c of the circuit substrate 100 using a fourth target 240. The third and fourth oblique deposition processes form a second conductive material layer 320' on the first conductive material layer 310'. The second conductive material layer 320' extends from above the front surface 100a of the circuit substrate 100, passing through the first oblique surface 100c1, the side surface 100c, and the second oblique surface 100c2, and extends to above the back surface 100b of the circuit substrate 100. The second conductive material layer 320' completely or partially covers the first conductive material layer 310'.

[0091] Please also refer to Figure 5D and Figure 6D In this embodiment, a third angle θ3 is formed between the front surface of the third target 230 and the side surface 100 of the circuit substrate 100, and a fourth angle θ4 is formed between the front surface of the fourth target 240 and the side surface 100 of the circuit substrate 100. Both the third angle θ3 and the fourth angle θ4 are greater than 0 degrees. In a preferred embodiment, the third angle θ3 and the fourth angle θ4 are between 10 and 40 degrees. When the third angle θ3 and the fourth angle θ4 are between 10 and 40 degrees, the formed second conductive material layer 320' has appropriate uniformity. In some embodiments, the distance TS between the third target 230 and the circuit substrate 100 and between the fourth target 240 and the circuit substrate 100 is between 8 cm and 14 cm.

[0092] In some embodiments, the third target 230 and the fourth target 240 comprise the same material, and the material of the second conductive material layer 320' formed by the third and fourth oblique deposition processes includes tungsten, copper, titanium, molybdenum, silver, aluminum, thallium, nickel, chromium, or alloys of the aforementioned metals. In some embodiments, the second conductive material layer 320' and the first conductive material layer 310' comprise different materials. For example, the first conductive material layer 310' is selected from materials with high adhesion to the substrate 102, while the second conductive material layer 320' is selected from materials with high conductivity.

[0093] In this embodiment, the maximum thickness T4 of the second conductive material layer 320' above the side surface 100c of the circuit substrate 100 is greater than the maximum thickness T5 of the second conductive material layer 320' above the front surface 100a of the circuit substrate 100 and the maximum thickness T6 of the second conductive material layer 310' above the back surface 100b of the circuit substrate 100.

[0094] Furthermore, in this embodiment, since the second conductive material layer 320' is formed using an oblique deposition process, the cross-sectional structure of the second conductive material layer 320' includes multiple strip-shaped traces ST2. In some embodiments, the cross-sectional structure of the second conductive material layer 320' includes strip-shaped traces ST2 with different extension directions. For example, the cross-sectional structure of the second conductive material layer 320' includes strip-shaped traces ST2 with three or more extension directions. In some embodiments, the strip-shaped traces ST1 in the first conductive material layer 310' and the strip-shaped traces ST2 in the second conductive material layer 320' may or may not be connected. For example, some of the strip-shaped traces ST1 are connected to the strip-shaped traces ST2, while other parts of the strip-shaped traces ST1 are not connected to the strip-shaped traces ST2. Figure 6D In the example, the strip-shaped trace ST1 and the strip-shaped trace ST2 are connected.

[0095] Please refer to Figures 7A to 7D A masking layer 400 is formed on the second conductive material layer 320'. In some embodiments, the material of the masking layer 400 includes cured photoresist, and the method of forming the masking layer 400 includes photolithography, screen printing, or inkjet printing. The masking layer 400 shields at least a portion of the second conductive material layer 320', and extends from above the front side 100a of the circuit substrate 100, through the first inclined surface 100c1, the side surface 100c, and the second inclined surface 100c2, and extends above the back side 100b of the circuit substrate 100.

[0096] Please refer to Figures 8A to 8D An etching process is performed using a mask layer 400 as a mask to pattern the first conductive material layer 310' and the second conductive material layer 320', resulting in a side trace structure 300 with a multi-layer structure. In this embodiment, the first conductive material layer 310' is patterned to form a buffer layer 310, and the second conductive material layer 320' is patterned to form a conductive layer 320. The side trace structure 300 includes stacked buffer layers 310 and conductive layers 320. The etching process is a wet etching process, wherein the etching solution can be selected corresponding to the metals of the first conductive material layer 310' and the second conductive material layer 320'.

[0097] In some embodiments, the buffer layer 310 and the conductive layer 320 comprise different materials. For example, the adhesion between the material of the buffer layer 310 and the substrate 102 is greater than the adhesion between the material of the conductive layer 320 and the substrate 102. The conductivity of the material of the conductive layer 320 is greater than the conductivity of the material of the buffer layer 310.

[0098] The side trace structure 300 extends from the front circuit structure 110 to the back circuit structure 120. The cross-sectional structure of the side trace structure 300 includes a first portion P1 located above the front surface 100a of the circuit board 100, a second portion P2 located above the side surface 100c of the circuit board 100, and a third portion P3 located above the back surface 100b of the circuit board 100. In this embodiment, the second portion P2 is also located on the first inclined surface 100c1 and the second inclined surface 100c2, and the second portion P2 connects the first portion P1 and the third portion P3.

[0099] In this embodiment, the first part P1 includes a first part 312 of the buffer layer 310 and a first part 322 of the conductive layer 320 stacked together; the second part P2 includes a second part 314 of the buffer layer 310 and a second part 324 of the conductive layer 320 stacked together; and the third part P3 includes a third part 316 of the buffer layer 310 and a third part 326 of the conductive layer 320 stacked together.

[0100] In this embodiment, the ratio between the maximum thickness T8 of the first part P1 and the maximum thickness T7 of the second part P2 is A, and the ratio between the maximum thickness T9 of the third part P3 and the maximum thickness T7 of the second part P2 is B, with A and B each ranging from 0.25 to 0.6. Since the second part P2 is thicker, the problem of breakage or peeling of the side trace structure 300 caused by the roughness of the side surface 100c of the circuit board 100 can be improved. In this embodiment, A and B are less than 0.6 to improve the problem of easy breakage or peeling of the side trace structure 300 on the side surface 100c; A and B are greater than 0.25 to avoid the problem of difficulty in controlling the etching process due to excessive thickness differences at different locations in the first conductive material layer 310' and the second conductive material layer 320'.

[0101] In this embodiment, the conductive layer 320 and the buffer layer 310 respectively include corresponding strip-shaped traces ST2 and ST1. In some embodiments, a portion of the corresponding strip-shaped trace ST2 in the conductive layer 320 is connected to the corresponding strip-shaped trace ST1 in the buffer layer 310. In some embodiments, a portion of the corresponding strip-shaped trace ST2 in the conductive layer 320 is not connected to the corresponding strip-shaped trace ST1 in the buffer layer 310. Figure 8D In the example, the strip-shaped trace ST1 and the strip-shaped trace ST2 are connected.

[0102] The buffer layer 310 includes at least three strip-shaped traces ST1 extending in three different directions in its first portion 312, second portion 314, and third portion 316; the conductive layer 320 includes at least three strip-shaped traces ST2 extending in three different directions in its first portion 322, second portion 324, and third portion 326. For example, the angle α1 between the extension direction E1 of the strip-shaped trace ST1 in the first portion 312 and the strip-shaped trace ST2 in the first portion 322 and the front side 100a of the circuit board 100 is 10 to 80 degrees. The angle α3 between the extension direction E3 of the strip-shaped trace ST1 in the third portion 316 and the strip-shaped trace ST2 in the third portion 326 and the back side 100b of the circuit board 100 is 10 to 80 degrees. The angle α2 between the extension direction E2 of the strip-shaped trace ST1 in the second portion 314 and the strip-shaped trace ST2 in the second portion 324 and the side side 100c of the circuit board 100 is approximately 80 to 90 degrees. In some embodiments, strip-shaped marks ST1 and ST2 have a gradually changing direction of extension. For example, as they approach the second portion 314 / second portion 324, the direction of extension of strip-shaped marks ST1 / ST2 gradually changes from being inclined to the side 100c to being perpendicular to the side 100c.

[0103] Adjust the angles (first angle θ1 to fourth angle θ4) between the front surface of the target (first target 210 to fourth target 240) and the side surface 100 of the circuit substrate 100 in the first to fourth oblique deposition processes, and adjust the distance TS between the target (first target 210 to fourth target 240) and the circuit substrate 100. Measure the obtained conductive material layer (e.g., ... Figure 6D The average thickness F of the first conductive material layer 310' plus the second conductive material layer 320' on the front side 100a of the circuit substrate 100, the average thickness S on the side side 100c of the circuit substrate 100, and the average thickness B on the back side 100b of the circuit substrate 100 are shown in Table 1.

[0104] Table 1

[0105]

[0106] As can be seen from Table 1, when the first included angle θ1 to the fourth included angle θ4 is 10° to 30°, the average thickness S of the second part P2 of the obtained side wiring structure 300 is greater than the average thickness F of the first part P1 and the average thickness B of the third part P3.

[0107] Figure 9 This is a schematic cross-sectional view of a component substrate according to an embodiment of the present invention. It should be noted that... Figure 9 The embodiments follow Figures 1A to 4DThe component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0108] Please refer to Figure 9 The front circuit structure 110 is located on the front side 102a of the substrate 102. In this embodiment, the side of the front circuit structure 110 is aligned with the side of the substrate 102, and a first inclined surface 100c1 is formed between the side of the front circuit structure 110 and the front side, thereby preventing damage to the edge of the circuit structure 200. However, the present invention is not limited thereto. In other embodiments, the side of the front circuit structure 110 and the front side are rounded or right-angled.

[0109] In some embodiments, the front circuit structure 110 includes multiple insulating layers and multiple conductive layers. In some embodiments, the front circuit structure 110 further includes multiple semiconductor layers. For example, the front circuit structure 110 includes a first insulating layer I1, a second insulating layer I2, a third insulating layer I3, a fourth insulating layer I4, and a fifth insulating layer I5 stacked in sequence. The pad 112 includes a first conductive layer C1, a second conductive layer C2, a third conductive layer C3, a fourth conductive layer C4, and a fifth conductive layer C5 stacked in sequence.

[0110] In some embodiments, the materials of the first insulating layer I1, the second insulating layer I2, the third insulating layer I3, the fourth insulating layer I4, and the fifth insulating layer I5 each include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, organic insulating materials, or other suitable insulating materials. In some embodiments, the materials of the first conductive layer C1, the second conductive layer C2, the third conductive layer C3, the fourth conductive layer C4, and the fifth conductive layer C5 each include metals, metal oxides, metal nitrides, or other suitable conductive materials.

[0111] A first conductive layer C1 is located on a first insulating layer I1. A second insulating layer I2 is located on both the first conductive layer C1 and the first insulating layer I1, and has an opening overlapping the first conductive layer C1. A second conductive layer C2 is located on the second insulating layer I2, and fills the opening of the second insulating layer I1 to connect to the first conductive layer C1. A third insulating layer I3 is located on both the second conductive layer C2 and the second insulating layer I2, and has an opening overlapping the second conductive layer C2. A third conductive layer C3 is located on the third insulating layer I3, and fills the opening of the third insulating layer I3 to connect to the second conductive layer C2. A fourth insulating layer I4 is located on both the third conductive layer C3 and the third insulating layer I3, and has an opening overlapping the third conductive layer C3. A fourth conductive layer C4 is located on the fourth insulating layer I4, and fills the opening of the fourth insulating layer I4 to connect to the third conductive layer C3. A fifth insulating layer I5 is located on both the fourth conductive layer C4 and the fourth insulating layer I4, and has an opening overlapping the fourth conductive layer C4. The fifth conductive layer C5 is located on the fifth insulating layer I5 and fills the opening of the fifth insulating layer I5 to connect to the fourth conductive layer C4.

[0112] Although in this embodiment, the front circuit structure 110 includes five insulating layers and the pads 112 of the front circuit structure 110 include five conductive layers, the present invention is not limited thereto. The number of insulating and conductive layers in the front circuit structure 110 can be adjusted according to actual needs. In this embodiment, the surface layer of the pads 112 includes a stepped structure.

[0113] In some embodiments, the front circuit structure 110 includes a peripheral area and a display area, wherein a pad 112 is disposed in the peripheral area, and the front circuit structure 110 also includes a plurality of display elements (e.g., inorganic light-emitting diodes, organic light-emitting diodes, liquid crystal pixels, or other suitable display elements) disposed in the display area. The pad 112 is electrically connected to the aforementioned display elements via signal lines and other electronic components.

[0114] The back-side circuit structure 120 is located on the back side 102b of the carrier board 102. In this embodiment, the back-side circuit structure 120 is a single-layer structure, but the present invention is not limited thereto. In other embodiments, the back-side circuit structure 120 is a multi-layer structure.

[0115] The side trace structure 300 electrically connects the pad 112 to the back circuit structure 120. In this embodiment, the side trace structure 300 includes a first portion P1 located above the front side 100a of the circuit board 100, a second portion P2 located above the side side 100c of the circuit board 100, and a third portion P3 located above the back side 100b of the circuit board 100. The side trace structure 300 includes strip-shaped traces ST1 with different extension directions.

[0116] In this embodiment, the first portion P1 of the side trace structure 300 contacts the surface of the fifth insulating layer I5 and the pad 112 with a stepped structure. Because the first portion P1 is thinner, the problem of peeling caused by excessive thickness of the first portion P1 can be mitigated. In some embodiments, the material of the side trace structure 300 is copper, and the material of the fifth insulating layer I5 is silicon nitride. Reducing the thickness of the first portion P1 can improve the stress problem caused by poor adhesion between copper and silicon nitride in the first portion P1.

[0117] In this embodiment, the back circuit structure 120 is formed first, followed by the side trace structure 300. Therefore, the third portion P3 of the side trace structure 300 partially covers the back circuit structure 120. In other embodiments, the side trace structure 300 is formed first, followed by the back circuit structure 120. In this case, the back circuit structure 120 partially covers the third portion P3 of the side trace structure 300.

[0118] The protective layer PL is formed on the side trace structure 300.

[0119] The thin-film flip-chip package 500 is bonded to the back circuit structure 120. In this embodiment, the thin-film flip-chip package 500 includes a flexible substrate 520 and pins 510 located on the flexible substrate 520. The pins 510 are electrically connected to the back circuit structure 120 via a conductive connection structure 530. The conductive connection structure 530 is, for example, conductive adhesive, solder, or other suitable material. In other embodiments, the back circuit structure 120 may be omitted, and the thin-film flip-chip package 500 is directly bonded to the third portion P3 of the side trace structure 300.

[0120] Figure 10 This is a perspective view of a circuit board carrier cassette 600 according to an embodiment of the present invention. In this embodiment, multiple circuit boards 100A to 100E are placed in the carrier cassette 600, thereby allowing oblique deposition processes to be performed on multiple circuit boards 100A to 100E simultaneously. The structure of the circuit boards 100A to 100E can refer to the circuit board 100 in any of the foregoing embodiments. In this embodiment, circuit boards 100A to 100E are mounted in one carrier cassette 600, but the present invention is not limited thereto. In other embodiments, the number of circuit boards in the carrier cassette 600 can be adjusted according to actual needs.

[0121] The circuit boards 100A to 100E are mounted in the carrier box 600 and then executed. Figures 1A to 2D The deposition process is then executed. Figures 5A to 6D The deposition process. The thickness of the conductive material layer deposited on the circuit board 100A~100E is measured (e.g., ...). Figure 6DThe thickness of the first conductive material layer 310' and the sum of the thicknesses of the second conductive material layer 320' shown are used to measure the thickness of the conductive material layer on the left side region L, the middle region M, and the right side region R of the circuit substrates 100A-100E, respectively. The average thickness of the conductive material layer on the front side 100a of the circuit substrates 100A-100E is denoted by F, the average thickness of the conductive material layer on the side side 100c of the circuit substrate 100 is denoted by S, and the average thickness of the conductive material layer on the back side 100b of the circuit substrate 100 is denoted by B.

[0122] When the angle between the front side of the target material used in the four deposition processes and the side surface of the circuit substrates 100A to 100E is 0 degrees (i.e., the front side of the target material is parallel to the side surface of the circuit substrates 100A to 100E), the thickness of the conductive material layer in the left region L, the middle region M, and the right region R is shown in Table 2. In Table 2, the unit of thickness is micrometers.

[0123] Table 2

[0124]

[0125] Calculate the ratio of average thickness F to average thickness S (F / S) and the ratio of average thickness B to average thickness S (B / S) in Table 2. The results are shown in Table 3. Map the data in Table 3 to obtain... Figure 11 .

[0126] Table 3

[0127]

[0128] When the angle between the front side of the target material used in the four deposition processes and the side surface of the circuit substrate 100A-100E is 10 degrees (i.e., the first angle θ1 to the fourth angle θ4 are all 10 degrees), the thickness of the conductive material layer in the left region L, the middle region M, and the right region R is shown in Table 4. In Table 4, the unit of thickness is micrometers.

[0129] Table 4

[0130]

[0131] Calculate the ratio of average thickness F to average thickness S (F / S) and the ratio of average thickness B to average thickness S (B / S) in Table 4. The results are shown in Table 5. Map the data in Table 5 to obtain... Figure 12 .

[0132] Table 5

[0133]

[0134] Compare Figure 11 and Figure 12 It can be seen that when the angle between the front side of the target and the side surface of the circuit substrates 100A to 100E is 10 degrees, a larger F / S and B / S can be obtained. Specifically, the B / S of circuit substrate 100B and the F / S and B / S of circuit substrate 100C can even exceed 0.4. Therefore, in oblique deposition processes, an angle of 10 degrees or more between the front side of the target and the side surface of the circuit substrate is more likely to result in increased F / S and B / S.

Claims

1. A method for manufacturing a component substrate, comprising: A circuit board is provided, the circuit board including a substrate and a front circuit structure located on the front side of the substrate; as well as A side trace structure is formed to electrically connect the front circuit structure, wherein the side trace structure extends from the front circuit structure to the back of the circuit substrate, and the method of forming the side trace structure includes: A first oblique deposition process is performed on the front and side surfaces of a circuit substrate using a first target to deposit a conductive material on the front and side surfaces of the circuit substrate, wherein the front surface of the first target and the side surface of the circuit substrate have a first included angle of 10 degrees to 40 degrees; and A second oblique deposition process is performed on the back side and the side side of the circuit substrate using a second target material, wherein the front side of the second target material and the side side of the circuit substrate have a second included angle of 10 degrees to 40 degrees, wherein the first oblique deposition process and the second oblique deposition process together form a first conductive material layer, wherein the maximum thickness of the first conductive material layer on the side side of the circuit substrate is greater than the maximum thickness of the first conductive material layer on the front side of the circuit substrate and the maximum thickness of the first conductive material layer on the back side of the circuit substrate, wherein: The cross-sectional structure of the side trace structure includes a first portion located above the front side of the circuit board, a second portion located above the side of the circuit board, and a third portion located above the back side of the circuit board. Each of the first, second, and third portions includes multiple strip-shaped traces. The ratio between the maximum thickness of the first portion and the maximum thickness of the second portion is A, and the ratio between the maximum thickness of the third portion and the maximum thickness of the second portion is B. A and B are each 0.25 to 0.

6.

2. The method for manufacturing a component substrate as claimed in claim 1, wherein the circuit substrate further includes a back circuit located on the back side of the substrate, wherein the side trace structure extends from the front circuit structure to the back circuit.

3. The method for manufacturing a component substrate as claimed in claim 1, wherein the first portion, the second portion, and the third portion of the side trace structure include at least three strip-shaped traces extending in three different directions, wherein the circuit substrate further includes a first inclined surface located between the front side and the side side, and the conductive material is further deposited on the first inclined surface, wherein the circuit substrate further includes a second inclined surface located between the back side and the side side, the first conductive material layer extending from above the front side of the circuit substrate through the first inclined surface, the side side, and the second inclined surface, and extending to above the back side of the circuit substrate, wherein the roughness of the side side of the circuit substrate is greater than the roughness of the first inclined surface and the second inclined surface of the circuit substrate.

4. The method for manufacturing a component substrate as claimed in claim 1, wherein the method for forming the side trace structure further includes: A masking layer is formed on the first conductive material layer; as well as An etching process is performed using the mask layer as a mask to pattern the first conductive material layer.

5. The method for manufacturing a component substrate as claimed in claim 4, wherein the method for forming the mask layer includes photolithography, screen printing, or inkjet printing, wherein the angle between the extension direction of the strip-shaped traces of the first portion and the front side of the circuit substrate is 10 degrees to 80 degrees, the angle between the extension direction of the strip-shaped traces of the second portion and the side side of the circuit substrate is 80 to 90 degrees, the angle between the extension direction of the strip-shaped traces of the third portion and the back side of the circuit substrate is 10 degrees to 80 degrees, and as it gets closer to the second portion, the extension direction of the strip-shaped traces of the cross-sectional structure of the side wiring structure gradually changes from being inclined to the side side to being perpendicular to the side side.

6. The method for manufacturing a component substrate as claimed in claim 1, wherein the method for forming the side trace structure further includes: A third oblique deposition process is performed on the front side and the side side of the circuit substrate using a third target, wherein the front side of the third target and the side side of the circuit substrate have a third included angle. A fourth oblique deposition process is performed on the back side and the side side of the circuit substrate using a fourth target, wherein the front side of the fourth target and the side side of the circuit substrate have a fourth included angle, wherein the third oblique deposition process and the fourth oblique deposition process form a second conductive material layer on the first conductive material layer, and the maximum thickness of the second conductive material layer above the side side of the circuit substrate is greater than the maximum thickness of the second conductive material layer above the front side of the circuit substrate and the maximum thickness of the second conductive material layer above the back side of the circuit substrate; A masking layer is formed on the second conductive material layer; as well as An etching process is performed using the mask layer as a mask to pattern the first conductive material layer and the second conductive material layer.

7. The method for manufacturing a component substrate as claimed in claim 6, wherein the first conductive material layer is patterned to form a buffer layer, and the second conductive material layer is patterned to form a conductive layer, the side trace structure includes the stacked buffer layer and the conductive layer, and the buffer layer and the conductive layer include different materials, wherein the adhesion between the material of the buffer layer and the substrate is greater than the adhesion between the material of the conductive layer and the substrate, and the conductivity of the material of the conductive layer is greater than the conductivity of the material of the buffer layer.

8. A component substrate, comprising: A circuit board includes a substrate and a front circuit structure located on the front side of the substrate. as well as A side-side trace structure electrically connects to the front circuit structure and extends from the front circuit structure to the back of the circuit board. The cross-sectional structure of the side-side trace structure includes a first portion located above the front of the circuit board, a second portion located above the side of the circuit board, and a third portion located above the back of the circuit board. Each of the first, second, and third portions includes multiple strip-shaped traces. The ratio A between the maximum thickness of the first portion and the maximum thickness of the second portion, and the ratio B between the maximum thickness of the third portion and the maximum thickness of the second portion, are both between 0.25 and 0.

6. The maximum thickness of the second part is greater than the maximum thickness of the first part and the maximum thickness of the third part.

9. The component substrate of claim 8, wherein the circuit substrate further includes a back circuit located on the back side of the substrate, wherein the side trace structure extends from the front circuit structure to the back circuit.

10. The component substrate of claim 8, wherein the first portion, the second portion, and the third portion of the side trace structure include at least three strip-shaped traces extending in three different directions.

11. The component substrate of claim 8, wherein the angle between the extending direction of the strip-shaped traces of the first portion and the front side of the circuit substrate is 10 degrees to 80 degrees, and the angle between the extending direction of the strip-shaped traces of the third portion and the back side of the circuit substrate is 10 degrees to 80 degrees.

12. The component substrate of claim 8, wherein the angle between the extending direction of the strip-shaped traces of the second portion and the side surface of the circuit substrate is 80 to 90 degrees.

13. The component substrate of claim 8, wherein the substrate further comprises a first inclined surface located between the front side and the side side and a second inclined surface located between the back side and the side side, wherein the roughness of the side side of the substrate is greater than the roughness of the first inclined surface and the roughness of the second inclined surface of the substrate.

14. The component substrate of claim 13, wherein the roughness of the side surface of the substrate is 0.5 micrometers to 2 micrometers, and the roughness of the first inclined surface and the roughness of the second inclined surface of the substrate are 0.1 micrometers to 0.5 micrometers, wherein the front circuit structure has a stepped pad, and the first portion of the side trace structure contacts the stepped pad.

15. The component substrate of claim 8, wherein the side trace structure includes a stacked buffer layer and a conductive layer, and the buffer layer and the conductive layer comprise different materials.

16. The component substrate of claim 15, wherein the adhesion between the material of the buffer layer and the substrate is greater than the adhesion between the material of the conductive layer and the substrate.

17. The component substrate of claim 15, wherein the conductivity of the material of the conductive layer is greater than the conductivity of the material of the buffer layer.

18. The component substrate of claim 15, wherein the conductive layer and the buffer layer each include corresponding strip-shaped traces, and a portion of the corresponding strip-shaped traces in the conductive layer is not connected to the corresponding strip-shaped traces in the buffer layer.

19. The component substrate of claim 15, wherein the conductive layer and the buffer layer each include corresponding strip-shaped traces, and a portion of the corresponding strip-shaped traces in the conductive layer is connected to the corresponding strip-shaped traces in the buffer layer.

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