Chip dual-face interconnection package structure and preparation method thereof

Abstract

This application provides a chip double-sided interconnect packaging structure and its fabrication method, relating to the field of semiconductor device packaging technology. It includes a molding compound substrate and a chip and a metal conductive sheet embedded within the molding compound substrate. The chip and the metal conductive sheet are spaced apart, with both sides of the chip and the metal conductive sheet exposed on the surface of the molding compound substrate. A conductive terminal is pre-set on the front side of the chip. A wiring layer is provided on at least one side of the molding compound substrate to connect the front and / or back sides of the chip with the metal conductive sheet. A first encapsulation layer is provided on the side of the molding compound substrate corresponding to the front side of the chip, and a second encapsulation layer is provided on the side of the molding compound substrate corresponding to the back side of the chip. The chip double-sided interconnect packaging structure and its fabrication method of this application achieve double-sided interconnection without the need for electroplated metal pillars, reducing process complexity, resulting in a compact structure and effectively reducing the overall thickness of the electronic device.

Description

Technical Field

[0001] This application relates to the field of semiconductor device packaging technology, specifically to a chip double-sided interconnect packaging structure and its fabrication method. Background Technology

[0002] With the development of electronic technology and the increasingly widespread and in-depth application of electronic products in all walks of life, in order to meet the requirements of the structure and application scenarios of various electronic devices, the requirements for miniaturization and thinning of electronic devices have also been put forward.

[0003] Electronic devices typically require one or more chips to be placed on a substrate to achieve corresponding functions. Chips include single-sided electrode chips and double-sided electrode chips. In order to make efficient use of the surface size of electronic devices, it is necessary to perform interconnection operations on the upper and lower electrodes of the chips, as well as interconnection between multiple chips.

[0004] In existing technologies, double-sided interconnect structures for chips typically use a ceramic substrate with implanted / electroplated metal pillars to achieve interconnection between the upper and lower electrodes of the chip. The metal pillars themselves need to have a certain thickness to ensure the stability of the interconnection. When the thickness of the chip itself is also relatively large, the stacked metal pillars result in a relatively large overall thickness of the packaging structure. Moreover, it also increases the number of process steps and the difficulty of the process during the fabrication of the packaging structure. At the same time, the manufacturing cost of the packaging structure is also very high, and it is difficult to guarantee the reliability of the electronic device. Summary of the Invention

[0005] The purpose of this application is to provide a chip double-sided interconnect packaging structure and its preparation method, which can achieve double-sided interconnect without setting electroplated metal pillars, reducing process complexity, making the structure compact, and effectively reducing the overall thickness of electronic devices.

[0006] One aspect of this application provides a chip double-sided interconnect packaging structure, including a molding compound board and a chip and a metal conductive sheet embedded in the molding compound board. The chip and the metal conductive sheet are spaced apart, and both sides of the chip and the metal conductive sheet are exposed on the surface of the molding compound board. A conductive terminal is pre-set on the front side of the chip. A wiring layer is provided on at least one side of the molding compound board to connect the front and / or back sides of the chip with the metal conductive sheet. A first encapsulation layer is provided on the side of the molding compound board corresponding to the front side of the chip, and a second encapsulation layer is provided on the side of the molding compound board corresponding to the back side of the chip.

[0007] In one feasible embodiment of this application, the thickness of the chip is equal to the thickness of the metal conductive sheet and equal to the thickness of the molding compound.

[0008] In one feasible embodiment of this application, the conductive end is a conductive post, and the sum of the thickness of the chip and the conductive post is equal to the thickness of the metal conductive sheet.

[0009] In one feasible embodiment of this application, the conductive terminals of the chip are exposed on the surface of the first encapsulation layer, and / or the back side of the chip is exposed on the surface of the second encapsulation layer.

[0010] In one feasible embodiment of this application, the conductive end of the chip is flush with the surface of the first encapsulation layer, and / or the back side of the chip is flush with the surface of the second encapsulation layer.

[0011] In one feasible embodiment of this application, the metal conductive sheet is rectangular, and all four sides of the rectangle are recessed inward with grooves.

[0012] In one feasible embodiment of this application, a through hole is provided at the center of the rectangle.

[0013] In one feasible embodiment of this application, the length of the rectangle is greater than or equal to 0.5 mm; and / or, the width of the rectangle is greater than or equal to 0.5 mm.

[0014] In one feasible embodiment of this application, the chip includes multiple chips, which are spaced apart and disposed around the metal conductive sheet.

[0015] In one feasible embodiment of this application, the chip includes a first chip with a single-sided electrode and a second chip with a double-sided electrode. Wiring layers are respectively provided on both sides of the molding compound to connect the front and back sides of the chip with the metal conductive sheet. When there are multiple second chips, the distance between two adjacent second chips is less than or equal to the distance between the second chip and the first chip, and less than or equal to the distance between the second chip and the metal conductive sheet.

[0016] Another aspect of this application provides a method for fabricating a chip double-sided interconnect package structure, comprising: depositing a chip and a metal conductive sheet at intervals on a pyrolysis film, wherein a conductive terminal is pre-set on the side of the chip exposed on the surface of the pyrolysis film; molding the chip; attaching the side of the pyrolysis film on which the chip and the metal conductive sheet are deposited to a molding compound and thermoforming it; removing the pyrolysis film, transferring the chip and the metal conductive sheet to the molding compound, with the back side of the chip and the surface of the metal conductive sheet exposed on the molding compound; spin-coating passivating adhesive on the back side of the exposed chip and the surface of the metal conductive sheet on the molding compound and curing it to form a second encapsulation layer; thinning the other side of the molding compound to expose the side of the chip with the conductive terminal and the surface of the exposed metal conductive sheet; redistributing wiring on the side of the chip with the conductive terminal to interconnect the conductive terminal of the chip with the metal conductive sheet; spin-coating passivating adhesive on the thinned side of the molding compound and curing it to form a first encapsulation layer; sputtering electrode metal on the first encapsulation layer and etching to form an electrode panel.

[0017] In one feasible embodiment of this application, the chip includes a first chip with a single-sided electrode and a second chip with a double-sided electrode; before spin-coating passivating adhesive onto the back side of the exposed chip and the surface of the metal conductive sheet on the molding compound and curing it to form a second encapsulation layer, the preparation method further includes: redistributing wiring on the chip and the metal conductive sheet to interconnect the back side of the chip with the metal conductive sheet.

[0018] In one feasible embodiment of this application, spin-coating passivating adhesive onto the back side of the exposed chip and the surface of the metal conductive sheet on the molding compound board and curing it to form a second encapsulation layer includes: spin-coating passivating adhesive onto the back side of the exposed chip and the surface of the metal conductive sheet on the molding compound board; photolithography on the passivating adhesive at positions corresponding to the chip to expose the back side of the chip; and curing the passivating adhesive to form a second encapsulation layer having a window exposing the back side of the chip.

[0019] In one feasible embodiment of this application, spin-coating passivating adhesive on the thinned side of the molding compound and curing it to form a first encapsulation layer includes: spin-coating passivating adhesive on the thinned side of the molding compound; photolithography on the passivating adhesive at the position corresponding to the chip to expose the working area of ​​the chip, wherein the working area includes the surface of the chip, or the working area includes a preset conductive terminal on the chip; and curing the passivating adhesive to form a first encapsulation layer having a window exposing the working area of ​​the chip.

[0020] In one feasible embodiment of this application, the thickness of the chip is equal to the thickness of the metal conductive sheet and equal to the thickness of the thinned molding compound.

[0021] The chip double-sided interconnect packaging structure provided in this application includes a molding compound and a chip and a metal conductive sheet embedded in the molding compound. The embedding method can reduce the thickness of the components stacked together in the packaging structure. The chip and the metal conductive sheet are spaced apart on the molding compound, and both sides of the chip and the metal conductive sheet are exposed on the surface of the molding compound for easy electrical connection. The front side of the chip has a pre-set conductive terminal. A wiring layer is provided on at least one side of the molding compound to connect the front and / or back sides of the chip with the metal conductive sheet. A first encapsulation layer is provided on the side of the molding compound corresponding to the front side of the chip, and a second encapsulation layer is provided on the side of the molding compound corresponding to the back side of the chip. The chip double-sided interconnect packaging structure of this application is fabricated based on the molding compound, without the need for an additional substrate or interconnection by drilling holes and setting copper pillars. Moreover, the method of embedding the chip and the metal conductive sheet into the molding compound allows the packaging to be performed in one step, thereby simplifying the fabrication process and reducing the process difficulty. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is one of the planar structural diagrams of a chip double-sided interconnect packaging structure provided in the embodiments of this application;

[0024] Figure 2 This is one of the hierarchical structure diagrams of a chip double-sided interconnect packaging structure provided in the embodiments of this application;

[0025] Figure 3 This is a second schematic diagram of the hierarchical structure of a chip double-sided interconnect packaging structure provided in this application embodiment;

[0026] Figure 4 This is the third schematic diagram of the hierarchical structure of a chip double-sided interconnect packaging structure provided in this application embodiment;

[0027] Figure 5 This is a schematic diagram of the structure of a metal conductive sheet in a chip double-sided interconnect packaging structure provided in this application embodiment;

[0028] Figure 6 This is a second planar structural diagram of a chip double-sided interconnect packaging structure provided in the embodiments of this application;

[0029] Figure 7 This is one of the flowcharts of a method for fabricating a chip double-sided interconnect packaging structure provided in the embodiments of this application;

[0030] Figure 8 This is a second flowchart of a method for fabricating a chip double-sided interconnect packaging structure provided in the embodiments of this application;

[0031] Figure 9 This is the third flowchart of a method for fabricating a chip double-sided interconnect packaging structure provided in the embodiments of this application;

[0032] Figure 10 This is the fourth flowchart of a method for fabricating a chip double-sided interconnect packaging structure provided in the embodiments of this application.

[0033] Icons: 10-molding board; 20-chip; 21-conductive terminal; 30-metal conductive sheet; 40-wiring layer; 50-first encapsulation layer; 60-second encapsulation layer. Detailed Implementation

[0034] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0035] In the description of this application, it should be noted that the terms "inner" and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0036] It should also be noted that, unless otherwise explicitly specified and limited, the terms "setup" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0037] Electronic devices typically consist of multiple functional chips mounted on a substrate, electrically interconnected to achieve their functions. Interconnection between these chips is generally achieved by drilling holes in the substrate and electroplating metal pillars within those holes. This creates electrical connections between the chips, as well as between the top and bottom sides of double-sided electrode chips. Especially when the chip thickness is significant, the corresponding metal pillars also need to be quite tall, increasing the overall thickness of the electronic device and hindering its miniaturization. This makes it difficult to apply the device to applications with limited height space. Furthermore, the increased height of the metal pillars also increases the manufacturing complexity. Since the metal pillars are used to connect the electrodes to the chips, if they break during the manufacturing process or the connection between the pillar and the chip is interrupted, the reliability of the entire package structure will decrease, or it may even become unusable.

[0038] Based on this, embodiments of this application provide a chip double-sided interconnect packaging structure, such as... Figure 1 As shown, the chip double-sided interconnect package structure includes a molding compound 10 and a chip 20 and a metal conductive sheet 30 embedded in the molding compound 10. The chip 20 and the metal conductive sheet 30 are spaced apart, as shown. Figure 2 As shown, both sides of the chip 20 and the metal conductive sheet 30 are exposed on the surface of the molding compound 10. The front side of the chip 20 (refer to...) Figure 2The molded plate 10 has a conductive terminal 21 on the side facing upward. A wiring layer 40 is provided on at least one side of the molded plate 10 to connect the front and / or back sides of the chip 20 with the metal conductive sheet 30. A first encapsulation layer 50 is provided on the side of the molded plate 10 corresponding to the front side of the chip 20, and a second encapsulation layer 60 is provided on the side of the molded plate 10 corresponding to the back side of the chip 20.

[0039] like Figure 1 As shown, in the chip double-sided interconnect packaging structure of this application embodiment, a chip 20 and a metal conductive sheet 30 are embedded at intervals on the molding compound 10. Since the chip 20 and the metal conductive sheet 30 are embedded in the molding compound 10, as... Figure 2 As shown, in the thickness direction, the thicknesses of the molding compound 10, chip 20, and metal conductive sheet 30 are shared, and the thickness is not increased due to the stacking arrangement. For example, Figure 1 As shown, the chip 20 and the metal conductive sheet 30 are spaced apart on the molding compound 10 and are not connected to each other. Each is fixed to the molding compound 10. In the specific fabrication process, through holes can be pre-drilled in the molding compound 10 to embed the chip 20 and the metal conductive sheet 30. This allows the front and back sides of the embedded chip 20, as well as both sides of the metal conductive sheet 30, to be exposed on the surface of the molding compound 10. A wiring layer 40 is provided on at least one side of the molding compound 10 to connect the chip 20 and the metal conductive sheet 30. Figure 1 To clearly show the planar positional relationship between chip 20 and metal conductive sheet 30 on molding compound 10, other layer structures such as wiring layer 40 and first packaging layer 50 are not shown. The following... Figure 3 same.

[0040] For example, such as Figure 2 As shown, chip 20 is a single-sided electrode chip. A conductive terminal 21 is preset on the front side of the single-sided electrode chip. A wiring layer 40 is provided on the front side of the molding compound 10. The wiring layer 40 connects the front side of chip 20 with the upper surface of the metal conductive sheet 30. The entire molding compound 10 after connection is then encapsulated, including providing a first encapsulation layer 50 on one side of the molding compound 10 corresponding to the front side of chip 20, and providing a second encapsulation layer 60 on one side of the molding compound 10 corresponding to the back side of chip 20.

[0041] It should be noted that, based on its structure and function, chip 20 is divided into single-sided electrode chips and double-sided electrode chips. A single-sided electrode chip refers to a chip 20 where the electrode is located on one side, and the other side has no electrode. For a single-sided electrode chip, wiring is only required on the side with the electrode. However, for a double-sided electrode chip, electrodes are located on both the front and back sides of the chip 20. Therefore, wiring is required on both sides of the double-sided electrode chip. In this case, wiring layers 40 need to be provided on both the front and back sides of the molding compound 10 corresponding to the chip 20, followed by the first encapsulation layer 50 and the second encapsulation layer 60. Since both sides of the chip 20 and both sides of the metal conductive sheet 30 are exposed on the surface of the molding compound 10, when wiring layers 40 also need to be provided on the back side of the chip 20, [the following applies]. Figure 2 The same wiring layer 40 can be provided on the back side in the same manner as shown.

[0042] In this embodiment, the thickness of the chip 20 and the metal conductive sheet 30 is not specifically limited. In fact, since the chip 20 and the metal conductive sheet 30 are embedded in the molding compound 10, the overall layer structure is inevitably thinner compared to the stacked structure. On this basis, by selecting and setting the thickness of the molding compound 10, the chip 20 and the metal conductive sheet 30 and their thickness relationship, the overall thickness of the packaging structure can be further optimized and thinned. This will be explained in detail later.

[0043] The chip double-sided interconnect packaging structure provided in this application includes a molding compound 10 and a chip 20 and a metal conductive sheet 30 embedded in the molding compound 10. The embedding method can reduce the thickness of the components stacked together in the packaging structure. The chip 20 and the metal conductive sheet 30 are spaced apart on the molding compound 10. Both sides of the chip 20 and the metal conductive sheet 30 are exposed on the surface of the molding compound 10 to facilitate electrical connection. The front side of the chip 20 is provided with a conductive terminal 21. A wiring layer 40 is provided on at least one side of the molding compound 10 to connect the front and / or back sides of the chip 20 with the metal conductive sheet 30. A first encapsulation layer 50 is provided on the side of the molding compound 10 corresponding to the front side of the chip 20, and a second encapsulation layer 60 is provided on the side of the molding compound 10 corresponding to the back side of the chip 20. The chip double-sided interconnect packaging structure of this application embodiment is prepared based on the molding compound 10. It does not require additional substrate or interconnection by drilling and setting copper pillars. Moreover, the way the chip 20 and the metal conductive sheet 30 are embedded into the molding compound 10 allows the packaging to be performed in one step, thereby simplifying the preparation process and reducing the difficulty of the process.

[0044] In one possible implementation of this application, such as Figure 3 As shown, the thickness of chip 20 is equal to the thickness of metal conductive sheet 30 and equal to the thickness of molding compound 10.

[0045] like Figure 3 As shown, the thickness of the chip 20 is set to be equal to the thickness of the metal conductive sheet 30 and the thickness of the molding compound 10. In this way, the chip 20 and the metal conductive sheet 30 can be completely embedded in the molding compound 10, and there will be no recess or protrusion on either side of the molding compound 10. At this time, the wiring layer 40 is set. On the one hand, due to the highest layer reuse rate, the molding compound 10 with embedded chip 20 and metal conductive sheet 30 can be reduced as much as possible while ensuring the function is realized. On the other hand, the wiring layer 40 can be set relatively flat, effectively improving the stability of the wiring connection.

[0046] It should be noted that the wiring layer 40 connecting the chip 20 and the metal conductive sheet 30 on the packaging structure is usually a metal conductive line layer with a specific hollow pattern. The wiring is directly related to the function to be achieved by the packaging structure and the structure of the chip 20. In this embodiment, the setting of the line pattern is not specifically limited. The wiring layer 40 mentioned in this embodiment refers to the entire area containing the hollow pattern formed by the metal conductive line.

[0047] Therefore, wiring layer 40 can be as follows: Figure 3 As shown, the wiring layer 40 covers or partially covers the area of ​​chip 20 and metal conductive sheet 30 to achieve electrical connection between chip 20 and metal conductive sheet 30, or it can be the entire layer. When the packaging structure of this embodiment includes multiple chips 20, it should be understood that the wiring layer 40 should cover the area of ​​multiple chips 20 and metal conductive sheet 30 with electrodes on that side surface, or it may also include other structural areas on that side surface that require electrical connection.

[0048] In one possible implementation of this application, such as Figure 3 As shown, the conductive end 21 is a conductive pillar, and the sum of the thickness of the chip 20 and the conductive pillar is equal to the thickness of the metal conductive sheet 30.

[0049] like Figure 3 As shown, when the conductive end 21 is a conductive post, the conductive post itself also has a certain height, which will affect the overall thickness of the chip 20. Therefore, when the conductive end 21 is a conductive post, the sum of the thickness of the chip 20 and the conductive post is defined to be equal to the thickness of the metal conductive sheet 30 and the molding compound 10. When installing the wiring layer 40, it is sufficient to make the wiring layer 40 and the conductive post of the chip 20 conduct, which can also make the wiring layer 40 relatively flat and the wiring connection stable.

[0050] In one possible implementation of this application, such as Figure 4As shown, the conductive terminal 21 of the chip 20 is exposed on the surface of the first encapsulation layer 50, and / or the back side of the chip 20 is exposed on the surface of the second encapsulation layer 60.

[0051] like Figure 4 As shown, on the upper surface of chip 20, the first encapsulation layer 50 can be thinned until the conductive end 21 is exposed on the upper surface of the first encapsulation layer 50. At the same time, the metal conductive sheet 30 can also be exposed on the upper surface of the first encapsulation layer 50. In this way, better heat dissipation can be achieved for chip 20 through the upper surface of chip 20. If the upper surface of the metal conductive sheet 30 is also exposed after the first encapsulation layer 50 is thinned, the metal conductive sheet 30 can also achieve the corresponding heat dissipation function.

[0052] The lower surface of chip 20 can also be exposed to improve heat dissipation by exposing the encapsulation layer. On the lower surface of chip 20, openings can be formed on the second encapsulation layer 60 at positions corresponding to chip 20 by etching, exposing the lower surface of chip 20. This is particularly beneficial for high-power chips 20, which generate significant heat during operation. The exposed upper and lower surfaces effectively enhance the heat dissipation capacity of chip 20, extending its lifespan. In some applications, electrode metal can be sputtered onto the exposed lower surface of chip 20 after etching and etched to form electrode PADs. The electrode PADs themselves have good thermal conductivity and heat dissipation capabilities, and their placement ensures the encapsulation function of the package structure. Furthermore, when applied to electronic devices, the electrode PADs facilitate connection to the PCB.

[0053] In one possible implementation of this application, such as Figure 4 As shown, the conductive terminal 21 of the chip 20 is flush with the surface of the first encapsulation layer 50, and / or the back surface of the chip 20 is flush with the surface of the second encapsulation layer 60.

[0054] Taking the front side of chip 20 with conductive terminal 21 as an example, such as Figure 4 As shown, by setting the thickness relationship, the conductive end 21 of the chip 20 is flush with the surface of the first encapsulation layer 50. In this way, the top of the conductive end 21 can be exposed to make electrical connection with external circuits or external components. At the same time, the entire chip 20 is covered by the sealing area of ​​the molding compound 10, the first encapsulation layer 50, and the second encapsulation layer 60, which protects the chip 20 from contact with external moisture and impurities, and improves the working stability and service life of the chip 20.

[0055] In one possible implementation of this application, such as Figure 5 As shown, the metal conductive sheet 30 is rectangular, with grooves recessed inward on all four sides. A through hole is formed in the center of the rectangle.

[0056] For example, the metal conductive sheet 30 can be a copper sheet. The length and width of the rectangle can be set within the range of 5-10mm. Inwardly recessed grooves are machined on the four sides of the rectangle to increase the perimeter of the edge of the metal conductive sheet 30, thereby increasing the contact area between the metal conductive sheet 30 and the molding compound 10, thus increasing the bonding force between the metal conductive sheet 30 and the molding compound 10 and improving the stability of the metal conductive sheet 30.

[0057] For example, a hollowed-out portion can be made in the center of the metal conductive sheet 30. On the one hand, this reduces material costs while ensuring the conductive function of the metal conductive sheet 30. On the other hand, the through hole in the center can also help increase the contact area between the metal conductive sheet 30 and the molding compound 10, thereby increasing the bonding force between them. Moreover, the design of recessed grooves and through holes is not complicated in terms of processing technology and will not affect production efficiency or production volume.

[0058] Of course, the embodiments of this application are not limited to this. Based on the purpose of increasing the bonding force between the metal conductive sheet 30 and the molding compound 10, those skilled in the art can also design other processing forms based on the above ideas on the metal conductive sheet 30, or make additional processing on this basis.

[0059] In one feasible embodiment of this application, the length of the rectangle is greater than or equal to 0.5 mm; and / or, the width of the rectangle is greater than or equal to 0.5 mm.

[0060] Considering that the metal conductive sheet 30 needs to achieve stable connection between chips 20, if the size of the metal conductive sheet 30 is too small, the point connection of the metal conductive sheet 30 may be unstable due to processing errors or other reasons. Therefore, the length and width of the rectangular metal conductive sheet 30 are required to be greater than or equal to 0.5 mm.

[0061] Based on this consideration, those skilled in the art should know that in the selection and design of the processing forms such as grooves on the aforementioned metal conductive sheet 30, it should also be considered to avoid the local size of the processed metal conductive sheet 30 being too small.

[0062] In this embodiment, the metal conductive sheet 30 only needs to be set as a sheet-like structure. Meeting the above-mentioned basic size requirements can realize the electrode connection of the chip 20. The metal conductive sheet 30 can play a conductive role through the two opposite sides of the molding compound 10. Moreover, the thickness of the sheet-like structure of the metal conductive sheet 30 can also be specifically set as needed. In general, in order to avoid increasing the thickness of the packaging structure, the thickness of the metal conductive sheet 30 can be set to be equivalent to the thickness of the chip 20 and the molding compound 10. The simplified structure can replace the existing technology that requires processing through holes on the substrate and electroplating copper pillars to achieve interconnection.

[0063] In one possible implementation of this application, such as Figure 6 As shown, the chip 20 includes multiple chips, which are spaced apart and arranged around the metal conductive sheet 30.

[0064] like Figure 6 As shown, the chip double-sided interconnect package structure includes three chips 20 and a metal conductive sheet 30 disposed on the molding compound 10. The three chips 20 are distributed at intervals around the metal conductive sheet 30. Through this planar design, the distance difference between the three chips 20 and the metal conductive sheet 30 is not large. In this way, the length of the wires on the wiring layer 40 between any chip 20 and the metal conductive sheet 30 is relatively equal and not too long. Thus, the problem of large parasitic inductance caused by excessive wire length on the wiring layer 40 is effectively avoided.

[0065] In one feasible embodiment of this application, the chip 20 includes a first chip with a single-sided electrode and a second chip with a double-sided electrode. Wiring layers 40 are respectively provided on both sides of the molding compound 10 to connect the front and back sides of the chip 20 with the metal conductive sheet 30. When there are multiple second chips, the distance between two adjacent second chips is less than or equal to the distance between the second chip and the first chip, and less than or equal to the distance between the second chip and the metal conductive sheet 30.

[0066] For the second chip with double-sided electrodes, it needs to be connected to the metal conductive sheet 30 through wiring layer 40 on both the front and back sides of the second chip. Therefore, when there are multiple second chips, on the front side, the first chip and the second chip, as well as two adjacent second chips, need to be connected through wiring layer 40. On the back side, only the multiple second chips with double-sided electrodes need to be connected through wiring layer. Therefore, setting the spacing between two adjacent second chips to be less than or equal to the distance between the second chip and the first chip is more conducive to the overall layout of the package structure, saves the laying range of wiring layer 40, saves materials, and reduces the occurrence of wiring disconnection.

[0067] Another aspect of this application provides a method for fabricating a chip double-sided interconnect packaging structure, such as... Figure 7 As shown, the preparation method includes:

[0068] S101. Chips 20 and metal conductive sheets 30 are attached to the pyrolysis film at intervals, wherein the side of chip 20 exposed on the surface of the pyrolysis film has a pre-set conductive end 21, and chip 20 is molded.

[0069] S102. The side of the pyrolytic film with the chip 20 and the metal conductive sheet 30 is attached to the molding compound 10 and thermoformed.

[0070] S103. Remove the pyrolysis film, and transfer the chip 20 and the metal conductive sheet 30 onto the molding compound 10, with the back of the chip 20 and the surface of the metal conductive sheet 30 exposed on the molding compound 10.

[0071] S104. A passivating adhesive is spin-coated onto the back of the exposed chip 20 and the surface of the metal conductive sheet 30 on the molding compound 10 and cured to form a second encapsulation layer 60.

[0072] S105, the other side of the molding compound 10 is thinned to expose the side of the chip 20 where the conductive end 21 is provided and the surface of the exposed metal conductive sheet 30.

[0073] S106. Rewire the side of the chip 20 where the conductive terminal 21 is provided to interconnect the conductive terminal 21 of the chip 20 with the metal conductive sheet 30.

[0074] S107. Spin-coat passivating adhesive onto the thinned side of the molding compound 10 and cure it to form the first encapsulation layer 50.

[0075] S108, Electrode metal is sputtered onto the first encapsulation layer 50 and etched to form an electrode panel.

[0076] like Figure 7 As shown, the chip double-sided interconnect package structure is prepared using the preparation method of the embodiment of this application. First, the chip 20 and the metal conductive sheet 30 are attached to the pyrolysis film at a preset interval position. The back side of the chip 20 is attached to the pyrolysis film so that the conductive end 21 of the front side of the chip 20 is exposed on the surface of the pyrolysis film. Molding is performed from the front side of the chip 20.

[0077] Then, the pyrolytic film is attached to one side of the chip 20 and the metal conductive sheet 30 onto the molding compound 10 and heated. Heating causes the pyrolytic film to separate from the chip 20 and the metal conductive sheet 30. At the same time, heating also causes the front side of the chip 20 and the metal conductive sheet 30 to be thermoformed with the molding compound 10. During the heating process, the front side of the chip 20 and the metal conductive sheet 30 are embedded in the molding compound 10, thus forming a state in which they are embedded in the molding compound 10.

[0078] After the pyrolysis film is removed, the chip 20 and the metal conductive sheet 30 are transferred onto the molding compound 10. The front side of the chip 20 is fixed inside the molding compound 10, while the back side of the chip 20 and the other side of the metal conductive sheet 30 are exposed on the surface of the molding compound 10.

[0079] Passivating adhesive is spin-coated onto the surfaces of the chip 20 and the metal conductive sheet 30 on the molding compound 10. Passivating adhesive is also applied to the exposed back side of the chip 20 and the surface of the metal conductive sheet 30. The passivating adhesive is then cured, forming the second encapsulation layer 60. Typically, the thickness of the second encapsulation layer 60 is less than or equal to 10 micrometers to avoid affecting heat dissipation from the back side of the chip 20.

[0080] The other side of the molding compound 10 is thinned until the conductive terminal 21 on the front side of the chip 20 and the surface of the metal conductive sheet 30 are exposed. The front side of the chip 20 is then rewired to interconnect the conductive terminal 21 of the chip 20 with the metal conductive sheet 30. After interconnection, the front side of the chip 20 is interconnected. When the package structure includes multiple chips 20, the wiring layer 40 provides electrical connections between the front sides of the multiple chips 20 and between the chip 20 and the surface of the metal conductive sheet 30 on the front side.

[0081] Next, a passivating adhesive is spin-coated onto the surface of the molding compound 10 after the wiring layer 40 is formed to achieve interconnection, and then cured to form a first encapsulation layer 50 on one side of the front of the chip 20. In this way, the surface encapsulation of the chip's double-sided interconnect structure is completed.

[0082] Finally, electrode metal is sputtered onto the first packaging layer 50 and etched to form an electrode panel, which is used to bring out the double-sided interconnect package structure of the chip and electrically connect it to the PCB board through the electrode panel.

[0083] The chip double-sided interconnect package structure of this application embodiment is fabricated using this method. The entire fabrication process does not require the introduction of a substrate. Firstly, it eliminates the need for a substrate to increase the thickness of the package structure. The thickness of the package structure can be determined by setting the thickness of the chip 20 and the metal conductive sheet 30, as well as the thickness of the thinned molding compound 10. This allows the thickness of the entire package structure to be compressed to within 300 micrometers. The reduced thickness also effectively improves the dissipation speed of heat generated by the chip 20 during operation, thus improving the heat dissipation capacity of the chip 20. The design of the metal conductive sheet 30 eliminates the need for drilling holes in the substrate and then electroplating copper pillars, simplifying the fabrication process, reducing costs, and avoiding the influence of the copper pillar height on the thickness of the package structure. Furthermore, in the fan-out structure, this application embodiment encapsulates the chip 20 and the metal conductive sheet 30 together, saving process steps compared to the prior art of drilling holes, electroplating copper pillars, and then encapsulating.

[0084] In one feasible embodiment of this application, chip 20 includes a first chip with a single-sided electrode and a second chip with a double-sided electrode. S104, before spin-coating passivating adhesive onto the back side of the molding compound 10 exposed to the metal conductive sheet 30 and curing it to form the second encapsulation layer 60, as... Figure 8 As shown, the preparation method also includes:

[0085] S201. Rewire the chip 20 and the metal conductive sheet 30 to interconnect the back side of the chip 20 with the metal conductive sheet 30.

[0086] like Figure 8 As shown, when chip 20 includes a first chip with a single-sided electrode and a second chip with a double-sided electrode, before forming the second encapsulation layer 60 on the back side of the molding compound 10, the chip 20 and the metal conductive sheet 30 are redistributed on the back side of the molding compound 10. This allows the back side of the second chip with the double-sided electrode to be interconnected with the back side of other second chips and with the surface of the metal conductive sheet 30 on that side via the wiring layer 40. At this time, the electrodes on the back side of the second chip are also double-sided interconnected with the front side of chip 20 via the metal conductive sheet 30.

[0087] In one possible implementation of this application, such as Figure 9 As shown, S104, spin-coating passivating adhesive onto the back side of the exposed chip 20 and the surface of the metal conductive sheet 30 on the molding compound 10 and curing it to form the second encapsulation layer 60 includes:

[0088] S1041. Spin-coat passivating adhesive onto the back of the exposed chip 20 and the surface of the metal conductive sheet 30 on the molding compound 10.

[0089] S1042. Photolithography is performed on the passivation adhesive at the position corresponding to chip 20 to expose the back side of chip 20.

[0090] S1043. Curing passivating adhesive to form a second encapsulation layer 60 with a window exposing the back side of the chip 20.

[0091] like Figure 9 As shown, the second encapsulation layer 60 on the back of the molding compound 10 specifically includes: firstly, spin coating a passivating adhesive onto the back of the molding compound 10. The passivating adhesive is in a gel state before curing and has a certain degree of fluidity. The spin coating method can completely seal the passivating adhesive on the surface of the back side of the molding compound 10, and at the same time, it can also make the thickness of the passivating adhesive layer smaller.

[0092] Then, the passivation adhesive is removed from the surface of the passivation adhesive at the location corresponding to chip 20 using photolithography, thereby exposing the back side of chip 20. In this way, the back side of chip 20 can be directly exposed, which is equivalent to providing a new direct heat dissipation window for chip 20. Especially for high-power chip 20, the back side of chip 20 directly exposed through this window has better heat dissipation capacity and effect.

[0093] Finally, the passivation adhesive with the photolithographic openings is cured to form a second encapsulation layer 60 with a window exposing the back side of the chip 20.

[0094] It should be noted that the purpose of photolithography to form the window is to improve the heat dissipation capacity of the back side of chip 20. If the power of chip 20 is not high, the window may not be set. Alternatively, the passivation adhesive may simply be thinned at the position corresponding to chip 20, which can also improve the heat dissipation capacity of the back side of chip 20 to a certain extent.

[0095] In one possible implementation of this application, such as Figure 10 As shown, S107, spin-coating passivating adhesive onto the thinned side of the molding compound 10 and curing it to form the first encapsulation layer 50 includes:

[0096] S1071. Spin-coat passivating adhesive onto the thinned side of the molding compound 10.

[0097] S1072. Photolithography is performed on the passivation adhesive at the position corresponding to the chip 20 to expose the working area of ​​the chip 20, wherein the working area includes the surface of the chip 20, or the working area includes the preset conductive terminal 21 on the chip 20.

[0098] S1073. Curing passivating adhesive to form a first encapsulation layer 50 with a window exposing the working area of ​​the chip 20.

[0099] like Figure 10 As shown, setting the first encapsulation layer 50 on the front side of the molding compound 10 specifically includes: firstly, spin-coating passivating adhesive onto the front side of the molding compound 10; then, photolithographically removing the passivating adhesive at the position corresponding to the chip 20 to expose the working area of ​​the chip 20 covered by the passivating adhesive. Exposing the working area of ​​the chip 20 also aims to improve heat dissipation by creating a direct heat dissipation window on the front side of the chip 20. Therefore, those skilled in the art can specifically define the working area based on the actual function and heat generation of the selected chip 20. For example, the working area can at least include the surface of the chip 20. Typically, the surface of the chip 20 generates heat to varying degrees during operation. Exposing the entire chip through a window significantly improves heat dissipation, especially for high-power chips and chips with high heat generation. Alternatively, for conventional chips 20 or chips 20 with low heat dissipation requirements, the working area can also only include the pre-set conductive terminal 21 on the chip 20, meaning that the heat dissipated by the chip 20 during operation can be dissipated through the conductive terminal 21.

[0100] In one feasible embodiment of this application, the thickness of the chip 20 is equal to the thickness of the metal conductive sheet 30, and equal to the thickness of the plastic molding compound 10 after thinning.

[0101] Please refer to Figure 3As shown, when the thickness of chip 20 is equal to the thickness of metal conductive sheet 30, and chip 20 and metal conductive sheet 30 are spaced apart in the molding compound 10, their equal thickness means that chip 20 does not need to increase its thickness due to the interconnect structure. Since chip 20 is also equal to the reduced thickness of molding compound 10, molding compound 10 will not increase its structural thickness. The packaging structure only needs to retain the necessary thickness of chip 20 itself; other structures are arranged on the same plane as chip 20 and have the same thickness, maximizing space utilization. Furthermore, metal conductive sheet 30 is arranged on the same plane near chip 20. Through the wiring layer 40 on the front side of chip 20, or even the back side of chip 20, the front side of chip 20 can be interconnected with the surface of metal conductive sheet 30, and the back side of chip 20 can also be interconnected with the surface of metal conductive sheet 30. Due to the conductivity of metal conductive sheet 30 itself, chip 20 achieves double-sided interconnection. Based on this, by packaging from the front and back sides separately, the thickness of the entire packaging structure is reduced to the maximum extent.

[0102] Furthermore, the method for fabricating the chip double-sided interconnect packaging structure in this application embodiment not only enables the fabrication of the thinnest possible packaging structure, but also significantly simplifies the fabrication process. First, it eliminates the need for an additional substrate, thus avoiding the influence of the substrate's thickness on the overall thickness of the packaging structure. Second, it eliminates the need for drilling and electroplating copper pillars to achieve double-sided interconnection, simplifying the fabrication process and improving the stability of the interconnection. Third, by placing the chip 20 and the metal conductive sheet 30 in a flat layer and encapsulating them together, it not only improves the conductivity stability of the metal conductive sheet 30, but also simplifies the packaging process.

[0103] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for fabricating a chip double-sided interconnect packaging structure, characterized in that, The preparation method includes: Chips and metal conductive sheets are spaced together on a pyrolysis film, wherein the side of the chip exposed on the surface of the pyrolysis film has a pre-set conductive end, and the chip is molded. The side of the pyrolysis film with the chip and the metal conductive sheet attached is bonded to a molding compound and thermoformed. After removing the pyrolysis film, the chip and the metal conductive sheet are transferred to the molding compound, with the back side of the chip and the surface of the metal conductive sheet exposed on the molding compound. A passivating adhesive is spin-coated onto the back of the exposed chip and the surface of the metal conductive sheet on the molding compound board and cured to form a second encapsulation layer; The other side of the molding compound is thinned to expose the side of the chip where the conductive end is located and the surface of the metal conductive sheet. Rewire the side of the chip where the conductive terminal is located to interconnect the conductive terminal of the chip with the metal conductive sheet; A passivating adhesive is spin-coated onto the thinned side of the molding compound and cured to form a first encapsulation layer; Electrode metal is sputtered onto the first encapsulation layer and etched to form an electrode panel.

2. The preparation method according to claim 1, characterized in that, The chip includes a first chip with a single-sided electrode and a second chip with a double-sided electrode. Before spin-coating passivating adhesive onto the back side of the molding compound exposed by the chip and the surface of the metal conductive sheet and curing it to form the second encapsulation layer, the preparation method further includes: Rewiring is performed on the chip and the metal conductive sheet to interconnect the back side of the chip with the metal conductive sheet.

3. The preparation method according to claim 1, characterized in that, The step of spin-coating passivating adhesive onto the back side of the exposed chip and the surface of the metal conductive sheet on the molding compound and curing it to form a second encapsulation layer includes: Passivating adhesive is spin-coated onto the back of the exposed chip and the surface of the metal conductive sheet on the molding compound plate; Photolithography is performed on the passivation adhesive at the positions corresponding to the chip to expose the back side of the chip; The passivation adhesive is cured to form a second encapsulation layer with a window exposing the back side of the chip.

4. The preparation method according to claim 1, characterized in that, The step of spin-coating passivating adhesive onto the thinned side of the molding compound and curing it to form the first encapsulation layer includes: A passivating adhesive is spin-coated onto the thinned side of the molding compound plate; Photolithography is performed on the passivation adhesive at the position corresponding to the chip to expose the working area of ​​the chip, wherein the working area includes the surface of the chip, or the working area includes a pre-set conductive terminal on the chip; The passivation adhesive is cured to form a first encapsulation layer with a window exposing the working area of ​​the chip.

5. The preparation method according to claim 1, characterized in that, The thickness of the chip is equal to the thickness of the metal conductive sheet, and equal to the thickness of the thinned molding compound.

6. A chip double-sided interconnect packaging structure, characterized in that, The chip double-sided interconnect package structure is prepared using the fabrication method of any one of claims 1 to 5. The chip double-sided interconnect package structure includes a molding compound and a chip and a metal conductive sheet embedded in the molding compound. The chip and the metal conductive sheet are spaced apart. Both sides of the chip and the metal conductive sheet are exposed on the surface of the molding compound. A conductive terminal is pre-set on the front side of the chip. A wiring layer is provided on at least one side of the molding compound to connect the front and / or back sides of the chip with the metal conductive sheet. A first encapsulation layer is provided on the side of the molding compound corresponding to the front side of the chip, and a second encapsulation layer is provided on the side of the molding compound corresponding to the back side of the chip.

7. The chip double-sided interconnect packaging structure according to claim 6, characterized in that, The thickness of the chip is equal to the thickness of the metal conductive sheet and the thickness of the molding compound.

8. The chip double-sided interconnect packaging structure according to claim 6, characterized in that, The conductive end is a conductive pillar, and the sum of the thickness of the chip and the conductive pillar is equal to the thickness of the metal conductive sheet.

9. The chip double-sided interconnect packaging structure according to any one of claims 6-8, characterized in that, The conductive terminals of the chip are exposed on the surface of the first encapsulation layer, and / or the back side of the chip is exposed on the surface of the second encapsulation layer.

10. The chip double-sided interconnect packaging structure according to claim 9, characterized in that, The conductive terminals of the chip are flush with the surface of the first encapsulation layer, and / or the back surface of the chip is flush with the surface of the second encapsulation layer.

11. The chip double-sided interconnect packaging structure according to any one of claims 6-8, characterized in that, The metal conductive sheet is rectangular, and each of the four sides of the rectangle has an inwardly recessed groove.

12. The chip double-sided interconnect packaging structure according to claim 11, characterized in that, A through hole is provided at the center of the rectangle.

13. The chip double-sided interconnect packaging structure according to claim 11, characterized in that, The length of the rectangle is greater than or equal to 0.5 mm; and / or, the width of the rectangle is greater than or equal to 0.5 mm.

14. The chip double-sided interconnect packaging structure according to claim 6, characterized in that, The chip comprises multiple chips, which are spaced apart and arranged around the metal conductive sheet.

15. The chip double-sided interconnect packaging structure according to claim 14, characterized in that, The chip includes a first chip with a single-sided electrode and a second chip with a double-sided electrode. Wiring layers are respectively provided on both sides of the molding compound to connect the front and back sides of the chip with the metal conductive sheet. When there are multiple second chips, the distance between two adjacent second chips is less than or equal to the distance between the second chip and the first chip, and less than or equal to the distance between the second chip and the metal conductive sheet.

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