Electronic module and electronic device

Abstract

The present disclosure relates to electronic modules and electronic devices. An electronic module includes a wiring board having a first major surface and a second major surface on a back side of the first major surface, and a first semiconductor element and a second semiconductor element mounted on the wiring board. The first semiconductor element includes a first signal terminal and a second signal terminal. The second semiconductor element includes a third signal terminal and a fourth signal terminal. The wiring board includes a first signal line including a first signal trace disposed in a first conductor layer, a second signal line including a second signal trace disposed in a second conductor layer closer to the second major surface than the first conductor layer, a first ground trace disposed in the first conductor layer, and a second ground trace disposed in the second conductor layer.

Description

Technical Field

[0001] This disclosure relates to electronic modules and electronic devices. Background Technology

[0002] As an example of an electronic module incorporated into an electronic device, Japanese Patent Publication No. 2016-213340 discloses a control device comprising a control circuit, a Double Data Rate 3 (DDR3) memory, and a control board on which the control circuit and the DDR3 memory are disposed. The control circuit and the DDR3 memory are typically each composed of semiconductor components. The control circuit includes multiple signal terminals through which address signals can be transmitted, and the DDR3 memory includes multiple signal terminals through which address signals can be received. The multiple signal terminals of the control circuit and the multiple signal terminals of the DDR3 memory are electrically connected to each other in a one-to-one relationship via signal lines on the control board. Summary of the Invention

[0003] According to one aspect of the invention, an electronic module includes a wiring board having a first main surface and a second main surface behind the first main surface, and a first semiconductor element and a second semiconductor element mounted on the wiring board. At least one of the first semiconductor element or the second semiconductor element is disposed on one side of the first main surface. The first semiconductor element includes a first signal terminal and a second signal terminal. The second signal terminal is closer to the second semiconductor element than the first signal terminal. The second semiconductor element includes a third signal terminal and a fourth signal terminal. The fourth signal terminal is closer to the first semiconductor element than the third signal terminal. The wiring board includes: a first signal line configured to electrically interconnect a second signal terminal and a third signal terminal and including a first signal trace disposed in a first conductor layer; a second signal line configured to electrically interconnect a first signal terminal and a fourth signal terminal and including a second signal trace disposed in a second conductor layer closer to a second main surface than the first conductor layer; a first ground trace disposed in the first conductor layer and extending along the first signal trace such that the first signal trace is located between two portions of the first ground trace in the width direction of the first signal trace; and a second ground trace disposed in the second conductor layer and extending along the second signal trace such that the second signal trace is located between two portions of the second ground trace in the width direction of the second signal trace.

[0004] Further features of the invention will become clear from the following description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0005] Figure 1A This is a front view of an image forming device according to a first embodiment, which serves as an example of an electronic device.

[0006] Figure 1BThis is a side view of the image forming apparatus according to the first embodiment.

[0007] Figure 2 This is an explanatory diagram of the control module according to the first embodiment.

[0008] Figure 3A This is a plan view of a portion of the control module according to the first embodiment.

[0009] Figure 3B This is a cross-sectional view of the control module according to the first embodiment.

[0010] Figure 3C This is a cross-sectional view of the printed wiring board according to the first embodiment.

[0011] Figure 4 This is a plan view of the terminal layout of the memory device according to the first embodiment.

[0012] Figure 5A This is a plan view of the wiring structure in a portion of the first outer layer of the printed wiring board according to the first embodiment.

[0013] Figure 5B This is a plan view of the wiring structure in a portion of the first inner layer of the printed wiring board according to the first embodiment.

[0014] Figure 5C This is a plan view of the wiring structure in a portion of the second outer layer of the printed wiring board according to the first embodiment.

[0015] Figure 6A This is a plan view of a portion of the control unit according to the first embodiment.

[0016] Figure 6B This is a plan view of a portion of the control unit according to a modified example of the first embodiment.

[0017] Figure 7 This is a cross-sectional view of the printed wiring board according to the second embodiment.

[0018] Figure 8 This is a cross-sectional view of the printed wiring board according to the third embodiment.

[0019] Figure 9A This is a plan view of a portion of the control module according to the fourth embodiment, which serves as an example of an electronic module.

[0020] Figure 9B This is a cross-sectional view of the control module according to the fourth embodiment.

[0021] Figure 9C This is a cross-sectional view of the printed wiring board according to the fourth embodiment.

[0022] Figure 10AThese are cross-sectional views of the three printed wiring boards in Example 4-2.

[0023] Figure 10B This is a graph of the characteristic impedance of Example 4-2.

[0024] Figure 10C This is a graph of the crosstalk coefficients in Example 4-2.

[0025] Figure 11A This is a plan view of a portion of the control module according to the fifth embodiment, which serves as an example of an electronic module.

[0026] Figure 11B This is a cross-sectional view of the control module according to the fifth embodiment.

[0027] Figure 11C This is a cross-sectional view of the printed wiring board according to the fifth embodiment.

[0028] Figure 12A This is a floor plan of a portion of the control module in the comparative example.

[0029] Figure 12B This is a cross-sectional view of the control module in the comparative example.

[0030] Figure 12C This is a cross-sectional view of a comparative example printed wiring board. Detailed Implementation

[0031] Recently, with the demand for miniaturization of electronic devices, there is a need for miniaturization of electronic modules installed in these devices. Along with the miniaturization of electronic modules, signal quality degradation has become a problem, and improvements in signal quality are desired.

[0032] This disclosure is intended to provide an electronic module that improves signal quality and achieves miniaturization.

[0033] Exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0034] First Embodiment

[0035] Figure 1A This is a front view of an image forming apparatus 100 according to a first embodiment, which serves as an example of an electronic device. Figure 1BThis is a side view of an image forming apparatus 100 according to a first embodiment. The image forming apparatus 100 is a digital device of an electrophotographic system such as a printer, copier, fax machine, or multifunction device. The image forming apparatus 100 includes a housing 101, a sheet transport mechanism (not shown), an image forming section 120 that forms an image on a sheet transported by the sheet transport mechanism, and a control module 110 that controls the image forming section 120. The image forming section 120, the control module 110, and the sheet transport mechanism (not shown) are disposed within the housing 101. The image forming section 120 includes a photosensitive drum, a charging section, a developing section, a transfer section, a fixing section, etc., which are not shown.

[0036] The control module 110 is an example of an electronic module and is constructed from a printed circuit board. The control module 110 receives image data from an external device via an interface such as a local area network (LAN) or a universal serial bus (USB). Furthermore, the control module 110 processes the received image data and controls the image forming section 120 to form an image on a sheet.

[0037] Figure 2 This is an explanatory diagram of the control module 110 according to the first embodiment. The control module 110 includes a memory controller 130, which serves as an example of a first semiconductor element, and a memory device 140, which serves as an example of a second semiconductor element. Furthermore, the control module 110 includes connectors 150, 151, and 152, a conversion chip 160, and a printed wiring board 200. The memory controller 130, the memory device 140, the connectors 150, 151, and 152, and the conversion chip 160 are mounted on the printed wiring board 200. The printed wiring board 200 is a rigid printed wiring board.

[0038] Memory device 140 is either Double Data Rate 3 Synchronous Dynamic Random Access Memory (DDR3 SDRAM) or Double Data Rate 4 Synchronous Dynamic Random Access Memory (DDR4 SDRAM), with DDR4 SDRAM being preferred. LAN cable 170 is attached to connector 150 and receives image data from an external device via LAN cable 170. Conversion chip 160 processes the image data received by connector 150 and outputs the processed image data to memory controller 130. Memory controller 130 stores image data in memory device 140 and reads image data stored in memory device 140. Memory controller 130 outputs image data to connectors 151 and 152 and transmits image data to... Figure 1A The image forming portion 120 shown is connected to connectors 151 and 152 via a cable (not shown).

[0039] The memory controller 130 and the memory device 140 are each configured in a single semiconductor package. The printed wiring board 200 includes a bus wiring 210 consisting of multiple wirings that serve as communication paths for signals transmitted between the memory controller 130 and the memory device 140.

[0040] The memory controller 130 and the memory device 140 transmit data signals representing image data via data lines included in the bus wiring 210. Furthermore, the memory controller 130 stores and deletes data in the memory device 140 by transmitting data address signals and command signals to the memory device 140 via signal lines included in the bus wiring 210. The memory system includes the memory controller 130, the memory device 140, and the printed wiring board 200.

[0041] Figure 3A This is a plan view of a portion of the control module 110 according to the first embodiment. The memory controller 130 and the memory device 140 are both deployed on the main surface 201, one of the two main surfaces 201 and 202 of the printed circuit board 200. Main surface 201 serves as an example of a first main surface. Main surface 202 serves as an example of a second main surface. Main surface 202 is the main surface on the back side of main surface 201. Main surfaces 201 and 202 are substantially parallel. The direction perpendicular to main surfaces 201 and 202 will be referred to as the Z-direction. The Z-direction also serves as the thickness direction, i.e., the stacking direction of the printed circuit board 200. The two directions intersecting the Z-direction will be referred to as the X-direction and the Y-direction. The X-direction and the Y-direction intersect each other. The X-direction, Y-direction, and Z-direction are preferably orthogonal to each other. The memory controller 130 and the memory device 140 are deployed on the printed circuit board 200 so as not to overlap each other when viewed from the Z-direction.

[0042] Viewed from the Z-direction, both the memory controller 130 and the memory device 140 have a rectangular shape. Viewed from the Z-direction, the memory controller 130 is larger than the memory device 140.

[0043] In the first embodiment, the memory controller 130 and the memory device 140 are deployed on the printed wiring board 200 opposite each other in the X direction, such that the edges 131 of the memory controller 130 and 141 of the memory device 140 are parallel to each other when viewed from the Z direction. When viewed from the Z direction, edge 141 of the memory device 140 is the longer edge; that is, edge 141 extends in the Y direction. In the first embodiment, the X direction also acts as the shorter direction of the memory device 140, and the Y direction also acts as the longitudinal direction of the memory device 140.

[0044] It should be noted that components such as capacitors (not shown) and resistors (not shown) can be mounted on each of the main surfaces 201 and 202.

[0045] Figure 3B This is a cross-sectional view of the control module 110 according to the first embodiment. Figure 3B Schematic illustration along Figure 3A The control module 110 is shown as a cross section intercepted by line IIIB-IIIB. Figure 3C This is a cross-sectional view of the printed wiring board 200 according to the first embodiment. Figure 3C Schematic illustration along Figure 3B The cross section of the printed wiring board 200 cut by line IIIC-IIIC.

[0046] The printed wiring board 200 includes an insulating substrate and conductive wiring. The substrate is formed of an insulator such as epoxy resin. The wiring is formed of a conductor such as copper. In a first embodiment, the printed wiring board 200 is a through-hole board. By using a through-hole board as the printed wiring board 200, productivity can be high and manufacturing costs can be low.

[0047] The printed wiring board 200 is a laminate comprising at least four conductor layers L1 to L4. The conductor layers L1 to L4 are arranged at intervals in the Z direction. An insulating material, i.e., an insulating layer, is disposed in each gap between the conductor layers L1 to L4. The conductor layers L1 to L4 are arranged from the main surface 201 toward the main surface 202 in the order of conductor layer L1, conductor layer L2, conductor layer L3, and conductor layer L4.

[0048] Conductor layer L1 is disposed on the main surface 201, which serves as a mounting surface. Conductor layer L1 is an example of a first outer layer. Conductor layer L4 is disposed on the main surface 202, which serves as a mounting surface. Conductor layer L4 is an example of a second outer layer. Conductor layer L2 is an example of a first inner layer deployed inside the printed wiring board 200. Conductor layer L3 is an example of a second inner layer deployed inside the printed wiring board 200. Conductor layer L3 exists between conductor layer L2 and conductor layer L4 (i.e., the main surface 202). Therefore, conductor layer L3 is positioned further away from the main surface 201 than conductor layer L2.

[0049] It should be noted that solder resist (not shown) can be applied to conductor layer L1. Additionally, solder resist (not shown) can also be applied to conductor layer L4. Conductor patterns constituting wiring are provided in each of the conductor layers L1 to L4 of the printed wiring board 200. The printed wiring board 200 is provided with through-holes penetrating conductor layers L1 to L4 and constituting wiring. The through-holes are conductors disposed within the through-holes.

[0050] The memory controller 130 is bonded to the printed circuit board 200 via, for example, solder. The memory device 140 is bonded to the printed circuit board 200 via, for example, solder. The memory controller 130 and the memory device 140 each have a ball grid array (BGA) or interconnect disk grid array (LGA) package structure and include a plurality of terminals arranged in the array. The memory controller 130 and the memory device 140 each include a plurality of signal terminals, a plurality of power terminals, and a plurality of ground terminals.

[0051] The data terminals of the memory controller 130 and the memory device 140 are electrically interconnected via data lines (not shown) on the printed wiring board 200. Due to improvements in the functionality of the image forming apparatus 100 as an electronic device, large amounts of data can be processed.

[0052] The memory controller 130 includes a plurality of signal terminals 11 and a plurality of signal terminals 12 that are closer to the memory device 140 than each of the plurality of signal terminals 11. The memory device 140 includes a plurality of signal terminals 13 and a plurality of signal terminals 14 that are closer to the memory controller 130 than each of the plurality of signal terminals 13. Focusing on one of the plurality of signal terminals 11, one of the plurality of signal terminals 12, one of the plurality of signal terminals 13, and one of the plurality of signal terminals 14, signal terminal 12 is closer to the memory device 140 than signal terminal 11, and signal terminal 14 is closer to the memory controller 130 than signal terminal 13. It should be noted that in Figure 3B In the diagram, each of signal terminals 11 and 14 is indicated by a vertical shading. Furthermore, in... Figure 3B In the diagram, each of signal terminals 12 and 13 is indicated by a grid of shaded areas.

[0053] Examples of signal terminals 11 each acting as a first signal terminal. Examples of signal terminals 12 each acting as a second signal terminal. Examples of signal terminals 13 each acting as a third signal terminal. Examples of signal terminals 14 each acting as a fourth signal terminal.

[0054] Signal terminals 11 and 12 of the memory controller 130 are each used to transmit address signals or command signals. Hereinafter, this signal will be referred to as an address / command signal. Signal terminals 13 and 14 of the memory device 140 are each used to receive address / command signals.

[0055] The printed wiring board 200 includes multiple signal lines S10 that electrically connect multiple signal terminals 12 of the memory controller 130 to multiple signal terminals 13 of the memory device 140 in a one-to-one relationship. Additionally, the printed wiring board 200 includes multiple signal lines S20 that electrically connect multiple signal terminals 11 of the memory controller 130 to multiple signal terminals 14 of the memory device 140 in a one-to-one relationship.

[0056] Signal lines S10 each serve as an example of a first signal line. Signal lines S20 each serve as an example of a second signal line. The wiring width of each of signal lines S10 and S20 is preferably 75 μm or greater. It should be noted that... Figure 3B Only one signal line S10 and one signal line S20 are shown.

[0057] Here, the control module of the comparison example will be described. Figure 12A This is a partial plan view of the control module 110X in the comparative example. The memory controller 130X and the memory device 140X are both deployed on the main surface 201X of the two main surfaces 201X and 202X of the printed wiring board 200X. Figure 12B This is a cross-sectional view of the control module 110X, a comparative example. Figure 12B Schematic illustration along Figure 12A The control module 110X is shown as a cross section cut by line XIIB-XIIB. Figure 12C This is a cross-sectional view of the 200X printed wiring board, a comparative example. Figure 12C Schematic illustration along Figure 12B The XIIC-XIIC line is a 200X cross-section of the printed wiring board.

[0058] Viewed from the Z-direction, both the memory controller 130X and the memory device 140X have a rectangular shape. Viewed from the Z-direction, the size of the memory controller 130X is larger than that of the memory device 140X.

[0059] In the comparative example, the memory controller 130X and the memory device 140X are deployed on the printed wiring board 200X opposite each other in the X direction, such that the edges 131X of the memory controller 130X and 141X of the memory device 140X are parallel to each other when viewed from the Z direction. When viewed from the Z direction, the edge 141X of the memory device 140X is the longer edge.

[0060] The printed wiring board 200X is a laminate comprising at least four conductor layers L1X to L4X. The conductor layers L1X to L4X are arranged from the main surface 201X toward the main surface 202X in the order of conductor layer L1X, conductor layer L2X, conductor layer L3X and conductor layer L4X.

[0061] The memory controller 130X includes a plurality of signal terminals 11X and a plurality of signal terminals 12X that are closer to the memory device 140X than each of the plurality of signal terminals 11X. The memory device 140X includes a plurality of signal terminals 13X and a plurality of signal terminals 14X that are closer to the memory controller 130X than each of the plurality of signal terminals 13X. Signal terminals 11X and 12X of the memory controller 130X are each terminals used for transmitting address / command signals. Signal terminals 13X and 14X of the memory device 140X are each terminals used for receiving address / command signals.

[0062] The printed wiring board 200X includes multiple signal lines S10X that electrically connect multiple signal terminals 12X of the memory controller 130X to multiple signal terminals 14X of the memory device 140X in a one-to-one relationship. Furthermore, the printed wiring board 200X includes multiple signal lines S20X that electrically connect multiple signal terminals 11X of the memory controller 130X to multiple signal terminals 13X of the memory device 140X in a one-to-one relationship.

[0063] Signal lines S10X are each formed by signal traces S11X disposed within conductor layer L1X. In contrast, each signal line S20X includes a signal trace S21X disposed within conductor layer L4X, a signal via S22X contacting signal terminal 11X and signal trace S21X, and a signal via S23X contacting signal terminal 13X and signal trace S21X. Signal vias S22X and S23X are each through-holes. Signal line S10X does not include signal vias that are through-holes. Figure 12C In this configuration, ground traces are deployed in conductor layer L2X. Power traces or ground traces to which a power supply potential is applied are deployed in conductor layer L3X.

[0064] If the signal trace S11X of signal line S10X is arranged in a straight line, the path difference (i.e., the difference in wiring length between signal lines S10X and S20X) increases. When the operating frequency of signals is increased in a timing synchronization type circuit in a memory system, the delay time difference between multiple signals increases. When the delay time difference derived from the wiring length difference exceeds a predetermined value defined according to the signal operating frequency, the possibility of errors in logic determination in the memory device 140X increases. If errors exist in logic determination, noise may be generated in the image, or the electronic device may malfunction. Therefore, it is necessary to reduce the path difference between signal lines S10X and S20X.

[0065] Therefore, in the comparative example, by arranging the signal trace S11X of signal line S10X in a zigzag manner, the path difference can be reduced. However, a large wiring area is required to arrange the signal trace S11X in a zigzag manner. That is, the wiring pitch of the zigzag signal trace S11X is set to minimize electromagnetic coupling in order to reduce self-crosstalk of signal trace S11X. Furthermore, among the two signal lines S10X, the two signal traces S11X that are opposite each other in the Y direction will be referred to as signal traces S11X1 and S11X2. Similarly, among the two signal lines S20X, the two signal traces S21X that are opposite each other in the Y direction will be referred to as signal traces S21X1 and S21X2. The wiring pitch between signal traces S11X1 and S11X2, and the wiring pitch between signal traces S21X1 and S21X2, are also set to minimize electromagnetic coupling in order to reduce crosstalk.

[0066] As described above, it is necessary to reduce crosstalk between the two signal traces S11X1 and S11X2, crosstalk between the two signal traces S21X1 and S21X2, and self-crosstalk within each of the signal traces S11X1 and S11X2. To reduce this crosstalk, the wiring pitch needs to be increased, thus requiring even larger wiring areas. For example, the thickness from each of the signal traces S11X1 and S11X2 to the ground plane is set to 100 μm, and an insulating layer is present between each of the signal traces S11X1 and S11X2 and the ground plane. With the self-wiring pitch of each of the tortuous signal traces S11X1 and S11X2, and the pitch between the signal traces S11X1 and S11X2, set to three times the pitch between each of the signal traces S11X1 and S11X2 and the ground plane, the minimum wiring pitch is 300 μm. If the signal line S10X is arranged in a zigzag manner as a short wiring to reduce the difference between the wiring length of signal line S10X and the wiring length of signal line S20X while ensuring a 300μm pitch, then the wiring area increases.

[0067] Furthermore, in the case where, for example, DDR4 SDRAM is used as memory device 140X to further accelerate the memory system, the shape and pitch of the solder balls are the same as those in DDR3 SDRAM. Therefore, the aforementioned problems also occur when memory device 140X is DDR4 SDRAM. In addition, since DDR4 SDRAM operates at a higher speed than DDR3 SDRAM, the wiring area of ​​the tortuous wiring used to reduce wiring length and thus reduce latency difference increases.

[0068] Furthermore, in order to employ a wiring structure in which all bus wirings in the control module 110X described in the comparative example are connected with the shortest path, for example, the wiring width or wiring pitch of the printed wiring board 200X needs to be less than 75 μm, or the shape of the pads of the memory device 140X needs to be small. Therefore, problems arise regarding reduced productivity of the printed wiring board 200X or decreased component mountability.

[0069] Therefore, in the first embodiment, the terminal layout of the memory controller 130 differs from that of the memory controller 130X, and the wiring structure of the printed wiring board 200 differs from that of the printed wiring board 200X in the comparative example. It should be noted that the terminal layout of the memory device 140 in the first embodiment is substantially the same as that of the memory device 140X in the comparative example. Reference will be made below. Figures 3A to 3C Provide a description.

[0070] In the first embodiment, the memory controller 130 and the memory device 140 are deployed as close to each other as possible. Among the signals used for communication between the memory controller 130 and the memory device 140 and requiring synchronization, the number of signals for address / command signals is the largest.

[0071] Since the multiple signal lines S10 in the first embodiment each have substantially the same wiring structure, the focus will be on describing one of the signal lines S10. Since the multiple signal lines S20 in the first embodiment each have substantially the same wiring structure, the focus will be on describing one of the signal lines S20. For the memory controller 130, the focus will be on describing one of the signal terminals 11 and one of the signal terminals 12, and for the memory device 140, the focus will be on describing one of the signal terminals 13 and one of the signal terminals 14. In the first embodiment, as... Figure 3B As shown, the distance D1 between signal terminal 12 and signal terminal 13 is greater than the distance D2 between signal terminal 11 and signal terminal 14.

[0072] The signal line S10, which electrically interconnects signal terminals 12 and 13, includes a signal trace S11, which serves as an example of a first signal trace. Signal trace S11 is disposed in conductor layer L2. The signal line S20, which electrically interconnects signal terminals 11 and 14, includes a signal trace S21, which serves as an example of a second signal trace. Signal trace S21 is disposed in conductor layer L4. That is, signal trace S21 is disposed on the main surface 202. It should be noted that a power trace (not shown) or a ground trace (not shown) may be disposed in each of conductor layers L1 and L3.

[0073] The signal line S10 includes a signal via S12, a signal via S13, and a signal trace S14. The signal trace S14 is disposed in the conductor layer L1 and is electrically connected to the signal terminal 12 by contacting the signal terminal 12.

[0074] The signal via S12 is a through-hole conductor that electrically interconnects the signal terminal 12 and the signal trace S11 by contacting the signal trace S14 connected to the signal terminal 12 and the signal trace S11 connected to the conductor layer L2 in the conductor layer L1. In this embodiment, the signal via S12 is a portion of the through-hole between the conductor layer L1 and the conductor layer L2.

[0075] The signal via S13 is a via conductor that electrically interconnects the signal terminal 13 and the signal trace S11 by contacting the signal trace (not shown) in the conductor layer L1 that is connected to the signal terminal 13 and the signal trace S11 in the conductor layer L2. In this embodiment, the signal via S13 is a portion of the through-hole between the conductor layer L1 and the conductor layer L2.

[0076] Furthermore, signal line S20 includes signal via S22 and signal via S23. Signal via S22 is a through-hole conductor that electrically interconnects signal terminal 11 and signal trace S21 by contacting signal trace S21 (not shown) connected to signal terminal 11 in conductor layer L1 and conductor layer L4. This through-hole conductor is a through-hole.

[0077] The signal via S23 is a through-hole conductor that electrically interconnects the signal terminal 14 and the signal trace S21 by contacting the signal trace (not shown) connected to the signal terminal 14 in the conductor layer L1 and the signal trace S21 in the conductor layer L4. This via conductor is a through-hole.

[0078] In the first embodiment, since the signal trace S11 is deployed in the conductor layer L2, which acts as the first inner layer, the signal line S10 includes signal vias S12 and S13. Therefore, the path length (i.e., the wiring length of the signal line S10) is adjusted by the signal vias S12 and S13. Thus, compared to the comparative example where the signal trace S11X is arranged in a zigzag manner, the wiring area can be reduced regardless of whether the signal line S10 is arranged in a zigzag manner.

[0079] As described above, since signal lines S10 and S20 have the aforementioned wiring structure in the printed wiring board 200, the difference between the path lengths of signal lines S10 and S20 is reduced. Therefore, the tortuous wiring of signal lines S10 and S20 can be shortened or omitted, thereby reducing the wiring area of ​​each signal line in signal lines S10 and S20 when viewed from the Z direction, and reducing the time delay difference of the address / command signal between signal terminals 13 and 14. Therefore, signal quality is improved, and miniaturization of the printed wiring board 200, i.e., miniaturization of the control module 110, is achieved.

[0080] Figure 4 This is a plan view showing the terminal layout in the memory device 140 according to the first embodiment. Figure 4 The memory device 140 is shown from the side opposite to the side where the terminals are arranged. Figure 4 In the diagram, each terminal is indicated by a dashed line.

[0081] The memory device 140 is, for example, a DDR4 SDRAM. Multiple terminals, including signal terminals, power terminals, and ground terminals, are arranged in an array in the first to third and seventh to ninth columns of a 16-row × 9-column configuration. No terminals are provided in the fourth to sixth columns. The total number of terminals in the memory device 140 is 96.

[0082] exist Figure 4 In the memory device 140, among the multiple terminals, terminals A0 to A16, BA0, BA1, BG0, and ACT are signal terminals 13 and 14 used to receive address / command signals. Figure 4 In the example, signal terminals 13 and 14 have a total of 21 terminals. Signal terminals 13 and 14 are arranged in rows 11 to 16. Additionally, signal terminal 14 is arranged in columns 7 and 8, and signal terminal 13 is arranged in columns 2 and 3. Furthermore, signal terminals 13 and 14 are arranged in rows L (11) to T (16) of rows A (1) to T (16).

[0083] The memory device 140 can determine the mounting orientation of the memory controller 130 based on the position of the terminals. In the first embodiment, edge 141 is aligned with... Figure 3A The memory controller 130 shown has its sides 131 opposite each other. Therefore, in Figure 4 In the example, terminals A0, A2, A4, A6, A8, A10, A11, A14, BA0, BG0, and ACT in the second and third columns each serve as third signal terminals. Furthermore, terminals A1, A3, A5, A7, A9, A12, A13, A15, A16, and BA1 in the seventh and eighth columns each serve as fourth signal terminals.

[0084] It should be noted that when making the edge 142 of the memory device 140 and Figure 3A When the sides 131 of the memory controller 130 shown are opposite each other, terminals A0, A2, A4, A6, A8, A10, A11, A14, BA0, BG0, and ACT in the second and third columns each serve as fourth signal terminals. Furthermore, terminals A1, A3, A5, A7, A9, A12, A13, A15, A16, and BA1 in the seventh and eighth columns each serve as third signal terminals.

[0085] like Figure 4 As shown, the spacing between signal terminals 13 in the third column and signal terminals 14 in the seventh column is greater than the pitch of the multiple signal terminals 13 and the pitch of the multiple signal terminals 14. Therefore, as Figure 3B As shown, the distance D3 between signal terminal 13 and signal terminal 14 is greater than the distance D4 between signal terminal 11 and signal terminal 12. In this positional relationship of the terminals, it is preferable that signal lines S10 and S20 each have the above-described wiring structure.

[0086] Figure 5A This is a plan view of the wiring structure of a portion of the conductor layer L1 in the printed wiring board 200 according to the first embodiment. Figure 5B This is a plan view of the wiring structure of a portion of the conductor layer L2 in the printed wiring board 200 according to the first embodiment. Figure 5C This is a plan view of the wiring structure of a portion of the conductor layer L4 in the printed wiring board 200 according to the first embodiment. Figures 5A to 5C Each shows the wiring structure of the area on the printed wiring board 200 where the memory device 140 is mounted and the surrounding area.

[0087] like Figure 3C and Figure 5B As shown, two signal traces S11 of two signal lines S10 among the multiple signal lines S10 will be referred to as signal traces S111 and S112. Furthermore, as... Figure 3C and Figure 5C As shown, two signal traces S21 of the multiple signal lines S20 will be referred to as signal traces S211 and S212.

[0088] The printed wiring board 200 includes ground traces G1 and G2. Ground trace G1 serves as an example of a first ground trace. Ground trace G2 serves as an example of a second ground trace. Ground trace G1 is deployed at the same location in the Z direction as signal traces S111 and S112, that is, deployed in the same conductor layer L2. Ground trace G2 is deployed at the same location in the Z direction as signal traces S211 and S212, that is, deployed in the same conductor layer L4. In other words, ground trace G2 is deployed on the main surface 202.

[0089] Ground trace G1 extends along signal trace S111 in the X direction, such that signal trace S111 lies between the two portions of ground trace G1 in the width direction W11 of signal trace S111. Similarly, ground trace G1 extends along signal trace S112 in the X direction, such that signal trace S112 lies between the two portions of ground trace G1 in the width direction W12 of signal trace S112.

[0090] Furthermore, ground trace G2 extends along signal trace S211 in the X direction, such that signal trace S211 lies between the two portions of ground trace G2 in its width direction W21. Similarly, ground trace G2 extends along signal trace S212 in the X direction, such that signal trace S212 lies between the two portions of ground trace G2 in its width direction W22. Figure 3C In the diagram, signal traces S111, S112, S211, and S212 all extend in the X direction, therefore the width directions W11, W12, W21, and W22 are parallel to the Y direction.

[0091] As described above, in the first embodiment, a ground trace G1 is deployed on both sides of each of the signal traces S111 and S112 in the Y direction, with an insulator between the ground trace G1 and each of the signal traces S111 and S112. That is, the ground trace G1 at the reference potential is deployed opposite each of the signal traces S111 and S112, with an insulator between the ground trace G1 and each of the signal traces S111 and S112, such that each of the signal traces S111 and S112 is located between two portions of the ground trace G1. Due to the ground trace G1, a path for the return current corresponding to the signal flowing in each of the signal traces S111 and S112 can be ensured, thus reducing the characteristic impedance mismatch in each of the signal traces S10. Therefore, signal reflection in each signal trace S10 can be reduced. Thus, signal quality is improved, and radiated noise can be further reduced. Furthermore, since there is a ground trace G1 between each pair of signal lines S10, crosstalk in each signal line S10 can be reduced, thereby improving signal quality. The same effect is achieved for signal line S20.

[0092] It should be noted that power traces can be formed in conductor layer L3 to supply power potential to memory controller 130 and memory device 140. Alternatively, power traces for supplying power potential can be formed in conductor layer L1 to form ground traces in conductor layer L3.

[0093] Viewed from the Z direction, at least a portion of signal trace S111 overlaps with at least a portion of signal trace S211. Therefore, further miniaturization of the printed wiring board 200 can be achieved. Viewed from the Z direction, half or more of the area of ​​signal trace S111 preferably overlaps with half or more of the area of ​​signal trace S211. Signal traces S112 and S212 are also arranged in substantially the same manner. Furthermore, viewed from the Z direction, at least a portion of ground trace G1 overlaps with at least a portion of ground trace G2. Therefore, ground trace G1 and ground trace G2 can be interconnected via, for example, via conductors, thereby facilitating the electrical connection of ground trace G1 to ground trace G2.

[0094] In the first embodiment, each of the multiple signal lines S10 and S20 used for transmitting address / command signals is configured to include a via conductor. Specifically, multiple signal vias corresponding to multiple signal terminals 11 are deployed near the multiple signal terminals 11. Multiple signal vias corresponding to multiple signal terminals 12 are deployed near the multiple signal terminals 12. Multiple signal vias corresponding to multiple signal terminals 13 are deployed near the multiple signal terminals 13. Multiple signal vias corresponding to multiple signal terminals 14 are deployed near the multiple signal terminals 14.

[0095] exist Figure 5A In the memory device 140, the pads 31 to which the terminals in rows L (11) to T (16) are connected are indicated by dotted lines. Multiple pads 31 are deployed in the conductor layer L1. The multiple pads 31 include multiple pads S15 corresponding to multiple signal terminals 13 and multiple pads S25 corresponding to multiple signal terminals 14. Each pad S15 is a pad to which one of the signal terminals 13 is connected. Each pad S25 is a pad to which one of the signal terminals 14 is connected.

[0096] The multiple signal lines S10 include multiple signal vias S13 located closer to the memory device 140 than the memory controller 130. Each signal via S13 corresponds to a signal terminal 13. It should be noted that the signal vias S13 are located in... Figure 5A and Figure 5B The shaded areas of each free cell are indicated.

[0097] The multiple signal lines S20 include multiple signal vias S23 located closer to the memory device 140 than the memory controller 130. Each signal via S23 serves as an example of a first signal via and corresponds to a signal terminal 14. It should be noted that the signal vias S23 are located in... Figures 5A to 5C The shadows on the vertical lines in the middle indicate the direction of travel.

[0098] Multiple signal vias S13 are connected to multiple pads S15 via multiple signal traces S16. The multiple signal traces S16 are deployed in the conductor layer L1. Each signal trace S16 corresponds to a pad S15. Furthermore, multiple signal vias S23 are connected to multiple pads S25 via multiple signal traces S26. The multiple signal traces S26 are deployed in the conductor layer L1. Each signal trace S26 corresponds to a pad S25.

[0099] Focusing on a signal line S10, signal line S10 includes a signal via S13, a pad S15, and a signal trace S16. Additionally, focusing on a signal line S20, signal line S20 includes a signal via S23, a pad S25, and a signal trace S26.

[0100] Multiple signal vias S13 are arranged at intervals in the X and Y directions near multiple pads S15. Multiple signal vias S23 are arranged at intervals in the X and Y directions near multiple pads S25.

[0101] The focus will be on description Figure 5B Among the multiple signal lines S10, two signal lines S101 and S102 are used. For example... Figure 5B As shown, signal line S101 includes signal trace S111 as signal trace S11 and signal via S131 as signal via S13. Signal line S102 includes signal trace S112, which is different from signal trace S111, and signal via S132, which is different from signal via S131. Signal trace S111 includes an extension portion S1111 extending from memory device 140 toward memory controller 130. Signal trace S112 includes an extension portion S1112 extending from memory device 140 toward memory controller 130. Extension portions S1111 and S1112 are each linearly extending portions in the X direction.

[0102] The extensions S1111 and S1112 are each deployed through a gap between two signal vias S231 and S232 included in a plurality of signal vias S23, and the two signal vias S231 and S232 are arranged at intervals in the Y direction intersecting the X direction of each extension in the extensions S1111 and S1112.

[0103] Ground trace G1 exists in the gaps between signal vias S231 and S232 and extensions S1111 and S1112. Specifically, ground trace G1 exists in the gaps between signal vias S231 and extensions S1111, between extensions S1111 and S1112, and between signal vias S232 and extensions S1112. Furthermore, ground trace G1 exists in the gaps between multiple signal vias S13 and between multiple signal vias S23. That is, ground trace G1 is disposed in conductor layer L2 at predetermined intervals from wiring other than ground, so as not to contact wiring other than ground. Additionally, when viewed from the Z direction, ground trace G1 is formed as a solid pattern in the smallest rectangular area including multiple pads S15, multiple pads S25, multiple signal vias S13, and multiple signal vias S23. In the first embodiment, each of all signal traces S11 is surrounded by a ground trace G1 formed as a solid pattern.

[0104] Since the ground trace G1 deployed in the conductor layer L2 exists between the signal trace S11 of signal line S10 and the signal via S23 of signal line S20, the radiated noise from signal lines S10 and S20 can be effectively reduced. Furthermore, crosstalk between adjacent signal traces S11 and signal vias S23 sandwiching the ground trace G1, as well as crosstalk between two adjacent signal vias S23 sandwiching the ground trace G1, can also be effectively reduced.

[0105] Furthermore, signal lines S101 and S102 are configured such that two signal traces S111 and S112 pass through the gap between two signal vias S231 and S232, which are spaced apart in the Y direction among a plurality of signal vias S23. Therefore, further miniaturization of the printed wiring board 200 can be achieved.

[0106] In a minimal rectangular area comprising multiple pads S15, multiple pads S25, multiple signal vias S13, and multiple signal vias S23 when viewed from the Z direction, signal lines S10 and S20 are arranged without reducing the productivity of the printed wiring board 200 and the mountability of the memory device 140. Specifically, in the conductor layer L1, among the multiple pads S15, only one of the multiple signal traces S16 or no signal trace S16 is provided between two adjacent pads S15 in the X or Y direction. Furthermore, in the conductor layer L1, among the multiple pads S25, only one of the multiple signal traces S26 or no signal trace S26 is provided between two adjacent pads S25 in the X or Y direction. Therefore, in the small area where the memory device 140 is mounted, each of the signal traces S16 and S26 can be set to an appropriate wiring width, and each of the pads S15 and S25 can be set to an appropriate size. In addition, multiple signal vias S13 and multiple signal vias S23 can be deployed in a small area, multiple signal traces S11 can be configured to connect to multiple signal vias S13 in conductor layer L2, and multiple signal traces S21 can be configured to connect to multiple signal vias S23 in conductor layer L4.

[0107] It is important to note that Figure 4 The terminal indicated by the white dashed circle, such as the terminal located in row T (16th row, third column), can be used as a terminal for outputting a parity signal (PAR signal). Furthermore, Figures 5A to 5C The through-holes indicated by the white circles can be used as power through-holes or ground through-holes. Furthermore, Figures 5A to 5C The through-hole indicated by the white circle can be omitted. The number of signal lines used to transmit address / command signals can be determined by the control module 110 and is not limited to 21.

[0108] In addition, Figure 5A In the structure shown, the plurality of signal vias S13 are preferably formed with a pitch of 0.8 mm in the X direction and a pitch of 1.6 mm in the Y direction. Similarly, the plurality of signal vias S23 are preferably formed with a pitch of 0.8 mm in the X direction and a pitch of 1.6 mm in the Y direction.

[0109] It should be noted that the three signal vias S13 included in the signal line S10 corresponding to one signal terminal 13 in row T (16) and the two signal lines S10 corresponding to two signal terminals 13 in row R (15) are deployed on the outer side of the area formed by connecting the centers of multiple pads 31 in the Y direction. Therefore, all signal lines S10 can be provided via conductor layer L2.

[0110] The focus will be on description Figure 5CAmong the multiple signal lines S20, two signal lines S201 and S202 are used. For example... Figure 5C As shown, signal line S201 includes signal trace S211, which is signal trace S21. Signal line S202 includes signal trace S212, which is signal trace S21, different from signal trace S211. Signal trace S211 includes an extension S2111 extending from memory device 140 toward memory controller 130. Signal trace S212 includes an extension S2112 extending from memory device 140 toward memory controller 130. Extensions S2111 and S2112 are each a portion extending linearly in the X direction.

[0111] The ground trace G2 is set as a solid pattern in the conductor layer L4 at predetermined intervals with the wiring other than ground, so as not to contact the wiring other than ground in the aforementioned minimum rectangular area. In the first embodiment, each of all signal traces S21 is surrounded by a ground trace G2 formed as a solid pattern.

[0112] Therefore, in the first embodiment, the ground trace G2 deployed in the conductor layer L4 can effectively reduce radiated noise from signal lines S10 and S20. Furthermore, it can also effectively reduce crosstalk between two adjacent signal lines S20 sandwiching the ground trace G2. Moreover, all of the multiple signal lines S20 can be arranged via the conductor layer L4.

[0113] Due to the above wiring structure, multiple signal lines S10 and multiple signal lines S20 can be formed with the smallest possible path length, and grounding can be formed on both sides of each signal line in the width direction, with an insulator sandwiched between each signal line and the grounding.

[0114] Furthermore, multiple signal vias S22 included in the multiple signal lines S20 are deployed at locations that overlap with the memory controller 130 when viewed from the Z direction. In contrast, multiple signal vias S12 included in the multiple signal lines S10 are deployed at locations that do not overlap with the memory controller 130.

[0115] Figure 6A This is a partial plan view of a portion of the control module 110 according to the first embodiment, namely the memory controller 130 and the printed wiring board 200. Signal lines S10 include signal vias S12 deployed closer to the memory controller 130 than the memory device 140. The signal vias S12 serve as examples of second signal vias. That is, multiple signal lines S10 include multiple signal vias S12 deployed closer to the memory controller 130 than the memory device 140. Viewed in the Z direction, the multiple signal vias S12 are deployed between the memory controller 130 and the memory device 140.

[0116] Figure 5A The multiple signal vias S13 shown are arranged in three rows in the X direction with a maximum pitch of 0.8 mm. Furthermore, the multiple signal vias S13 are arranged in four rows in the Y direction with a pitch of 1.6 mm. Similarly, the multiple signal vias S23 are arranged in three rows in the X direction with a maximum pitch of 0.8 mm. Furthermore, the multiple signal vias S23 are arranged in four rows in the Y direction with a pitch of 1.6 mm. Figure 5B As shown, two signal traces S111 and S112, as well as a ground trace G1, are deployed between two signal vias S23 arranged in the Y direction with a pitch of 1.6 mm.

[0117] At this time, similar to the multiple signal vias S13 and S23, the multiple signal vias S12 positioned near the multiple signal terminals 12 of the memory controller 130 are also preferably arranged in the X direction with a pitch of 0.8 mm or less. Furthermore, the multiple signal vias S12 are preferably arranged in the Y direction with a pitch of 1.6 mm or less. That is, the minimum pitch XA of the multiple signal vias S12 is preferably equal to or less than the minimum pitch XB of the multiple signal vias S23. In the first embodiment, the minimum pitch XA is the pitch of the multiple signal vias S12 in the X direction. The minimum pitch XB is the pitch of the multiple signal vias S23 in the X direction in the first embodiment. When the multiple signal vias S12 are arranged in this way, the wiring efficiency is highest. By adopting this wiring structure, a connection with the memory device 140, which is a DDR4 SDRAM, can be easily established.

[0118] Figure 6B This is a partial plan view of a portion of the control module 110, namely the memory controller 130 and the printed wiring board 200, according to a modified example of the first embodiment. In this modified example, the memory device 140 is a DDR3 SDRAM. The terminal layout of DDR3 SDRAM differs from that of DDR4 SDRAM. Therefore, the wiring is highly flexible because changes come from... Figure 6A The signal via S12 in the conductor layer L1 that connects the signal trace S14 is sufficient.

[0119] It is important to note that in conductor layer L1, a ground trace can also be placed between signal trace S14 and signal via S12. Therefore, a ground trace can also be placed between two signal traces S14, which can reduce radiated noise and crosstalk. In addition, it can also reduce the electromagnetic coupling between signal trace S14 and signal via S12 and other signal lines or power lines.

[0120] By employing the wiring structure shown in Figure 5 as described above, the tortuous wiring of all signal lines for the address / command signals of the interconnect memory controller 130 and memory device 140 can be shortened or omitted. Furthermore, since the ground wire is formed on both sides of the signal line in the width direction separated by an insulator, impedance variations in the wiring can be reduced, and detours in the return path can also be avoided.

[0121] Furthermore, in the first embodiment, a pad shape can be used that sufficiently ensures the wiring width and wiring pitch of the printed wiring board 200 without reducing the mountability of the memory device 140 in the printed wiring board 200. Additionally, since the difference in wiring length between signal line S10 and signal line S20 can be reduced, the spacing between the memory controller 130 and the memory device 140 can be reduced, thus reducing the wiring area.

[0122] Example 1-1

[0123] In the corresponding to the first embodiment Figure 3B In the wiring structure shown, the wiring length difference Δd between the wiring length of signal line S10 and the wiring length of signal line S20 is obtained. Note that the direction parallel to the X direction from memory controller 130 to memory device 140 will be referred to as the X1 direction. The X1 direction will be indicated with a positive value, and the direction opposite to the X1 direction will be indicated with a negative value. Furthermore, Figure 3B The direction parallel to the Z direction and upward from the main surface 201 will be called the Z1 direction. The Z1 direction will be indicated with a positive value, and the direction opposite to the Z1 direction will be indicated with a negative value.

[0124] The distance from signal terminal 11 to signal terminal 12 in the X1 direction is represented by Δd1. The distance from signal terminal 13 to signal terminal 14 in the X1 direction is represented by Δd2. The difference obtained by subtracting the sum of the lengths of signal vias S22 and S23 in the Z1 direction from the sum of the lengths of signal vias S12 and S13 in the Z1 direction is represented by Δd3. The difference in wiring length Δd between the wiring length of signal line S10 and the wiring length of signal line S20 can be roughly calculated by Δd = Δd1 + Δd2 + Δd3.

[0125] A rough calculation is performed under the following conditions. The pitch of the terminals of the memory controller 130 is set to 0.8 mm, which is equal to the pitch of the terminals of the memory device 140.

[0126] Figure 3B The two signal terminals 12 shown are located on the outer periphery and second column of the memory controller 130. Furthermore, Figure 3BThe two signal terminals 11 shown are located in the third and fourth columns of the memory controller 130. As a condition for roughly calculating the wiring length difference Δd, the following terminals are used: Specifically, the signal terminal 11 in the fourth column of the memory controller 130 is used. Furthermore, the signal terminal 12 located on the outer periphery of the memory controller 130 is used. Furthermore, the signal terminal 13 in the column further away from the memory controller 130 is used. And the signal terminal 14 in the column closer to the memory controller 130 is used.

[0127] The thickness of the printed wiring board 200 is set to 1.6 mm. The distance between conductor layers L1 and L2, and the distance between conductor layers L4 and L3, are each set to 100 μm. It is assumed that each of the signal lines S10 and S20 in conductor layer L1 is identical, therefore calculations are omitted.

[0128] Under the above conditions, Δd1, Δd2, and Δd3 are calculated, and the results are as follows.

[0129] Δd1 = 0.8 mm × (-3 pitch) = -2.4 mm

[0130] Δd2 = 0.8 mm × (6 pitches) = 4.8 mm

[0131] Δd3 = (0.1mm × 2 through holes) – (1.6mm × 2 through holes) = -3.0mm

[0132] Therefore, the wiring length difference Δd between signal line S10 and signal line S20 is as follows.

[0133] Δd=(-2.4mm)+(4.8mm)+(-3.0mm)=-0.6mm

[0134] Comparison Example 1-1

[0135] Next, for the comparison examples... Figure 12B The wiring structure shown also performs the same calculations. The distance from signal terminal 11X to signal terminal 12X in the X1 direction is represented by Δd1X. The distance from signal terminal 13X to signal terminal 14X in the X1 direction is represented by Δd2X. The difference obtained by subtracting the sum of the lengths of signal vias S22X and S23X in the Z1 direction from the sum of the lengths of the signal vias of signal line S10X in the Z1 direction is represented by Δd3. The difference in wiring length ΔdX between signal line S10X and signal line S20X can be roughly calculated by ΔdX = Δd1X + Δd2X + Δd3X. The cross-sectional structure of the printed wiring board 200X is set to be consistent with... Figure 3BThe printed wiring board 200 shown has the same cross-sectional structure.

[0136] Under the above conditions, Δd1X, Δd2X, and Δd3X were calculated, and the results are as follows.

[0137] Δd1X = 0.8mm × (-3 pitch) = -2.4mm

[0138] Δd2X = 0.8mm × (-6 pitch) = -4.8mm

[0139] Δd3X=0–(1.6mm×2 through holes)=-3.2mm

[0140] Therefore, the wiring length difference ΔdX between signal line S10X and signal line S20X is as follows.

[0141] ΔdX=(-2.4mm)+(-4.8mm)+(-3.2mm)=-10.4mm

[0142] Comparison between Example 1-1 and Comparison Example 1-1

[0143] In Example 1-1, the wiring length difference Δd is -0.6 mm, while in Comparative Example 1-1, the wiring length difference ΔdX is -10.4 mm. Therefore, in Example 1-1, the wiring length difference can be reduced compared to Comparative Example 1-1.

[0144] Example 1-2

[0145] The following will refer to Figures 3A to 5C Description of Example 1-2. The printed wiring board 200 of Example 1-2 is a four-layer board including through-holes. The layer structure of the printed wiring board 200 of Example 1-2 is set as follows: The thickness of conductor layer L1 in the Z direction is set to 37 μm. The thickness of the insulating layer between conductor layer L1 and conductor layer L2 in the Z direction is set to 100 μm. The thickness of conductor layer L2 in the Z direction is set to 35 μm. The thickness of the insulating layer between conductor layer L2 and conductor layer L3 is set to 1200 μm. The thickness of conductor layer L3 in the Z direction is set to 35 μm. The thickness of the insulating layer between conductor layer L3 and conductor layer L4 in the Z direction is set to 100 μm. The thickness of conductor layer L4 in the Z direction is set to 37 μm.

[0146] Figure 3C The width of each of the signal traces S111 and S112 in the cross-section shown is set to 125 μm. Figure 3CThe width of each portion of the ground trace G1 in the cross-section shown is set to 100 μm. The spacing between all signal traces and the ground trace is set to 87.5 μm. The spacing between the through-holes formed at the corresponding ends of the ground trace and the signal trace in the wiring direction is set to 75 μm. The ground trace is deployed in conductor layer L1, and the power trace for supplying power potential is deployed in conductor layer L3.

[0147] The diameter of the through-hole pad is set to a maximum of 550 μm. The pitch Y1 between the two signal vias S231 and S232 arranged in the Y direction is set to 1.6 mm. Using the above wiring structure, two signal traces S111 and S112, as well as a ground trace G1, can be provided between the two signal vias S231 and S232 arranged in the Y direction. Furthermore, two signal lines S10 passing through conductor layer L2 and two signal lines S20 passing through conductor layer L4 can be provided in the printed wiring board 200. Therefore, all signal lines S10 and S20 extending in the X direction can be provided... Figures 5A to 5C The area shown.

[0148] In the printed wiring board 200, it can also be used with Figures 5A to 5C The wiring structure of the memory device 140 shown is similar to that of the area where the signal terminals 11 and 12 of the memory controller 130 are connected. Therefore, all signal lines S10 and S20 extending from the memory device 140 to the memory controller 130 can be formed in the shortest path, and in each signal trace, ground traces can be provided on both sides in the width direction of the signal trace, with an insulator located between the ground trace and the signal trace. Furthermore, since the ground trace is formed between the signal trace and the via, the signal lines are not close to each other. In addition, crosstalk between a signal line and the signal via of another signal line, as well as crosstalk between a signal line and the power via of a power line, can be reduced.

[0149] For example, when the via pad shape differs between conductor layer L2 and conductor layer L4, the wiring width of the ground trace G1 or ground trace G2 near the via pad can be increased. By making a portion of ground trace G1 and a portion of ground trace G2 overlap each other when viewed from the Z direction, ground trace G1 and ground trace G2 can be easily electrically interconnected through the via. Therefore, the grounding characteristics are improved. For example, in Figure 5B and Figure 5C In the cross section along line IIIC-IIIC shown, where no through-holes exist, through-holes for interconnecting ground traces G1 and G2 can be easily provided.

[0150] Meanwhile, the pitch of the multiple signal vias S13 in the X direction and the pitch of the multiple signal vias S23 in the X direction are each integer multiples of the pitch of the terminals of the memory device 140. Therefore, the minimum pitch of the multiple signal vias S13 in the X direction and the minimum pitch of the multiple signal vias S23 in the X direction are each 0.8 mm. By setting the gap diameter between the ground traces G1 and G2 and the through-holes passing through them to Φ0.65 mm or less, a ground wire with a width of 75 μm or greater can be formed between the through-holes set at the minimum pitch. By adopting this structure, crosstalk between the signal lines and the through-holes of the power supply potential can also be reduced.

[0151] It is important to note that the pad diameter and wiring structure of the through-hole can be adjusted to take into account the specifications required by the memory system and the productivity of the printed circuit board 200. For example, in Figure 3C In the cross-section shown, the width and pitch of each of the signal and ground traces can be changed to 0.1 mm and 0.09 mm, respectively. Furthermore, the wiring width and pitch of all components do not need to be equal. For example, the width of the ground trace near the through-hole can be increased, or the width of the portion of the ground trace positioned between two signal traces can be changed.

[0152] Although Figure 3C The cross-section shown employs a structure in which the entirety of the wiring pattern deployed in conductor layer L2 in the Y direction, when viewed from the Z direction, overlaps with the entirety of the wiring pattern deployed in conductor layer L4 in the Y direction, but the configuration is not limited to this. It is sufficient that a portion or the entirety of the wiring pattern deployed in conductor layer L2 in the Y direction, when viewed from the Z direction, overlaps with a portion or the entirety of the wiring pattern deployed in conductor layer L4 in the Y direction. For example, it is sufficient that a portion or the entirety of signal trace S111 in the Y direction overlaps with a portion or the entirety of signal trace S211 in the Y direction, when viewed from the Z direction. The same applies to ground traces G1 and G2.

[0153] Furthermore, the pitch Y1 is not limited to 1.6mm and can be appropriately set according to the shape of the pads or the pitch of the pads. It is sufficient to provide signal traces S11 between the signal vias S23 arranged in the Y direction and to provide ground traces G1 on both sides of the signal traces S11 with an insulator between them.

[0154] Furthermore, the number of signal lines S10 and S20 is not limited to the examples described above. Additionally, the number of signal lines S10 and S20 may be equal or different.

[0155] Any of the ground trace, power trace, and other signal traces can be deployed in each of the conductor layers L1 and L3. For example, the conductor layers L1 or L3 can be formed substantially entirely as a ground connection. Furthermore, each signal trace preferably has a uniform cross-sectional structure at each location in the direction in which the signal trace extends (i.e., in the X direction).

[0156] Furthermore, as a result of the wiring structure in Examples 1-2, the difference in wiring length between the multiple signal lines S10 and S20 is reduced. Therefore, the memory controller 130 and the memory device 140 are arranged as close as possible with a 2mm spacing between their outlines. Moreover, all wiring related to the memory system is contained within a 13mm × 17mm wiring area starting from the end of the outline of the memory controller 130. In contrast, in relation to... Figures 12A to 12C In Comparative Examples 1-2, corresponding to the control module 110X shown in the comparative example, the memory controller 130X and the memory device 140X need to be arranged with a spacing of 7 mm or greater. Therefore, as a result of the wiring structure of Examples 1-2, the printed wiring board 200 is miniaturized.

[0157] It should be noted that although the case where the pitch of the terminals of the memory controller 130 is equal to the pitch of the terminals of the memory device 140 has been described, the pitch can be different. The position and number of columns of the signal terminals 11 and 12 can be arbitrarily set according to the specifications of the semiconductor element that is the memory controller 130. Furthermore, the center of gravity of the plurality of terminals including the signal terminals 11 and 12 of the memory controller 130 is defined according to the distance between the memory controller 130 and the memory device 140. The memory device 140 is not limited to a device where the spacing between one terminal group and another terminal group is greater than the inter-terminal pitch, such as DDR4 SDRAM. Furthermore, DDR4 SDRAM can be a semiconductor package including 78 terminals arranged in 12 rows × 9 columns. In the semiconductor package including 78 terminals, similar to the semiconductor package including 96 terminals, terminals are provided in the first to third columns and the seventh to ninth columns, and no terminals are provided in the fourth to sixth columns. That is, the memory device 140 can be a semiconductor package including 96 terminals or a semiconductor package including 78 terminals.

[0158] While the scenario where the first semiconductor element is a memory controller 130 and the second semiconductor element is a memory device 140 has been described, the configuration is not limited thereto. The first semiconductor element may be a semiconductor element different from that of the memory controller 130, and the second semiconductor element may be a semiconductor element different from that of the memory device 140. Moreover, in this case, the second semiconductor element is not limited to a device in which the spacing between one terminal group and another terminal group is greater than the inter-terminal pitch, such as DDR4 SDRAM.

[0159] Furthermore, the thickness of the printed wiring board 200, the thickness of each of the conductor layers L1 to L4, and the thickness of each insulating layer are not limited to the examples described above. The wiring structure and wiring length can be determined based on the operating frequency of the memory system and the specifications of the semiconductor components.

[0160] Second Embodiment

[0161] The second embodiment will be described. Figure 7 This is a cross-sectional view of the printed wiring board 200A according to the second embodiment. In the second embodiment, the printed wiring board 200A is used instead of the printed wiring board 200 in the control module 110 of the first embodiment. Other components are substantially the same as in the first embodiment. In the second embodiment, the same symbols are used to label the components that are substantially the same as in the first embodiment, and their descriptions are omitted.

[0162] Similar to the printed wiring board 200 of the first embodiment, the printed wiring board 200A of the second embodiment is a four-layer board. The printed wiring board 200A includes signal lines S10A1 and S10A2, which serve as examples of first signal lines, and signal lines S20A1 and S20A2, which serve as examples of second signal lines. Furthermore, the printed wiring board 200A includes a ground trace G1A, which serves as an example of a first ground trace, and a ground trace G2A, which serves as an example of a second ground trace.

[0163] Signal line S10A1 includes signal trace S11A1, which serves as an example of a first signal trace. Signal line S10A2 includes signal trace S11A2, which serves as an example of a first signal trace. Signal line S20A1 includes signal trace S21A1, which serves as an example of a second signal trace. Signal line S20A2 includes signal trace S21A2, which serves as an example of a second signal trace. Signal traces S11A1 and S11A2 are deployed in conductor layer L2. Ground trace G1A is deployed at the same location in the Z direction as signal traces S11A1 and S11A2, i.e., in the same conductor layer L2. Signal traces S21A1 and S21A2 are deployed in conductor layer L4, i.e., on main surface 202. Ground trace G2A is deployed at the same location in the Z direction as signal traces S21A1 and S21A2, i.e., in the same conductor layer L4. That is, the grounding trace G2A is deployed on the main surface 202.

[0164] Ground trace G1A extends along signal trace S11A1 in the X direction, such that signal trace S11A1 lies between the two portions of ground trace G1A in the width direction W1A1 of signal trace S11A1. Similarly, ground trace G1A extends along signal trace S11A2 in the X direction, such that signal trace S11A2 lies between the two portions of ground trace G1A in the width direction W1A2 of signal trace S11A2.

[0165] Furthermore, the ground trace G2A extends along the signal trace S21A1 in the X direction, such that the signal trace S21A1 lies between the two portions of the ground trace G2A in its width direction W2A1. Similarly, the ground trace G2A extends along the signal trace S21A2 in the X direction, such that the signal trace S21A2 lies between the two portions of the ground trace G2A in its width direction W2A2. Figure 7 In the diagram, signal traces S11A1, S11A2, S21A1, and S21A2 all extend in the X direction, therefore the width directions W1A1, W1A2, W2A1, and W2A2 are parallel to the Y direction.

[0166] Viewed from the Z direction, at least a portion of signal trace S11A1 overlaps with at least a portion of signal trace S21A1. Therefore, further miniaturization of the printed wiring board 200A can be achieved. Viewed from the Z direction, half or more of the area of ​​signal trace S11A1 preferably overlaps with half or more of the area of ​​signal trace S21A1. Signal traces S11A2 and S21A2 are also arranged in substantially the same manner. Furthermore, viewed from the Z direction, at least a portion of ground trace G1A overlaps with at least a portion of ground trace G2A. Therefore, ground trace G1A and ground trace G2A can be interconnected, for example, through via conductors, thus making it easier to electrically connect ground trace G1A to ground trace G2A.

[0167] Here, an insulating layer is disposed on both sides of each of the signal traces S11A1 and S11A2 deployed inside the printed wiring board 200A in the Z direction. In contrast, solder resist or air is present on one side of each of the signal traces S21A1 and S21A2 deployed in the conductor layer L4, which acts as the outer layer. The solder resist is thinner than the insulating layer. Furthermore, the dielectric constant of the solder resist and air is lower than that of the epoxy resin constituting the insulating layer. As described above, the dielectric constant around the signal traces S21A1 and S21A2, which are closer to the air, is lower than that of the signal traces S11A1 and S11A2.

[0168] The output characteristics of the circuitry used to transmit address / command signals in a memory controller and the input characteristics of the circuitry used to receive address / command signals in a memory device are generally equivalent because these circuits are typically constructed from the same circuitry used for all address / command signals. Therefore, it is expected that signal lines S10A1, S20A1, S10A2, and S20A2 have equivalent characteristic impedances.

[0169] In the second embodiment, the width of signal trace S11A1 is smaller than the width of signal trace S21A1. That is, the width D1A1 of signal trace S11A1 is smaller than the width D2A1 of signal trace S21A1. Similarly, the width of signal trace S11A2 is smaller than the width of signal trace S21A2. That is, the width D1A2 of signal trace S11A2 is smaller than the width D2A2 of signal trace S21A2.

[0170] Therefore, by reducing the width D1A1, the characteristic impedance of signal trace S11A1 is made closer to the characteristic impedance of signal trace S21A1, which is closer to air. That is, the characteristic impedance of signal trace S11A1 is approximately equal to that of signal trace S21A1. Similarly, by reducing the width D1A2, the characteristic impedance of signal trace S11A2 is made closer to the characteristic impedance of signal trace S21A2, which is closer to air. That is, the characteristic impedance of signal trace S11A2 is approximately equal to that of signal trace S21A2. Therefore, the width of ground trace G1A in conductor layer L2 can be increased, thus stabilizing the characteristics of ground trace G1A.

[0171] Furthermore, when viewed from the Z direction, preferably, a portion or all of the wiring pattern deployed in the conductor layer L2 in the Y direction overlaps with a portion or all of the wiring pattern deployed in the conductor layer L4 in the Y direction. For example, when viewed from the Z direction, a portion or all of the signal trace S11A1 in the Y direction may overlap with a portion or all of the signal trace S21A1 in the Y direction. This also applies to ground traces G1A and G2A.

[0172] Third Embodiment

[0173] The third embodiment will be described. Figure 8 This is a cross-sectional view of the printed wiring board 200B according to the third embodiment. In the third embodiment, the printed wiring board 200B is used instead of the printed wiring board 200 in the control module 110 of the first embodiment. Other components are substantially the same as in the first embodiment. In the third embodiment, the same symbols are used to label the components that are substantially the same as in the first embodiment, and their descriptions are omitted.

[0174] Similar to the printed wiring board 200 of the first embodiment, the printed wiring board 200B of the third embodiment is a four-layer board. The printed wiring board 200B includes signal lines S10B1 and S10B2, which serve as examples of first signal lines, and signal lines S20B1 and S20B2, which serve as examples of second signal lines. Furthermore, the printed wiring board 200B includes a ground trace G1B, which serves as an example of a first ground trace, and a ground trace G2B, which serves as an example of a second ground trace.

[0175] Signal line S10B1 includes signal trace S11B1, which serves as an example of a first signal trace. Signal line S10B2 includes signal trace S11B2, which serves as an example of a first signal trace. Signal line S20B1 includes signal trace S21B1, which serves as an example of a second signal trace. Signal line S20B2 includes signal trace S21B2, which serves as an example of a second signal trace. Signal traces S11B1 and S11B2 are deployed in conductor layer L2. Ground trace G1B is deployed at the same location in the Z direction as signal traces S11B1 and S11B2, i.e., in the same conductor layer L2. Signal traces S21B1 and S21B2 are deployed in conductor layer L4, i.e., on main surface 202. Ground trace G2B is deployed at the same location in the Z direction as signal traces S21B1 and S21B2, i.e., in the same conductor layer L4. That is, the grounding trace G2B is deployed on the main surface 202.

[0176] Ground trace G1B extends along signal trace S11B1 in the X direction, such that signal trace S11B1 lies between the two portions of ground trace G1B in the width direction W1B1 of signal trace S11B1. Similarly, ground trace G1B extends along signal trace S11B2 in the X direction, such that signal trace S11B2 lies between the two portions of ground trace G1B in the width direction W1B2 of signal trace S11B2.

[0177] Furthermore, the ground trace G2B extends along the signal trace S21B1 in the X direction, such that the signal trace S21B1 lies between the two portions of the ground trace G2B in its width direction W2B1. Similarly, the ground trace G2B extends along the signal trace S21B2 in the X direction, such that the signal trace S21B2 lies between the two portions of the ground trace G2B in its width direction W2B2. Figure 8 In the diagram, signal traces S11B1, S11B2, S21B1, and S21B2 all extend in the X direction, therefore the width directions W1B1, W1B2, W2B1, and W2B2 are parallel to the Y direction.

[0178] Viewed from the Z direction, at least a portion of signal trace S11B1 overlaps with at least a portion of signal trace S21B1. Therefore, further miniaturization of the printed wiring board 200B is possible. Viewed from the Z direction, half or more of the area of ​​signal trace S11B1 preferably overlaps with half or more of the area of ​​signal trace S21B1. Signal traces S11B2 and S21B2 are also arranged in substantially the same manner. Furthermore, viewed from the Z direction, at least a portion of ground trace G1B overlaps with at least a portion of ground trace G2B. Therefore, ground trace G1B and ground trace G2B can be interconnected, for example, via via conductors, thus making it easier to electrically connect ground trace G1B to ground trace G2B.

[0179] Here, an insulating layer is disposed on both sides of each of the signal traces S11B1 and S11B2 deployed within the printed wiring board 200B in the Z direction. In contrast, solder resist or air is present on one side of each of the signal traces S21B1 and S21B2 deployed in the conductor layer L4, which serves as the outer layer. The solder resist is thinner than the insulating layer. Furthermore, the dielectric constant of the solder resist and air is lower than that of the epoxy resin constituting the insulating layer. As described above, the dielectric constant around the signal traces S21B1 and S21B2, which are closer to the air, is lower than that of the signal traces S11B1 and S11B2. Moreover, in a four-layer through-type board, the thickness of the conductor layer L2 is often set to be greater than the thickness of the conductor layer L4.

[0180] The output characteristics of the circuitry used to transmit address / command signals in a memory controller and the input characteristics of the circuitry used to receive address / command signals in a memory device are generally equivalent because these circuits are typically constructed from the same circuitry used for all address / command signals. Therefore, it is expected that signal lines S10B1, S20B1, S10B2, and S20B2 have equivalent characteristic impedances.

[0181] In the third embodiment, the distance D1B1 between signal trace S11B1 and ground trace G1B is greater than the distance D2B1 between signal trace S21B1 and ground trace G2B. Similarly, the distance D1B2 between signal trace S11B2 and ground trace G1B is greater than the distance D2B2 between signal trace S21B2 and ground trace G2B.

[0182] Therefore, by increasing the distance D1B1, the characteristic impedance of signal trace S11B1 is made closer to the characteristic impedance of signal trace S21B1, which is closer to air. That is, the characteristic impedance of signal trace S11B1 is approximately equal to that of signal trace S21B1. Similarly, by increasing the distance D1B2, the characteristic impedance of signal trace S11B2 is made closer to the characteristic impedance of signal trace S21B2, which is closer to air. That is, the characteristic impedance of signal trace S11B2 is approximately equal to that of signal trace S21B2. Therefore, the width of ground trace G2B in conductor layer L4 can be increased, thus stabilizing the characteristics of ground trace G2B.

[0183] Furthermore, when viewed from the Z direction, preferably, a portion or all of the wiring pattern deployed in the conductor layer L2 in the Y direction overlaps with a portion or all of the wiring pattern deployed in the conductor layer L4 in the Y direction. For example, when viewed from the Z direction, a portion or all of the signal trace S11B1 in the Y direction may overlap with a portion or all of the signal trace S21B1 in the Y direction. This also applies to ground traces G1B and G2B.

[0184] Fourth embodiment

[0185] The fourth embodiment will be described. Figure 9A This is a plan view of the control module 110C according to the fourth embodiment, which serves as an electronic module. Figure 9B This is a cross-sectional view of the control module 110C according to the fourth embodiment. Figure 9B Schematic illustration along Figure 9A The control module 110C is shown as a cross section intercepted by line IXB-IXB. Figure 9C This is a cross-sectional view of the printed wiring board 200C according to the fourth embodiment. Figure 9C Schematic illustration along Figure 9B The cross-section of the printed wiring board 200C is taken by line IXC-IXC. In the fourth embodiment, control module 110C is used instead of control module 110 in the first embodiment. Other components are substantially the same as in the first embodiment. In the fourth embodiment, the same symbols are used for components that are substantially the same as in the first embodiment, and their descriptions are omitted.

[0186] Similar to the first embodiment, the control module 110C includes a memory controller 130 and a memory device 140. Furthermore, the control module 110C includes a printed wiring board 200C. The printed wiring board 200C is a rigid printed wiring board. Moreover, the printed wiring board 200C is a through-hole board. By using a through-hole board as the printed wiring board 200C, productivity can be high and production costs can be low.

[0187] Memory controller 130 and memory device 140 are deployed on printed wiring board 200C so as not to overlap when viewed from the Z direction. Furthermore, memory controller 130 and memory device 140 are deployed on printed wiring board 200C opposite to each other in the X direction, such that edges 131 of memory controller 130 and edges 141 of memory device 140 are parallel to each other when viewed from the Z direction. In a fourth embodiment, both memory controller 130 and memory device 140 are deployed on the main surface 201 of the two main surfaces 201 and 202 of printed wiring board 200C. Figure 9B As shown, similar to the first embodiment, the distance D1 between signal terminal 12 and signal terminal 13 is greater than the distance D2 between signal terminal 11 and signal terminal 14. Furthermore, similar to the first embodiment, the distance D3 between signal terminal 13 and signal terminal 14 is greater than the distance D4 between signal terminal 11 and signal terminal 12.

[0188] Similar to the first embodiment, the printed wiring board 200C is a laminate comprising at least four conductor layers L1 to L4. The conductor layers L1 to L4 are arranged from the main surface 201 toward the main surface 202 in the order of conductor layer L1, conductor layer L2, conductor layer L3, and conductor layer L4. Similar to the first embodiment, the printed wiring board 200C includes multiple signal lines S10 that electrically connect multiple signal terminals 12 of the memory controller 130 to multiple signal terminals 13 of the memory device 140 in a one-to-one relationship. Furthermore, the printed wiring board 200C includes multiple signal lines S20C that electrically connect multiple signal terminals 11 of the memory controller 130 to multiple signal terminals 14 of the memory device 140 in a one-to-one relationship. In the fourth embodiment, the configuration of the signal lines S20C differs from the configuration of the signal lines S20 in the first embodiment.

[0189] Signal lines S10 each serve as an example of a first signal line. Signal lines S20C each serve as an example of a second signal line. The wiring width of each of signal lines S10 and S20C is preferably 75 μm or greater. It should be noted that... Figure 9B Only one signal line S10 and one signal line S20C are shown.

[0190] The following description focuses on a signal line S10 and a signal line S20C. Signal line S10 includes signal trace S11, signal via S12, signal via S13, and signal trace S14, which serve as examples of a first signal trace. Signal line S20C includes signal trace S21C, which serves as an example of a second signal trace. Signal trace S21C is deployed in conductor layer L3. It should be noted that power traces or ground traces (not shown) may be deployed in each of conductor layers L1 and L4.

[0191] Furthermore, signal line S20C includes signal via S22C and signal via S23C. Signal via S22C is a via conductor that electrically interconnects signal terminal 11 and signal trace S21C by contacting a signal trace (not shown) connected to signal terminal 11 in conductor layer L1 and a signal trace S21C in conductor layer L3. In the fourth embodiment, signal via S22C is a portion of a through-hole located between conductor layer L1 and conductor layer L3.

[0192] The signal via S23C is a via conductor that electrically interconnects the signal terminal 14 and the signal trace S21C by contacting the signal trace (not shown) connected to the signal terminal 14 in the conductor layer L1 and the signal trace S21C in the conductor layer L3. In the fourth embodiment, the signal via S23C is a portion of a through-hole between the conductor layer L1 and the conductor layer L3.

[0193] As described above, since signal lines S10 and S20C have the aforementioned wiring structure in the printed wiring board 200C, the difference between the path lengths of signal lines S10 and S20C is reduced. Therefore, the tortuous wiring of signal lines S10 and S20C can be shortened or omitted, thereby reducing the wiring area of ​​each of signal lines S10 and S20C when viewed from the Z direction, and reducing the time delay difference of the address / command signal between signal terminals 13 and 14. Therefore, signal quality is improved, and miniaturization of the printed wiring board 200C, i.e., miniaturization of the control module 110C, is achieved.

[0194] like Figure 9C As shown, the two signal traces S11 of two signal lines S10 among the multiple signal lines S10 are referred to as signal traces S111 and S112. Furthermore, as... Figure 9C As shown, the two signal traces S21C of two signal lines S20C among the multiple signal lines S20C are called signal traces S21C1 and S21C2.

[0195] The printed wiring board 200C includes ground traces G1 and G2C. Ground trace G1 serves as an example of a first ground trace. Ground trace G2C serves as an example of a second ground trace. Ground trace G1 and signal traces S111 and S112 are deployed at the same location in the Z direction, i.e., deployed in the same conductor layer L2. Ground trace G2C and signal traces S21C1 and S21C2 are deployed at the same location in the Z direction, i.e., deployed in the same conductor layer L3.

[0196] Furthermore, ground trace G1 extends along signal trace S111 in the X direction, such that signal trace S111 lies between the two portions of ground trace G1 in the width direction W11 of signal trace S111. Similarly, ground trace G1 extends along signal trace S112 in the X direction, such that signal trace S112 lies between the two portions of ground trace G1 in the width direction W12 of signal trace S112.

[0197] Furthermore, the ground trace G2C extends along the signal trace S21C1 in the X direction, such that the signal trace S21C1 lies between the two portions of the ground trace G2C in its width direction W2C1. Similarly, the ground trace G2C extends along the signal trace S21C2 in the X direction, such that the signal trace S21C2 lies between the two portions of the ground trace G2C in its width direction W2C2. Figure 9C In the diagram, signal traces S111, S112, S21C1, and S21C2 all extend in the X direction, therefore the width directions W11, W12, W2C1, and W2C2 are parallel to the Y direction.

[0198] As described above, in the fourth embodiment, the ground trace G2C is deployed on both sides of each of the signal traces S21C1 and S21C2 in the Y direction, and the ground trace G2C has an insulator between it and each of the signal traces S21C1 and S21C2 in the Y direction. That is, the ground trace G2C at the reference potential is deployed adjacent to each of the signal traces S21C1 and S21C2, and the ground trace G2C has an insulator between it and each of the signal traces S21C1 and S21C2, such that each of the signal traces S21C1 and S21C2 is located between the ground trace G2C. Due to the ground trace G2C, the path of the return current corresponding to the signal flowing in each of the signal traces S21C1 and S21C2 can be ensured, thus reducing the characteristic impedance mismatch in each of the signal traces S20C. Therefore, signal reflection in each of the signal traces S20C can be reduced. Therefore, signal quality is improved, and radiated noise can be further reduced. Furthermore, since there is a ground trace G2C between each pair of signal lines S20C, crosstalk in each signal line S20C can also be reduced, thereby improving signal quality. The same effect is achieved for signal line S10.

[0199] It should be noted that power traces for supplying power potential to the memory controller 130 and the memory device 140 can be formed in conductor layer L4. Alternatively, power traces for supplying power potential can be formed in conductor layer L1 to form a ground trace in conductor layer L4.

[0200] Viewed from the Z direction, at least a portion of signal trace S111 overlaps with at least a portion of signal trace S21C1. Therefore, further miniaturization of the printed wiring board 200C can be achieved. Viewed from the Z direction, half or more of the area of ​​signal trace S111 preferably overlaps with half or more of the area of ​​signal trace S21C1. Signal traces S112 and S21C2 are also arranged in substantially the same manner. Furthermore, viewed from the Z direction, at least a portion of ground trace G1 overlaps with at least a portion of ground trace G2C. Therefore, ground trace G1 and ground trace G2C can be interconnected, for example, via via conductors, thus making it easier to electrically connect ground trace G1 to ground trace G2C.

[0201] Example 4-1

[0202] In the corresponding fourth embodiment Figure 9B In the wiring structure shown, the wiring length difference ΔdC between the wiring length of signal line S10 and the wiring length of signal line S20C is obtained.

[0203] The distance from signal terminal 11 to signal terminal 12 in the X1 direction is represented by Δd1C. The distance from signal terminal 13 to signal terminal 14 in the X1 direction is represented by Δd2C. The difference obtained by subtracting the sum of the lengths of signal vias S22C and S23C in the Z1 direction from the sum of the lengths of signal vias S12 and S13 in the Z1 direction is represented by Δd3C. The difference in wiring length ΔdC between the wiring length of signal line S10 and the wiring length of signal line S20C can be roughly calculated by ΔdC = Δd1C + Δd2C + Δd3C. It should be noted that the cross-sectional structure of the printed wiring board 200C is set to be consistent with... Figure 3C The printed wiring board 200 of the first embodiment shown has the same cross-sectional structure.

[0204] Calculate Δd1C, Δd2C, and Δd3C under the above conditions, and the results are as follows.

[0205] Δd1C = 0.8 mm × (-3 pitch) = -2.4 mm

[0206] Δd2C=0.8mm×(6 pitch)=4.8mm

[0207] Δd3C = (0.1mm × 2 through holes) – (1.5mm × 2 through holes) = -2.8mm

[0208] The difference in wiring length ΔdC between signal line S10 and signal line S20C is as follows.

[0209] ΔdC=(-2.4mm)+(4.8mm)+(-2.8mm)=-0.4mm

[0210] Therefore, in Example 4-1, the wiring length difference ΔdC can be reduced compared to Comparative Example 1-1. As described above, the wiring length difference ΔdC can also be reduced in the configuration where signal trace S21C is deployed in conductor layer L3. Furthermore, all signal lines S10 and S20C can be provided in the printed wiring board 200C.

[0211] Example 4-2

[0212] Figure 10A These are cross-sectional views of the three printed wiring boards in Example 4-2. Figure 10A A wiring structure including wiring patterns formed in conductor layer L2 and wiring patterns formed in conductor layer L3 is shown.

[0213] Structure 1 corresponds to the first wiring structure in Example 4-2. Signal traces Sig1 and Sig2, and ground trace GND1 are deployed in conductor layer L2. Signal traces Sig3 and Sig4, and ground trace GND2 are deployed in conductor layer L3. Ground trace GND1 or GND2 is deployed in the Y direction on both sides of signal traces Sig1 to Sig4, separated by an insulator. The width of each wiring trace is set to 125 μm, and the spacing between wiring traces is set to 87.5 μm.

[0214] Structure 2 corresponds to the second wiring structure in Example 4-2. Signal traces Sig1 and Sig2, and ground trace GND1 are deployed in conductor layer L2. Signal traces Sig3 to Sig5, and ground trace GND2 are deployed in conductor layer L3. Signal traces Sig1 to Sig5 are each deployed opposite ground trace GND1 or GND2 in the Y direction, separated by an insulator. Ground trace GND1 or GND2 is deployed on both sides of signal traces Sig1, Sig2, and Sig4 in the Y direction, separated by an insulator. On one side of each of signal traces Sig3 and Sig5 in the Y direction, other signal lines (not shown) or through-holes (not shown) set to power supply potential are deployed opposite signal traces Sig3 or Sig5, separated by an insulator. On the other hand, ground trace GND2 is deployed opposite signal traces Sig3 and Sig5, separated by an insulator. The wiring width and pitch in Structure 2 are the same as those in Structure 1. In Structure 2, for the conditions used to compare the aforementioned electrical characteristics, only signal traces Sig1 to Sig4 are compared. This is because the electrical characteristics of signal trace Sig5 can be considered equivalent to the electrical characteristics of signal trace Sig3.

[0215] Structure 3 corresponds to the wiring structure of the comparative example. A ground trace GND1 or GND2 is deployed across one side of each of the signal traces Sig1 to Sig4 in the Y direction, separated by an insulator. Simultaneously, signal traces Sig1 and Sig2 are deployed opposite each other in the Y direction, separated by an insulator, and signal traces Sig3 and Sig4 are also deployed opposite each other in the Y direction, separated by an insulator. The width of each of the ground traces GND1 and GND2 in the Y direction is set to 218.5 μm.

[0216] In the cross-sectional structure of the printed wiring board in each of structures 1 to 3, the distance t0 in the Z direction between conductor layers L2 and L3 is set to 400 μm. The other dimensions of each of the conductor layers and insulating layers are set to be the same as in Examples 1-2.

[0217] Figure 10B This is a graph showing the calculated characteristic impedances of the signal traces Sig1 to Sig4 in structures 1 to 3.

[0218] In structure 1, the characteristic impedance of each of the signal traces Sig1 to Sig4 is constant at 50Ω.

[0219] In structure 2, each of the signal traces Sig1, Sig2, and Sig4 has a characteristic impedance of 50Ω, with ground traces GND1 or GND2 deployed on both sides of the signal traces Sig1, Sig2, and Sig4 separated by an insulator. In contrast, the characteristic impedance of the signal trace Sig3, which has a ground trace GND2 deployed on only one side separated by an insulator, increases to 67Ω.

[0220] In structure 3, the characteristic impedance of each of the signal traces Sig1 to Sig4 is 59Ω, which is a high value.

[0221] Therefore, by adopting the wiring structure of Structure 1, the characteristic impedance of signal traces Sig1 to Sig4 can be uniformized and reduced. That is, considering the characteristic impedance, the wiring structures of Structures 1 and 2 are preferred, and the wiring structure of Structure 1 is the most preferred. It should be noted that in Structure 2, the shape of the signal waveform derived from the characteristic impedance can be improved, for example, by using terminating resistors.

[0222] Figure 10C This is a graph showing the calculated crosstalk coefficient between two signal traces in structures 1 to 3. When the common-mode impedance in the two signal traces is represented by Zc and the differential-mode impedance by Zd, the crosstalk coefficient can be calculated by (Zc–Zd) / (Zc+Zd).

[0223] In structures 1 and 2, signal traces Sig1 and Sig3, separated by an insulating layer between conductor layers L2 and L3, are most strongly electromagnetically coupled. The crosstalk coefficient in structure 1 is 0.056. The crosstalk coefficient in structure 2 is 0.062. In contrast, the crosstalk coefficient in structure 3 is greater than that in both structure 1 and structure 2. Furthermore, with a distance t0 set to 300 μm, the crosstalk coefficient in structure 2 is confirmed to be lower than that in structure 1.

[0224] The distance between signal trace Sig1 or Sig2 and ground trace GND1 in the Y direction will be denoted by t1, and the distance between signal trace Sig3 or Sig4 and ground trace GND2 will be denoted by t2. In structures 1 and 2, distance t0 is preferably four times or more the shorter of distances t1 and t2. In particular, in structure 1, distance t0 is preferably four times or more the shorter of distances t1 and t2. Under these conditions, crosstalk between signal traces Sig1 and Sig3, and between signal traces Sig2 and Sig4, can be effectively reduced. In particular, crosstalk can be reduced more effectively in structure 1.

[0225] Fifth embodiment

[0226] The fifth embodiment will be described. Figure 11A This is a plan view of the control module 110D according to the fifth embodiment, which serves as an electronic module. Figure 11B This is a cross-sectional view of the control module 110D according to the fifth embodiment. Figure 11B Schematic illustration along Figure 11A The control module 110D is shown as a cross section cut by line XIB-XIB. Figure 11C This is a cross-sectional view of the printed wiring board 200D according to the fifth embodiment. Figure 11C Schematic illustration along Figure 11B The cross-section of the printed wiring board 200D is taken by line XIC-XIC. In the fifth embodiment, control module 110D is used instead of control module 110 in the first embodiment. Other components are substantially the same as in the first embodiment. In the fifth embodiment, the same symbols are used for components that are substantially the same as in the first embodiment, and their descriptions are omitted.

[0227] Similar to the first embodiment, the control module 110D includes a memory controller 130 and a memory device 140. Furthermore, the control module 110D includes a printed wiring board 200D. The printed wiring board 200D is a rigid printed wiring board. Moreover, the printed wiring board 200D is a through-hole board. By using a through-hole board as the printed wiring board 200D, productivity can be high and production costs can be low.

[0228] Memory controller 130 and memory device 140 are deployed on printed wiring board 200D so as not to overlap when viewed in the Z direction. Furthermore, memory controller 130 and memory device 140 are deployed on printed wiring board 200D opposite to each other in the X direction, such that edges 131 of memory controller 130 and edges 141 of memory device 140 are parallel to each other when viewed in the Z direction. In a fifth embodiment, memory controller 130 and memory device 140 are deployed on different main surfaces of two main surfaces 201 and 202 of printed wiring board 200D, respectively. Figure 11A and Figure 11B In the example, memory controller 130 is deployed on main surface 201, while memory device 140 is deployed on main surface 202. It should be noted that memory device 140 can be deployed on main surface 201, while memory controller 130 can be deployed on main surface 202.

[0229] like Figure 11B As shown, similar to the first embodiment, the distance D1 between signal terminal 12 and signal terminal 13 is greater than the distance D2 between signal terminal 11 and signal terminal 14. Furthermore, similar to the first embodiment, the distance D3 between signal terminal 13 and signal terminal 14 is greater than the distance D4 between signal terminal 11 and signal terminal 12.

[0230] Similar to the first embodiment, the printed wiring board 200D is a laminate comprising at least four conductor layers L1 to L4. The conductor layers L1 to L4 are arranged from the main surface 201 toward the main surface 202 in the order of conductor layer L1, conductor layer L2, conductor layer L3, and conductor layer L4. The printed wiring board 200D includes multiple signal lines S10D that electrically connect multiple signal terminals 12 of the memory controller 130 to multiple signal terminals 13 of the memory device 140 in a one-to-one relationship. Furthermore, the printed wiring board 200D includes multiple signal lines S20D that electrically connect multiple signal terminals 11 of the memory controller 130 to multiple signal terminals 14 of the memory device 140 in a one-to-one relationship. In the fifth embodiment, the configuration of signal lines S10D and S20D differs from the configuration of signal lines S10 and S20 in the first embodiment.

[0231] Signal lines S10D each serve as an example of a first signal line. Signal lines S20D each serve as an example of a second signal line. The wiring width of each of signal lines S10D and S20D is preferably 75 μm or greater. It should be noted that... Figure 11B Only one signal line S10D and one signal line S20D are shown.

[0232] The following description will focus on a signal line S10D and a signal line S20D. Signal line S10D includes signal trace S11D, signal via S12D, signal via S13D, and signal trace S14D, which serve as examples of first signal traces. Signal trace S14D is disposed in conductor layer L1 and is electrically connected to signal terminal 12 by contact with signal terminal 12. Signal trace S11D is disposed in conductor layer L2.

[0233] The signal via S12D is a via conductor that electrically interconnects the signal terminal 12 and the signal trace S11D by contacting the signal trace S14D in the conductor layer L1 and the signal trace S11D in the conductor layer L2. In this embodiment, the signal via S12D is a portion of the through-hole between the conductor layer L1 and the conductor layer L2.

[0234] The signal via S13D is a via conductor that electrically interconnects the signal terminal 13 and the signal trace S11D by contacting the signal trace (not shown) connected to the signal terminal 13 in the conductor layer L4 and the signal trace S11D in the conductor layer L2. In this embodiment, the signal via S13D is a portion of the through-hole between the conductor layer L2 and the conductor layer L4.

[0235] Signal line S20D includes signal trace S21D, signal via S22D, and signal via S23D, which serve as examples of second signal traces. Signal trace S21D is deployed in conductor layer L3.

[0236] The signal via S22D is a via conductor that electrically interconnects the signal terminal 11 and the signal trace S21D by contacting the signal trace (not shown) connected to the signal terminal 11 in the conductor layer L1 and the signal trace S21D in the conductor layer L3. In the fifth embodiment, the signal via S22D is a portion of a through-hole between the conductor layer L1 and the conductor layer L3.

[0237] The signal via S23D is a via conductor that electrically interconnects the signal terminal 14 and the signal trace S21D by contacting the signal trace (not shown) connected to the signal terminal 14 in the conductor layer L4 and the signal trace S21D in the conductor layer L3. In the fifth embodiment, the signal via S23D is a portion of a through-hole between the conductor layers L3 and L4. Note that a power trace (not shown) or a ground trace (not shown) may be deployed in each of the conductor layers L1 and L4.

[0238] As described above, since signal lines S10D and S20D have the aforementioned wiring structure in the printed wiring board 200D, the difference between the path lengths of signal lines S10D and S20D is reduced. Therefore, the tortuous wiring of signal lines S10D and S20D can be shortened or omitted, thereby reducing the wiring area of ​​each of signal lines S10D and S20D when viewed from the Z direction, and reducing the time delay difference of the address / command signal between signal terminals 13 and 14. Therefore, signal quality is improved, and miniaturization of the printed wiring board 200D, i.e., miniaturization of the control module 110D, is achieved.

[0239] like Figure 11C As shown, two signal traces S11D of two signal lines S10D among the multiple signal lines S10D are referred to as signal traces S11D1 and S11D2. Furthermore, as... Figure 11C As shown, the two signal traces S21D of two signal lines S20D among the multiple signal lines S20D are referred to as signal traces S21D1 and S21D2.

[0240] The printed wiring board 200D includes ground traces G1D and G2D. Ground trace G1D serves as an example of a first ground trace. Ground trace G2D serves as an example of a second ground trace. Ground trace G1D and signal traces S11D1 and S11D2 are deployed at the same location in the Z direction, i.e., deployed in the same conductor layer L2. Ground trace G2D and signal traces S21D1 and S21D2 are deployed at the same location in the Z direction, i.e., deployed in the same conductor layer L3.

[0241] Furthermore, the ground trace G1D extends along the signal trace S11D1 in the X direction, such that the signal trace S11D1 lies between the two portions of the ground trace G1D in the width direction W1D1 of the signal trace S11D1. Similarly, the ground trace G1D extends along the signal trace S11D2 in the X direction, such that the signal trace S11D2 lies between the two portions of the ground trace G1D in the width direction W1D2 of the signal trace S11D2.

[0242] Furthermore, the ground trace G2D extends along the signal trace S21D1 in the X direction, such that the signal trace S21D1 lies between the two portions of the ground trace G2D in its width direction W2D1. Similarly, the ground trace G2D extends along the signal trace S21D2 in the X direction, such that the signal trace S21D2 lies between the two portions of the ground trace G2D in its width direction W2D2. Figure 11CIn the diagram, signal traces S11D1, S11D2, S21D1, and S21D2 all extend in the X direction, therefore the width directions W1D1, W1D2, W2D1, and W2D2 are parallel to the Y direction.

[0243] As described above, in the fifth embodiment, the ground trace G1D is deployed on both sides of each of the signal traces S11D1 and S11D2. That is, the ground trace G1D at the reference potential is deployed opposite each of the signal traces S11D1 and S11D2, separated by an insulator, such that each of the signal traces S11D1 and S11D2 is located between two portions of the ground trace G1D. Due to the ground trace G1D, a path for the return current corresponding to the signal flowing in each of the signal traces S11D1 and S11D2 can be ensured, thus reducing the characteristic impedance mismatch of each of the signal traces S10D. Therefore, signal reflection in each of the signal traces S10D can be reduced. Thus, signal quality is improved, and radiated noise can be further reduced. Furthermore, since there is a ground trace G1D between each pair of signal traces S10D, crosstalk in each signal trace S10D can also be reduced, thereby improving signal quality. The same effect is obtained for the signal trace S20D.

[0244] Viewed from the Z direction, at least a portion of signal trace S11D1 overlaps with at least a portion of signal trace S21D1. Therefore, further miniaturization of the printed wiring board 200D can be achieved. Viewed from the Z direction, half or more of the area of ​​signal trace S11D1 preferably overlaps with half or more of the area of ​​signal trace S21D1. Signal traces S11D2 and S21D2 are also arranged in substantially the same manner. Furthermore, viewed from the Z direction, at least a portion of ground trace G1D overlaps with at least a portion of ground trace G2D. Therefore, ground trace G1D and ground trace G2D can be interconnected, for example, through via conductors, thus making it easier to electrically connect ground trace G1D to ground trace G2D.

[0245] Example 5

[0246] In the corresponding fifth embodiment Figure 11B In the wiring structure shown, the wiring length difference ΔdD between the wiring length of signal line S10D and the wiring length of signal line S20D is obtained.

[0247] The distance from signal terminal 11 to signal terminal 12 in the X1 direction is represented by Δd1D. The distance from signal terminal 13 to signal terminal 14 in the X1 direction is represented by Δd2D. The difference obtained by subtracting the sum of the lengths of signal vias S22D and S23D in the Z1 direction from the sum of the lengths of signal vias S12D and S13D in the Z1 direction is represented by Δd3D. The difference in wiring length ΔdD between the wiring length of signal line S10D and the wiring length of signal line S20D can be roughly calculated by ΔdD = Δd1D + Δd2D + Δd3D. It should be noted that the cross-sectional structure of the printed wiring board 200D is set to be consistent with... Figure 3C The printed wiring board 200 of the first embodiment shown has the same cross-sectional structure.

[0248] Δd1D, Δd2D, and Δd3D were calculated under the above conditions, and the results are as follows.

[0249] Δd1D = 0.8mm × (-3 pitch) = -2.4mm

[0250] Δd2D=0.8mm×(6 pitch)=4.8mm

[0251] Δd3D=(0.1mm+1.5mm)–(1.5mm+0.1mm)=0mm

[0252] The difference in wiring length ΔdD between signal line S10 and signal line S20D is as follows.

[0253] ΔdD=(-2.4mm)+(4.8mm)+(0mm)=2.4mm

[0254] Therefore, in Example 5, the wiring length difference ΔdD can be reduced compared to Comparative Example 1-1. As described above, the wiring length difference ΔdD can also be reduced in a configuration where the memory controller 130 and the memory device 140 are deployed on different main surfaces of the printed wiring board 200D. Furthermore, all signal lines S10D and S20D can be provided in the printed wiring board 200D.

[0255] The distance between conductor layer L2 and conductor layer L3 in the Z direction is preferably four times or more the shorter of the distance between signal trace S11D and ground trace G1D in the Y direction and the distance between signal trace S21D and ground trace G2D in the Y direction.

[0256] It should be noted that although the case where signal traces S11D and S21D are deployed inside the printed wiring board 200D, i.e., deployed in conductor layers L2 and L3 as inner layers respectively, has been described, the configuration is not limited to this. For example, when signal trace S11D is deployed in an inner layer, signal trace S21D can be deployed on the main surface 202, i.e., in conductor layer L4. Furthermore, when signal trace S21D is deployed in an inner layer, signal trace S11D can be deployed on the main surface 201, i.e., in conductor layer L1.

[0257] This invention is not limited to the embodiments described above, and can be modified in various ways within the scope of the technical concept disclosed herein. Furthermore, the effects described in the embodiments are merely an enumeration of the most preferred effects obtainable from this invention, and the effects of this disclosure are not limited to those described in the embodiments.

[0258] While the above embodiments describe the electronic module as a control module of a storage system including a memory controller and a memory device, the configuration is not limited thereto. This disclosure prefers an electronic module in which multiple signals are synchronously transmitted between a first semiconductor element and a second semiconductor element.

[0259] Furthermore, although the above embodiments describe a printed wiring board as a four-layer board comprising four conductor layers, the configuration is not limited to this. This disclosure also prefers a multilayer board comprising four or more conductor layers. The substrate of the printed wiring board can be an inorganic insulator such as ceramic. As a wiring board having similar functions to a printed wiring board, a silicon interposer in which the conductor layers are formed using semiconductor manufacturing techniques can be used. In a wiring board that serves as a silicon interposer, the vias can be through-silicon vias (TSVs). The electronic module can be a 2.5D-IC with semiconductor elements mounted in 2.5D on the wiring board, or a 3D-IC with semiconductor elements mounted in 3D on the wiring board, and the semiconductor elements mounted on the wiring board can be referred to as chips or chip assemblies. The bonding between the wiring board and the semiconductor elements is not limited to solder bonding, and can be a direct metal-to-metal bonding, or a hybrid bonding using both insulator bonding and metal bonding.

[0260] Furthermore, although the above embodiments describe the electronic device as an image forming apparatus, the configuration is not limited thereto. The electronic module of this disclosure is applicable to any electronic device. For example, the electronic module of the present invention is applicable to electronic devices such as image pickup devices (e.g., digital cameras), smartphones, tablet PCs, desktop PCs, laptop PCs, and gaming devices.

[0261] According to this disclosure, an electronic module in which signal quality is improved and miniaturization is achieved can be provided.

[0262] While the invention has been described with reference to exemplary embodiments, it should be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the appended claims should be given the broadest interpretation to cover all such modifications and equivalent structures and functions.

Claims

1. An electronic module, characterized in that, The electronic module includes: A wiring board having a first main surface and a second main surface on the back side of the first main surface; and A first semiconductor element and a second semiconductor element are mounted on the wiring board. In this configuration, at least one of the first semiconductor element or the second semiconductor element is deployed on one side of the first main surface. The first semiconductor element includes a first signal terminal and a second signal terminal, wherein the second signal terminal is closer to the second semiconductor element than the first signal terminal. The second semiconductor element includes a third signal terminal and a fourth signal terminal, wherein the fourth signal terminal is closer to the first semiconductor element than the third signal terminal. The wiring board includes A first signal line is configured to electrically interconnect the second signal terminal and the third signal terminal and includes a first signal trace deployed in a first conductor layer. A second signal line is configured to electrically interconnect the first signal terminal and the fourth signal terminal and includes a second signal trace deployed in a second conductor layer, the second conductor layer being closer to the second main surface than the first conductor layer. A first ground trace is deployed in the first conductor layer and extends along the first signal trace, such that the first signal trace is located between two portions of the first ground trace in the width direction of the first signal trace. A second ground trace is disposed in the second conductor layer and extends along the second signal trace, such that the second signal trace is located between two portions of the second ground trace in the width direction of the second signal trace. Wherein, the distance between the second signal terminal and the third signal terminal is greater than the distance between the first signal terminal and the fourth signal terminal, and / or the distance between the third signal terminal and the fourth signal terminal is greater than the distance between the first signal terminal and the second signal terminal.

2. The electronic module according to claim 1, wherein, The distance between the second signal terminal and the third signal terminal is greater than the distance between the first signal terminal and the fourth signal terminal.

3. The electronic module according to claim 1, wherein, The distance between the third signal terminal and the fourth signal terminal is greater than the distance between the first signal terminal and the second signal terminal.

4. The electronic module according to claim 1, wherein, When viewed from a direction perpendicular to the first main surface, at least a portion of the first signal trace overlaps with at least a portion of the second signal trace.

5. The electronic module according to claim 1, wherein, When viewed from a direction perpendicular to the first main surface, at least a portion of the first ground trace overlaps with at least a portion of the second ground trace.

6. An electronic module, characterized in that, The electronic module includes: A wiring board having a first main surface and a second main surface on the back side of the first main surface; and A first semiconductor element and a second semiconductor element are mounted on the wiring board. In this configuration, at least one of the first semiconductor element or the second semiconductor element is deployed on one side of the first main surface. The first semiconductor element includes a first signal terminal and a second signal terminal, wherein the second signal terminal is closer to the second semiconductor element than the first signal terminal. The second semiconductor element includes a third signal terminal and a fourth signal terminal, wherein the fourth signal terminal is closer to the first semiconductor element than the third signal terminal. The wiring board includes A first signal line is configured to electrically interconnect the second signal terminal and the third signal terminal and includes a first signal trace deployed in a first conductor layer. A second signal line is configured to electrically interconnect the first signal terminal and the fourth signal terminal and includes a second signal trace deployed in a second conductor layer, the second conductor layer being closer to the second main surface than the first conductor layer. A first ground trace is deployed in the first conductor layer and extends along the first signal trace, such that the first signal trace is located between two portions of the first ground trace in the width direction of the first signal trace. A second ground trace is disposed in the second conductor layer and extends along the second signal trace, such that the second signal trace is located between two portions of the second ground trace in the width direction of the second signal trace. Wherein, the second conductor layer is deployed on the second main surface, and The width of the first signal trace is smaller than the width of the second signal trace.

7. An electronic module, characterized in that, The electronic module includes: A wiring board having a first main surface and a second main surface on the back side of the first main surface; and A first semiconductor element and a second semiconductor element are mounted on the wiring board. In this configuration, at least one of the first semiconductor element or the second semiconductor element is deployed on one side of the first main surface. The first semiconductor element includes a first signal terminal and a second signal terminal, wherein the second signal terminal is closer to the second semiconductor element than the first signal terminal. The second semiconductor element includes a third signal terminal and a fourth signal terminal, wherein the fourth signal terminal is closer to the first semiconductor element than the third signal terminal. The wiring board includes A first signal line is configured to electrically interconnect the second signal terminal and the third signal terminal and includes a first signal trace deployed in a first conductor layer. A second signal line is configured to electrically interconnect the first signal terminal and the fourth signal terminal and includes a second signal trace deployed in a second conductor layer, the second conductor layer being closer to the second main surface than the first conductor layer. A first ground trace is deployed in the first conductor layer and extends along the first signal trace, such that the first signal trace is located between two portions of the first ground trace in the width direction of the first signal trace. A second ground trace is disposed in the second conductor layer and extends along the second signal trace, such that the second signal trace is located between two portions of the second ground trace in the width direction of the second signal trace. Wherein, the second conductor layer is deployed on the second main surface, and The distance between the first signal trace and the first ground trace is greater than the distance between the second signal trace and the second ground trace.

8. An electronic module, characterized in that, The electronic module includes: A wiring board having a first main surface and a second main surface on the back side of the first main surface; and A first semiconductor element and a second semiconductor element are mounted on the wiring board. In this configuration, at least one of the first semiconductor element or the second semiconductor element is deployed on one side of the first main surface. The first semiconductor element includes a first signal terminal and a second signal terminal, wherein the second signal terminal is closer to the second semiconductor element than the first signal terminal. The second semiconductor element includes a third signal terminal and a fourth signal terminal, wherein the fourth signal terminal is closer to the first semiconductor element than the third signal terminal. The wiring board includes A first signal line is configured to electrically interconnect the second signal terminal and the third signal terminal and includes a first signal trace deployed in a first conductor layer. A second signal line is configured to electrically interconnect the first signal terminal and the fourth signal terminal and includes a second signal trace deployed in a second conductor layer, the second conductor layer being closer to the second main surface than the first conductor layer. A first ground trace is deployed in the first conductor layer and extends along the first signal trace, such that the first signal trace is located between two portions of the first ground trace in the width direction of the first signal trace. A second ground trace is disposed in the second conductor layer and extends along the second signal trace, such that the second signal trace is located between two portions of the second ground trace in the width direction of the second signal trace. The second conductor layer is disposed between the first conductor layer and the second main surface, and The distance between the first conductor layer and the second conductor layer is four times or more the smaller of the distance between the first signal trace and the first ground trace and the distance between the second signal trace and the second ground trace.

9. The electronic module according to claim 1, in, The first conductor layer is deployed within the wiring board, and The first semiconductor element and the second semiconductor element are deployed on one side of the first main surface.

10. An electronic module, characterized in that, The electronic module includes: A wiring board having a first main surface and a second main surface on the back side of the first main surface; and A first semiconductor element and a second semiconductor element are mounted on the wiring board. In this configuration, at least one of the first semiconductor element or the second semiconductor element is deployed on one side of the first main surface. The first semiconductor element includes a first signal terminal and a second signal terminal, wherein the second signal terminal is closer to the second semiconductor element than the first signal terminal. The second semiconductor element includes a third signal terminal and a fourth signal terminal, wherein the fourth signal terminal is closer to the first semiconductor element than the third signal terminal. The wiring board includes A first signal line is configured to electrically interconnect the second signal terminal and the third signal terminal and includes a first signal trace deployed in a first conductor layer. A second signal line is configured to electrically interconnect the first signal terminal and the fourth signal terminal and includes a second signal trace deployed in a second conductor layer, the second conductor layer being closer to the second main surface than the first conductor layer. A first ground trace is deployed in the first conductor layer and extends along the first signal trace, such that the first signal trace is located between two portions of the first ground trace in the width direction of the first signal trace. A second ground trace is disposed in the second conductor layer and extends along the second signal trace, such that the second signal trace is located between two portions of the second ground trace in the width direction of the second signal trace. The wiring board includes multiple second signal lines. The plurality of second signal lines include a plurality of first signal vias, which are deployed at a location closer to the second semiconductor element than the first semiconductor element. The first signal trace includes an extension portion extending from the second semiconductor element toward the first semiconductor element, and The extension is deployed through a gap between two first signal vias, the two first signal vias being arranged with a gap between them in a direction intersecting the direction of extension of the extension, and the two first signal vias being included in the plurality of first signal vias.

11. The electronic module according to claim 10, wherein, The first ground trace is located between the two first signal vias and the extension portion of the first signal trace.

12. The electronic module according to claim 10, wherein, The first ground trace is located between the plurality of first signal vias.

13. The electronic module according to claim 10, wherein, The extended portion is a linearly extended portion.

14. An electronic module, characterized in that, The electronic module includes: A wiring board having a first main surface and a second main surface on the back side of the first main surface; and A first semiconductor element and a second semiconductor element are mounted on the wiring board. In this configuration, at least one of the first semiconductor element or the second semiconductor element is deployed on one side of the first main surface. The first semiconductor element includes a first signal terminal and a second signal terminal, wherein the second signal terminal is closer to the second semiconductor element than the first signal terminal. The second semiconductor element includes a third signal terminal and a fourth signal terminal, wherein the fourth signal terminal is closer to the first semiconductor element than the third signal terminal. The wiring board includes A first signal line is configured to electrically interconnect the second signal terminal and the third signal terminal and includes a first signal trace deployed in a first conductor layer. A second signal line is configured to electrically interconnect the first signal terminal and the fourth signal terminal and includes a second signal trace deployed in a second conductor layer, the second conductor layer being closer to the second main surface than the first conductor layer. A first ground trace is deployed in the first conductor layer and extends along the first signal trace, such that the first signal trace is located between two portions of the first ground trace in the width direction of the first signal trace. A second ground trace is disposed in the second conductor layer and extends along the second signal trace, such that the second signal trace is located between two portions of the second ground trace in the width direction of the second signal trace. The first signal line includes a second signal via, which is positioned closer to the first semiconductor element than the second semiconductor element. The second signal via is deployed at a position where it does not overlap with the first semiconductor element when viewed from a direction perpendicular to the first main surface.

15. The electronic module according to claim 10, in, The wiring board includes multiple first signal lines. The plurality of first signal lines include a plurality of second signal vias, the plurality of second signal vias being deployed at a location closer to the first semiconductor element than the second semiconductor element, and The minimum interval among the plurality of second signal vias is equal to or less than the minimum interval among the plurality of first signal vias.

16. The electronic module according to claim 1, in, When viewed from a direction perpendicular to the first main surface, both the first semiconductor element and the second semiconductor element have rectangular shapes. When viewed from a direction perpendicular to the first main surface, one side of the first semiconductor element is opposite to one side of the second semiconductor element.

17. The electronic module according to claim 1, in, The first semiconductor element is a memory controller, and The second semiconductor element is a memory device.

18. The electronic module according to claim 17, wherein, The memory device is a Double Data Rate 3 Synchronous Dynamic Random Access Memory or a Double Data Rate 4 Synchronous Dynamic Random Access Memory.

19. An electronic device, characterized in that, The electronic device includes: Casing; and An electronic module according to any one of claims 1 to 18, deployed within the housing.

20. The electronic device of claim 19, further comprising an image forming portion configured to form an image on a sheet.

Images