Semiconductor memory device and method of manufacturing the same

Abstract

The present embodiment relates to a semiconductor storage device and a manufacturing method thereof. The semiconductor storage device of the embodiment includes a first storage device and a second storage device arranged in a first direction, and a plurality of first bump electrodes provided between the first storage device and the second storage device. The first storage device and the second storage device each include a first chip including a memory cell array and a plurality of first electrodes, a second chip including a peripheral circuit and a plurality of second electrodes, and a plurality of second bump electrodes provided between the first chip and the second chip. At least one of the plurality of first bump electrodes electrically connects at least one of the plurality of first electrodes included in the first storage device and at least one of the plurality of second electrodes included in the second storage device. In the first storage device and the second storage device, at least one of the plurality of second bump electrodes electrically connects the memory cell array and the peripheral circuit.

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2021-205592 (filed on December 17, 2021). This application incorporates all the contents of the basic application by reference to that basic application. Technical Field

[0003] This embodiment relates to a semiconductor memory device and a method for manufacturing the same. Background Technology

[0004] A semiconductor memory device is known, which includes a first memory chip and a second memory chip, and the first memory chip and the second memory chip are electrically connected via bump electrodes. Summary of the Invention

[0005] The embodiment provides a highly reliable semiconductor memory device and a method for manufacturing the same.

[0006] One embodiment of a semiconductor memory device includes a first memory device and a second memory device arranged in a first direction, and a plurality of first bump electrodes disposed between the first memory device and the second memory device. The first memory device and the second memory device each include: a first chip having a memory cell array and a plurality of first electrodes; a second chip having peripheral circuitry and a plurality of second electrodes; and a plurality of second bump electrodes disposed between the first chip and the second chip. The first direction is the thickness direction of the first memory device and the second memory device. At least one of the plurality of first bump electrodes electrically connects at least one of the plurality of first electrodes included in the first memory device to at least one of the plurality of second electrodes included in the second memory device. In both the first and second memory devices, at least one of the plurality of second bump electrodes electrically connects the memory cell array to the peripheral circuitry. The peripheral circuitry of the first memory device is capable of controlling the memory cell array of the first memory device. At least one of the plurality of second bump electrodes of the first storage device is disposed between the peripheral circuit of the first storage device and the storage cell array of the first storage device, and connects the peripheral circuit of the first storage device and the storage cell array of the first storage device in a first direction. Attached Figure Description

[0007] Figure 1 This is a schematic cross-sectional view of the semiconductor package PG1 according to the first embodiment.

[0008] Figure 2 This is a schematic exploded perspective view showing an example of the configuration of the storage device MD according to the first embodiment.

[0009] Figure 3 This is a schematic bottom view showing an example of the configuration of a chip CM.

[0010] Figure 4 This is a schematic top view showing an example of the configuration of a chip CP.

[0011] Figure 5 It corresponds to Figure 3 The A1-A1' line and Figure 4 A schematic cross-sectional view of line B1-B1'.

[0012] Figure 6 It corresponds to Figure 3 The A2-A2' line and Figure 4 A schematic cross-sectional view of line B2-B2'.

[0013] Figure 7 yes Figure 6 A schematic enlarged view of a portion of the structure.

[0014] Figure 8 This is a schematic cross-sectional view used to illustrate the connection of a storage device MD using bump electrodes (BMD).

[0015] Figure 9 This is a flowchart illustrating the manufacturing method of the semiconductor package PG1 according to the first embodiment.

[0016] Figure 10 It is a schematic diagram used to illustrate the processes of chip manufacturing, testing, and dicing.

[0017] Figures 11-14 This is a schematic cross-sectional view used to illustrate the manufacturing method of semiconductor package PG1.

[0018] Figure 15 This is a flowchart used to illustrate the manufacturing method of the semiconductor memory device of the comparative example.

[0019] Figure 16 This is a schematic diagram illustrating a portion of the manufacturing process of a comparative example semiconductor memory device.

[0020] Figure 17 This is a schematic cross-sectional view illustrating a configuration example of a comparative storage device.

[0021] Figure 18 This is a schematic cross-sectional view of the semiconductor package PG2 according to the second embodiment.

[0022] Figure 19 This is a flowchart illustrating the manufacturing method of the semiconductor package PG2 according to the second embodiment.

[0023] Figures 20-24 This is a schematic cross-sectional view used to illustrate the manufacturing method of semiconductor package PG2.

[0024] Figure 25 This is a schematic exploded perspective view showing an example of the configuration of the storage device MD3 according to the third embodiment.

[0025] Figure 26 This is a schematic bottom view showing an example of the configuration of chip CM3.

[0026] Figure 27 This is a schematic top view showing an example of the configuration of chip CP3.

[0027] Figure 28 It corresponds to Figure 26 The D-D' line and Figure 27 A schematic cross-sectional view of the E-E' line.

[0028] Figure 29 This is a schematic cross-sectional view showing an example of the configuration of the storage device MD4 according to the fourth embodiment.

[0029] Figure 30 This is a schematic cross-sectional view showing an example of the configuration of the storage device MD4 according to the fourth embodiment.

[0030] Figure 31 This is a schematic cross-sectional view illustrating the connection of the storage device MD4 using the bump electrode BMD4. Detailed Implementation

[0031] Next, the semiconductor memory device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the scope of the invention. Additionally, the following drawings are schematic diagrams, and for ease of explanation, some components may be omitted. Furthermore, common parts among the various embodiments are labeled with the same symbols, and sometimes descriptions are omitted.

[0032] Furthermore, in this specification, when "semiconductor memory device" is mentioned, it sometimes refers to a memory device, and sometimes to a memory system that includes a controller die, such as a memory card or an SSD (Solid State Drive). It also sometimes refers to a semiconductor package. Moreover, it sometimes refers to a component including a host, such as a smartphone, tablet, or personal computer.

[0033] Furthermore, in this specification, when it is mentioned that the first component is "electrically connected" to the second component, the first component can be directly connected to the second component, or the first component can be connected to the second component via wiring, semiconductor components, or transistors. For example, in the case of three transistors connected in series, even if the second transistor is in an off state, the first transistor is still "electrically connected" to the third transistor.

[0034] In addition, when it is mentioned in this specification that the first component is "connected" to the second and third components, it sometimes means that the first, second and third components are connected in series, and the second component is connected to the third component via the first component.

[0035] In addition, in this specification, the specified direction parallel to the upper surface of the substrate is called the X direction, the direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and the direction perpendicular to the upper surface of the substrate is called the Z direction.

[0036] In addition, in this specification, the direction along a specified surface is sometimes referred to as the first direction, the direction along the specified surface and intersecting the first direction is referred to as the second direction, and the direction intersecting the specified surface is referred to as the third direction. These first, second, and third directions may correspond to any of the X, Y, and Z directions, or they may not correspond to each other.

[0037] Furthermore, in this specification, expressions such as "upper" or "lower" are based on the configuration, such as the encapsulation substrate. For example, the direction away from the encapsulation substrate along the Z direction is called "upper," and the direction closer to the encapsulation substrate along the Z direction is called "lower." Additionally, when referring to a configuration, "lower surface" or "lower end" refers to a surface or end of that configuration on one side of the encapsulation substrate, and when referring to "upper surface" or "upper end," it refers to a surface or end of that configuration opposite to the encapsulation substrate. Furthermore, surfaces intersecting the X or Y direction are called "side surfaces," etc.

[0038] In addition, when referring to components, parts, etc., the "width", "length" or "thickness" in a specified direction is mentioned in this specification, it sometimes refers to the width, length or thickness in a cross-section observed using SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy).

[0039] [First Implementation]

[0040] [The structure of semiconductor package PG1]

[0041] Figure 1 This is a schematic cross-sectional view of semiconductor package PG1. Semiconductor package PG1 includes a package substrate PS, multiple memory devices MD, a controller die CD, sealing resin 20, and multiple solder balls 30. Figure 1 In this example, three memory devices MD(1), MD(2), and MD(3) are mounted on the packaging substrate PS. Additionally, the semiconductor package PG1 has bump electrodes B disposed between two memory devices MD. MDFurthermore, the Z-direction is the thickness direction of the storage device MD.

[0042] The packaging substrate PS has multiple wirings 10. These wirings 10 electrically connect the storage device MD, the controller die CD, external terminals, etc. Additionally, although not shown, electrodes are formed on the upper surface of the packaging substrate PS to electrically connect the wirings 10 to the storage device MD and the controller die CD. Furthermore, multiple solder balls 30 are mounted on the lower surface of the packaging substrate PS. The packaging substrate PS is electrically connected to the substrate of an electronic device, for example, via the solder balls 30.

[0043] Storage device MD includes: chip C M It includes a memory cell array; and a chip C. P It includes peripheral circuitry (PC). Additionally, the storage device (MD) has a chip (C)... M With chip C P Bump electrode B C .

[0044] Chip C M Capable of chip C M Multiple first electrodes C extending along the Z direction inside TSV1 Additionally, chip C P Capable of chip C P Multiple second electrodes C extending along the Z direction inside TSV2 .also, Figure 1 The first electrode C in the storage device MD(3) is not shown in the figure. TSV1 However, the chip C of the storage device MD(3) M The first electrode C can also be set in the middle. TSV1 .

[0045] Multiple bump electrodes B C Chip C M Multiple first electrodes C in TSV1 With chip C P Multiple second electrodes C in TSV2 Electrical connection. Additionally, multiple bump electrodes B C Chip C M Internal wiring paths and chip C P Internal wiring and other electrical connections. Therefore, in chip C... M Memory cell array and chip C P Signals are transmitted between the peripheral circuits of the PC.

[0046] The controller die CD, for example, includes a processor, RAM (Random Access Memory), ROM (Read Only Memory), and ECC (Error Check and Correction) circuitry, performing tasks such as logical address to physical address conversion, bit error detection / correction, and wear leveling. The controller die CD interacts with the chip C. P The peripheral circuit PC is used for input and output of data signals corresponding to reading and writing data, as well as external control signals used to control the peripheral circuit PC.

[0047] Multiple bump electrodes B MD Chip C in a storage device (e.g., storage device MD(1)) M Multiple first electrodes C TSV1 , and chip C in another storage device (e.g., storage device MD(2)) P Multiple second electrodes C TSV2 Electrical connection. Additionally, multiple bump electrodes B MD The wiring paths inside one storage device MD(1) are electrically connected to the wiring paths inside another storage device MD(2). In this way, signals are transmitted between multiple storage devices MD.

[0048] In addition, multiple storage devices MD(1) to MD(3) are connected via these multiple bump electrodes B MD The wiring 10 of the packaging substrate PS is electrically connected to the controller die CD. Therefore, in chip C... P The peripheral circuit PC transmits signals between the controller and the bare CD.

[0049] [Structure of Storage Device MD]

[0050] Figure 2 This is a schematic exploded perspective view showing an example of the configuration of the storage device MD according to the first embodiment. Figure 2 As shown, the storage device MD includes a chip C on the storage cell array side. M and peripheral circuit PC-side chip C P . Figure 2 Several bump electrodes B are omitted in the text. C and multiple bump electrodes B MD .

[0051] In chip C M Multiple first external electrodes P are disposed on the upper surface. T1 Additionally, in chip C... M Multiple first internal electrodes P are disposed on the lower surface.I1 Additionally, in chip C... P Multiple second internal electrodes P are disposed on the upper surface. I2 Additionally, in chip C... P Multiple second external electrodes P are disposed on the lower surface. T2 The following section concerns chip C. M Multiple first internal electrodes P will be set. I1 The side referred to as the front side will have multiple first external electrodes P set on it. T1 The side facing out is called the back side. Additionally, regarding chip C... P Multiple second internal electrodes P will be set. I2 The side referred to as the front side will have multiple second external electrodes P set on it. T2 The side facing out is called the back side. In the example shown, chip C... P The front side is set higher than the chip C. P On the back, at the upper part, is chip C M The back is set at a higher position than chip C M The front is positioned higher up.

[0052] Chip C M and chip C P Based on chip C M The front of the chip C P They are arranged in a face-to-face configuration. Multiple first internal electrodes P I1 It is with multiple second internal electrodes P I2 They are respectively set accordingly, and configured to interact with multiple second internal electrodes P. I2 Connection location. Internal electrode P (first type) I1 With the second internal electrode P I2 It is via bump electrode B C And make chip C M Wiring and other components in the chip C P The wiring in the middle is electrically conductive.

[0053] Multiple first external electrodes P in a storage device MD T1 Each of the multiple second external electrodes P in another storage device MD corresponds to one of them. T2 And configured to interact with multiple second external electrodes P in another storage device MD. T2 Connection location. External electrode P (first external electrode) T1 and the second external electrode P T2 As for use via bump electrode B MD Make a chip C in a storage device MD M Wiring, etc., and chip C in another storage device MD. P The electrodes in the wiring, which are electrically conductive, perform their function.

[0054] In addition, Figure 2 In the example, chip C M The corners a1, a2, a3, and a4 are respectively connected to chip C P The corners b1, b2, b3, and b4 correspond.

[0055] Figure 3 This indicates that chip C M A schematic bottom view of the composition example. Figure 4 This indicates that chip C P A schematic top view of the composition example. Figure 5 It corresponds to Figure 3 The A1-A1' line and Figure 4 A schematic cross-sectional view of line B1-B1'. Figure 6 It corresponds to Figure 3 The A2-A2' line and Figure 4 A schematic cross-sectional view of line B2-B2'. Figure 5 and Figure 6 Indicates will Figure 3 and Figure 4 The structure shown is a cross-section when viewed in the direction of the arrows after being cut along each line. Figure 7 yes Figure 6 A schematic enlarged view of a portion of the structure.

[0056] also, Figures 2-7 The schematic configuration is shown in the diagram. Additionally, Figures 2-7 A portion of the composition has been omitted.

[0057] [Chip C] M [Structure]

[0058] For example Figure 3 As shown, chip C M It has four memory planes (MPs) arranged in the X and Y directions. Each memory plane (MP) has a memory cell array region (R). MCA The storage cell array MCA and the wiring area R are configured therein. HU Set in the storage cell array area R MCA One end and the other end in the X direction. Additionally, chip C... M With surrounding area R P The surrounding area R P It is set on one end of the Y direction, which is closer to the four storage planes MP.

[0059] Furthermore, in the illustrated example, the wiring area R HU Set in the storage cell array region R MCAThe two ends in the X direction. However, this configuration is only illustrative, and the specific configuration can be adjusted appropriately. For example, the wiring area R HU Alternatively, it can be located at one end in the X direction, instead of the memory cell array region R. MCA The two ends in the X direction. Additionally, the wiring area R... HU It can also be set in the storage cell array area R MCA The central position or the position near the center in the X direction.

[0060] For example Figure 5 and Figure 6 As shown, chip C M Features: matrix layer L SB Storage cell array layer L MCA Set in the matrix layer L SB Below; and wiring layer L MM Set in the storage cell array layer L MCA Below.

[0061] [Chip C] M The base layer L SB [Structure]

[0062] For example Figure 5 As shown, the matrix layer L SB It comprises: an uppermost insulating layer 100; an insulating layer 101 disposed below the insulating layer 100; and a conductive layer 102 disposed below the insulating layer 101. The insulating layer 100 is, for example, a passivation layer containing an insulating material such as polyimide. The insulating layer 101 contains, for example, silicon oxide (SiO2). The conductive layer 102 may contain, for example, a semiconductor layer such as silicon (Si) implanted with N-type impurities such as phosphorus (P) or P-type impurities such as boron (B), or may contain a metal such as tungsten (W), or may contain a silicide such as tungsten silicide (WSi).

[0063] In the storage cell array region R MCA and wiring area R HU A conductive layer 102 is disposed inside. The conductive layer 102 corresponds to four storage planes MP arranged in the X and Y directions. Figure 3 Four are provided. Regions VZ without conductive layer 102 are provided at the ends of the storage plane MP in the X and Y directions.

[0064] For example Figure 6 As shown, in the surrounding area R P The internal part is provided with the first external electrode P. T1The back-side wiring MZ performs its function. The back-side wiring MZ contains, for example, a conductive material such as aluminum (Al). The back-side wiring MZ is electrically insulated from the conductive layer 102 by an insulating layer 101. Within the region VZ where the conductive layer 102 is not present, the back-side wiring MZ is connected to the memory cell array layer L. MCA The contact CC is connected in the middle. Additionally, a portion of the back wiring MZ exposes from the opening TV provided in the insulating layer 100 to the outside of the storage device MD, serving as the first external electrode P. T1 To fulfill its function.

[0065] [Chip C] M L storage cell array layer MCA Storage cell array region R MCA [Internal Structure]

[0066] For example Figure 6 As shown, in the memory cell array layer L MCA The system contains multiple memory blocks (BLKs) arranged in the Y direction. Each memory block (BLK) has multiple string sets (SUs) arranged in the Y direction. An inter-block insulating layer (ST) such as silicon oxide (SiO2) is provided between two adjacent memory blocks (BLKs) in the Y direction. In addition, an inter-string set insulating layer (SHE) such as silicon oxide (SiO2) is provided between two adjacent string sets (SUs) in the Y direction.

[0067] The memory block BLK includes: a plurality of conductive layers 110 arranged in the Z direction; a plurality of semiconductor layers 120 extending along the Z direction; and a plurality of gate insulating films 130 disposed between the plurality of conductive layers 110 and the plurality of semiconductor layers 120.

[0068] The conductive layer 110 has a generally plate-like shape extending in the X direction. The conductive layer 110 may comprise a multilayer film containing a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Alternatively, the conductive layer 110 may also comprise, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 111, such as silicon oxide (SiO2), is disposed between the plurality of conductive layers 110 arranged in the Z direction.

[0069] The conductive layer 102 functions as the source line SL of the NAND (Not AND) flash memory. The source line SL, for example, is for the memory cell array region R. MCA ( Figure 3 All storage blocks BLK contained in ) are configured in a common way.

[0070] In addition, among the multiple conductive layers 110, the uppermost one or more conductive layers 110 function as the select gate line (SGS) of the NAND flash memory and the gate electrodes of multiple select transistors connected to the select gate line (SGS). These multiple conductive layers 110 are electrically independent in each memory block (BLK).

[0071] Additionally, the plurality of conductive layers 110 located below the one or more uppermost conductive layers 110 function as word lines WL of the NAND flash memory and as gate electrodes of the plurality of memory cells connected to the word lines WL. Each of these conductive layers 110 is electrically independent in each memory block BLK.

[0072] Additionally, one or more conductive layers 110 located further below the aforementioned conductive layers 110 function as the select gate line (SGD) of the NAND flash memory and the gate electrodes of multiple select transistors connected to the select gate line (SGD). These conductive layers 110 have a narrower width in the Y direction than the other conductive layers 110. Furthermore, a string set insulating layer (SHE) is disposed between two adjacent conductive layers 110 in the Y direction. Each of these conductive layers 110 is electrically independent within each string set (SU).

[0073] Semiconductor layer 120 is arranged in a specified pattern in the X and Y directions. Semiconductor layer 120 functions as a channel region for multiple memory cells and selection transistors. Semiconductor layer 120 may contain, for example, polysilicon (Si). Semiconductor layer 120 may have, for example, a generally cylindrical or generally cylindrical shape. In addition, the outer peripheral surfaces of semiconductor layer 120 are surrounded by conductive layer 110 and are opposite to conductive layer 110.

[0074] An impurity region containing N-type impurities such as phosphorus (P) is formed at the lower end of semiconductor layer 120. This impurity region is connected to bit lines BL via contact Ch and contact Vy. Furthermore, these multiple bit lines BL are connected via wiring m1 in wiring layer M1 and the first internal electrode P in wiring layer M2. I1 Connected to chip C P The composition of [the text]. Furthermore, such as... Figure 5 and Figure 6 exemplified, Figure 3 The memory cell array region R illustrated in the figure MCA Multiple first internal electrodes P in I1 Electrically connected to the first external electrode P T1 .

[0075] An impurity region containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B) is provided at the upper end of the semiconductor layer 120. This impurity region is connected to the conductive layer 102.

[0076] The gate insulating film 130 has a generally cylindrical shape covering the outer peripheral surface of the semiconductor layer 120. For example... Figure 7As shown, the gate insulating film 130 includes a tunnel insulating film 131, a charge accumulation film 132, and a barrier insulating film 133 deposited between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating film 131 and the barrier insulating film 133 may contain, for example, silicon oxide (SiO2). The charge accumulation film 132 may contain, for example, a film capable of accumulating charge in silicon nitride (Si3N4). The tunnel insulating film 131, the charge accumulation film 132, and the barrier insulating film 133 have a generally cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120, excluding the contact portion between the semiconductor layer 120 and the conductive layer 102.

[0077] also, Figure 7 An example is shown where the gate insulating film 130 has a charge accumulation film 132 such as silicon nitride. However, the gate insulating film 130 may also have a floating gate such as polysilicon containing N-type or P-type impurities.

[0078] [Chip C] M L storage cell array layer MCA Wiring area R HU [Internal Structure]

[0079] like Figure 5 As shown, in the wiring area R HU The interior contains the ends of multiple conductive layers 110 in the X direction, which function as word lines WL, select gate lines SGS, or select gate lines SGD. Additionally, in the wiring area R... HU Multiple contacts CC are disposed within the core. These contacts CC extend along the Z-direction and are connected at their upper ends to the conductive layer 110. The contacts CC may, for example, comprise a multilayer film of a barrier conductive film such as titanium nitride (TiN) or a metal film such as tungsten (W). Figure 5 As illustrated, these multiple contacts CC are connected via wirings m0 and m1 in wiring layers M0 and M1, and the first internal electrode P in wiring layer M2. I1 Connected to chip C P The composition of [the text]. Furthermore, such as... Figure 5 exemplified, Figure 3 The wiring area R shown in the example HU Multiple first internal electrodes P in I1 Electrically connected to conductive layer 110.

[0080] [Chip C] M L storage cell array layer MCA The surrounding area R P [Internal Structure]

[0081] For example Figure 6 As shown, in the surrounding area R P Inside, with the first external electrode P T1Correspondingly, multiple contacts CC are provided. The upper ends of these multiple contacts CC are connected to the back wiring MZ. In addition, these multiple contacts CC are connected via wirings m0 and m1 in wiring layers M0 and M1 and the first internal electrode P in wiring layer M2. I1 With chip C P The components are connected. Furthermore, as... Figure 6 exemplified, Figure 3 The surrounding area R shown in the example P Multiple first internal electrodes P in I1 Electrically connected to the first external electrode P T1 .

[0082] [Chip C] M wiring layer L MM [Structure]

[0083] For example Figure 5 and Figure 6 As shown, wiring layer L MM It comprises multiple wiring layers M0, M1, and M2. The wiring layers M0, M1, and M2 contain multiple wirings and electrodes, for example, electrically connected to the memory cell array layer L. MCA The composition and chip C in P At least one of the components in the composition.

[0084] The wiring layer M0 comprises multiple wirings m0. These multiple wirings m0 may, for example, comprise a multilayer film of barrier conductive films such as titanium nitride (TiN) and metal films such as copper (Cu). Furthermore, a portion of the multiple wirings m0 serves as a potential line BL (…). Figure 5 The bit lines BL are arranged in the X direction and extend in the Y direction. Furthermore, these multiple bit lines BL are each connected to a semiconductor layer 120 contained in each string group SU.

[0085] For example Figure 5 and Figure 6 As shown, the wiring layer M1 comprises multiple wirings m1. These multiple wirings m1 may, for example, comprise a stacked film of barrier conductive films such as titanium nitride (TiN) and metal films such as tungsten (W).

[0086] Wiring layer M2 contains multiple first internal electrodes P I1 These multiple first internal electrodes P I1 For example, it can be a multilayer film containing barrier conductive films such as titanium nitride (TiN) and metal films such as copper (Cu).

[0087] In addition, the first external electrode P T1 With the first internal electrode P I1 The contacts CC set on the current path between them and the wiring m0 and m1 in the wiring layers M0 and M1 are equivalent to Figure 1The first electrode C is schematically represented in the diagram. TSV1 .

[0088] [Chip C] P [Structure]

[0089] For example Figure 4 As shown, chip C P It has four peripheral circuit regions R arranged in the X and Y directions corresponding to the storage plane MP. PC Peripheral circuit region R PC Features: Sensing amplifier module area R SAM Set in the memory cell array region R MCA A portion of the relative region; and the line decoder region R RD Set in the wiring area R HU Within the corresponding area. Additionally, chip C P Equipped with the ability to be set up in the surrounding area R P The circuit region R in the relative region C .

[0090] In addition, for example Figure 5 and Figure 6 As shown, chip C P Features: Semiconductor substrate 200; Transistor layer L TR It is disposed above the semiconductor substrate 200; and the wiring layer L MP Set in transistor layer L TR Above. Wiring layer L MP It includes multiple wiring layers M0', M1', M2', M3', and M4'.

[0091] [Chip C] P [Structure of semiconductor substrate 200]

[0092] Semiconductor substrate 200, for example, comprises P-type silicon (Si) containing P-type impurities such as boron (B). Figure 5 As shown, on the front side of the semiconductor substrate 200, there are an N-type well region 200N containing N-type impurities such as phosphorus (P), a P-type well region 200P containing P-type impurities such as boron (B), a semiconductor substrate region 200S without N-type well regions 200N and P-type well regions 200P, and an insulating region 200I. The N-type well region 200N, the P-type well region 200P, and the semiconductor substrate region 200S function as part of multiple transistors Tr and multiple capacitors constituting the peripheral circuit PC, respectively.

[0093] [Chip C] P transistor layer L TR [Structure]

[0094] For example Figure 5 As shown, a wiring layer GC is disposed on the upper surface of the semiconductor substrate 200, separated by an insulating layer 200G. The wiring layer GC includes a plurality of electrodes gc facing the front side of the semiconductor substrate 200. Furthermore, each region of the semiconductor substrate 200 and the plurality of electrodes gc included in the wiring layer GC are respectively connected to a contact CS.

[0095] The multiple electrodes gc contained in the wiring layer GC function as the gate electrodes of multiple transistors Tr that constitute the peripheral circuit PC, and as electrodes on one side of multiple capacitors.

[0096] The contact CS may include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). An impurity region containing N-type or P-type impurities is provided at the connection between the contact CS and the semiconductor substrate 200.

[0097] [Chip C] P wiring layer L MP [Structure]

[0098] As mentioned above, chip C P wiring layer L MP It includes wiring layers M0', M1', M2', M3', and M4'. Wiring layer M0' is located on transistor layer L. TR Above. Wiring layer M0' contains, for example, a conductive material such as tungsten (W). Wiring layer M1' is disposed above wiring layer M0'. Wiring layer M1' contains, for example, a conductive material such as tungsten (W). Wiring layer M2' is disposed above wiring layer M1', but... Figure 5 and Figure 6 Illustrations are omitted. Wiring layer M2' may contain conductive materials such as copper (Cu). Wiring layer M3' may contain conductive materials such as copper (Cu) or aluminum (Al). Wiring layer M4' may be a wiring layer containing conductive materials such as copper (Cu) and has multiple second internal electrodes P. I2 .

[0099] [Chip C] P Substrate through electrode C 200 [Structure]

[0100] For example Figure 6 As shown, in circuit region R C A substrate through electrode C is provided in the middle, penetrating the semiconductor substrate 200. 200 Substrate through-electrode C 200 For example, it can be a multilayer film containing a barrier conductive film such as titanium nitride (TiN), a seed layer such as tungsten (W), and a metal film such as nickel (Ni). Additionally, an insulating region 200I is formed on the upper surface of the semiconductor substrate 200. TA second external electrode P is disposed on the lower surface of the semiconductor substrate 200. T2 Substrate through-electrode C 200 The lower end is connected to the second external electrode P T2 Connection, the upper end connects to the wiring in the wiring layer.

[0101] In addition, the second external electrode P T2 With the second internal electrode P I2 Substrate through electrode C set on the current path between 200 The wiring in wiring layers M0', M1', M2', and M3' is equivalent to Figure 1 The second electrode C is schematically represented in the diagram. TSV2 .

[0102] [Using bump electrode B] C The chip C being performed P C M [Connection]

[0103] For example Figure 5 and Figure 6 As shown, chip C M Multiple first internal electrodes P I1 With chip C P Multiple second internal electrodes P I2 Each via multiple bump electrodes B C connect.

[0104] Multiple bump electrodes B C Each contains conductive materials such as copper (Cu).

[0105] The bit line BL and the sensing amplifier of the peripheral circuit PC are connected via wiring layers M0, M1, and the first internal electrode P of wiring layer M2. I1 Bump electrode B C The second internal electrode P of wiring layer M4' I2 The wiring of wiring layers M3', M2', M1', and M0', and the path of contact CS are electrically conductive.

[0106] Additionally, the word line WL (conductive layer 110) and the horizontal decoder of the peripheral circuit PC are connected via the contact CC, wiring layers M0 and M1, wiring m0 and m1, and the first internal electrode P of wiring layer M2. I1 Bump electrode B C The second internal electrode P of wiring layer M4' I2 The wiring of wiring layers M3', M2', M1', and M0', and the path of contact CS are electrically conductive.

[0107] In addition, the first external electrode P T1 and the second external electrode PT2 The input / output circuit (not shown) is connected via contact CC, wiring layers M0 and M1, wiring m0 and m1, and the first internal electrode P of wiring layer M2. I1 Bump electrode B C The second internal electrode P of wiring layer M4' I2 The wiring of wiring layers M3', M2', M1', and M0', and the path of contact CS are electrically conductive.

[0108] [Using bump electrode B] MD [Connection of storage device MD]

[0109] Figure 8 This is used to illustrate the use of bump electrode B MD A schematic cross-sectional view of the connections made to the storage device MD. First internal electrode P I1 and the second internal electrode P I2 The size (area in the XY plane) is smaller than that of the first external electrode P. T1 and the second external electrode P T2 The size (area in the XY plane). Additionally, the bump electrode B... C The size (width in the Z direction and area in the XY plane) is smaller than that of the bump electrode B. MD The size (width in the Z direction and area in the XY plane). However, in Figure 8 In the middle, the first internal electrode P I1 and the second internal electrode P I2 , and the first external electrode P T1 and the second external electrode P T2 They are represented as being the same size. Additionally, bump electrode B... C With bump electrode B MD They are represented as the same size.

[0110] For example Figure 8 As shown, the chip C of a storage device (e.g., MD(1)) M Multiple first external electrodes P T1 , and another storage device (e.g., MD(2)) chip C P Multiple second external electrodes P T2 Each via multiple bump electrodes B MD connect.

[0111] Multiple bump electrodes B MD Each can be formed from a conductive material, such as tin (Sn), or multiple metal layers can be stacked.

[0112] Multiple chips C P Peripheral circuit PC and controller bare CD ( Figure 1) via the path within the storage device MD (first external electrode P) T1 Electrode C TSV1 , First internal electrode P I1 Bump electrode B C , second internal electrode P I2 Electrode C TSV2 and the second external electrode P T2 Bump electrode B between storage device MD MD The wiring 10 within the packaging substrate PS is electrically conductive. For example, in the controller die CD ( Figure 1 ) and chip C P The peripheral circuit PC performs input and output of data signals, external control signals, etc. Furthermore, multiple electrodes formed on the upper surface of the packaging substrate PS are respectively connected to multiple second external electrodes P disposed on the lower surface of the storage device MD(1). T2 Electrical connection.

[0113] [Manufacturing method of semiconductor package PG1]

[0114] Next, refer to Figures 9-14 The manufacturing method of semiconductor package PG1 is described.

[0115] Figure 9 This is a flowchart illustrating the manufacturing method of semiconductor package PG1. Figure 10 It is a schematic diagram used to illustrate the processes of chip manufacturing, testing, and dicing. Figures 11-14 This is a schematic cross-sectional view used to illustrate the manufacturing method of semiconductor package PG1. Furthermore, Figure 9 The "CR" in this context refers to a cleanroom.

[0116] First, perform chip C M C P Manufacturing (step S1). For example, in a cleanroom CR, a semiconductor manufacturing apparatus processes the wafer W on the MCA side of the memory cell array. MCA The manufacturing processes include film formation, masking, exposure, development, etching, and impurity diffusion. Therefore, as... Figure 10 As shown, on wafer W MCA Multiple chips C arranged in a lattice are formed on the surface. M At this time, in chip C M Multiple first electrodes C are formed on the surface. TSV1 Additionally, regarding chip C... M Grind the front side.

[0117] Additionally, within the cleanroom CR, semiconductor manufacturing equipment processes the wafer W on the peripheral circuit PC side. PC The manufacturing processes include film formation, masking, exposure, development, etching, and impurity diffusion. Therefore, as... Figure 10 As shown, on wafer W PC Multiple chips C are also formed in a lattice-like arrangement on it. P At this time, in chip C P Multiple second electrodes C are formed on top TSV2 Additionally, regarding chip C... P Grind the front side.

[0118] Next, for wafer W MCA W PC Individual simplified tests are performed (step S2). As a simplified test, for example, a test apparatus is used to test the individual wafers formed on the W wafer. MCA W PC Multiple chips on C M C P Perform electrical connection verification tests, circuit operation verification tests, etc. Use simple tests to determine the performance of multiple chips. M C P Is it good or bad?

[0119] Next, perform chip C... M C P Cutting (step S3). For example Figure 10 As shown, from wafer W MCA Cut out multiple chips C M Similarly, from wafer W PC Cut out multiple chips C P .also, Figure 9 In the example, it is on wafer W MCA W PC After performing a simple test (step S2), proceed with chip C. M C P Cutting (step S3). However, it can also be done during chip C... M C P After cutting, the chip C M C P Conduct a simple test.

[0120] Then, perform chip C M C P Selection (Step S4). Here, a chip C with good characteristics is selected through simple testing. M C P .

[0121] Next, install chip C. M C P And perform chip C M C P Connections between (step S5). For example... Figure 11 As shown, chip C PIt is mounted on the upper surface of the packaging substrate PS. At this time, chip C P Multiple second external electrodes P T2 It is electrically connected to multiple electrodes formed on the upper surface of the packaging substrate PS. Furthermore, Figure 11 Although not shown in the diagram, multiple chips (C) can be mounted on the upper surface of the packaging substrate PS. P .

[0122] In addition, such as Figure 12 As shown, chip C M via multiple bump electrodes B C Built on chip C P Above. At this moment, chip C M Multiple first internal electrodes P I1 With multiple bump electrodes B C They are electrically connected separately. This constitutes the storage device MD(1).

[0123] In addition, for example Figure 13 As shown, chip C P via multiple bump electrodes B MD Chip C mounted in storage device MD(1) M Above. At this moment, chip C P Multiple second external electrodes P T2 With multiple bump electrodes B MD Electrically connected separately. Similarly, chip C... M via multiple bump electrodes B C Chip C mounted in storage device MD(2) P Above, chip C P via multiple bump electrodes B MD Chip C mounted in storage device MD(2) M Above, chip C M via multiple bump electrodes B C Chip C mounted in storage device MD(3) P Above. Additionally, for example... Figure 13 As shown, the controller die CD is mounted on the upper surface of the package substrate PS. At this time, the multiple pad electrodes of the controller die CD are electrically connected to the multiple electrodes formed on the upper surface of the package substrate PS.

[0124] Next, a die sort test is performed (step S6). This die sort test involves performing electrical characteristic tests on components such as transistors and capacitors required for circuit operation to determine their functionality. Additionally, the C values ​​of each chip are determined... M C PIs the connection normal? Through bare die screening tests, determine the multiple devices (chips C) mounted on the packaging substrate PS. M C P Is it good or bad?

[0125] Next, multiple memory devices (MDs, Cs) on the packaging substrate PS were processed. M C P The controller bare die CD is molded (step S7). For example Figure 14 As shown, multiple memory devices (MDs, Cs) are mounted on the packaging substrate PS. M C P The region ER of the controller bare die CD is molded with thermosetting sealing resin 20. Sealing resin 20 is, for example, primarily composed of epoxy resin. At this point, the two chips C... M C P The area between (where bump electrodes B are configured) C The area between the two storage devices MD and the area between them (where bump electrodes B are located). MD The area is also molded with sealing resin 20. Then, multiple solder balls 30 are mounted on the lower surface of the encapsulation substrate PS.

[0126] Next, the semiconductor package PG1 is cut (step S8). In this embodiment, the processes of steps S1 to S8 are performed in a cleanroom CR.

[0127] In addition, tests are performed on the semiconductor package PG1 (step S9). Tests on the semiconductor package PG1 include, for example, temperature and voltage tests, electrical characteristic tests, and appearance structure inspections.

[0128] Then, the semiconductor package PG1 is shipped (step S10).

[0129] [Comparative Example]

[0130] Next, refer to Figures 15-17 The manufacturing method of the comparative example semiconductor memory device will be described.

[0131] Figure 15 This is a flowchart used to illustrate the manufacturing method of the semiconductor memory device of the comparative example. Figure 16 This is a schematic diagram illustrating a portion of the manufacturing process of a comparative example semiconductor memory device. Figure 17 This is a schematic cross-sectional view illustrating a configuration example of the storage device used in the comparison example. Furthermore, Figure 15 The "CR" in this context refers to a cleanroom.

[0132] First, perform chip C ME C PEManufacturing (step S21). In the cleanroom CR, the semiconductor manufacturing apparatus processes the wafer W on the MCA side of the memory cell array. MCAE Multiple manufacturing processes are employed. On the wafer W... MCAE Multiple chips C arranged in a lattice are formed on the surface. ME Additionally, within the cleanroom CR, semiconductor manufacturing equipment processes the wafers W on the PC side of the peripheral circuitry. PCE Multiple manufacturing processes are employed. On the wafer W... PCE Multiple chips C are also formed in a lattice-like arrangement on it. PE .

[0133] Next, for example Figure 16 As shown, individual wafers W are manufactured in the cleanroom CR. MCAE With W PCE Adhesion (step S22). For example... Figure 17 As shown, chip C ME With chip C PE via multiple first internal electrodes P I1 and multiple second internal electrodes P I2 Adhesion. In the comparative example, the processes described in steps S21 and S22 are performed in a cleanroom (CR).

[0134] Next, the wafer W that was bonded in step S22 is... MCAE W PCE Perform bare die screening test (step S23). Additionally, perform chip C... ME C PE Cutting (step S24).

[0135] Next, it will have chip C ME C PE The storage device is mounted on the upper surface of the packaging substrate, and the storage device is electrically connected to the packaging substrate (step S25). At this time, the controller die is also mounted on the upper surface of the packaging substrate.

[0136] Next, multiple memory devices (chips C) are packaged on the substrate. ME C PE Then, the semiconductor package PG1 is cut (step S27).

[0137] Then, after testing the semiconductor package PG1 (step S28), the semiconductor package PG1 is shipped (step S29).

[0138] [Effects of the first embodiment]

[0139] In the first embodiment, since the chip C on the MCA side of the memory cell array is respectively... MChip C on the PC side of the peripheral circuit P By performing tests, highly reliable chips (chips with good characteristics) can be combined to complete the memory device (MD). Furthermore, due to the use of bump electrodes B... C Chip C M With chip C P Connected, and via bump electrode B MD By connecting two memory devices (MDs), it is possible to easily connect chips to each other and memory devices (MDs) to each other. Furthermore, due to the use of electrode C... TSV1 C TSV2 and bump electrode B MD By electrically connecting the storage devices M and D, signal input and output can be performed at high speed compared to the case where bonding wires are used to electrically connect the storage devices M and D.

[0140] [Second Implementation]

[0141] [The structure of semiconductor package PG2]

[0142] Figure 18 This is a schematic cross-sectional view of the semiconductor package PG2. Furthermore, Figure 18 In the middle, to and Figure 1 The same symbols are used to mark the same components, and their descriptions are omitted.

[0143] The semiconductor package PG2 includes a redistribution layer Lw, a memory device MD2, a controller die CD, a sealing resin 20, and multiple solder balls 30.

[0144] The redistribution layer Lw electrically connects the storage device MD2, the controller die CD, and external terminals. Additionally, multiple solder balls 30 are mounted on the lower surface of the redistribution layer Lw.

[0145] The storage device MD2 features: multiple chips C M2 It includes a memory cell array; and one chip C. P2 It includes the peripheral circuitry PC. In Figure 18 In the example, storage device MD2 has 3 chips C M2 and 1 chip C P2 Additionally, the storage device MD2 includes: bump electrodes B C Set in chip C P2 With chip C M2 Between; and bump electrode B C2 Set in 2 chips C M2 between.

[0146] Chip C M2 Its basic structure is similar to that of a chip C M Same. However, chip C M2Equipped with multiple first electrodes C TSV11 To replace multiple first electrodes C TSV1 Electrode C TSV11 The structure and the first electrode C TSV1 same.

[0147] also, Figure 18 The third (topmost) chip C is not shown in the diagram. M2 The first electrode C in TSV11 However, the chip C M2 The first electrode C can also be set in the middle. TSV11 .

[0148] Chip C P2 Its basic structure is similar to that of a chip C P Same. However, chip C P The peripheral circuit PC and a chip C M The memory cell array is connected within the chip. On the other hand, chip C... P2 The peripheral circuit PC and multiple (3 in the example) chips C M2 The memory cell array is connected within the chip. Additionally, chip C... P2 Electrodes can be set in it ( Figure 1 The second electrode C TSV2 ), or you can leave it unset.

[0149] Multiple bump electrodes B C Composition and Figure 1 , Figure 5 and Figure 6 The multiple bump electrodes B shown C Same. Multiple bump electrodes B C Chip C at the bottom of the first segment M2 Internal wiring paths, and C P2 Internal wiring and other electrical connections. Therefore, in the first segment chip C... M2 The memory cell array and the chip C P2 Signals are transmitted between the peripheral circuits of the PC.

[0150] Multiple bump electrodes B C2 A chip C M2 Multiple first electrodes C TSV11 , and another chip C M2 Multiple first electrodes C TSV11 Electrical connection. Therefore, except for the first segment chip C... M2 Other chips C M2 (For example, chip C in segments 2 and 3) M2 The memory cell array and chip C P2 Signals are transmitted between the peripheral circuits of the PC.

[0151] The storage device MD2 is electrically connected to the controller die CD via wiring in the rewiring layer Lw. Thus, in chip C... P2 The peripheral circuit PC transmits signals between the controller and the bare CD.

[0152] [Manufacturing method of semiconductor package PG2]

[0153] Next, refer to Figures 19-24 The manufacturing method of semiconductor package PG2 is explained.

[0154] Figure 19 This is a flowchart illustrating the manufacturing method of the semiconductor package PG2. Figures 20-24 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor package PG2. Furthermore, Figure 19 The "CR" in this context refers to a cleanroom.

[0155] Figure 19 Steps S1 to S4 and Figure 9 Steps S1 to S4 are the same. However, on wafer W... MCA Multiple chips C are formed on top M2 In wafer W PC Multiple chips C are formed on top P2 .

[0156] Next, in step S5A, chip C is installed. M2 C P2 And perform chip C M2 C P2 Connections between them. For example Figure 20 As shown, chip C P2 It is mounted on the upper surface of the support wafer 500. The support wafer 500 may be, for example, a glass wafer.

[0157] In addition, such as Figure 21 As shown, chip C M2 via multiple bump electrodes B C Built on chip C P2 Above. At this moment, chip C M2 With bump electrode B C Electrical connection. Additionally, for example... Figure 22 As shown, the second chip C M2 via multiple bump electrodes B C2 Equipped in the first segment chip C M2 Above. At this time, the second chip C M2 With bump electrode B C2 Electrical connection. Similarly, the third chip C M2 via multiple bump electrodes B C2Equipped in the second segment chip C M2 Above. At this time, the third chip C M2 With bump electrode B C2 Electrical connection. Additionally, the controller die CD is mounted on the upper surface of the supporting wafer 500.

[0158] Next, with use Figure 9 Similarly, in the case described above, a bare wafer screening test is performed (step S6). Additionally, for example... Figure 23 As shown, the memory device MD2 (chip C) on the supporting wafer 500 is implemented. M2 C P2 Molding of the controller bare die CD and the two chips C (step S7). At this time, the two chips C M2 C P2 The area between (where bump electrodes B are configured) C (area), and 2 chips C M2 The area between (where bump electrodes B are configured) C2 The area was also sealed with resin 20 and molded.

[0159] Next, the rewiring layer Lw is formed (step S11). For example... Figure 24 As shown, from storage device MD2 (chip C) P2 The support wafer 500 is peeled off from the lower surface of the memory device MD2. Then, a rewiring layer Lw is formed on the lower surface of the memory device MD2. In this process, the semiconductor manufacturing apparatus performs manufacturing processes such as film deposition, masking, exposure, development, and etching on the lower surface of region ER. This technique of using the manufacturing process of a semiconductor memory device to manufacture the rewiring layer Lw is sometimes called FO-WLP (Fan Out-Wafer Level Package). By using FO-WLP, the packaging substrate PS of the first embodiment is no longer needed, and the semiconductor package can be made thinner. In addition, the wiring length is shortened, and signal transmission is faster.

[0160] Next, multiple solder balls 30 are mounted on the lower surface of the rewiring layer Lw.

[0161] Next, the semiconductor package PG2 is cut (step S8). In this embodiment, the processes of steps S1 to S4, S5A, S6, S7, and S11 are performed in a cleanroom CR.

[0162] After that, the semiconductor package PG2 is tested (step S9), and then the semiconductor package PG2 is shipped (step S10).

[0163] [Third Implementation]

[0164] [Chip C] M3 and chip C P3[Structure]

[0165] Figure 25 This is a schematic exploded perspective view showing an example of the configuration of the storage device MD3 according to the third embodiment. Figure 26 This indicates that chip C M3 A schematic bottom view of the composition example. Figure 27 This indicates that chip C P3 A schematic top view of the composition example. Figure 28 It corresponds to Figure 26 The D-D' line and Figure 27 A schematic cross-sectional view of the E-E' line. Figure 28 Indicates will Figure 26 and Figure 27 The structure shown is a cross-section viewed in the direction of the arrows after being cut along each line. Furthermore, Figures 25-27 In the middle, to and Figures 2-4 The same symbols are used to mark the same components, and their descriptions are omitted.

[0166] The semiconductor package of the third embodiment is basically the same as the semiconductor package PG1 of the first embodiment. However, the semiconductor package of the third embodiment includes a memory device MD3 instead of a memory device MD. Figure 25 As shown, the storage device MD3 includes: chip C M3 It includes a memory cell array; and a chip C. P3 It includes the peripheral circuitry PC. Chip C M3 C P3 Its basic structure is similar to that of a chip C M C P same.

[0167] However, for example Figure 26 As shown, in chip C M3 External electrode areas R are respectively located near the corners a1, a2, a3, and a4 on the front side. T In the four external electrode regions R T Multiple third internal electrodes P are respectively set inside. T11 To replace multiple first internal electrodes P I1 Additionally, in chip C... M3 External electrode areas R are also provided near the corners a1, a2, a3, and a4 on the back side. T .For example Figure 25 As shown, in these external electrode regions R T Multiple third external electrodes P are respectively set inside. T12 To replace multiple first external electrodes P T1 Furthermore, the third internal electrode P T11 and the third external electrode P T12Its basic structure is similar to that of the first internal electrode P. I1 and the first external electrode P T1 same.

[0168] In addition, for example Figure 27 As shown, in chip C P3 External electrode areas R are respectively located near the corners b1, b2, b3, and b4 on the front side. T In the four external electrode regions R T Multiple fourth internal electrodes P are respectively set inside. T21 To replace multiple second internal electrodes P I2 Additionally, in chip C... P3 External electrode areas R are also provided near the corners b1, b2, b3, and b4 on the back side. T In these external electrode regions R T Multiple fourth external electrodes P are respectively set inside. T22 To replace multiple second external electrodes P T2 In addition, the fourth internal electrode P T21 and the fourth external electrode P T22 Its basic structure is similar to that of the second internal electrode P. I2 and the second external electrode P T2 same.

[0169] Furthermore, in the illustrated example, the external electrode region R T Set in chip C M3 C P3 Near the corner. However, this configuration is only an example, and the specific configuration can be adjusted appropriately.

[0170] In addition, chip C M3 Equipped with multiple first electrodes C TSV21 To replace multiple first electrodes C TSV1 Additionally, chip C P3 Equipped with multiple second electrodes C TSV22 To replace multiple second electrodes C TSV2 In addition, multiple first electrodes C TSV21 Its basic structure is similar to that of multiple first electrodes C TSV1 Same. Additionally, multiple second electrodes C TSV22 Its basic structure is related to multiple second electrodes C TSV2 same.

[0171] In addition, for example Figure 28 As shown, the storage device MD3 has a chip C P3 With chip C M3 Multiple bump electrodes B C3 Bump electrode B C3Chip C P3 With chip C M3 Electrical connection. In addition... Figure 28 Although not shown, the storage device MD3 also includes the bump electrode B of the first embodiment. C Multiple bump electrodes B C3 Set in a configuration with multiple bump electrodes B C area ( Figure 3 , Figure 4 , Figure 6 Region R C R P Different external electrode regions R T ( Figure 26 and Figure 27 Inside. Additionally, bump electrode B C3 The size is larger than bump electrode B C Size.

[0172] Multiple bump electrodes B C3 Chip C from a storage device MD3 M3 Multiple first electrodes C TSV21 , and chip C P3 Multiple second electrodes C TSV22 Electrical connection. Furthermore, in the third embodiment, similarly to the first embodiment, multiple bump electrodes B... MD Chip C from a storage device MD3 M3 Multiple first electrodes C TSV21 , and multiple second electrodes C in another storage device MD3 TSV22 Electrical connection. Like this, the controller die CD is connected to the chip C. P3 The peripheral circuit PC is connected via the first electrode C TSV21 and the second electrode C TSV22 Electrical connection. Therefore, in chip C... P3 The peripheral circuit PC transmits signals between the controller and the bare CD.

[0173] [Fourth Implementation]

[0174] Figure 29 and Figure 30 This is a schematic cross-sectional view showing an example of the configuration of the storage device MD4 according to the fourth embodiment. Figure 31 This is used to illustrate the use of bump electrode B MD4 A schematic cross-sectional view of the connection of the storage device MD4. Figure 29 It corresponds to Figure 5 The picture, Figure 30 It corresponds to Figure 6 The picture, Figure 31 It corresponds to Figure 8 The image. Furthermore... Figures 29-31 In the middle, to and Figure 5 , Figure 6 and Figure 8 The same symbols are used to mark the same components, and their descriptions are omitted.

[0175] In the storage device MD of the first embodiment, chip C M C P There are gaps between them. Furthermore, multiple bump electrodes B are disposed within these gaps. C ( Figure 5 and Figure 6 On the other hand, for example Figure 29 and Figure 30 As shown, in the storage device MD4 of the fourth embodiment, the chip C on the storage cell array side... M4 C on the PC side of the peripheral circuit P There are no gaps between them. Multiple bump electrodes B C41 Formed on chip C M4 On the wiring layer M3. Multiple bump electrodes B C41 Each with multiple first internal electrodes P I1 Connection, and not from chip C M4 The front protrudes. Multiple bump electrodes B C42 Formed on chip C P4 On the wiring layer M5'. Multiple bump electrodes B C42 Each with multiple second internal electrodes P I2 Connection, and not from chip C P4 The front is prominent. Furthermore, on chip C... M4 The front of the chip C P4 In the front-fitting state, multiple bump electrodes B C41 With multiple bump electrodes B C42 Connect them electrically separately.

[0176] For example, multiple bump electrodes B C41 Formed in multiple first internal electrodes P I1 Above. Multiple bump electrodes B C41 It is covered by insulating material. Then, the chip C... M4 The front side is ground. Multiple bump electrodes B C42 Multiple second internal electrodes P are formed respectively I2 Above. Multiple bump electrodes B C42 It is covered by insulating material. Then, the chip C... P4 The front side is polished. Then, the chip C... M4 The front of the chip C P4 The front surfaces are properly aligned. At this point, multiple bump electrodes B... C41 With multiple bump electrodes B C42Connect them electrically separately.

[0177] For example Figure 31 As shown, a plurality of first external electrodes P of a storage device MD4(1) T1 、and multiple second external electrodes P of another storage device MD4(2) T2 via multiple bump electrodes B MD4 Electrically connected separately. Multiple bump electrodes B MD4 For example, it contains solder. In addition, multiple bump electrodes B MD4 It can also contain conductive materials other than solder.

[0178] [Other Implementation Methods]

[0179] The semiconductor memory devices and manufacturing methods according to the first to fourth embodiments have been described above. However, the configuration and manufacturing methods of the semiconductor memory devices in the first to fourth embodiments are merely illustrative examples, and the specific configuration and manufacturing methods can be appropriately adjusted.

[0180] For example, in the semiconductor package PG1 of the first embodiment, a redistribution layer Lw can be used instead of the package substrate PS. Furthermore, the bump electrode shape in the first to fourth embodiments can be cylindrical, spherical, or the like. Additionally, as... Figure 3 and Figure 4 As shown, the chip has 4 memory planes MP, but it can also have 1 memory plane MP, 2 memory planes MP, or more than 4 memory planes MP.

[0181] Furthermore, the semiconductor package PG1 of the first embodiment has three memory devices MD(1), (2), and (3), but it may also have two or more memory devices. Additionally, the semiconductor package PG2 of the second embodiment has three chip C... M2 However, it can also have two chip Cs. M2 or 4 or more chips C M2 Furthermore, the semiconductor package of the third embodiment, like the semiconductor package PG1 of the first embodiment, may also include three memory devices MD3. Moreover, the semiconductor package of the third embodiment may also include two or more memory devices MD3.

[0182] Furthermore, the material of the bump electrode in the first to fourth embodiments can also be appropriately adjusted.

[0183] In addition, the chip C in embodiments 1 to 4 M C M2 C M3 C M4A semiconductor substrate may also be provided. In this case, a substrate-through electrode may also be provided in the semiconductor substrate. In this case, the first electrode C TSV1 C TSV11 C TSV21 It may also include a through electrode in the substrate.

[0184] Furthermore, regarding the manufacturing methods of the semiconductor memory device in the first and second embodiments, some steps may be omitted or the order of some steps may be changed. For example, the die screening test in step S6 may be omitted. Alternatively, the die screening test in step S6 may be performed after molding in step S7.

[0185] Furthermore, in the semiconductor memory device manufacturing method of the second embodiment, a rewiring layer is formed in step S11 after molding in step S7. However, molding in step S7 may also be performed after forming the rewiring layer in step S11.

[0186] Additionally, the bump electrode B in the second embodiment C B C2 and the bump electrode B of the third embodiment. C3 Also related to the bump electrode B in the fourth embodiment. C41 B C42 Similarly, chip C can be configured not to be from the second embodiment. M2 C P2 The front side and the chip C of the third embodiment M3 C P3 The front is prominent.

[0187] Additionally, the bump electrode B in the third embodiment MD The configuration can also be the same as the bump electrode B in the first embodiment. MD4 same.

[0188] [other]

[0189] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor memory device, comprising: The first storage device and the second storage device arranged in the first direction, and A plurality of first bump electrodes are disposed between the first storage device and the second storage device; and The first storage device and the second storage device each include: The first chip has a memory cell array and multiple first electrodes; The second chip has peripheral circuitry and multiple second electrodes; and Multiple second bump electrodes are disposed between the first chip and the second chip; The first direction is the thickness direction of the first storage device and the second storage device; At least one of the plurality of first bump electrodes is electrically connected to at least one of the plurality of first electrodes included in the first storage device and at least one of the plurality of second electrodes included in the second storage device; In the first storage device and the second storage device, at least one of the plurality of second bump electrodes electrically connects the storage cell array to the peripheral circuit. The peripheral circuitry of the first storage device is capable of controlling the storage cell array of the first storage device; At least one of the plurality of second bump electrodes of the first storage device is disposed between the peripheral circuit of the first storage device and the storage cell array of the first storage device, and the peripheral circuit of the first storage device and the storage cell array of the first storage device are connected in the first direction.

2. The semiconductor memory device according to claim 1, wherein in the first memory device and the second memory device, at least one of the plurality of second bump electrodes electrically connects at least one of the plurality of first electrodes to at least one of the plurality of second electrodes.

3. The semiconductor memory device according to claim 1, wherein the first memory device and the second memory device each have a plurality of third bump electrodes disposed between the first chip and the second chip. In the first storage device and the second storage device, at least one of the plurality of third bump electrodes electrically connects at least one of the plurality of first electrodes to at least one of the plurality of second electrodes.

4. The semiconductor memory device of claim 3, wherein the plurality of third bump electrodes are disposed in a region different from the region where the plurality of second bump electrodes are disposed, in a plane orthogonal to the first direction.

5. The semiconductor memory device of claim 3, wherein the size of the third bump electrode is larger than the size of the second bump electrode in a plane orthogonal to the first direction.

6. The semiconductor memory device of claim 1, wherein the first bump electrode and the second bump electrode comprise different materials.

7. The semiconductor memory device of claim 1, wherein the size of the second bump electrode is smaller than the size of the first bump electrode in a plane (XY plane) orthogonal to the first direction.

8. A semiconductor memory device comprising: Two first chips are arranged in the first direction and each has a memory cell array and multiple electrodes; The second chip, together with the two first chips, is arranged in the first direction and has peripheral circuitry. A plurality of first bump electrodes are disposed between one of the first chips and the second chip; and Multiple second bump electrodes are disposed between the two first chips; and The first direction is the thickness direction of the two first chips and the second chip; At least one of the plurality of first bump electrodes electrically connects the memory cell array of one of the first chips to the peripheral circuitry of the second chip; The plurality of second bump electrodes electrically connect the plurality of electrodes of the two first chips respectively, and electrically connect the memory cell array of the other first chip to the peripheral circuit of the second chip. The peripheral circuit of the second chip can control the memory cell array of the two first chips; At least one of the plurality of first bump electrodes is disposed between the memory cell array of one of the first chips and the peripheral circuit of the second chip, and the memory cell array of one of the first chips and the peripheral circuit of the second chip are connected in the first direction.

9. The semiconductor memory device of claim 8, wherein the first bump electrode and the second bump electrode comprise different materials.

10. The semiconductor memory device of claim 8, wherein the size of the second bump electrode is smaller than the size of the first bump electrode in a plane orthogonal to the first direction.

11. A method for manufacturing a semiconductor memory device, comprising the following steps: Multiple first chips with memory cell arrays are formed; Multiple second chips with peripheral circuits are formed; Perform a first test on the plurality of first chips and the plurality of second chips; Based on the results of the first test, one of the first chips is selected from the plurality of first chips; Based on the results of the first test, one of the second chips is selected from the plurality of second chips; Based on the results of the first test, one third chip is selected from the other first chips and the other second chips; The selected first chip and the selected second chip are electrically connected via a plurality of first bump electrodes, with at least a portion of the plurality of first bump electrodes disposed between the memory cell array of the selected first chip and the peripheral circuit of the selected second chip. The selected first chip and the selected third chip are electrically connected via a plurality of second bump electrodes; and The peripheral circuitry of the selected second chip is capable of controlling the memory cell array of the selected first chip.

12. The method of manufacturing a semiconductor memory device according to claim 11, wherein a second test is performed on the electrically connected first chip and second chip.

13. The method of manufacturing a semiconductor memory device according to claim 12, wherein a rewiring layer is formed on the first chip and the second chip after the second test has been performed.

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