Test structure, failure analysis localization method, and electronic device

Abstract

The application provides a test structure, a failure analysis positioning method and electronic equipment. Specifically, in the test structure provided by the application, a plurality of test units and pad units corresponding to each test unit are included, a PN junction is built in each pad unit corresponding to each test unit, and then, according to the principle that the photons radiated by the PN junction under forward bias can be detected by an InGaAs CCD, a test structure capable of accurately and quickly positioning the test unit with a metal interconnection line short circuit (leakage) failure from a plurality of test units with the same structure is designed without occupying the substrate (wafer) space of the test structure, that is, the positioning speed of the short circuit failure is accelerated.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a test structure, a failure analysis and location method, and an electronic device. Background Technology

[0002] In semiconductor manufacturing, various test structures are typically designed to monitor various semiconductor process issues on the production line. If electrical failure events occur during the monitoring of these test structures, the causes of these failures can be analyzed to help resolve process problems on-line, thereby promoting the research and development of semiconductor processes.

[0003] Failure localization is a prerequisite for failure analysis, requiring the identification of the failure location using various methods. Currently, semiconductor failure localization methods primarily utilize tools such as EMMI (Electrical Emission Microscopy), OBIRCH (Optical Impedance Transformation Microscopy), and Thermal (Thermal Emission Microscopy). In practical applications, when the test structure contains numerous repetitive or similar structures, failure points need to be captured at lower magnification before accurately locating the target area. If the leakage current of the failed structure is small, in the nA range, the capture time needs to be extended to obtain hotspots. At this point, the background noise signal is significant, overwhelming the failure point signal and making localization impossible. To minimize background noise interference, failure points need to be captured at higher magnification targeting the target area. However, when using EMMI / OBIRCH or Thermal for failure localization, locating the test structure under an InGaAs lens takes a considerable amount of time. Summary of the Invention

[0004] The purpose of this invention is to provide a test structure, a failure analysis and location method, and an electronic device. The invention proposes a new test structure and a failure analysis and location method based on this new test structure for detecting whether a short circuit (leakage) failure has occurred in a metal interconnect, thereby improving the accuracy and efficiency of locating leakage failures.

[0005] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a test structure, specifically comprising: multiple test units and multiple pad units, wherein,

[0006] The plurality of test units have the same structure and are arranged at intervals in the X and Y directions to form a test array.

[0007] The plurality of pad units each have at least one PN junction inside, and the plurality of pad units are respectively located in the gap between two adjacent test units in the test array or in the gap on one side of a test unit, and are electrically connected to a test unit.

[0008] Furthermore, the test unit may specifically include: a serpentine metal wire and two relatively interlaced test comb structures. Each test comb structure includes several parallel finger structures and a handle connecting one end of each finger structure on the same side. All handles in each test comb structure are connected together by a lead wire. The serpentine metal wire is located between the interlaced finger structures and is on the same plane as all the finger structures but does not contact them.

[0009] Furthermore, each of the pad units may include four test pads; wherein, two of the test pads and the two ends of the serpentine metal wires in the test unit corresponding to them are electrically connected, while the remaining two test pads are electrically connected to the external ends of the leads of the two test comb structures included in the test unit after all their stems are connected together.

[0010] Furthermore, the test structure also includes a substrate for supporting the plurality of test units and the plurality of pad units. The PN junction contained in each pad unit is formed in the substrate below a test pad contained in the test unit by an ion implantation process and is electrically connected to the test pad through a conductive plug.

[0011] Secondly, based on the test structure described above, the present invention also provides a failure analysis and localization method, which may specifically include the following steps:

[0012] A test structure as described above is provided, wherein the test structure includes multiple test units and multiple pad units, and each pad unit has at least one PN junction disposed inside;

[0013] The PN junction in the pad unit of the test structure is turned on, and the test unit corresponding to the pad unit with PN junction conduction is located using an image sensor, and the test unit is defined as the target area.

[0014] The PN junction in the target area is reverse biased, and hot spots are captured using a microscope to locate the leakage failure location in the target area.

[0015] Furthermore, after defining the test unit as the target area and before reversing the PN junction in the target area, the failure analysis and localization method further includes: moving the target area to the center of the field of view and increasing the magnification.

[0016] Furthermore, the target area is a test unit containing short-circuit bright spots in an image obtained by hotspot capture using an image sensor.

[0017] Furthermore, after determining the exact location of the leakage failure defect in the target area, the failure analysis and location method may further include: performing further physical property failure analysis on the target area to determine the cause of the leakage failure location.

[0018] Furthermore, the microscope can be a photoresistivity-changing microscope or an electron beam resistivity-changing microscope.

[0019] Thirdly, the present invention also provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus;

[0020] Memory, used to store computer programs;

[0021] The processor, when executing a program stored in memory, implements the method steps of the failure analysis and location method described above.

[0022] Fourthly, based on the same inventive concept as the test structure described above, the present invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method steps of the failure analysis and location method described in any of the first aspects.

[0023] Fifthly, based on the same inventive concept as the failure location method described above, the present invention also provides a computer program product containing instructions that, when run on a computer, cause the computer to execute the method steps of any of the failure analysis and location methods described in the first aspect above.

[0024] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0025] In a novel test structure proposed in this invention, there are multiple test units and pad units corresponding to each test unit. A PN junction is built into the pad unit corresponding to each test unit. Then, by utilizing the principle that the photons emitted by the PN junction when it is forward biased can be detected by an InGaAsCCD, a test structure can be designed to accurately and quickly locate the test unit with short circuit (leakage) failure in the metal interconnect from among many test units with the same structure without occupying additional substrate (wafer) space in the test structure. That is, the speed of short circuit failure location is accelerated.

[0026] Furthermore, in the failure analysis and location method proposed in this invention, since each test unit in the test structure is based on a PN junction built into its corresponding pad unit, it can first utilize the principle that when the PN junction is forward biased (on), a large number of electron-hole pairs recombine and emit photons, and these photons can be detected by InGaAsCCD, to quickly determine the test unit (target area) where a short-circuit failure occurs. Then, OBIRCH / EBIRCH is used to capture hotspots in the target area to accurately and efficiently determine the specific location of the short-circuit failure in the test unit. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a test structure provided in one embodiment of the present invention;

[0028] Figure 2 The present invention provides a method for addressing [issues] in one embodiment. Figure 1 A schematic diagram of the structure after electrical connection between any test unit and its corresponding pad unit;

[0029] Figure 3 The present invention provides a method for addressing [issues] in one embodiment. Figure 2 A structural diagram showing the specific location of the PN junction contained in the described structure;

[0030] Figure 4 This is a flowchart illustrating a failure analysis and location method provided in one embodiment of the present invention. Detailed Implementation

[0031] As described in the background section, there are currently two common methods for locating the target failure location: 1. Locate the target area by using an InGaAs lens image and corresponding to the layout. This method is time-consuming. 2. Use a laser to print a mark near the target area and locate the target location by using an InGaAs lens image. However, this method will damage the integrity of the wafer and may affect other tests and analyses.

[0032] However, when the test structure contains many repetitive or similar structures, failure points need to be captured at a lower magnification before the target area is accurately located. If the leakage current of the failed structure is small, in the nA range, the capture time needs to be extended to obtain the hot spot. At this time, the background noise signal is large, which will drown out the failure point signal and make it impossible to locate. In order to minimize the interference of background noise, failure points need to be captured in the target area at a higher magnification. However, when using EMMI / OBIRCH or Thermal for failure localization, it takes a long time to find the location of the test structure under the InGaAs lens.

[0033] Therefore, the present invention provides a test structure, a failure analysis and location method, and an electronic device, to propose a new test structure and a failure analysis and location method based on the proposed test structure for detecting whether a short circuit (leakage) failure has occurred in a metal interconnect, so as to improve the accuracy and efficiency of leakage failure location.

[0034] It should be noted that in the back-end metal interconnect process of semiconductor manufacturing, the interconnect lines often experience short-circuit or open-circuit failures, primarily due to design and process issues. To address this problem, and in order to evaluate the design structure and monitor the stability of the on-line process, it is necessary to extract the complex product structure individually or reassemble it into repeatable, large-area, easily testable structures. Electrical testing of these test structures yields a large number of corresponding electrical parameters. Analyzing these parameters allows for early detection and resolution of problems. This type of structure is called a test structure.

[0035] The test structure, failure analysis and location method, and electronic device proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention. Many specific details are set forth in the following description to provide a thorough understanding of this invention; however, this invention may be implemented in other ways different from those described herein, and therefore this invention is not limited to the specific embodiments disclosed below.

[0036] See Figures 1-3 , Figure 1 This is a schematic diagram of a test structure provided in one embodiment of the present invention; Figure 2 The present invention provides a method for addressing [issues] in one embodiment. Figure 1 A schematic diagram of the structure after electrical connection between any test unit and its corresponding pad unit; Figure 3 The present invention provides a method for addressing [issues] in one embodiment. Figure 2 A structural diagram showing the specific location of the PN junction contained in the structure.

[0037] See Figure 1 The new test structure proposed in this invention for detecting whether a metal interconnect has a short circuit (leakage) failure may include: multiple test units 11 and multiple pad units 22.

[0038] The multiple test units 11 have the same structure and are arranged at intervals in the X and Y directions to form a test array.

[0039] See Figure 2 and Figure 3 Each of the plurality of pad units 22 has at least one PN junction inside, and the plurality of pad units 22 are respectively located in the gap between two adjacent test units 11 in the test array or in the gap on one side of a test unit 11, and are electrically connected to a test unit 11.

[0040] Furthermore, the test unit 11 includes a serpentine metal wire 11.1 and two relatively interleaved test comb structures 11.2a and 11.2b. Each test comb structure (11.2a or 11.2b) includes several parallel finger structures and a handle connecting one end of each finger structure on the same side. All handles in each test comb structure are connected together by a lead wire. The serpentine metal wire is located between the interlaced finger structures and is on the same plane as all the finger structures but does not contact them.

[0041] Furthermore, each of the pad units 22 includes four test pads; wherein, two of the test pads are electrically connected to the two ends of the serpentine metal wires 11.1 in the test unit 11 corresponding to them, while the remaining two test pads are electrically connected to the external ends of the leads of the two test comb structures contained in the test unit after all their stems are connected together.

[0042] Furthermore, the test structure also includes a substrate 100 for supporting the plurality of test units 11 and the plurality of pad units 22, such as... Figure 3 As shown, the PN junction contained in each of the pad units 22 can be formed in the substrate 100 below a test pad contained in the test unit 11 by an ion implantation process, and electrically connected to the test pad through a conductive plug.

[0043] Among them, such as Figure 3 As shown, as an example, the present invention forms a PN junction by implanting N-type ions into a P-type doped substrate 100.

[0044] In this embodiment, a PN junction can be set in the substrate corresponding to one test pad in each pad unit. Then, by utilizing the principle that the PN junction can emit electrons under electron beam scanning, a new test structure can be proposed to detect whether a short circuit (leakage) failure of a metal interconnect is achieved without occupying additional substrate (wafer) space in the test structure.

[0045] It should be noted that the examples provided in this invention are... Figure 2 In the middle, it is to show the location where the PN junction is formed, therefore it is in Figure 2 This is just one example; its specific structure and formation location require further reference. Figure 3 Furthermore, in the test structure provided by this invention, the specific connection relationship between each test unit 11 and the four test pads in its corresponding pad unit 22 should be as follows: each end of the serpentine metal wire 11.1 is connected to a test pad, and the two relatively staggered test comb structures 11.2a and 11.2b also have an external terminal and are connected to a test pad.

[0046] Furthermore, based on the present invention, such as Figures 1-3 The present invention also provides a failure analysis and location method based on the test structure shown.

[0047] See Figure 4 The failure analysis and location method provided by the present invention may include at least the following steps:

[0048] Step S401: First, a test structure is provided, wherein the test structure includes multiple test units and multiple pad units, and each pad unit has at least one PN junction inside.

[0049] In this step, first provide a... Figures 1-3 The test structure described herein can be formed using conventional semiconductor manufacturing processes. For example, specifically, ion implantation can be performed on a material such as silicon, germanium, silicon germanium, silicon carbide, silicon carbide, indium arsenide, gallium arsenide, indium phosphide, or other III / V compound semiconductors, or silicon-on-insulator, silicon-on-insulator, silicon-on-germanide, silicon-on-insulator, and germanium-on-insulator to form a PN junction. Subsequently, the test unit and the pad unit are formed sequentially using deposition and etching processes.

[0050] Step S402: Turn on the PN junction in the pad unit of the test structure, and use the image sensor CCD to locate the test unit corresponding to the pad unit with the PN junction conducting, and define the test unit as the target area.

[0051] In this step, a forward bias voltage can be applied to both ends of the PN junction to forward bias it and turn it on. Then, using the principle that the photons emitted by the PN junction when it is forward biased can be detected by the InGaAsCCD, the short-circuit leakage problem in which test unit has occurred can be determined from the multiple test units of the test structure. In this embodiment, the test unit where the short-circuit leakage problem occurs is defined as the target area.

[0052] Step S403: Reverse bias the PN junction in the target area and use a microscope to capture hot spots in order to locate the leakage failure location in the target area.

[0053] In this step, after defining the test unit as the target region, and before reversing the PN junction in the target region, the target region can be moved to the center of the field of view and magnified to obtain the following result: Figure 2 The structure shown is an enlarged version of the structure described above. Then, a reverse bias voltage is applied across the PN junction, while the other two test pads of the pad unit containing the PN junction are applied with low voltage. This ensures that the PN junction corresponding to the pad unit in the target area is not visible in the image obtained using OBIRCH / EBIRCH, but rather as a bright spot corresponding to the short-circuit leakage failure location in the test unit of the target area. This achieves the goal of detecting whether a short-circuit (leakage) failure has occurred in the metal interconnect, thereby improving the accuracy and efficiency of leakage failure location.

[0054] Following the step of determining the exact location of the leakage failure defect in the target area, the failure analysis and location method further includes:

[0055] Step S404: Perform further physical property failure analysis on the target area to determine the cause of the leakage failure location.

[0056] In summary, the novel test structure proposed in this invention includes multiple test units and pad units corresponding to each test unit. A PN junction is built into the pad unit corresponding to each test unit. By utilizing the principle that the photons emitted by the PN junction when it is forward biased can be detected by an InGaAsCCD, a test structure can be designed to accurately and quickly locate the test unit with short circuit (leakage) failure in the metal interconnect from among many test units with the same structure without occupying additional substrate (wafer) space in the test structure. That is, the speed of short circuit failure location is accelerated.

[0057] Furthermore, in the failure analysis and location method proposed in this invention, since each test unit in the test structure is based on a PN junction built into its corresponding pad unit, it can first utilize the principle that when the PN junction is forward biased (on), a large number of electron-hole pairs recombine and emit photons, and these photons can be detected by InGaAsCCD, to quickly determine the test unit (target area) where a short-circuit failure occurs. Then, OBIRCH / EBIRCH is used to capture hotspots in the target area to accurately and efficiently determine the specific location of the short-circuit failure in the test unit.

[0058] Furthermore, embodiments of the present invention also provide an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus.

[0059] Memory, used to store computer programs;

[0060] When the processor executes the program stored in the memory, it implements the steps described in the above-described failure analysis and location method.

[0061] For details on the implementation of each step of this method and related explanations, please refer to the above. Figure 4 The method embodiments shown are not described in detail here.

[0062] In addition, other implementations of the application setup method implemented by the processor executing the program stored in the memory are the same as those mentioned in the aforementioned method embodiment section, and will not be repeated here.

[0063] In another embodiment of the present invention, a computer-readable storage medium is provided, wherein a computer program is stored therein, and when the computer program is executed by a processor, it implements the steps of the above-described failure analysis and location method.

[0064] In another embodiment of the present invention, the present invention also provides a computer program product containing instructions that, when run on a computer, causes the computer to execute the above-described failure analysis and location method.

[0065] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., [missing information]), or a semiconductor medium (e.g., a solid-state drive (SSD)).

[0066] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0067] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments for apparatus, user terminals, computer-readable storage media, and computer program products are basically similar to the method embodiments, and therefore the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0068] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A failure analysis and location method, characterized in that, include: A test structure is provided, the test structure comprising: Multiple test units, all of which have the same structure, are arranged sequentially at intervals in the X and Y directions to form a test array; Multiple pad units, each of which has at least one PN junction inside, and the multiple pad units are respectively located in the gap between two adjacent test units in the test array or in the gap on one side of a test unit, and are electrically connected to a test unit. The PN junction in the pad unit of the test structure is turned on, and the test unit corresponding to the pad unit with PN junction conduction is located using an image sensor, and the test unit is defined as the target area. The PN junction in the target area is reverse biased, and hot spots are captured using a microscope to locate the leakage failure location in the target area.

2. The failure analysis and location method as described in claim 1, characterized in that, The test unit includes a serpentine metal wire and two intersecting test comb structures. Each test comb structure includes several parallel finger structures and a handle connecting one end of each finger structure on the same side. All handles in each test comb structure are connected together by a lead wire. The serpentine metal wire is located between the intersecting finger structures and is on the same plane as all the finger structures but does not contact them.

3. The failure analysis and location method as described in claim 2, characterized in that, Each of the pad units includes four test pads; wherein, two of the test pads are electrically connected to the two ends of the serpentine metal wires in the test unit corresponding to them, and the remaining two test pads are electrically connected to the external ends of the leads of the two test comb structures contained in the test unit after all their stems are connected together.

4. The failure analysis and location method as described in claim 3, characterized in that, The test structure also includes a substrate for supporting the plurality of test units and the plurality of pad units. The PN junction contained in each pad unit is formed in the substrate below a test pad contained in the test unit by an ion implantation process and is electrically connected to the test pad by a conductive plug.

5. The failure analysis and location method as described in claim 1, characterized in that, After defining the test unit as the target area, and before reversing the PN junction in the target area, the failure analysis and localization method further includes: moving the target area to the center of the field of view and increasing the magnification.

6. The failure analysis and location method as described in claim 1, characterized in that, The target area is a test unit containing short-circuit bright spots in an image obtained by using an image sensor to capture hotspots.

7. The failure analysis and location method as described in claim 1, characterized in that, After determining the exact location of the leakage failure defect in the target area, the failure analysis and location method further includes: performing further physical property failure analysis on the target area to determine the cause of the leakage failure.

8. The failure analysis and location method as described in claim 1, characterized in that, The microscope is a photoresistivity alteration microscope or an electron beam resistivity alteration microscope.

9. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; When a processor executes a program stored in a memory, it implements the method steps of the failure analysis and location method according to any one of claims 1 to 8.

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