Semiconductor device and method of manufacturing the same

Abstract

This application relates to a semiconductor device and its fabrication method. The semiconductor device includes: a substrate, an epitaxial layer of a first conductivity type, a buried layer of a second conductivity type, a gate structure, a cover dielectric layer, a gate lead-out electrode, a via, a source lead-out electrode, and an insulating layer. The cover dielectric layer covers the gate structure and has an opening that exposes the gate structure. The gate lead-out electrode is located at least within the opening and is in contact with the gate structure. The via is located within the opening and extends through the gate lead-out electrode and the gate structure along its thickness direction to expose the buried layer of the second conductivity type. The source lead-out electrode is located within the via and is electrically connected to the buried layer of the second conductivity type. The insulating layer is located between the source lead-out electrode, the gate lead-out electrode, and the gate structure. The above semiconductor device has good surge current resistance and reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] With the continuous development of semiconductor processing technology, semiconductor devices are increasingly being used in electronics, communications and other fields due to their smaller size, higher performance and higher conversion efficiency.

[0003] Existing conventional vertical double-diffused metal-oxide-semiconductor (VDMOS) devices only have parasitic diodes in the cell array region. Therefore, the area of ​​the diodes in VDMOS devices is relatively small, resulting in weak surge current resistance and thus low device reliability.

[0004] Therefore, improving the surge current resistance of VDMOS devices is an urgent problem to be solved. Summary of the Invention

[0005] Therefore, it is necessary to provide a semiconductor device and its fabrication method to effectively improve the surge current resistance of VDMOS devices.

[0006] This application provides a semiconductor device, including: a substrate, an epitaxial layer of a first conductivity type, a buried layer of a second conductivity type, a gate structure, a cover dielectric layer, a gate lead-out electrode, a via, a source lead-out electrode, and an isolation insulating layer. The epitaxial layer of the first conductivity type is located on the surface of the substrate. The buried layer of the second conductivity type is located within the epitaxial layer of the first conductivity type. The gate structure is located on the surface of the epitaxial layer of the first conductivity type away from the substrate. The cover dielectric layer covers the gate structure; the cover dielectric layer has an opening that exposes the gate structure. The gate lead-out electrode is located at least within the opening and is in contact with the gate structure. The via is located within the opening and extends along its thickness through the gate lead-out electrode and the gate structure to expose the buried layer of the second conductivity type. The source lead-out electrode is located within the via and is electrically connected to the buried layer of the second conductivity type. The isolation insulating layer is located between the source lead-out electrode and the gate lead-out electrode and the gate structure.

[0007] In this embodiment, the semiconductor device adopts the structure described above. The via in the semiconductor device penetrates both the gate electrode and the gate structure, allowing the source electrode to be electrically connected to the buried layer of the second conductivity type via the via. Thus, without increasing the area of ​​the semiconductor device or occupying its effective area, this application integrates the diode within the essential epitaxial layer of the semiconductor device by electrically connecting the source electrode to the buried layer of the second conductivity type via the via, thereby increasing the area of ​​the diode in the semiconductor device and improving its surge current resistance. Therefore, the semiconductor device described above has good surge current resistance and reliability.

[0008] Optionally, the semiconductor device further includes: a metal contact layer located at the bottom of the lead-out hole and between the source lead-out electrode and the buried layer of the second conductivity type, and in contact with the buried layer of the second conductivity type.

[0009] In this embodiment, the metal contact layer between the source electrode and the buried layer of the second conductivity type facilitates the formation of a good ohmic contact between the source electrode and the buried layer of the second conductivity type, thereby improving the electrical performance of the diode.

[0010] Optionally, the orthographic projections of the openings and leads on the surface of the epitaxial layer of the first conductivity type away from the substrate are both located within the buried layer of the second conductivity type.

[0011] Optionally, the gate structure includes: a gate dielectric layer located on the surface of the epitaxial layer of the first conductivity type away from the substrate; and a gate located on the surface of the gate dielectric layer away from the epitaxial layer of the first conductivity type.

[0012] Optionally, the first conductivity type is N-type and the second conductivity type is P-type; or the first conductivity type is P-type and the second conductivity type is N-type.

[0013] Based on the same inventive concept, this application also provides a method for fabricating a semiconductor device, characterized by comprising the following steps: providing a substrate; forming an epitaxial layer of a first conductivity type on the surface of the substrate; forming a buried layer of a second conductivity type within the epitaxial layer of the first conductivity type; forming a gate structure on the surface of the epitaxial layer of the first conductivity type away from the substrate; forming a covering dielectric layer that covers the gate structure; having an opening in the covering dielectric layer that exposes the gate structure; forming a gate lead electrode within the opening that is in contact with the gate structure; forming a lead hole within the gate lead electrode and within the gate structure that exposes the buried layer of the second conductivity type; forming an isolation insulating layer on the sidewall of the lead hole; forming a source lead electrode within the lead hole that is electrically connected to the buried layer of the second conductivity type.

[0014] In this embodiment, the semiconductor device is fabricated using the method described above. First, a via is formed within the gate electrode and the gate structure to expose a buried layer of the second conductivity type. Second, a source electrode is formed within the via to electrically connect the source electrode to the buried layer of the second conductivity type. Thus, without increasing the area of ​​the semiconductor device or occupying its effective area, this application integrates the diode within the essential epitaxial layer of the semiconductor device by electrically connecting the source electrode to the buried layer of the second conductivity type through the via, thereby increasing the diode area and improving the surge current resistance of the semiconductor device. Therefore, the above-described semiconductor device fabrication method improves the surge current resistance of the semiconductor device, thereby improving its reliability, without increasing additional fabrication costs.

[0015] Optionally, forming a gate structure on the surface of the epitaxial layer of the first conductivity type away from the substrate includes: forming a gate dielectric material layer on the surface of the epitaxial layer of the first conductivity type away from the substrate; forming a gate conductive layer on the surface of the gate dielectric material layer away from the epitaxial layer of the first conductivity type; etching the gate conductive layer to form a gate, and etching the gate dielectric material layer to form a gate dielectric layer, wherein the gate dielectric layer and the gate together constitute a gate structure.

[0016] Optionally, forming a cover dielectric layer includes: forming a cover dielectric material layer covering the gate structure; and etching the cover dielectric material layer to form a cover dielectric layer with openings.

[0017] Optionally, before forming the source lead electrode in the lead hole, the method further includes: forming a metal contact layer at the bottom of the lead hole, the metal contact layer being in contact with a buried layer of the second conductivity type; and the source lead electrode being in contact with the surface of the metal contact layer away from the buried layer of the second conductivity type.

[0018] In this embodiment, a metal contact layer is formed between the source electrode and the buried layer of the second conductivity type, which is beneficial for forming a good ohmic contact between the source electrode and the buried layer of the second conductivity type, thereby improving the electrical performance of the diode.

[0019] Optionally, the first conductivity type is N-type and the second conductivity type is P-type; or the first conductivity type is P-type and the second conductivity type is N-type. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a cross-sectional structural diagram of a semiconductor device provided in one embodiment of this application;

[0022] Figure 2 This is a flowchart of a semiconductor device fabrication method provided in one embodiment of this application;

[0023] Figure 3 This is a schematic cross-sectional view of the structure obtained in step S10 of the semiconductor device fabrication method provided in one embodiment of this application;

[0024] Figure 4 This is a schematic cross-sectional view of the structure obtained in step S20 of the semiconductor device fabrication method provided in one embodiment of this application;

[0025] Figure 5 This is a flowchart of the process of forming a gate structure in a semiconductor device fabrication method provided in one embodiment of this application;

[0026] Figure 6 This is a schematic cross-sectional view of the structure obtained in step S30 of the semiconductor device fabrication method provided in one embodiment of this application;

[0027] Figure 7 This is a schematic cross-sectional view of the structure obtained in step S40 of the semiconductor device fabrication method provided in one embodiment of this application;

[0028] Figure 8 This is a schematic cross-sectional view of the structure obtained in step S60 of the semiconductor device fabrication method provided in an embodiment of this application.

[0029] Figure 9 This is a schematic cross-sectional view of the structure obtained in step S70 of the semiconductor device fabrication method provided in one embodiment of this application;

[0030] Figure 10 This is a cross-sectional view of the structure obtained in step S80 of the semiconductor device fabrication method provided in one embodiment of this application.

[0031] Explanation of reference numerals in the attached figures:

[0032] 10 - Substrate; 11 - Epitaxial layer of first conductivity type; 111 - Buried layer of second conductivity type; 20 - Gate structure; 21 - Gate dielectric layer; 22 - Gate; 30 - Cover dielectric layer; 40 - Isolation insulating layer; 50 - Metal contact layer;

[0033] A - Gate electrode; B - Source electrode; G - Opening; H - Through-hole. Detailed Implementation

[0034] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, which illustrate embodiments of the present disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0036] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0037] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0038] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0039] When used here, "deposition" processes include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0040] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0041] With the continuous development of semiconductor processing technology, semiconductor devices are increasingly being used in electronics, communications and other fields due to their smaller size, higher performance and higher conversion efficiency.

[0042] Existing conventional vertical double-diffused metal-oxide-semiconductor (VDMOS) devices only have parasitic diodes in the cell array region. Therefore, the area of ​​the diodes in VDMOS devices is relatively small, resulting in weak surge current resistance and thus low device reliability.

[0043] Therefore, improving the surge current resistance of VDMOS devices is an urgent problem to be solved.

[0044] In view of the shortcomings of the prior art, the purpose of this application is to provide a semiconductor device and a method for fabricating the same, so as to effectively improve the surge current resistance of VDMOS devices.

[0045] Please see Figure 1 This application provides a semiconductor device, including: a substrate 10, an epitaxial layer 11 of a first conductivity type, a buried layer 111 of a second conductivity type, a gate structure 20, a covering dielectric layer 30, a gate lead-out electrode A, a source lead-out electrode B, and an isolation insulating layer 40.

[0046] In this design, an epitaxial layer 11 of a first conductivity type is located on the surface of the substrate 10. A buried layer 111 of a second conductivity type is located within the epitaxial layer 11 of the first conductivity type. A gate structure 20 is located on the surface of the epitaxial layer 11 of the first conductivity type away from the substrate 10. A covering dielectric layer 30 covers the gate structure 20; the covering dielectric layer 30 has an opening that exposes the gate structure 20. A gate lead-out electrode A, located at least within the opening, is in contact with the gate structure 20. A via is located within the opening and extends along the thickness direction through the gate lead-out electrode A and the gate structure 20 to expose the buried layer 111 of the second conductivity type. A source lead-out electrode B, located within the via H, is electrically connected to the buried layer 111 of the second conductivity type. An insulating layer 40 is located between the source lead-out electrode B and the gate lead-out electrode A and the gate structure 20.

[0047] In this embodiment, the semiconductor device adopts the structure described above. The via in the semiconductor device penetrates both the gate electrode A and the gate structure 20, allowing the source electrode B to be electrically connected to the buried layer 111 of the second conductivity type via the via. Thus, without increasing the area of ​​the semiconductor device or occupying its effective area, this application integrates the diode within the essential epitaxial layer 11 of the semiconductor device by electrically connecting the source electrode B to the buried layer 111 of the second conductivity type via the via, thereby increasing the area of ​​the diode in the semiconductor device and improving its surge current resistance. Therefore, the semiconductor device described above has good surge current resistance and reliability.

[0048] Optionally, the substrate 10 can be a single-layer structure or a multilayer structure. For example, the substrate 10 can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 can be a layered substrate comprising, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0049] Optionally, the material of the epitaxial layer 11 of the first conductivity type includes silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), or other III / V or II / VI semiconductors.

[0050] In some examples, the first conductivity type is N-type and the second conductivity type is P-type; or the first conductivity type is P-type and the second conductivity type is N-type.

[0051] For example, the epitaxial layer 11 of the first conductivity type is an N-type epitaxial layer, and the buried layer 111 of the second conductivity type is a P-type buried layer; or the epitaxial layer 11 of the first conductivity type is a P-type epitaxial layer, and the buried layer 111 of the second conductivity type is an N-type buried layer.

[0052] In some examples, please refer to [link / reference]. Figure 1 The gate structure 20 includes: a gate dielectric layer 21 located on the surface of the epitaxial layer 11 of the first conductivity type away from the substrate 10; and a gate 22 located on the surface of the gate dielectric layer 21 away from the epitaxial layer 11 of the first conductivity type.

[0053] For example, the gate dielectric layer 21 includes a gate oxide layer. The gate oxide layer may include, but is not limited to, a silicon oxide layer.

[0054] For example, the material of gate 22 includes, but is not limited to, polysilicon.

[0055] In some examples, the gate lead electrode A may also be located on the surface of the covering dielectric layer 30 away from the gate structure 20.

[0056] For example, the covering dielectric layer 30 may include, but is not limited to, a silicon oxide layer.

[0057] For example, the material of the gate lead-out electrode A may include, but is not limited to, aluminum (Al).

[0058] Accordingly, in some examples, the insulating layer 40 may also be located on a portion of the surface of the gate lead electrode A away from the buried layer 111 of the second conductivity type.

[0059] Optionally, the material of the insulating layer 40 may include, but is not limited to, silicon oxide or polyimide.

[0060] Accordingly, in some examples, the source lead electrode B may also be located on a portion of the surface of the insulating layer 40 away from the buried layer 111 of the second conductivity type.

[0061] For example, the material of the source electrode B can be, but is not limited to, aluminum (Al).

[0062] In some examples, the semiconductor device further includes a metal contact layer 50 located at the bottom of the lead-out hole and between the source lead-out electrode B and the buried layer 111 of the second conductivity type, and in contact with the buried layer 111 of the second conductivity type.

[0063] In this embodiment, the metal contact layer 50 between the source electrode B and the buried layer 111 of the second conductivity type facilitates the formation of a good ohmic contact between the source electrode B and the buried layer 111 of the second conductivity type, thereby improving the electrical performance of the diode.

[0064] For example, the material of the metal contact layer 50 may include, but is not limited to, nickel (Ni) or titanium (Ti).

[0065] In some examples, the orthographic projections of the openings and leads on the surface of the epitaxial layer 11 of the first conductivity type away from the substrate 10 are both located within the buried layer 111 of the second conductivity type.

[0066] Based on the same inventive concept, please refer to Figure 2 This application also provides a method for fabricating a semiconductor device, comprising the following steps.

[0067] S10: Provide a substrate; form an epitaxial layer of a first conductivity type on the surface of the substrate.

[0068] S20: A buried layer of the second conductivity type is formed within an epitaxial layer of the first conductivity type.

[0069] S30: A gate structure is formed on the surface of the epitaxial layer of the first conductivity type away from the substrate.

[0070] S40: A cover dielectric layer is formed, which covers the gate structure; the cover dielectric layer has an opening that exposes the gate structure.

[0071] S50: A gate lead-out electrode is formed in the opening, and the gate lead-out electrode is in contact with the gate structure.

[0072] S60: A lead-out hole is formed in the gate lead-out electrode and in the gate structure, and the lead-out hole exposes a buried layer of the second conductivity type.

[0073] S70: An insulating layer is formed on the sidewall of the lead-out hole.

[0074] S80: A source electrode is formed in the lead-out hole, and the source electrode is electrically connected to the buried layer of the second conductivity type.

[0075] In this embodiment, the semiconductor device is fabricated using the method described above. First, a via is formed within the gate electrode and the gate structure to expose a buried layer of the second conductivity type. Second, a source electrode is formed within the via to electrically connect the source electrode to the buried layer of the second conductivity type. Thus, without increasing the area of ​​the semiconductor device or occupying its effective area, this application integrates the diode within the essential epitaxial layer of the semiconductor device by electrically connecting the source electrode to the buried layer of the second conductivity type through the via, thereby increasing the diode area and improving the surge current resistance of the semiconductor device. Therefore, the above-described semiconductor device fabrication method improves the surge current resistance of the semiconductor device, thereby improving its reliability, without increasing additional fabrication costs.

[0076] To more clearly illustrate the fabrication method of the semiconductor device provided in the embodiments of this disclosure, the following is combined with... Figures 3 to 10 The method for fabricating the semiconductor device provided in the embodiments of this application is described in detail.

[0077] In step S10, please refer to Figure 3 S10 and Figure 3 A substrate 10 is provided; an epitaxial layer 11 of a first conductivity type is formed on the surface of the substrate 10.

[0078] Optionally, the substrate 10 can be a single-layer structure or a multilayer structure. For example, the substrate 10 can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 can be a layered substrate comprising, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0079] Optionally, the material of the epitaxial layer 11 of the first conductivity type includes silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), or other III / V or II / VI semiconductors.

[0080] In some examples, the first conductivity type is N-type and the second conductivity type is P-type; or the first conductivity type is P-type and the second conductivity type is N-type.

[0081] For example, the epitaxial layer 11 of the first conductivity type is an N-type epitaxial layer, and the buried layer 111 of the second conductivity type is a P-type buried layer; or the epitaxial layer 11 of the first conductivity type is a P-type epitaxial layer, and the buried layer 111 of the second conductivity type is an N-type buried layer.

[0082] In step S20, please refer to Figure 3 S20 and Figure 4 A buried layer 111 of a second conductivity type is formed within an epitaxial layer 11 of a first conductivity type.

[0083] In some examples, forming a buried layer 111 of a second conductivity type within an epitaxial layer 11 of a first conductivity type includes performing ion implantation of the epitaxial layer 11 of the first conductivity type with a second conductivity type to form the buried layer 111 of the second conductivity type.

[0084] For example, when the epitaxial layer 11 of the first conductivity type is an N-type epitaxial layer, P-type ion implantation is performed on the epitaxial layer 11 of the first conductivity type to form a P-type buried layer, that is, a buried layer of the second conductivity type.

[0085] Accordingly, when the epitaxial layer 11 of the first conductivity type is a P-type epitaxial layer, N-type ion implantation is performed on the epitaxial layer 11 of the first conductivity type to form an N-type buried layer, that is, a buried layer of the second conductivity type.

[0086] In step S30, please refer to Figure 3 S30 in Figure 5 and Figure 6 A gate structure 20 is formed on the surface of the epitaxial layer 11 of the first conductivity type away from the substrate 10.

[0087] Optionally, please refer to Figure 5 A gate structure 20 is formed on the surface of the epitaxial layer 11 of the first conductivity type away from the substrate 10, comprising:

[0088] S31: A gate dielectric material layer is formed on the surface of the epitaxial layer of the first conductivity type away from the substrate.

[0089] S32: A gate conductive layer is formed on the surface of the epitaxial layer away from the first conductivity type of the gate dielectric material layer.

[0090] S33: Etch the gate conductive layer to form the gate, and etch the gate dielectric material layer to form the gate dielectric layer. The gate dielectric layer and the gate together constitute the gate structure.

[0091] In step S31, the gate dielectric material layer (not shown) may include, but is not limited to, a silicon oxide layer.

[0092] For example, a deposition process can be used to form a gate dielectric material layer.

[0093] In step S32, the gate conductive layer (not shown) may include, but is not limited to, a polysilicon layer.

[0094] For example, a deposition process can be used to form the gate conductive layer.

[0095] In step S33, please refer to Figure 6 The gate dielectric layer 21 includes a gate oxide layer. The gate oxide layer may include, but is not limited to, a silicon oxide layer.

[0096] In step S40, please refer to Figure 3 S40 and Figure 7 A covering dielectric layer 30 is formed, which covers the gate structure 20; the covering dielectric layer 30 has an opening G, which exposes the gate structure 20.

[0097] Optionally, forming a cover dielectric layer 30 includes: forming a cover dielectric material layer (not shown) that covers the gate structure 20; and etching the cover dielectric material layer to form a cover dielectric layer 30 having an opening G.

[0098] For example, the covering dielectric material layer may include, but is not limited to, a silicon oxide layer.

[0099] For example, a deposition process can be used to form a layer of covering medium material.

[0100] In some examples, the orthographic projection of the opening G on the surface of the epitaxial layer 11 of the first conductivity type away from the substrate 10 is located within the buried layer 111 of the second conductivity type.

[0101] In step S50, please refer to Figure 3 S50 and Figure 8 A gate lead-out electrode A is formed in the opening G, and the gate lead-out electrode A is in contact with the gate structure 20.

[0102] In some examples, the gate lead electrode A may also be located on the surface of the covering dielectric layer 30 away from the gate structure 20.

[0103] For example, the material of the gate lead-out electrode A may include, but is not limited to, aluminum (Al).

[0104] In step S60, please refer to Figure 3 S60 and Figure 8 An exit hole H is formed within the gate lead-out electrode A and within the gate structure 20, exposing a buried layer 111 of the second conductivity type.

[0105] In some examples, the orthographic projection of the lead-out hole H onto the surface of the epitaxial layer 11 of the first conductivity type away from the substrate 10 is located within the buried layer 111 of the second conductivity type.

[0106] For example, a lead-out hole H can be formed in the gate lead-out electrode A and the gate structure 20 by dry etching.

[0107] In step S70, please refer to Figure 3 S70 and Figure 9 An insulating layer 40 is formed on the sidewall of the lead-out hole H.

[0108] Accordingly, in some examples, the insulating layer 40 may also be located on a portion of the surface of the gate lead electrode A away from the buried layer 111 of the second conductivity type.

[0109] Optionally, the material of the insulating layer 40 may include, but is not limited to, silicon oxide or polyimide.

[0110] In step S80, please refer to Figure 3 S80 and Figure 10 A source electrode B is formed in the lead-out hole H, and the source electrode B is connected to the buried layer electrode 111 of the second conductivity type.

[0111] Optionally, before forming the source electrode B in the lead-out hole H, the method further includes: forming a metal contact layer 50 at the bottom of the lead-out hole H, the metal contact layer 50 being in contact with the buried layer 111 of the second conductivity type; and the source electrode B being in contact with the surface of the metal contact layer 50 away from the buried layer 111 of the second conductivity type.

[0112] In this embodiment, a metal contact layer 50 is formed between the source electrode B and the buried layer 111 of the second conductivity type, which is beneficial for the source electrode B to form a good ohmic contact with the buried layer 111 of the second conductivity type, thereby improving the electrical performance of the diode.

[0113] For example, the material of the metal contact layer 50 may include, but is not limited to, nickel (Ni) or titanium (Ti).

[0114] In the description of this specification, the technical features of the above-described embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0115] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A semiconductor device, characterized by, include: Substrate; An epitaxial layer of the first conductivity type is located on the surface of the substrate; The second conductivity type of buried layer is located within the first conductivity type of epitaxial layer; A gate structure is located on the surface of the epitaxial layer of the first conductivity type away from the substrate; A dielectric layer is provided to cover the gate structure; the dielectric layer has an opening that exposes the gate structure. The gate lead-out electrode is located at least within the opening and is in contact with the gate structure; An exit hole, located within the opening, extends along the thickness direction through the gate exit electrode and the gate structure to expose the buried layer of the second conductivity type; The orthographic projections of the opening and the lead-out hole onto the surface of the epitaxial layer of the first conductivity type away from the substrate are both located within the buried layer of the second conductivity type. The source electrode is located inside the lead-out hole and is electrically connected to the buried layer of the second conductivity type. An insulating layer is disposed on the sidewall of the lead-out hole and on the surface of the buried layer away from the second conductivity type of the gate lead-out electrode to electrically isolate the source lead-out electrode from the gate lead-out electrode and the gate structure.

2. The semiconductor device of claim 1, wherein, Also includes: A metal contact layer is located at the bottom of the lead-out hole and between the source lead-out electrode and the buried layer of the second conductivity type, and is in contact with the buried layer of the second conductivity type.

3. The semiconductor device of claim 1, wherein, The gate structure includes: A gate dielectric layer is located on the surface of the epitaxial layer of the first conductivity type away from the substrate; The gate is located on the surface of the gate dielectric layer away from the epitaxial layer of the first conductivity type.

4. The semiconductor device according to any one of Claims 1 to 3, wherein The first conductivity type is N-type and the second conductivity type is P-type; or the first conductivity type is P-type and the second conductivity type is N-type.

5. A method of fabricating a semiconductor device, characterized by, Includes the following steps: Provide substrate; An epitaxial layer of a first conductivity type is formed on the surface of the substrate; A buried layer of the second conductivity type is formed within the epitaxial layer of the first conductivity type; A gate structure is formed on the surface of the epitaxial layer of the first conductivity type away from the substrate; A cover dielectric layer is formed to cover the gate structure; the cover dielectric layer has an opening that exposes the gate structure; A gate lead-out electrode is formed within the opening, and the gate lead-out electrode is in contact with the gate structure; An exit hole is formed within the gate lead-out electrode and within the gate structure, the exit hole exposing a buried layer of the second conductivity type; the orthographic projections of the opening and the exit hole onto the surface of the epitaxial layer of the first conductivity type away from the substrate are both located within the buried layer of the second conductivity type; An insulating layer is formed on the sidewall of the lead-out hole and on the surface of the buried layer away from the second conductivity type of the gate lead-out electrode; A source electrode is formed in the lead-out hole, and the source electrode is electrically connected to the buried layer of the second conductivity type.

6. The semiconductor device fabrication method according to claim 5, characterized in that, The formation of a gate structure on the surface of the epitaxial layer of the first conductivity type away from the substrate includes: A gate dielectric material layer is formed on the surface of the epitaxial layer of the first conductivity type away from the substrate; A gate conductive layer is formed on the surface of the epitaxial layer away from the first conductivity type of the gate dielectric material layer; The gate conductive layer is etched to form the gate, and the gate dielectric material layer is etched to form the gate dielectric layer. The gate dielectric layer and the gate together constitute the gate structure.

7. The semiconductor device fabrication method according to claim 5, characterized in that, The formation of the covering medium layer includes: A covering dielectric material layer is formed, the covering dielectric material layer covering the gate structure; The overlay material layer is etched to form the overlay material layer having the opening.

8. The semiconductor device fabrication method according to claim 5, characterized in that, Before forming the source electrode in the lead-out hole, the method further includes: A metal contact layer is formed at the bottom of the lead-out hole, and the metal contact layer is in contact with the buried layer of the second conductivity type; the source lead-out electrode is in contact with the surface of the metal contact layer away from the buried layer of the second conductivity type.

9. The method for fabricating a semiconductor device according to any one of claims 5 to 8, characterized in that, The first conductivity type is N-type and the second conductivity type is P-type; or the first conductivity type is P-type and the second conductivity type is N-type.

Images