Integrated circuit device and method of manufacturing the same

Abstract

Embodiments of the present application provide integrated circuit devices and methods of manufacturing the same. An integrated circuit device includes a first vertical stack of nanostructures on a substrate, a second vertical stack of nanostructures on the substrate, a wall structure between and in direct contact with the first and second vertical stacks of nanostructures, a gate structure surrounding three sides of the nanostructures, and a source / drain region beside the first vertical stack of nanostructures.

Description

Technical Field

[0001] The embodiments of this application relate to the field of semiconductor technology, and more specifically, to integrated circuit devices and methods of manufacturing the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in generations of ICs, each with smaller and more complex circuitry than the previous one. During IC evolution, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This scaling down process typically provides benefits through increased production efficiency and reduced associated costs. However, this scaling down also increases the complexity of handling and manufacturing ICs. Summary of the Invention

[0003] According to one aspect of an embodiment of this application, an integrated circuit device is provided, comprising: a first vertical stack of nanostructures located above a substrate; a second vertical stack of nanostructures located above the substrate; a wall structure located between and in direct contact with the first and second vertical stacks; a gate structure surrounding three sides of the nanostructures; and a source / drain region located next to the first vertical stack of nanostructures.

[0004] According to another aspect of the embodiments of this application, an integrated circuit device is provided, comprising: a plurality of nanostructures located above a substrate, each of the nanostructures comprising: an upper side; a lower side opposite to the upper side; a first lateral side facing a first lateral direction; a second lateral side opposite to the first lateral side; a third lateral side facing a second lateral direction transverse to the first lateral direction; and a fourth lateral side opposite to the third lateral side; a gate structure extending in the first lateral direction, the gate structure contacting the upper side, lower side and first lateral side of each of the nanostructures, the gate structure being isolated from the third lateral side and fourth lateral side of each of the nanostructures; and a source / drain region adjacent to the plurality of nanostructures, the source / drain region having an asymmetrical shape in the first lateral direction.

[0005] According to another aspect of the embodiments of this application, a method for manufacturing an integrated circuit device is provided, comprising: forming a first stacked nanostructure, a second stacked nanostructure, and a third stacked nanostructure, the first stacked nanostructure, the second stacked nanostructure, and the third stacked nanostructure being laterally separated from each other; forming a wall structure between the first stacked nanostructure and the second stacked nanostructure; forming an isolation region between the second stacked nanostructure and the third stacked nanostructure; forming a first source / drain region in contact with the first stacked nanostructure, forming a second source / drain region in contact with the second stacked nanostructure, and forming a third source / drain region in contact with the third stacked nanostructure; trimming portions of the first source / drain region and the second source / drain region, the wall structures being partially facing each other and vertically overlapping; and forming a gate structure above the first stacked nanostructure, the second stacked nanostructure, and the third stacked nanostructure. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figures 1A-1S These are schematic top views and cross-sectional side views of portions of an IC device manufactured according to embodiments of the present disclosure.

[0008] Figures 2A-2Q This is an intermediate perspective view of an IC device at various stages of manufacturing according to various aspects of this disclosure.

[0009] Figures 3A-3I This is an intermediate perspective view of an IC device at various stages of manufacturing in accordance with various aspects of this disclosure.

[0010] Figure 4 This is a schematic cross-sectional side view of a gate structure according to various embodiments.

[0011] Figure 5 This is a flowchart of a method according to various embodiments. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, this document may use spacing relation terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing relation terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing relation descriptors used herein may be interpreted accordingly.

[0014] Terms indicating relative degree, such as “about” or “basically”, should be interpreted in the manner that a person skilled in the art would understand in accordance with current technical specifications.

[0015] This disclosure generally relates to semiconductor devices, and more specifically to field-effect transistors (FETs), such as planar FETs, three-dimensional fin-wire FETs (FinFETs), or nanostructured devices. Examples of nanostructured devices include gate-all-around (GAA) devices, nanosheet FETs (NSFETs), nanowire FETs (NWFETs), and the like. In advanced technology nodes, the active region spacing between nanostructured devices is typically uniform, the source / drain epitaxial structure is symmetrical, and a metal gate surrounds the four sides of the nanostructure (e.g., a nanosheet). Due to the larger metal gate endcap and the increased source / drain epitaxial dimensions, the gate-drain capacitance (“Cgd”) is increased.

[0016] Embodiments of this disclosure reduce gate-drain capacitance by decreasing the size of the metal gate cap and source / drain epitaxial layers. Active region spacing is also reduced. In some embodiments, wall structures are formed at cell boundaries. The wall structures can be multilayer structures. Source / drain epitaxial layers adjacent to the wall structures are cut or trimmed to prevent merging of adjacent source / drain epitaxial layers. By reducing the lateral dimensions of the metal gate cap and source / drain epitaxial layers, gate-drain capacitance can be reduced. Therefore, device performance is improved, and the active region spacing between nanostructured devices can be reduced, saving chip area.

[0017] Nanostructured transistor structures can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructured transistor structure.

[0018] Figures 1A-1S The illustration shows a schematic perspective view, as well as a cross-sectional top view and a side view of a portion of an IC device 10 manufactured according to an embodiment of the present disclosure, wherein the IC device 10 includes nanostructure devices 20A-20E, which may be full-ring gate field-effect transistors (GAAFETs). Figure 1A This is a schematic perspective view of a portion of an IC device 10 according to various embodiments. Figure 1B This is a schematic top view of a portion of the IC device 10, which includes nanostructure devices 20A-20E. Figure 1C It is along Figure 1B The diagram shows a schematic cross-sectional side view of a portion of the IC device 10, including nanostructure devices 20A-20E, along line CC. Figure 1D It has different Figure 1C The diagram shows the configuration of region 175. Figure 1E and Figure 1F According to various embodiments Figure 1C A detailed view of region 150 shown. Figure 1G It is along Figure 1B A schematic cross-sectional side view of a portion of the IC device 10 of line GG shown. Figure 1H It is along Figure 1B A schematic cross-sectional side view of a portion of the IC device 10 with line HH shown. For simplicity, [the diagram is shown in the original text]. Figures 1A-1H In the view, some components may be intentionally removed.

[0019] In some embodiments, nanostructure devices 20A-20E may include at least an N-type FET (NFET) or a P-type FET (PFET). Integrated circuit devices such as IC device 10 typically include transistors, which have different threshold voltages based on their function within the IC device. For example, input / output (IO) transistors typically have the highest threshold voltage, core logic transistors typically have the lowest threshold voltage, and a third threshold voltage between the threshold voltage of the IO transistors and the threshold voltage of the core logic transistors may also be used for certain other functional transistors, such as static random access memory (SRAM) transistors. Some circuit blocks within IC device 10 may include two or more NFETs and / or PFETs with two or more different threshold voltages.

[0020] Nanostructured devices 20A-20E are formed above and / or within substrate 110 and typically include gate structures 200A-200C. The gate structures 200A-200C, located above semiconductor fins 321-325, span and / or surround semiconductor channels (optionally referred to as "nanostructures"). Semiconductor fins 321-325 protrude from and are separated from isolation structures 361, 362. The channels are labeled "22AX" to "22CX," where "X" is an integer from 1 to 5, corresponding to five transistors 20A-20E respectively. Each gate structure 200A-200C controls the current flowing through the channels 22A1-22C5.

[0021] In many IC devices, it is advantageous to electrically connect the gate structures of two or more adjacent nanostructure devices. In a typical process, a material layer for the gate structure is formed over a large number of adjacent semiconductor fins, and an isolation structure formed before or after the material layer is used to "cut" the material layer to isolate certain portions of the material layer from other portions. Each portion of the material layer can be one or more gate structures corresponding to one or more nanostructure devices. For illustrative purposes, in Figures 1A-1H In the configuration shown, two gate isolation structures 99 isolate three gate structures 200A-200C, such that gate structure 200B and gate structures 200A, 200C are electrically isolated from each other (e.g., see...). Figure 1C The gate isolation structure 99 may alternatively be referred to as "dielectric plug 99". The gate structure 200B is on and surrounds the nanostructure 22 of the nanostructure devices 20B-20D. It should be understood that "surrounds" includes the meaning of surrounding three or more sides of the nanostructure 22. For example, as... Figure 1CAs shown, gate structure 200B extends between nanostructure 22B2 and nanostructures 22A2, 22C2, thereby adjacent to the upper, lower, and right sides of nanostructure 22B2, while substantially not or completely adjacent to the left side of nanostructure 22B2 (e.g., the side of nanostructure 22B2 facing nanostructure 22B1). As another example, Figure 1E and Figure 1F The nanostructure 22B3 is shown in a magnified view, wherein the gate structure 200B is adjacent to the upper, lower, and left sides of the nanostructure 22B3, and partially adjacent to the right side of the nanostructure 22B3. Figure 1E ) or not adjacent to the right side of adjacent nanostructure 22B3 ( Figure 1F ).like Figure 1A As shown, the two sidewalls of the nanostructure 22 can face either the positive X-axis direction or the negative X-axis direction, respectively, and are not adjacent to the gate structure 200. Therefore, as Figure 1A As shown, the gate structure 200A-200C can be in the cross-section (e.g., in...). Figure 1A In the YZ plane shown, each nanostructure 22 is "wrapped and surrounded".

[0022] refer to Figure 1H The channel 22 (e.g., channels 22A2, 22B2, 22C2) is laterally adjacent to the source / drain region 82 along the X-axis and is covered and surrounded by the gate structure 200B. The gate structure 200B controls the flow of current through channels 22A2-22C2 to and from the source / drain region 82 based on the voltage applied to the gate structure 200B and the source / drain region 82. Depending on the context, the source / drain region can refer to a single or shared source or drain.

[0023] Figure 1G The diagram illustrates the source / drain region 82 in the YZ plane. Figure 1GIn the diagram, source / drain regions 82A, 82B, 82C, 82D, and 82E, collectively referred to as source / drain regions 82, are located on fins 321, 322, 323, 324, and 325, respectively. As shown, source / drain regions 82 have an asymmetrical cross-sectional profile in the YZ plane. For example, source / drain region 82C has a first lateral extension 82EX1 that extends laterally in a first direction (e.g., the negative Y-axis direction) beyond the first width W1 of fin 323 and nanostructure 22, and a second lateral extension 82EX2 that extends laterally in a second direction (e.g., the positive Y-axis direction) beyond the second width W2 of fin 323 and nanostructure 22. The first and second widths W1 and W2 are different from each other. In some embodiments, the first width W1 is in the range of about 10 nm to about 20 nm, and the second width W2 is smaller than the first width W1, for example, in the range of about 0 nm to about 10 nm. The first width W1 can be greater than the second width W2 by approximately 0 nm to approximately 15 nm, for example, approximately 1 nm to approximately 15 nm. If the first width W1 is greater than the second width W2 by more than approximately 15 nm, the source / drain region 82 may not be large enough, resulting in excessively high resistance. If the first width W1 is too small compared to the second width W2, adjacent source / drain regions 82 (e.g., source / drain regions 82B and 82C) may merge instead of remaining separate, resulting in electrical bridging between device cells. Typically, adjacent source / drain regions 82 can remain separate by trimming one or more sides of the source / drain region 82 (or so-called "epitaxy cut"), reducing the size of the source / drain region 82, or using higher sidewalls during epitaxial growth to grow the source / drain region 82 to a smaller size.

[0024] In some embodiments, fins 321-325 comprise silicon. Fins 321-325 may not be present. In some embodiments, the nanostructure device 20B is an NFET, and its source / drain region 82 comprises silicon-phosphorus (SiP). In some embodiments, the nanostructure device 20B is a PFET, and its source / drain region 82 comprises silicon-germanium (SiGe).

[0025] Each of channels 22A2-22C2 comprises a semiconductor material, such as silicon or a silicon compound, such as silicon germanium. Channels 22A2-22C2 are nanostructures (e.g., having dimensions in the range of a few nanometers) and may also each have an elongated shape and extend in the X direction. In some embodiments, each of channels 22A2-22C2 has a nanowire (NW) shape, a nanosheet (NS) shape, a nanotube (NT) shape, or other suitable nanoscale shape. The cross-sectional profile of channels 22A2-22C2 in the YZ plane may be rectangular, annular, square, circular, elliptical, hexagonal, or a combination thereof.

[0026] In some embodiments, the lengths (e.g., measured in the X direction) of channels 22A2-22C2 may differ from one another, for example, due to a gradual taper during the fin etching process. In some embodiments, the length of channel 22A2 may be less than the length of channel 22B2, and the length of channel 22B2 may be less than the length of channel 22C2. Channels 22A2-22C2 may not each have a uniform thickness, for example, due to channel trimming processes used to increase the spacing between channels 22A2-22C2 (e.g., measured in the Z direction) to increase the gate structure fabrication process window. For example, the middle portion of each of channels 22A2-22C2 may be thinner than the ends of each of channels 22A2-22C2. This shape may be collectively referred to as a "dog bone" shape, such as... Figure 1H As shown.

[0027] In some embodiments, the spacing between channels 22A2-22C2 (e.g., between channel 22B2 and channel 22A2 or channel 22C2) is in the range of about 8 nanometers (nm) to about 12 nm. In some embodiments, the thickness of each of channels 22A2-22C2 (e.g., measured in the Z-axis direction) is in the range of about 5 nm to about 8 nm. In some embodiments, the width of each of channels 22A2-22C2 (e.g., measured in the Y-axis direction orthogonal to the XZ plane, not in the Z-axis direction) is in the range of about 5 nm to about 8 nm. Figure 1H (As shown in the figure) is at least about 8nm.

[0028] Gate structures 200B are respectively disposed above and between channels 22A2-22C2. In some embodiments, gate structures 200B are disposed above and between channels 22A2-22C2, and channels 22A2-22C2 are silicon channels for N-type devices or silicon-germanium channels for P-type devices. In some embodiments, gate structure 200B includes an interface layer (IL) 210, one or more gate dielectric layers 600, and one or more power function tuning layers 900 (e.g., ...). Figure 4 (as shown) and conductive filler layer 290.

[0029] Interface layer 210, which may be an oxide of the material of channels 22A2-22C2, is formed on the exposed areas of channels 22A2-22C2 and the top surface of fin 322. Interface layer 210 promotes the adhesion of gate dielectric layer 600 to channels 22A2-22C2. In some embodiments, interface layer 210 has approximately To date The thickness. In some embodiments, the interface layer 210 has approximately The thickness of the interface layer 210 is important. An interface layer 210 that is too thin may exhibit voids or insufficient adhesion. An interface layer 210 that is too thick consumes the gate fill window, which is related to threshold voltage tuning and resistance as described above. In some embodiments, the interface layer 210 is doped with dipoles, such as lanthanum, for threshold voltage tuning.

[0030] In some embodiments, the gate dielectric layer 600 includes at least one high-k gate dielectric material, which may refer to a dielectric material having a high dielectric constant greater than that of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or combinations thereof. In some embodiments, the gate dielectric layer 600 has approximately To date The thickness.

[0031] In some embodiments, the gate dielectric layer 600 may include a certain concentration of dopants, such as metal ions driven into the high-k gate dielectric from La2O3, MgO, Y2O3, TiO2, Al2O3, Nb2O5, etc., or boron ions driven into it from B2O3, to achieve threshold voltage tuning. As an example, for N-type transistor devices, a higher concentration of lanthanum ions lowers the threshold voltage compared to a layer with a lower concentration of lanthanum ions or no lanthanum ions, while the opposite is true for P-type devices. In some embodiments, the gate dielectric layer 600 of certain transistor devices (e.g., I / O transistors) does not contain dopants present in certain other transistor devices (e.g., N-type core logic transistors or P-type I / O transistors). For example, in N-type I / O transistors, a relatively high threshold voltage is required, making it preferable that the high-k dielectric layer of the I / O transistor is free of lanthanum ions, otherwise the threshold voltage would be lowered.

[0032] In some embodiments, the gate structure 200B further includes one or more function metal layers, collectively referred to as function metal layer 900. When configured as an NFET, the function metal layer 900 of the nanostructure device 20B may include at least an N-type function metal layer, an in-situ capping layer, and an oxygen barrier layer. In some embodiments, the N-type function metal layer is or includes an N-type metallic material, such as TiAlC, TiAl, TaAlC, TaAl, etc. The in-situ capping layer is formed on the N-type function metal layer and may include TiN, TiSiN, TaN, or other suitable materials. The oxygen barrier layer is formed on the in-situ capping layer to prevent oxygen diffusion into the N-type function metal layer, which would cause an undesirable shift in the threshold voltage. The oxygen barrier layer may be formed of a dielectric material that can prevent oxygen from penetrating into the N-type function metal layer and can protect the N-type function metal layer from further oxidation. The oxygen barrier layer may include oxides of silicon, germanium, SiGe, or other suitable materials. In some embodiments, the function metal layer 900 includes more or fewer layers than those described.

[0033] The work function metal layer 900 may further include one or more barrier layers, including metal nitrides such as TiN, WN, MoN, and TaN. Each of the one or more barrier layers may have a power function ranging from approximately To date The thickness of the barrier layer. Including one or more barrier layers provides additional threshold voltage tuning flexibility. Typically, each additional barrier layer increases the threshold voltage. Therefore, for NFETs, higher threshold voltage devices (e.g., IO transistor devices) may have at least one or more additional barrier layers, while lower threshold voltage devices (e.g., core logic transistor devices) may have few or no additional barrier layers. For PFETs, higher threshold voltage devices (e.g., IO transistor devices) may have few or no additional barrier layers, while lower threshold voltage devices (e.g., core logic transistor devices) may have at least one or more additional barrier layers. In the preceding discussion, the threshold voltage was described in terms of amplitude. As an example, NFET IO transistors and PFET IO transistors can have similar threshold voltages in amplitude but with opposite polarities, such as +1 volt for NFET IO transistors and -1 volt for PFET IO transistors. Thus, because each additional barrier layer increases the threshold voltage in a definite manner (e.g., +0.1 volts / layer), this increase leads to an increase in the threshold voltage (amplitude) of the NFET transistor and a decrease in the threshold voltage (amplitude) of the PFET transistor.

[0034] The gate structure 200B also includes a conductive fill layer 290. The conductive fill layer 290 may include a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or a combination thereof. Between channels 22A2-22C2, the conductive fill layer 290 is circumferentially surrounded by one or more function metal layers 900 (in the cross-sectional view), and then circumferentially surrounded by a gate dielectric layer 600. The gate structure 200B may also include an adhesive layer formed between the one or more function layers 900 and the conductive fill layer 290 to increase adhesion. For simplicity, in Figures 1A-1H The adhesive layer is not specifically illustrated. It should be understood that "filling" includes both complete and partial filling. For example, Figure 1H The conductive filling layer 290 shown partially fills the space between the gate spacers 41 above the uppermost nanostructure 22A2.

[0035] The nanostructure devices 20A-20E also include a gate spacer 41 and an internal spacer 74 disposed on the sidewalls of the gate dielectric layer 600 and IL 210. The internal spacer 74 is disposed between channels 22A2-22C2. The gate spacer 41 and the internal spacer 74 may comprise dielectric materials, such as low-k materials, such as SiOCN, SiON, SiN, or SiOC.

[0036] Nanostructured devices 20A-20E may include source / drain contacts 120 formed above source / drain regions 82. Figure 1H A single source / drain contact 120 is shown. The source / drain contact 120 may include a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or combinations thereof. The source / drain contact 120 may be surrounded by a barrier layer (not shown) (such as SiN or TiN), which helps prevent or reduce material diffusion from and into the source / drain contact 120. A silicide layer 118 may also be formed between the source / drain region 82 and the source / drain contact 120 to reduce the source / drain contact resistance. The silicide layer 118 may comprise a metallic silicide material, such as cobalt silicide in some embodiments, or TiSi in others.

[0037] The nanostructure devices 20A-20E also include an interlayer dielectric (ILD) 130. The ILD 130 provides electrical isolation between various components of the nanostructure devices 20A-20E, such as the gate structure 200B and the source / drain contact 120. An etch stop layer 131 may be formed prior to the formation of the ILD 130, and the etch stop layer 131 may be laterally positioned between the ILD 130 and the gate spacer 41 and vertically positioned between the ILD 130 and the source / drain region 82.

[0038] Figure 1Cand Figure 1G They are respectively along Figure 1B The cross-sectional view of lines CC and GG is shown. In gate structures 200A-200C ( Figure 1C ) and source / drain region 82 ( Figure 1G Cut at ) Figure 1C and Figure 1G The cross-sectional views shown are orthogonal to semiconductor fins 321-325 and parallel to gate structures 200A-200E, respectively.

[0039] The wall structure 300 can be located at the cell boundary to prevent jog degradation of the active region within the cell, wall dielectric deposition, etch-back, or both. The wall structure 300 includes a pad dielectric layer 302, an etch stop layer 304, and a core dielectric layer 306. The thickness of the pad dielectric layer 302 can range from about 2 nm to about 5 nm. A thickness greater than about 5 nm may result in an insufficiently low gate-drain capacitance Cgd. A thickness less than about 2 nm may result in insufficient lateral extension of the gate structure 200 (e.g., see...). Figure 1E The size D1) leads to reduced gate control. The core dielectric layer 306 can have a thickness (e.g., width) greater than about 15 nm. A thickness of core dielectric layer 306 less than about 15 nm may result in insufficient active region spacing, making the source / drain regions 82 too short, making it difficult to drive the channel 22 through the gate structure 200. Figure 1C As shown, the pad dielectric layer 302 and the core dielectric layer 306 can be made of the same or substantially the same material, such as SiN, SiCN, SiOC, SiOCN, etc. Due to the similar etch selectivity of the pad dielectric layer 302 and the core dielectric layer 306, making the pad dielectric layer 302 and the core dielectric layer 306 the same or substantially the same material can simplify the etching operation.

[0040] The etch stop layer 304 facilitates the formation of the gate structure 200, which has a pi (π) shape. This allows the gate structure 200 to be trimmed up to the etch stop layer 304 without over-etching into the core dielectric layer 306. The etch stop layer 304 is located between the pad dielectric layer 302 and the core dielectric layer 306. In some embodiments, the thickness of the etch stop layer 304 is in the range of about 0.1 nm to about 2 nm, such as about 1 nm. Typically, the etch stop layer 304 should be thinner than the pad dielectric layer and the core dielectric layers 302 and 306, and should have high etch selectivity compared to the pad dielectric layer 302, which is beneficial in the formation of… Figure 1E , Figure 1F The gate trimming operation of the structure shown is beneficial. If the etch stop layer 304 is too thick (e.g., greater than about 2 nm), the etch stop layer 304 may be consumed or partially consumed during the recessed isolation regions 361, 362, which may lead to defects.

[0041] Gate isolation structure 99 is located between gate structures 200A, 200B, and 200C, ensuring that gate structures 200A, 200B, and 200C are electrically isolated from each other. For example... Figure 1C As shown, gate isolation structure 99 is located between gate structures 200A and 200B, and gate isolation structure 99 is located between gate structures 200B and 200C. Gate isolation structure 99 may be located on isolation regions 361 and 362 or on wall structure 300. For example, gate isolation structure 99 between gate structures 200A and 200B is located on wall structure 300, and gate isolation structure 99 between gate structures 200B and 200C is located on isolation region 362. In some embodiments, gate isolation structure 99 comprises SiN or other suitable dielectric material.

[0042] exist Figure 1D In this structure, the gate isolation structure 99 extends into the wall structure 300, such as extending to a level approximately coplanar with the upper surfaces of the fins 321 and 322. The gate isolation structure 99 may extend into the wall structure 300 at a distance H1, such as... Figure 1D As shown. The distance H1 extends from the substantially upper surface of the uppermost channels 22A1, 22A2 to the substantially upper surface 304U of the etch stop layer 304. In some embodiments, the distance H1 is equal to or substantially equal to the distance between the upper surfaces of the uppermost channels 22A1-22A5 and the upper surfaces of the isolation regions 361, 362, such that the gate isolation structures 99 located on the wall structure 300 and the isolation region 362 have substantially the same height in the Z-axis direction. Typically, a single device (such as device 10) includes the gate isolation structure 99, or the gate isolation structure 99 as... Figure 1C As shown, it falls on the upper surface of the wall structure 300, or as... Figure 1D The diagram extends into wall structure 300 and will not include any combination thereof. In some embodiments, masking techniques may be used to form different regions of the same device. Figure 1C Gate isolation structure 99 and Figure 1D The gate isolation structure allows for the formation (e.g., deposition) of a gate isolation structure 99 on the upper surface of the wall structure 300 and a gate isolation structure 99 extending into the wall structure 300 during different operations.

[0043] Figure 1E and Figure 1F The illustration shows the spacer portion 302S of the pad dielectric layer 302. Figure 1EThe diagram also illustrates the sides of channel 22B3, including an upper side 22U, a lower side 22L, a first side 22LA1, and a second side 22LA2. The lower side 22L is opposite to the upper side 22U. The first lateral side 22LA1 contacts the gate structure 200B and faces away from the wall structure 300, for example, in a first lateral direction (e.g., the negative Y direction). The second lateral side 22LA2 is opposite to the first lateral side 22LA2, contacts the wall structure 300, and faces the wall structure 300, for example, in a direction opposite to the first lateral direction (e.g., the positive Y direction). The third and fourth sides of channel 22B3 are not shown in the diagram. Figure 1E As shown in the figure, because Figure 1E This is a cross-sectional view in the YZ plane. Each of the channels 22 includes an upper side, a lower side, and first to fourth transverse sides. Figure 1H In the diagram, the third lateral side 22LA3 and the fourth lateral side 22LA4 of the channel 22A2 are marked. The third lateral side 22LA3 faces a second lateral direction (e.g., the negative X direction) that is transverse to the first lateral direction. The fourth lateral side 22LA4 faces a direction opposite to the second lateral direction, such as the positive X direction.

[0044] Spacer portion 302S is located in nanostructure 22 (e.g., Figure 1E and Figure 1F The nanostructure 22B3 shown is located between the etch stop layer 304 and the core dielectric layer 306. Figure 1E and Figure 1F As shown, the spacer portion 302S contacts the sidewalls of the channel 22B3 and the etch stop layer 304. The upper and lower surfaces of the spacer portion 302S are in contact with the gate structure 200 (such as the gate dielectric layer 600). The distance or vertical extension D2 between the upper surface of the channel 22B3 and the upper surface of the spacer portion 302S is in the range of 0 nm to about 2 nm. Figure 1F The spacer portion 302S is shown when the distance D2 is zero, such that the upper surface of the spacer portion 302S is flush with the upper surface of the nanostructure 22B3. The distance or lateral extension D1 between the etch stop layer 304 and the nanostructure 22B3 is in the range of about 2 nm to about 5 nm, such as about 3 nm to about 5 nm. Distances D1 and D2 are beneficial for short-channel effect control and reducing AC capacitance loss. For example, when the lateral extension D1 is greater than about 5 nm, the gate-drain capacitance Cgd may not be small enough, and the distance from the gate structure 200 to the source / drain region 82 may be too short. When the lateral extension D1 is less than about 2 nm, controlling the gate structure 200 may be difficult.

[0045] like Figure 1E and Figure 1F As shown, due to the trimming of the pad dielectric layer 302, the conductive fill layer 290 may include an extension 290E adjacent to the wall structure 300 and the channel 22. For example, in Figure 1E In the middle, the extension portion 290E is laterally located between the channel 22B3 and the etch stop layer 304 and the core dielectric layer 306. Figure 1F In this configuration, the extension 290E is laterally located between the gate dielectric layer 600 and the etch stop layer 304 and the core dielectric layer 306. In some embodiments, the extension 290E is absent when the gate dielectric layer 600 is sufficiently thick, for example, when the gate dielectric layer 600 is thick enough to be incorporated in the space between the channel 22B3 and the etch stop layer 304 during the deposition of the gate dielectric layer 600. Figure 1E As shown, the gate structure 200 contacts the upper and lower sides of the channel 22B3 and the first lateral sides 22U, 22L, 22LA1, and partially contacts the second lateral side 22LA2 of the channel 22B3, while being isolated from the third and fourth lateral sides 22LA3, 22LA4 of the channel 22B3. Figure 1F As shown, the gate structure 200 contacts the upper and lower sides of the channel 22B3 and the first lateral sides 22U, 22L, 22LA1, while being isolated from the second, third, and fourth lateral sides 22LA2, 22LA3, 22LA4 of the channel 22B3. (Reference) Figure 4 The gate structure 200 is described in more detail.

[0046] The second conductive layer 297 can be on the gate structure 200, such as Figure 1A As shown. The second conductive layer 297 may be or include a metal, such as tungsten. The gate isolation structure 99 may extend through the second conductive layer 297.

[0047] In some embodiments, a capping layer is located above the gate structures 200A-200C. The capping layer may be a self-aligned cap (SAC) layer. The capping layer provides protection for the underlying gate structures 200A-200C and may also serve as a CMP stop layer during the planarization of the source / drain contacts 120 after their formation. The capping layer may be a dielectric layer comprising a dielectric material such as SiO2, SiN, SiCN, SiC, SiOC, SiOCN, HfO2, ZrO2, ZrAlOx, HfAlOx, HfSiOx, Al2O3, BN, or other suitable dielectric materials. An optional hard dielectric layer may be present between the capping layer and the conductive layer 204. The hard dielectric layer prevents current leakage after one or more etch operations, which may be performed to form the gate contacts, source / drain contacts 120, isolation structures (e.g., source / drain contact isolation structure 150), etc. In some embodiments, the hard dielectric layer is, for example, a dielectric material harder than the capping layer, such as aluminum oxide, or other suitable dielectric material. The hard dielectric layer may also be located between the capping layer and the spacer layer 41. The gate isolation structure 99 may extend through the capping layer.

[0048] Figure 1I This is a cross-sectional side view of device 10 according to various embodiments. In some embodiments, wall structure 300A includes a pad dielectric layer 302 and a core dielectric layer 306, while the etch stop layer 304 is absent, such as... Figure 1I As shown. An etch stop layer 304 (when present), which may be referred to as an oxide pad 304, an oxide pad dielectric layer 302, and a core dielectric layer 306. Different materials can be selected for the pad and core dielectric layers 302, 306 to avoid forming the oxide pad 304. In this configuration, the pad dielectric layer 302 can be a different material from the core dielectric layer 306. For example, the core dielectric layer 306 has higher etch selectivity than the pad dielectric layer 302. In some embodiments, the pad dielectric layer 302 is SiN or SiCN, and the core dielectric layer 306 is SiOC or SiOCN. In some embodiments, the core dielectric layer 306 is SiN or SiCN, and the pad dielectric layer 302 is SiOC or SiOCN. Figure 1I Further details of the device 10 shown are in reference. Figure 1C The devices 10 described are similar and will not be repeated for the sake of brevity.

[0049] exist Figure 1I In this context, the gate isolation structure 99 rests on the upper surface of the wall structure 300A, for example, on the upper surface of the core dielectric layer 306. Figure 1J In this structure, the gate isolation structure 99 extends into the wall structure 300A. Therefore, the sidewall of the gate isolation structure 99 contacts the inner sidewall of the core dielectric layer 306, which has a different material from the pad dielectric layer 302.

[0050] exist Figure 1K and Figure 1L In this configuration, the spacer portion 302S contacts the core dielectric layer 306. In some embodiments, the spacer portion 302S extends laterally from the sidewall of the channel 22B3 to the sidewall of the core dielectric layer 306, as shown. (Reference) Figure 1E and Figure 1F Further details of the spacer section 302S are described.

[0051] Figure 1M Similar to in many ways Figure 1G ,Apart from Figure 1M The device 10 shown includes a wall structure 300A instead of Figure 1G The wall structure 300 shown is illustrated. Figure 1M For details regarding device 10 shown, please refer to [link / reference]. Figure 1G The description has already been provided, so I will not repeat it here.

[0052] Figure 1N This is a perspective view of the device 10 according to various embodiments. Figure 1NDevice 10 can have a structure that is advantageous for use in SRAM applications. Figure 1N The device 10 is similar in many ways to Figures 1A-1M Device 10, except that the stack of fins 323 and the overlying nanostructures 22A3, 22B3, and 22C3 is replaced (e.g., partially replaced) by an active region isolation structure 530 and a gate structure 200B, as shown in the perspective view. The active region isolation structure 530 may include a dielectric material, such as a low-k dielectric material, which may be SiN or an oxide, such as silicon oxide. The dielectric material of the isolation structure 530 may differ from the dielectric material of one or more of the pad dielectric layer 302 and the core dielectric layer 306 of the wall structure 300. The active region isolation structure 530 may be used as an active region cut structure that isolates transistors (e.g., fins 32 and nanostructures 22) on either side of the active region isolation structure 530.

[0053] Figure 10 yes Figure 1N A cross-sectional side view of device 10. In some embodiments, the upper surface of the active region isolation structure 530 is coplanar or substantially coplanar with the upper surfaces of the isolation region 362 of the active region isolation structure 530 and the pad dielectric layer 302 of the wall structure 300. The lower surface of the active region isolation structure 530 may be coplanar or substantially coplanar with the lower surfaces of its adjacent isolation region 362 and pad dielectric layer 302, or may be slightly higher or slightly lower than the lower surfaces of the isolation region 362 and pad dielectric layer 302. In some embodiments, the lower surface of the active region isolation structure 530 may be substantially horizontal as shown, or may have a convex shape in the YZ plane. The lateral sidewalls of the active region isolation structure 530 may contact the isolation region 362 and the pad dielectric layer 302. The upper surface of the active region isolation structure 530 may contact the gate structure 200B (such as the gate dielectric layer 600 of the gate structure 200B). When substrate 110 is present, the lower surface of active region isolation structure 530 can contact substrate 110.

[0054] Figure 1P A gate isolation structure 99 is shown, which can extend to Figure 1N The wall structure 300 in device 10. Figure 1Q and Figure 1R It shows Figure 1N An embodiment of the spacer portion 302S in device 10. Figure 1P-Figure 1R and Figures 1D-1F Similarly, please refer to its description. Figures 1D-1F This will not be elaborated upon here. It should be understood that this includes the active region isolation structure 530. Figure 1N The device 10 may include wall structure 300 or wall structure 300A.

[0055] Figure 1S This is a detailed cross-sectional side view of the wall structure 300 adjacent to the channel 22B3 and the gate structure 200B according to various embodiments. In some embodiments, such as Figure 1S As shown, the pad dielectric layer 302 is not trimmed before forming the gate structure 200B, which reduces the number of operations required to manufacture the device 10. Thus, the conductive fill layer 290 can extend without reaching the sidewalls of the channel 22B3 adjacent to the wall structure 300, and the gate dielectric layer 600 can have sidewalls that are substantially coplanar with the sidewalls of the channel 22B3 and the pad dielectric layer 302.

[0056] Figures 2A-2Q and Figures 3A-3I Methods for forming IC device 10 according to various embodiments are shown. Figures 2A-2Q It shows Figure 1A The IC device 10 shown is a mid-range view at various points of operation of the method. Figures 3A-3I It shows Figure 1N The IC device 10 shown is a mid-range view at various points of operation of the method. In some embodiments, the IC device 10 includes logic devices and SRAM devices. Figures 2A-2Q The diagram illustrates the formation of a logic device according to various embodiments. Figures 3A-3I The formation of an SRAM device according to various embodiments is illustrated. Figures 2A-2Q The view in the middle shows many operations and is related to... Figures 3A-3I The operations shown in the view are performed simultaneously. For example, Figures 2A-2H They can correspond to respectively Figures 3A-3H ,in Figures 2A-2H The operation performed in the region including the logic device is shown, while Figures 3A-3H The operation performed in the region that includes the SRAM device is shown.

[0057] Figure 5 A flowchart of a method 1000 for forming an IC device or a portion thereof from a workpiece, according to one or more aspects of this disclosure, is shown. Method 1000 is merely an example and is not intended to limit this disclosure to what is expressly described in method 1000. Additional actions may be provided before, during, and after method 1000, and other embodiments of the method may replace, eliminate, or shift some of the described actions. For simplicity, not all actions are described in detail herein. The following is in conjunction with… Figures 2A-3I The method 1000 is described by partial perspective views and / or cross-sectional views of the workpiece at different stages of manufacturing, according to an embodiment of method 1000. For the avoidance of doubt, in all figures, the X direction is perpendicular to the Y direction, and the Z direction is perpendicular to both the X and Y directions. It is worth noting that because the workpiece can be manufactured as a semiconductor device, the workpiece may be referred to as a semiconductor device depending on the context.

[0058] exist Figure 2A and Figure 3A A substrate 110 is provided. The substrate 110 can be a semiconductor substrate, such as a bulk semiconductor, which can be doped (e.g., with p-type or n-type dopants) or undoped. The semiconductor material of the substrate 110 can include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as single-layer, multi-layer, or gradient substrates, can be used.

[0059] Further in Figure 2A and Figure 3A In this process, a multilayer stack 25 or "grid" is formed over alternating layers of a first semiconductor layer 21A-21C (collectively referred to as the first semiconductor layer 21) and a second semiconductor layer 23 on a substrate 110. In some embodiments, the first semiconductor layer 21 may be formed of a first semiconductor material suitable for n-type nano-FETs, such as silicon, silicon carbide, etc., and the second semiconductor layer 23 may be formed of a second semiconductor material suitable for p-type nano-FETs, such as silicon germanium, etc. Each layer of the multilayer stack 25 can be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. Figure 2A and Figure 3A As shown, an oxide layer 28 and a hard mask layer 29 are formed over the top first semiconductor layer 21A. In some embodiments, the oxide layer 28 is a pad oxide layer, and the hard mask layer 29 may include silicon. In some embodiments, a second semiconductor layer 27 may exist between the top first semiconductor layer 21A and the oxide layer 28, such as... Figure 2B and Figure 3B As shown.

[0060] Three layers of each of the first semiconductor layer 21 and the second semiconductor layer 23 are shown. In some embodiments, the multilayer stack 25 may include one or two or four or more of each of the first semiconductor layer 21 and the second semiconductor layer 23. Although the multilayer stack 25 is shown to include the second semiconductor layer 23 as the bottom layer of the multilayer stack 25, in some embodiments, the bottom layer of the multilayer stack 25 may be the first semiconductor layer 21.

[0061] Due to the high etch selectivity between the first and second semiconductor materials, the second semiconductor layer 23 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 21 of the first semiconductor material, thereby allowing the first semiconductor layer 21 to be released to form the channel region of the nanoFET. In some embodiments, the first semiconductor layer 21 is removed and the second semiconductor layer 23 is patterned to form the channel region. The high etch selectivity allows the first semiconductor layer 21 of the first semiconductor material to be removed without significantly removing the second semiconductor layer 23 of the second semiconductor material, thereby allowing the second semiconductor layer 23 to be patterned to form the channel region of the nanoFET.

[0062] exist Figure 2B In the middle, fins 321-325 and nanostructure stacks 22 are formed in the multilayer stack 25, corresponding to Figure 5 Operation 1100. A first nanostructure 22A1-22C5 (also collectively referred to as "channel 22") is formed from the first semiconductor layer 21, and a second nanostructure 24 is formed from the second semiconductor layer 23. Fin 321 is not present. Figure 2B and Figure 3B As shown in the figure, but for example, it can be found in the figure. Figure 1C and Figure 10 As seen below, fins 322-325 are described with reference to them, and it should be understood that this description also applies to fin 321. In some embodiments, nanostructures 22, 24 and fins 322-325 can be formed by etching trenches 35 in the multilayer stack 25 and the substrate 110. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching can be anisotropic. The distance between adjacent fins 322-325 and nanostructures 22, 24 in the Y-axis direction can be from about 18 nm to about 100 nm. Nanostructures 22A3, 22B3, 22C3 are a first stack, nanostructures 22A4, 22B4, 22C4 are a second stack, and nanostructures 22A5, 22B5, 22C5 are a third stack.

[0063] The fins 322-325 and nanostructures 22, 24 can be patterned using any suitable method. For example, one or more photolithography processes, including dual-patterning or multi-patterning processes, can be used to form the fins 322-325 and nanostructures 22, 24. Typically, dual-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing a pitch smaller than that achievable using a single direct photolithography process. As an example of a multi-patterning process, a sacrificial layer can be formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 322-325. In some embodiments, a hard mask layer 29 is patterned, for example, by a photolithography process, and then the pattern is transferred by an etching process to form the fins 322-325 and nanostructures 22, 24. Each of the fins 322-325 and the nanostructures 22, 24 overlaid thereon can be collectively referred to as a “fin stack”. The fin stack 26, including fin 322 and nanostructures 22A2, 22B2, 22C2, and 24, is composed of... Figure 2B and Figure 3B The dotted lines in the middle are used to outline it. Figure 2B and Figure 3B Four fin stacks 26 are shown, but fewer or more fin stacks can also be formed by a patterning process. In some embodiments, the fin stacks 26 on a first adjacent pair (e.g., fins 322, 323) of fins 322-325 can be separated by a first distance of about 40 nm to about 60 nm in the Y-axis direction, and the fin stacks 26 on a second adjacent pair (e.g., fins 323, 324) of fins 322-325 can be separated by a second distance of about 20 nm to about 60 nm in the Y-axis direction.

[0064] Figure 2B and Figure 3B Fins 322-325 with vertical straight sidewalls are shown. In some embodiments, the sidewalls are substantially vertical (non-tapered), such that the widths of fins 322-325 and nanostructures 22, 24 are substantially similar, and the shapes of nanostructures 22, 24 are rectangular (e.g., having a rectangular profile in the YZ plane). In some embodiments, fins 322-325 have tapered sidewalls, such that the width of each of fins 322-325 and / or nanostructures 22, 24 increases continuously in the direction toward the substrate 110. In such embodiments, nanostructures 22, 24 may have different widths from each other and be trapezoidal in shape (e.g., having a trapezoidal profile in the YZ plane).

[0065] exist Figure 2C and Figure 3C In the middle, the wall structure 300 is formed in one or more grooves 35, corresponding to Figure 5Operation 1200. As shown, a wall structure 300 may be adjacent to fin 322 (e.g., in such a way). Figure 1C and Figure 10 The fins 322 and 321 shown are formed, and another wall structure 300 may be formed between fins 323 and 324 and between the first and second stacks. The formation of the wall structure 300 may include one or more deposition operations. In some embodiments, a pad dielectric layer 302 is formed in the first deposition operation, such as CVD, ALD, or other suitable deposition operations. The pad dielectric layer 302 may be formed of a first dielectric material, such as a low-k dielectric material, which may be or include SiN, SiCN, SiOC, SiOCN, etc., as referenced. Figures 1A-1H As described.

[0066] After forming the pad dielectric layer 302, an etch stop layer 304 may be formed on the pad dielectric layer 302. The formation of the etch stop layer 304 may include manipulation of the material of the pad dielectric layer 302. In an embodiment, the etch stop layer 304 is formed by depositing a layer of silicon oxide on the pad dielectric layer 302, for example, by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof.

[0067] After forming the etch stop layer 304, for example, a core dielectric layer 306 is formed on the etch stop layer 304. In some embodiments, the core dielectric layer 306 is formed in a second deposition operation from a first dielectric material or a second dielectric material substantially different from the first dielectric material. The second deposition operation may be CVD, ALD, or other suitable deposition operations. The core dielectric layer 306 may be or include SiN, SiCN, SiOC, SiOCN, etc.

[0068] For reference Figure 1I The described structure can form a wall structure 300A to replace... Figure 2C or Figure 3C The wall structure 300 shown may be supplemented by a wall structure 300A. When the wall structure 300A is formed, the etch stop layer 304 may not be formed, and the core dielectric layer 306 is a different material from the pad dielectric layer 302, such that the pad dielectric layer 302 has high etch selectivity compared to the core dielectric layer 306. For example, the pad dielectric layer 302 may be or include SiN or SiCN, and the core dielectric layer 306 may be or include SiOC or SiOCN. In some embodiments, the pad dielectric layer 302 may be or include SiOC or SiOCN, and the core dielectric layer 306 may be or include SiN or SiCN.

[0069] After forming the core dielectric layer 306 of wall structure 300 or wall structure 300A, the pad dielectric layer 302, optional etch stop layer 304, and core dielectric layer 306 can be etched to remove their material to a level below the upper surface of hard mask layer 29. For example, as Figure 2C and Figure 3C As shown, the upper surface of the wall structure 300 (or wall structure 300A) can be at the level above the uppermost channels 22A2, 22A3, 22A4, 22A5, above the second semiconductor layer 27, or above the oxide layer 28.

[0070] exist Figure 2D and Figure 3D In the middle, a laterally extending trench 37 is formed on the channel 22 and wall structure 300 (or wall structure 300A) passing through fins 322-325 in the region including the logic device. Figure 2D The mask 400 is located above the area including the SRAM device. Figure 3D Trench 37 may extend to a level coplanar with, slightly above, or slightly below, trench 35. Trench 37 extends in a direction perpendicular to or substantially perpendicular to the direction in which trench 35 extends (e.g., the Y-axis direction) (e.g., the X-axis direction). One or more removal operations may be used to form trench 37. In some embodiments, the removal operation may be or include any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching may be anisotropic. The distance in the X-axis direction between adjacent fins 322-325 and nanostructures 22, 24 may be from about 18 nm to about 100 nm. During the formation of trench 37, mask 400 may be placed over the region of IC device 10 in which SRAM devices are formed. Figure 2F and Figure 3F In the subsequent operations shown, an isolation trench or opening 520 is formed for forming the SRAM device.

[0071] exist Figures 2E-2H and Figures 3E-3H In the middle, isolation zones 361 and 362 are formed near and between fins 322-325. Isolation zones 361 and 362 can be shallow trench isolation (STI) zones, corresponding to... Figure 5 Operation 1300. Isolation zones 361 and 362 can be accessed via trenches 35 and 37 ( Figure 2E ) or trench 35 ( Figure 3EAn insulating material layer 36 is formed by depositing an insulating material layer in the substrate 110. In some embodiments, the insulating material layer 36 is formed over the substrate 110, fins 322-325, and nanostructures 22, 24, and between adjacent fins 322-325 and nanostructures 22, 24. The insulating material layer 36 may be an oxide, such as silicon oxide, nitride, or a combination thereof, and may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof. In some embodiments, a liner (not shown separately) may first be formed along the surface of the substrate 110, fins 322-325, and nanostructures 22, 24. Subsequently, the insulating material layer 36 may be formed on the liner, for example, a material discussed above.

[0072] The insulating material layer 36 undergoes removal processes, such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof, to remove excess insulating material from the insulating material layer 36 above the hard mask 29. Figure 2E and Figure 3E As shown.

[0073] exist Figure 2F and Figure 3F In the middle, opening 520 is formed in the region including the SRAM device. Figure 3F The mask 500 is located above the area containing the logic devices. Figure 2F The opening 520 can be formed by one or more removal operations, such as suitable etching operations that may include RIE, NBE, atomic layer etching (ALE), etc. Figure 3F As shown, the opening 520 extends through or partially through the insulating material layer 36, the hard mask 29, the oxide layer 28, the second semiconductor layer 27, the channel 22, the second semiconductor layer 24, and one or more fins 322-325 (e.g., fins 323 and 324, as shown). In some embodiments, the opening 520 rests on the substrate 110, extends slightly into the substrate 110, or terminates slightly above the substrate 110 (e.g., leaving portions of fins 323, 324 retained). During the formation of the opening 520, a portion of the edge material layer 36 may cover the upper surface of the wall structure 300 (or wall structure 300A).

[0074] exist Figure 2G and Figure 3GIn the process, an active region isolation structure 530 is formed in the region including the SRAM device. A second removal process is then performed to remove portions of the hard mask 29, insulating material layer 36, active region isolation structure 530, and wall structure 300 (or wall structure 300A) to expose the second semiconductor layer 27. The active region isolation structure 530 can be formed by a suitable deposition process, such as CVD, ALD, etc., depositing the dielectric material of the active region isolation structure 530 in the opening 520. For example, the second removal process may include CMP. After the second removal process, the upper surfaces of the wall structure 300 (or wall structure 300A), the active region isolation structure 530 (in the region including the SRAM device), the insulating material layer 36, and the second semiconductor layer 27 are coplanar or substantially coplanar.

[0075] exist Figure 2H and Figure 3H In the process, a third removal process is performed to remove the second semiconductor layer 27, and a fourth removal process is performed to recess the isolation regions 361 and 362. Figure 2H The stereoscopic view comes from Figures 2A-2G In the X-axis direction. In some embodiments, after the third removal process, the top surface of the nanostructure 22 may be exposed and flush with the insulating material layer 36 after the third removal process is completed. The insulating material layer 36 is then recessed to form isolation regions 361, 362. After the isolation regions 361, 362 are recessed, the upper portions of the nanostructures 22, 24 and fins 322-325 may protrude above the isolation regions 361, 362. The isolation regions 361, 362 may have a flat, convex, concave or a combination thereof top surface as shown. In some embodiments, the isolation regions 361, 362 are recessed by an acceptable etching process, such as using an oxide such as dilute hydrofluoric acid (dHF) selectively applied to the insulating material, leaving the fins 322-325 and the nanostructures 22, 24 substantially unchanged.

[0076] exist Figure 3H In the region including the SRAM device, an active region isolation structure 530 is recessed, as shown. In some embodiments, the active region isolation structure 530 is recessed during a fourth removal process that forms isolation regions 361, 362. In some embodiments, the active region isolation structure 530 is recessed before or after the formation of isolation regions 361, 362, for example, in a fifth removal process different from the fourth removal process. After the insulating material layer 36 and the active region isolation structure 530 are recessed, the upper surfaces of isolation regions 361, 362 and the active region isolation structure 530 may be coplanar or substantially coplanar (e.g., slightly offset from each other in the Z-axis direction).

[0077] exist Figure 2H and Figure 3HSuitable wells (not shown separately) can be formed in fins 322-325, nanostructures 22, 24, and / or isolation regions 361, 362. Using a mask, n-type impurity implantation can be performed in the p-type region of substrate 110, and p-type impurity implantation can also be performed in the n-type region of substrate 110. Example n-type impurities may include phosphorus, arsenic, antimony, etc. Example p-type impurities may include boron, boron fluoride, indium, etc. Annealing can be performed after implantation to repair implantation damage and activate p-type and / or n-type impurities. In some embodiments, in-situ doping during the epitaxial growth of fins 322-325 and nanostructures 22, 24 can avoid separate implantation; however, in-situ and implantation doping can be used together.

[0078] Figures 2I-2P This is a perspective view illustrating the formation of a gate structure 200 and a source / drain region 82 according to various embodiments. Figures 2I-2P The description applies to regions that include logic devices and regions that include SRAM devices.

[0079] exist Figure 2I In the process, after the isolation regions 361 and 362 are formed, a sacrificial gate structure 40 is formed above the fins 322-325, the wall structure 300 (or the wall structure 300A), the isolation regions 361 and 362, and the nanostructures 22 and 24. Figure 2I Three sacrificial gate structures 40 are shown, and many additional sacrificial gate structures 40 may be formed substantially parallel to and simultaneously with the shown sacrificial gate structures 40.

[0080] When the sacrificial gate structure 40 is formed, a sacrificial gate layer 45 is formed over the fins 321-325 and / or the nanostructures 22, 24. The sacrificial gate layer 45 may be made of a material with high etch selectivity. The sacrificial gate layer 45 may be a conductive, semi-conductive, or non-conductive material, and may be or include amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The sacrificial gate layer 45 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. First and second mask layers 47A, 47B are formed over the sacrificial gate layer 45 and may include, for example, silicon nitride, silicon oxynitride, etc. In some embodiments, a gate dielectric layer 44 is formed before the sacrificial gate layer 45 between the sacrificial gate layer 45 and the fins 322-325 and / or the nanostructures 22, 24.

[0081] exist Figure 2JIn this process, after forming the sacrificial gate structure 40, one or more gate spacer layers 41 are formed, covering the exposed areas of the sacrificial gate structure 40 and the stack 26, fins 322-325, isolation regions 361, 362, and wall structure 300 (or wall structure 300A). The gate spacer layers 41 are formed by any suitable deposition process, such as PVD, CVD, ALD, etc. After forming the gate spacer layers 41, the horizontal portion of the gate spacer layers 41 (e.g., in the XY plane) can be removed to expose the upper surface of the stack 26, the upper surface of the wall structure 300 (or wall structure 300A), and the upper surfaces of the isolation regions 361, 362. In some embodiments, after removing the horizontal portion of the gate spacer layers 41, the cap portion 41C of the gate spacer layers 41 remains above the edge portions 361E, 362E of the isolation regions 361, 362, respectively.

[0082] After removing the horizontal portion of the gate spacer layer 41, one or more removal operations are performed to recess the stack 26, exposing the wall structure 300 (or wall structure 300A), isolation regions 361, 362, and fins 322-325 through the gate spacer layer 41. The removal operations may include suitable etching operations, such as RIE, NBE, ALE, etc., for removing material from the channel 22, the second semiconductor layer 24, the fins 322-325, the wall structure 300 (or wall structure 300A), and the isolation regions 361, 362.

[0083] exist Figure 2K In the process, internal spacers 74 are formed. A selective etching process is performed to recess the exposed ends of nanostructures 24 without substantially eroding nanostructures 22. After the selective etching process, grooves are formed at the locations where the removed ends of nanostructures 24 were previously located. Next, an internal spacer layer is formed to fill the grooves between nanostructures 22 formed by the previous selective etching process. The internal spacer layer can be a suitable dielectric material, such as silicon carbonitride (SiCN), silicon carbide (SiOCN), etc., and is formed by a suitable deposition method such as PVD, CVD, ALD, etc. An etching process, such as anisotropic etching, is performed to remove portions of the internal spacer layer located outside the grooves in nanostructures 24. The remaining portion of the internal spacer layer (e.g., the portion located inside the grooves in nanostructures 24) forms the internal spacer 74. The resulting structure is as follows: Figure 2K As shown.

[0084] Figure 2L The formation of the source / drain region 82 is shown, corresponding to Figure 5Operation 1400. In the illustrated embodiment, the source / drain region 82 is epitaxially grown from an epitaxial material. The source / drain region 82 grows on the exposed portions of fins 322-325 and contacts the nanostructure 22. Initially, the source / drain region 82 grows between adjacent isolation structures or between an isolation structure and a wall structure, for example, as shown, between the wall structure 300 and the isolation structure 361 on fin 322. The cap portion 41C on the isolation structure 361 laterally confines the source / drain region 82 as it grows upward from fin 322. In some embodiments, the source / drain regions 82 apply stress in their respective channels 22 to improve performance. The source / drain regions 82 are formed such that each sacrificial gate structure 40 is disposed between a corresponding adjacent pair of source / drain regions 82. In some embodiments, spacer layer 41 and inner spacer 74 separate source / drain region 82 from sacrificial gate layer 45 by an appropriate lateral distance (e.g., in the X-axis direction) to prevent electrical bridging to the gate of the subsequently formed device.

[0085] The source / drain region 82 may comprise any acceptable material, such as materials suitable for n-type or p-type devices. In some embodiments, for n-type devices, the source / drain region 82 comprises a material that applies tensile strain in the channel region, such as silicon, SiC, SiCP, SiP, etc. According to some embodiments, when forming a p-type device, the source / drain region 82 comprises a material that applies compressive strain in the channel region, such as SiGe, SiGeB, Ge, GeSn, etc. The source / drain region 82 may have a surface protruding from the corresponding surface of the fin and may have a facet. In some embodiments, adjacent source / drain regions 82 may be merged to form a single source / drain region 82 on two adjacent fins of fins 322-325.

[0086] The source / drain regions 82 can be doped with a dopant and then annealed. The impurity concentration in the source / drain regions can be around 10. 19 cm -3 Peace Treaty 10 21 cm -3 The N-type and / or p-type impurities in the source / drain region 82 can be any impurities discussed above. In some embodiments, the source / drain region 82 is doped in situ during growth. A contact etch stop layer (CESL) and an interlayer dielectric (ILD), which are not shown for simplicity, can then be formed over the sacrificial gate structure 40 and the source / drain region 82.

[0087] exist Figure 2M In the process, one or more of the source / drain regions 82 are cut or trimmed so that the source / drain regions 82 have a forked cross-sectional profile in the YZ plane, corresponding to Figure 5Operation 15005. In operation 1500, the portion of the source / drain region 82 overlapping with the wall structure 300 or 300A is trimmed. Prior to the etching operation for trimming the source / drain region 82, a patterned mask 550 covering the source / drain region 82, the sacrificial gate structure 40, the gate spacer layer 41, and the isolation regions 361, 362 can be formed. The patterned mask 550 includes a second lateral extension 82EX2 exposing the source / drain region 82 (see...). Figure 1G The opening 39, and the second lateral extension 82EX2, are on the wall structure 300 or 300A. In some embodiments, the opening 39 is a trench extending along the X-axis. The etching operation is performed through the opening 39 and may include appropriate anisotropic etching that substantially does not erode the portion of the source / drain region 82 covered by the patterned mask 550. After removing the lateral edge portions of the source / drain region 82, the lateral extensions of the source / drain region 82 passing through the edge of the channel 22 may be trimmed laterally in the range of about 0 nm to about 10 nm, and on the side covered by the patterned mask 550 in the range of about 10 nm to about 20 nm.

[0088] exist Figure 2N In this process, the channel 22 is released by removing the nanostructure 24, the mask layer 47, and the sacrificial gate layer 45. Prior to release, a planarization process, such as CMP, can be performed to flush the surfaces of the top sacrificial gate layer 45 and the gate spacer layer 41. The planarization process also removes the mask layers 47A and 47B on the sacrificial gate layer 45, as well as portions of the gate spacer layer 41 along the sidewalls of the mask layer 47. Thus, the top surface of the sacrificial gate layer 45 is exposed.

[0089] Next, the sacrificial gate layer 45 is removed in an etching process to form a trench. In some embodiments, the sacrificial gate layer 45 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the sacrificial gate layer 45 without etching the spacer layer 41. When the sacrificial gate dielectric 44 is present, it can be used as an etch stop layer when the sacrificial gate layer 45 is etched. The sacrificial gate dielectric 44 can then be removed after the sacrificial gate layer 45 has been removed.

[0090] Nanostructure 24 is removed to release nanostructure 22. After removal of nanostructure 24, nanostructure 22 forms multiple horizontally extending nanosheets (e.g., parallel to the main upper surface of substrate 110). The nanosheets can be collectively referred to as the channels 22 of the formed nanostructure devices 20A-20E.

[0091] In some embodiments, the nanostructure 24 is removed by a selective etching process using an etchant that is selective to the material of the nanostructure 24, such that the nanostructure 24 is removed without substantially eroding the nanostructure 22. In some embodiments, the etching process is an isotropic etching process using an etching gas and optionally a carrier gas, wherein the etching gas includes F2 and HF, and the carrier gas may be an inert gas such as Ar, He, N2, or combinations thereof.

[0092] In some embodiments, nanostructure 24 is removed and nanostructure 22 is patterned to form the channel regions of both the PFET and NFET. In some other embodiments, nanostructure 22 may be removed and nanostructure 24 may be patterned to form the channel regions of both the PFET and NFET.

[0093] In some embodiments, the nanosheets 22 of the nanostructure devices 20A-20E are reshaped (e.g., thinned) by a further etching process to improve the gate fill window. Reshaping can be performed by a selective isotropic etching process on the nanosheets 22. After reshaping, the nanosheets 22 can have a dog-bone shape, wherein the central portion of the nanosheets 22 is thinner than the peripheral portion along the X-axis.

[0094] In some embodiments, ILD 130 is deposited over source / drain region 82 before removing nanostructure 24, mask layer 47, and sacrificial gate layer 45. Etch stop layer 131 may also be formed before ILD 130 deposition. After ILD 130 deposition, ILD 130 may be slightly recessed, and a second etch stop layer (not specifically shown) may be formed over the recessed ILD 130. CMP operations or similar processes may then be performed to remove excess material from the second etch stop layer, such that the upper surface of the second etch stop layer is substantially coplanar with the upper surfaces of etch stop layer 131 and gate spacer 41.

[0095] exist Figure 2O In, corresponding to Figure 5 Operation 1600 forms an uncut replacement gate 200U. The uncut replacement gate 200U can be formed by one or more deposition operations such as CVD, ALD, etc. Figure 4 This corresponds to gate structure 200B (see...) Figure 2Q ) part Figure 2O Detailed view of area 170. (See also...) Figure 4As shown in the gate structure 200B, each replacement gate 200 typically includes an interface layer (IL, or "first IL" hereinafter) 210, at least one gate dielectric layer 600, a work function metal layer 900, and a conductive fill layer 290. In some embodiments, each replacement gate 200 further includes at least one of a second interface layer 240 or a second work function layer 700.

[0096] refer to Figure 4 In some embodiments, the first IL 210 comprises an oxide of the semiconductor material of the substrate 110, such as silicon oxide. In other embodiments, the first IL 210 may comprise another suitable type of dielectric material. The thickness of the first IL 210 is in the range of about 5 angstroms to about 50 angstroms. Figure 4 As shown, due to the presence of the spacer portion 302S adjacent to the channel 22, the first IL 210 can terminate on the bottom and top surfaces of the spacer portion 302S.

[0097] Still referencing Figure 4 A gate dielectric layer 600 is formed over the first IL 210. In some embodiments, an atomic layer deposition (ALD) process is used to form the gate dielectric layer 600 to precisely control the thickness of the deposited gate dielectric layer 600. In some embodiments, the ALD process is performed using about 40 to 80 deposition cycles within a temperature range of about 200 degrees Celsius to about 300 degrees Celsius. In some embodiments, the ALD process uses HfCl4 and / or H2O as precursors. This ALD process can form the first gate dielectric layer 220 to have a thickness in the range of about 10 angstroms to about 100 angstroms. Figure 4 As shown, the gate dielectric layer 600 may be a continuous layer of the sidewalls of the etch stop layer 304 (or the core dielectric layer 306 of the wall structure 300A) conforming to (e.g., contact) the wall structure 300, the spacer portion 302S, and the bottom and top surfaces of the first IL 210 or the channel 22 (when the first IL 210 is not present).

[0098] In some embodiments, the gate dielectric layer 600 includes a high-k dielectric material, which may refer to a dielectric material having a high dielectric constant greater than that of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or combinations thereof. In other embodiments, the gate dielectric layer 600 may include a non-high-k dielectric material, such as silicon oxide. In some embodiments, the gate dielectric layer 600 includes more than one high-k dielectric layer, wherein at least one layer includes dopants such as lanthanum, magnesium, yttrium, etc., which can be driven in by an annealing process to modify the threshold voltage of the nanostructure device 20A-20E.

[0099] Further reference Figure 4 A second IL 240 is formed on the gate dielectric layer 600, and a second work function layer 700 is formed on the second IL 240. The second IL 240 promotes better metal gate adhesion on the gate dielectric layer 600. In many embodiments, the second IL 240 further provides improved thermal stability for the gate structure 200B and serves to limit the diffusion of metal impurities from the work function metal layer 900 and / or the work function barrier layer 700 into the gate dielectric layer 600. In some embodiments, the second IL 240 is formed by first depositing a high-k capping layer (not shown for simplicity) on the gate dielectric layer 600. In various embodiments, the high-k capping layer includes one or more of the following: HfSiON, HfTaO, HfTiO, HfTaO, HfAlON, HfZrO, or other suitable materials. In one specific embodiment, the high-k capping layer includes titanium silicon nitride (TiSiN). In some embodiments, a high-k capping layer is deposited by ALD at a temperature of about 40 to about 450 degrees Celsius using about 40 to about 100 cycles. Thermal annealing is then performed to form a second IL 240, which in some embodiments may be or include TiSiNO. After forming the second IL 240 by thermal annealing, atomic layer etching (ALE) with artificial intelligence (AI) control can be cyclically performed to remove the high-k capping layer while substantially not removing the second IL 240. Each cycle may include a first WCl5 pulse, followed by an Ar purge, then a second O2 pulse, followed by another Ar purge. The high-k capping layer is removed to increase the gate fill window, which is used for further multi-threshold voltage tuning via metal gate patterning.

[0100] Further in Figure 4 In some embodiments, after forming the second IL 240 and removing the high-k capping layer, a power function barrier layer 700 may be optionally formed. The power function barrier layer 700 is or includes a metal nitride, such as TiN, WN, MoN, TaN, etc. In one specific embodiment, the power function barrier layer 700 is TiN. The power function barrier layer 700 may have a range from approximately To date The thickness of the barrier layer 700, including the work function barrier layer, provides additional threshold voltage tuning flexibility. Typically, the work function barrier layer 700 increases the threshold voltage of NFET transistor devices and decreases the threshold voltage (amplitude) of PFET transistor devices.

[0101] A function metal layer 900 is formed on the function barrier layer 700. The function metal layer 900 may include at least one of an N-type function metal layer, an in-situ capping layer, or an oxygen barrier layer. Some embodiments are described. The N-type function metal layer is or includes an N-type metallic material, such as TiAlC, TiAl, TaAlC, TaAl, etc. The N-type function metal layer can be formed by one or more deposition methods, such as CVD, PVD, ALD, plating, and / or other suitable methods, and has approximately [missing information - likely related to a specific feature]. arrive The thickness between [a certain value]. An in-situ capping layer is formed on the N-type work function metal layer. In some embodiments, the in-situ capping layer is or includes TiN, TiSiN, TaN, or other suitable materials, and has approximately [a certain thickness]. arrive The thickness between [a certain value]. An oxygen barrier layer is formed on the in-situ capping layer to prevent oxygen diffusion into the N-type work function metal layer, which would cause an undesirable shift in the threshold voltage. The oxygen barrier layer is formed of a dielectric material that prevents oxygen penetration into the N-type work function metal layer and protects it from further oxidation. The oxygen barrier layer may include oxides of silicon, germanium, SiGe, or other suitable materials. In some embodiments, the oxygen barrier layer is formed using an ALD and has approximately [a certain thickness]. To date The thickness between.

[0102] Figure 4 The conductive filler layer 290 is further illustrated. In some embodiments, an adhesive layer (not shown separately) is formed between the oxygen barrier layer of the function metal layer and the conductive filler layer 290. The adhesive layer can promote and / or enhance adhesion between the conductive filler layer 290 and the function metal layer 900. In some embodiments, the adhesive layer can be formed from a metal nitride using an ALD, such as TiN, TaN, MoN, WN, or other suitable materials. In some embodiments, the thickness of the adhesive layer is approximately Peace Treaty Between. The conductive filler layer 290 may be formed on the adhesive layer and may include a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or combinations thereof. In some embodiments, the conductive filler layer 290 may be deposited using methods such as CVD, PVD, plating, and / or other suitable processes. In some embodiments, a seam 510 (which may be an air gap) is formed perpendicularly between channels 22A2, 22B2 in the conductive filler layer 290. In some embodiments, the conductive filler layer 290 is conformally deposited on the function metal layer 900. The seam 510 may be formed due to the merging of sidewall deposited films during conformal deposition. In some embodiments, the seam 510 is not present between adjacent channels 22A2, 22B2.

[0103] Figure 2PThe formation of the second conductive layer 297 is illustrated. Prior to depositing the second conductive layer 297, the uncut gate structure 200U can be recessed by, for example, a suitable etching operation. The etching operation can include isotropic or anisotropic etching that removes the conductive fill layer 290 without substantially eroding the gate spacer layer 41, etch stop layer 131, and ILD 130. After the etching operation that recesses the uncut gate structure 200U, the second conductive layer 297 can be deposited by a suitable deposition operation, which can include PVD, sputtering, CVD, ALD, etc. In some embodiments, the second conductive layer 297 is formed by depositing a conductive material such as tungsten. After depositing the second conductive layer 297, excess conductive material on the etch stop layer 131, ILD 130, and gate spacer layer 41 can be removed by, for example, CMP.

[0104] Figure 2Q and Figure 3I The diagram illustrates the formation of the gate isolation structure 99. Figure 2Q and Figure 3I In this process, one or more mask layers may be formed over the uncuttered gate structure 200U. The mask layers may include silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the thickness of the mask layers may range from about 100 nm to about 200 nm. In some embodiments, the uppermost mask layer undergoes a planarization operation. The mask layers may include hard mask layers, which can be deposited using any suitable process, including spin coating, LPCVD, PECVD, PVD, ALD, or other suitable processes. According to some embodiments, the hard mask layer comprises one or more layers of SiN, SOC, etc.

[0105] A hard mask layer can be etched to form an opening over one or more of the wall structures 300 or 300A, one or more of the isolation regions 361, 362, or both. For example... Figure 2Q and Figure 3I As shown, one opening is formed above the wall structure 300 between fins 321 and 322 and exposes the wall structure 300, while the other opening is formed above the isolation structure 362. When formed above one of the wall structures 300 or 300A, the width of the opening (in the Y-axis direction) can be smaller than the width of the wall structure 300, but a larger width may also be appropriate.

[0106] To form the opening, in some embodiments, a photoresist pattern (not shown separately) is formed over the hard mask layer, and the hard mask layer is first etched using a material-selective anisotropic etching process, which forms the upper portion of the opening extending from the upper surface of the hard mask layer to expose the upper surface of the second conductive layer 297. After etching the hard mask layer, the photoresist pattern can be removed, and the hard mask layer can be used as a mask when forming the lower portion of the opening extending through the second conductive layer 297, the uncut gate structure 200U, and optionally into the wall structure 300 or 300A.

[0107] exist Figure 2Q and Figure 3I In this process, after forming the opening, a gate isolation structure 99 is formed within the opening. In some embodiments, the gate isolation structure 99 is or includes silicon nitride, silicon oxide, Al2O3, ZrO2, or another suitable material. The gate isolation structure 99 can be deposited in the opening using suitable processes such as CVD and / or other suitable techniques. After the deposition of the gate isolation structure 99, a removal process, such as CMP or other suitable processes, can be performed to remove excess material of the gate isolation structure 99 from above the second conductive layer 297, such that the upper surface of the gate isolation structure 99 is substantially flush with the upper surface of the second conductive layer 297. The gate isolation structure 99 typically inherits the shape of the opening. At this point, the gate structures 200A-200C are electrically isolated from each other.

[0108] The embodiments can provide advantages. By forming wall structures 300 or 300A at the cell boundaries, the gate-drain capacitance is reduced by decreasing the metal gate cap and source / drain epitaxial dimensions. The active region spacing is also reduced. The wall structures can be multilayered, which allows the gate structure 200 overlapping the channel 22 to be extended by removing portions of the pad dielectric layer 302 of the wall structures 300 or 300A, thereby enhancing the control of current through the channel 22 by the gate structure 200. The source / drain regions 82 adjacent to the wall structures are cut or trimmed to prevent adjacent source / drain regions 82 from merging. The gate-drain capacitance can be reduced by decreasing the lateral dimensions of the metal gate cap and source / drain regions 82. Thus, device performance is improved, and the active region spacing between the nanostructure devices 20A-20E can be reduced, saving chip area.

[0109] According to at least one embodiment, an integrated circuit device includes: a first vertical stack of nanostructures located above a substrate; a second vertical stack of nanostructures located above the substrate; a wall structure located between and in direct contact with the first and second vertical stacks; a gate structure surrounding three sides of the nanostructures; and a source / drain region located next to the first vertical stack of nanostructures.

[0110] In the aforementioned integrated circuit device, the wall structure includes: a core dielectric layer; and a pad dielectric layer located between the core dielectric layer and the first vertical stack and the second vertical stack.

[0111] In the aforementioned integrated circuit devices, the core dielectric layer and the pad dielectric layer have different etching selectivity.

[0112] In the aforementioned integrated circuit device, the core dielectric layer is in contact with the pad dielectric layer.

[0113] In the aforementioned integrated circuit device, the pad dielectric layer has substantially the same etch selectivity as the core dielectric layer, and the wall structure further includes an etch stop layer located between the pad dielectric layer and the core dielectric layer.

[0114] In the aforementioned integrated circuit device, the pad dielectric layer includes spacer portions that are perpendicularly separated from each other by the gate structure.

[0115] In the aforementioned integrated circuit device, the gate structure includes: a dielectric layer that contacts the upper and lower surfaces of the spacer portion; and a conductive layer that is perpendicularly separated from the spacer portion through the dielectric layer.

[0116] The aforementioned integrated circuit device also includes: a gate isolation structure that extends through the gate structure and contacts the wall structure.

[0117] In the aforementioned integrated circuit devices, the gate isolation structure extends into the wall structure.

[0118] According to at least one embodiment, an integrated circuit device includes: a plurality of nanostructures, a gate structure, and source / drain regions. The plurality of nanostructures are located above a substrate. Each nanostructure includes: an upper side; a lower side opposite to the upper side; a first lateral side facing a first lateral direction; a second lateral side opposite to the first lateral side; a third lateral side facing a second lateral direction transverse to the first lateral direction; and a fourth lateral side opposite to the third lateral side. The gate structure extends in the first lateral direction, contacting the upper side, lower side, and first lateral side of each of the nanostructures, and is isolated from the third lateral side and fourth lateral side of each of the nanostructures. The source / drain regions, adjacent to the plurality of nanostructures, have an asymmetrical shape in the first lateral direction.

[0119] In the aforementioned integrated circuit device, the source / drain region includes: a first lateral extension that extends laterally in a first lateral direction beyond the first width of a plurality of nanostructures; and a second lateral extension that extends laterally in a direction opposite to the first lateral direction beyond the second width of a plurality of nanostructures less than the first width.

[0120] In the aforementioned integrated circuit device, the first width is in the range of about 10 nanometers to about 20 nanometers; the second width is in the range of about 0 nanometers to about 10 nanometers.

[0121] The aforementioned integrated circuit device further includes: an isolation region located on a first side of the source / drain region; and a wall structure located on a second side of the source / drain region, the second side being opposite to the first side.

[0122] The aforementioned integrated circuit device also includes a gate spacer layer located on the gate structure, the gate spacer layer including: a cover portion located on the edge portion of the isolation region.

[0123] In the aforementioned integrated circuit device, the cover portion is in contact with the source / drain region.

[0124] According to at least one embodiment, a method of manufacturing an integrated circuit device includes: forming a first stack, a second stack, and a third stack of nanostructures, the first, second, and third stacks being laterally separated from each other; forming a wall structure between the first and second stacks; forming an isolation region between the second and third stacks; forming a first source / drain region in contact with the first stack, a second source / drain region in contact with the second stack, and a third source / drain region in contact with the third stack; trimming portions of the first and second source / drain regions, the wall structures being partially facing each other and vertically overlapping; and forming a gate structure over the first, second, and third stacks.

[0125] In the aforementioned integrated circuit device, forming a wall structure includes: forming a pad dielectric layer on the sidewalls of a first stack, a second stack, and a third stack of nanostructures; and forming a core dielectric layer on the pad dielectric layer.

[0126] In the aforementioned integrated circuit device, forming the wall structure further includes forming an etch stop layer on the pad dielectric layer before forming the core dielectric layer.

[0127] In the aforementioned integrated circuit device, the trimming portion includes: forming a patterned mask covering a first source / drain region, a second source / drain region, and a third source / drain region, the patterned mask having an opening above the wall structure; and etching the first source / drain region and the second source / drain region through the opening.

[0128] The aforementioned integrated circuit device also includes a gate isolation structure that extends through the gate structure and contacts the wall structure.

[0129] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made within the invention without departing from its spirit and scope.

Claims

1. An integrated circuit device, comprising: The first vertically stacked component of the nanostructure is located above the substrate; A second vertically stacked nanostructure is located above the substrate; A wall structure is located between and in direct contact with the first vertical stack and the second vertical stack. The wall structure includes a core dielectric layer and a pad dielectric layer, with the pad dielectric layer located between the core dielectric layer and the first vertical stack and the second vertical stack. A gate structure surrounds three sides of the nanostructure, wherein the pad dielectric layer includes spacer portions perpendicularly separated from each other by the gate structure; as well as The source / drain region is located next to the first vertically stacked part of the nanostructure.

2. The integrated circuit device according to claim 1, wherein, The pad dielectric layer and the core dielectric layer are made of the same material.

3. The integrated circuit device according to claim 1, wherein, The core dielectric layer and the pad dielectric layer have different etching selectivity.

4. The integrated circuit device according to claim 3, wherein, The core dielectric layer is in contact with the pad dielectric layer.

5. The integrated circuit device according to claim 1, wherein, The pad dielectric layer has substantially the same etch selectivity as the core dielectric layer, and the wall structure further includes: An etch stop layer is located between the pad dielectric layer and the core dielectric layer.

6. The integrated circuit device according to claim 5, wherein, The thickness of the etch stop layer is thinner than that of the pad dielectric layer and the core dielectric layer.

7. The integrated circuit device according to claim 1, wherein, The gate structure includes: A dielectric layer, in contact with the upper and lower surfaces of the spacer portion; and The conductive layer is perpendicularly separated from the spacer portion by the dielectric layer.

8. The integrated circuit device according to claim 1, further comprising: A gate isolation structure extends through the gate structure and contacts the wall structure.

9. The integrated circuit device according to claim 8, wherein, The gate isolation structure extends into the wall structure.

10. An integrated circuit device, comprising: Multiple nanostructures are located above a substrate, the multiple nanostructures including a first vertical stack of nanostructures and a second vertical stack of nanostructures on the substrate, each of the nanostructures comprising: upper side; The lower side, opposite to the upper side; The first lateral side faces the first lateral direction; The second lateral side is opposite to the first lateral side; The third lateral side faces the second lateral direction, which is transverse to the first lateral direction; and The fourth lateral side is opposite to the third lateral side; A gate structure extending in the first lateral direction, the gate structure contacting the upper side, the lower side and the first lateral side of each of the nanostructures, the gate structure being isolated from the third lateral side and the fourth lateral side of each of the nanostructures; Source / drain regions, located adjacent to the plurality of nanostructures, having an asymmetrical shape in the first lateral direction; and A wall structure is located between and in direct contact with the first vertical stack and the second vertical stack. The wall structure includes a core dielectric layer and a pad dielectric layer. The pad dielectric layer is located between the core dielectric layer and the first vertical stack and the second vertical stack. The pad dielectric layer includes spacer portions that are perpendicularly separated from each other by the gate structure.

11. The integrated circuit device according to claim 10, wherein, The source / drain region includes: A first lateral extension extends laterally in the first lateral direction beyond the first width of the plurality of nanostructures; and The second lateral extension extends laterally in a direction opposite to the first lateral direction, exceeding a second width smaller than the first width of the plurality of nanostructures.

12. The integrated circuit device according to claim 11, wherein: The first width is in the range of 10 nanometers to 20 nanometers; and The second width is in the range of 0 nanometers to 10 nanometers.

13. The integrated circuit device according to claim 10, further comprising: An isolation region is located on the first side of the source / drain region; The wall structure is located on the second side of the source / drain region, and the second side is opposite to the first side.

14. The integrated circuit device of claim 13, further comprising a gate spacer layer located on the gate structure, the gate spacer layer comprising: The cover portion is located on the edge portion of the isolation zone.

15. The integrated circuit device according to claim 14, wherein, The cover portion is in contact with the source / drain region.

16. A method for manufacturing an integrated circuit device, comprising: A first stack, a second stack, and a third stack of nanostructures are formed, wherein the first stack, the second stack, and the third stack are laterally separated from each other; A wall structure is formed between the first stack and the second stack, the wall structure including a core dielectric layer and a pad dielectric layer, the pad dielectric layer being located between the core dielectric layer and the first stack and the second stack; An isolation zone is formed between the second stack and the third stack; A first source / drain region is formed in contact with the first stack, a second source / drain region is formed in contact with the second stack, and a third source / drain region is formed in contact with the third stack. Trim portions of the first source / drain region and the second source / drain region, wherein the portions face each other and overlap the wall structure perpendicularly; as well as A gate structure is formed over the first stack, the second stack, and the third stack, wherein the pad dielectric layer includes spacer portions that are perpendicularly separated from each other by the gate structure.

17. The method according to claim 16, wherein, The wall structure is formed by: The pad dielectric layer is formed on the sidewalls of the first, second, and third nanostructured stacks; and The core dielectric layer is formed on the pad dielectric layer.

18. The method according to claim 17, wherein, The formation of the wall structure also includes: An etch stop layer is formed on the pad dielectric layer prior to the formation of the core dielectric layer.

19. The method of claim 16, wherein, The repair of the aforementioned parts includes: A patterned mask is formed covering the first source / drain region, the second source / drain region, and the third source / drain region, the patterned mask having an opening above the wall structure; and The first source / drain region and the second source / drain region are etched through the opening.

20. The method of claim 16, further comprising: A gate isolation structure is formed that extends through the gate structure and contacts the wall structure.

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