Semiconductor device and method of manufacturing the same

Abstract

This application provides a semiconductor device and its fabrication method. The high electron mobility transistor includes a specially designed gate structure. The gate structure includes a high-resistivity nitride epitaxial layer and a p-cap layer stacked together, and a first gate insulating layer disposed on the surface of the first barrier layer away from the channel layer. The projected length of the p-cap layer in the stacking direction of the stacked structure is greater than the projected length of the high-resistivity nitride epitaxial layer in the stacked structure. The thickness of the first gate insulating layer is less than the thickness of the high-resistivity nitride epitaxial layer. The high-resistivity nitride epitaxial layer can improve the crystal quality of the p-cap layer. The high-resistivity nitride epitaxial layer can prevent Mg diffusion and channel degradation. The high-resistivity nitride epitaxial layer can effectively reduce the leakage current of the gate electrode. This application reduces gate leakage current by setting a special gate structure, enabling the device to have a larger gate voltage operating range and greatly improving the reliability of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically to a semiconductor device and its fabrication method. Background Technology

[0002] Group III nitride semiconductors are important new types of semiconductor materials, mainly including AlN, GaN, InN, and their compounds such as AlGaN, InGaN, and AlInGaN. Due to their advantages such as direct bandgap, wide bandgap, and high breakdown electric field strength, Group III nitride semiconductors, represented by GaN, have broad application prospects in light-emitting devices, power electronics, and radio frequency devices. For example, GaN-based LED devices have become the main electrical devices emitting green and blue light, and have found widespread application in lighting, backlighting, and displays.

[0003] Another important device type of group III nitride semiconductors is the high electron mobility transistor (HEMT), which holds great promise in the field of power semiconductors. Due to spontaneous polarization and piezoelectric polarization effects, there is a strong polarization positive charge at the GaN-AlGaN interface on the (0001) plane. The presence of these polarization positive charges attracts and leads to the generation of a two-dimensional electron gas at the interface. This two-dimensional electron gas has a very high carrier concentration and a very high carrier mobility, making it a core component in the fabrication of HEMTs.

[0004] When traditional AlGaN / GaN heterojunction HEMT devices are used in power switches, a key issue lies in their normally-on characteristic. That is, the device is in a conducting state when no bias voltage is applied to the gate, and can only be turned off when a negative bias voltage is applied to the gate. This means that if the gate is de-energized, the device will lose control, causing leakage or short circuits, which poses a serious safety hazard in practical applications.

[0005] Therefore, achieving the normally-off state of the device is one of the core issues in the research of GaN-based HEMT power devices. That is, a device that only turns on when a gate bias voltage is applied is often called a normally-off device or enhancement-mode device. There are various existing methods for achieving normally-off GaN-based HEMT devices, such as grooved gate structures, MIS structures, cascaded structures, and p-type gate structures, among which the p-type gate structure is the most favored normally-off device solution. However, one of the main problems with the p-type gate structure is that the p-GaN is in direct contact with the AlGaN barrier layer, leading to severe gate leakage. This gate leakage also results in a limited gate voltage operating range; exceeding a certain voltage can easily damage the device, causing serious reliability issues.

[0006] Therefore, the inventors of this application provide a solution to the technical problem of severe gate leakage in normally off devices. Summary of the Invention

[0007] In view of this, this application provides a semiconductor device with a high threshold voltage and a method for fabricating the same, which can alleviate gate leakage, expand the gate voltage operating range, and improve the reliability of the device.

[0008] This application provides a high electron mobility transistor, comprising:

[0009] A stacked structure, the stacked structure comprising at least a channel layer and a first barrier layer;

[0010] A gate structure comprising a high-resistivity nitride epitaxial layer and a p-cap layer stacked thereon, wherein the projection length of the p-cap layer in the stacking direction of the stacked structure is greater than the projection length of the high-resistivity nitride epitaxial layer in the stacked structure; and

[0011] The gate structure further includes a first gate insulating layer disposed on the surface of the first barrier layer away from the channel layer, and the thickness of the first gate insulating layer is less than the thickness of the high-resistivity nitride epitaxial layer.

[0012] In one embodiment, the gate structure has: a first gate stack and a second gate stack;

[0013] The first gate stack comprises, from top to bottom, the p-cap layer, the high-resistivity nitride epitaxial layer, the first barrier layer, and the channel layer forming a gate stack; the p-cap layer and the first barrier layer in the first gate stack are separated by the high-resistivity nitride epitaxial layer, the p-cap layer cannot deplete the two-dimensional electron gas at the interface between the first barrier layer and the channel layer, and the first gate stack has a two-dimensional electron gas when the gate voltage is 0V;

[0014] The second gate stack comprises, from top to bottom, the p-cap layer, the first gate insulating layer, the first barrier layer, and the channel layer forming a gate stack; the p-cap layer in the second gate stack can deplete the two-dimensional electron gas at the interface between the first barrier layer and the channel layer, and the two-dimensional electron gas in the second gate stack is depleted when the gate voltage is 0V.

[0015] In one embodiment, the p-cap layer comprises: a first cap layer with a high doping concentration and a second cap layer with a low doping concentration;

[0016] The second cap layer wraps around the first cap layer;

[0017] The first cap layer is in contact with the high-resistivity nitride epitaxial layer;

[0018] The second cap layer is located away from the high-resistivity nitride epitaxial layer.

[0019] In one embodiment, the high electron mobility transistor further includes:

[0020] The second barrier layer comprises two parts;

[0021] The second barrier layer of the first part is formed between the first barrier layer and the high-resistivity nitride epitaxial layer;

[0022] The second barrier layer of the second portion is formed on the surface of the first gate insulating layer away from the first barrier layer; and a portion of the surface of the p-cap layer covers the second barrier layer.

[0023] In one embodiment, the high electron mobility transistor further includes:

[0024] A second gate insulating layer is disposed on the surface of the first gate insulating layer away from the first barrier layer. The thickness of the second gate insulating layer is less than the thickness of the p-cap layer, and a portion of the p-cap layer covers the second gate insulating layer.

[0025] In one embodiment, the gate structure further comprises: a third gate stack;

[0026] The third gate stack comprises, from top to bottom, the p-cap layer, the second gate insulating layer, the first gate insulating layer, the first barrier layer, and the channel layer forming a gate stack; the p-cap layer in the third gate stack cannot deplete the two-dimensional electron gas at the interface between the first barrier layer and the channel layer, and the third gate stack has a two-dimensional electron gas when the gate voltage is 0V.

[0027] In one embodiment, the high-resistivity nitride epitaxial layer is an unintentionally doped nitride, a carbon-doped nitride, or an iron-doped nitride.

[0028] In one embodiment, the thickness of the high-resistivity nitride epitaxial layer is greater than 20 nm.

[0029] This application also provides a method for fabricating a high electron mobility transistor, comprising:

[0030] S10, a stacked structure including at least a channel layer and a first barrier layer is sequentially prepared on the first surface of the substrate;

[0031] S20, a first gate insulating layer is formed on the first barrier layer, and the first gate insulating layer is etched to form a first groove exposing the first barrier layer, wherein the material of the first barrier layer is a nitride semiconductor.

[0032] S30, using the nitride semiconductor exposed in the first groove as a nucleation layer, a high-resistivity nitride epitaxial layer is selectively grown in the first groove, the thickness of the high-resistivity nitride epitaxial layer being greater than the thickness of the first gate insulating layer;

[0033] S40, using the high-resistivity nitride epitaxial layer as the nucleation layer, a p-cap layer is laterally epitaxially grown, wherein the projection length of the p-cap layer in the stacked structure is greater than the projection length of the high-resistivity nitride epitaxial layer in the stacked structure.

[0034] In one embodiment, the p-cap layer comprises: a first cap layer with a high doping concentration and a second cap layer with a low doping concentration, and the step of further depositing the p-cap layer in S40 includes:

[0035] S41, using the high-resistivity nitride epitaxial layer as the nucleation layer, a first cap layer with a high doping concentration is deposited;

[0036] S42, deposit a second cap layer outside the first cap layer, the second cap layer enclosing the first cap layer.

[0037] In one embodiment, the high electron mobility transistor further includes a second barrier layer, and S30 includes:

[0038] S31, deposit the second barrier layer into the first groove and the first gate insulating layer, wherein the material of the second barrier layer is a nitride semiconductor;

[0039] S32, using the nitride semiconductor exposed in the first groove as a nucleation layer, deposit the high-resistivity nitride epitaxial layer into the first groove, wherein the thickness of the high-resistivity nitride epitaxial layer is greater than the thickness of the first gate insulating layer.

[0040] This application also provides a method for fabricating a high electron mobility transistor, comprising:

[0041] S101, a stacked structure including at least a channel layer and a first barrier layer is sequentially prepared on the first surface of the substrate;

[0042] S102, a first gate insulating layer and a second gate insulating layer are formed on the first barrier layer, and the first gate insulating layer and the second gate insulating layer are etched for the first time to form a first groove exposing the first barrier layer, wherein the material of the first barrier layer is a nitride semiconductor.

[0043] S103, the second gate insulating layer is etched a second time to form a second groove that exposes the first gate insulating layer;

[0044] S104, using the nitride semiconductor exposed in the first groove as a nucleation layer, a high-resistivity nitride epitaxial layer is selectively grown in the first groove, the thickness of the high-resistivity nitride epitaxial layer being greater than the thickness of the first gate insulating layer.

[0045] S105, using the high-resistivity nitride epitaxial layer as the nucleation layer, a p-cap layer is laterally epitaxially grown into the second groove, a portion of the p-cap layer covering the second gate insulating layer, wherein the projection length of the p-cap layer in the stacked structure is greater than the projection length of the high-resistivity nitride epitaxial layer in the stacked structure.

[0046] The beneficial effects of this invention are as follows: The high electron mobility transistor includes a specially designed gate structure. The gate structure includes a stacked high-resistivity nitride epitaxial layer and a p-cap layer, and a first gate insulating layer disposed on the surface of the first barrier layer away from the channel layer. The projected length of the p-cap layer in the stacking direction of the stacked structure is greater than the projected length of the high-resistivity nitride epitaxial layer in the stacked structure. The thickness of the first gate insulating layer is less than the thickness of the high-resistivity nitride epitaxial layer. The high-resistivity nitride epitaxial layer in the gate structure can improve the crystal quality of the p-cap layer. The high-resistivity nitride epitaxial layer can prevent Mg diffusion and channel degradation. The high-resistivity nitride epitaxial layer can effectively reduce the leakage current of the gate electrode. This application reduces gate leakage current by setting a special gate structure, enabling the device to have a larger gate voltage operating range and greatly improving the reliability of the device. Attached Figure Description

[0047] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in the first embodiment of this application;

[0049] Figure 2 The first embodiment provided in this application is related to Figure 1 Schematic diagrams of semiconductor devices with different medium- and high-resistivity nitride epitaxial layer structures;

[0050] Figure 3 This is a schematic diagram of the structure of a semiconductor device provided in the second embodiment of this application;

[0051] Figure 4 This is a schematic diagram of the structure of a semiconductor device provided in the third embodiment of this application;

[0052] Figure 5 This is a schematic diagram of the structure of the semiconductor device provided in the fourth embodiment of this application;

[0053] Figure 6 This is a schematic diagram of the structure of the semiconductor device provided in the fifth embodiment of this application;

[0054] Figure 7 This is a schematic flowchart illustrating the steps of the semiconductor device provided in the first embodiment of this application;

[0055] Figure 8 A schematic diagram of the process flow of the semiconductor device provided in the first embodiment of this application;

[0056] Figure 9 This is a flowchart illustrating the steps of the semiconductor device provided in the fourth embodiment of this application;

[0057] Figure 10 This is a partial process flow diagram of the semiconductor device provided in the fourth embodiment of this application;

[0058] Figure 11 This is a schematic diagram of the remaining process flow of the semiconductor device provided in the fourth embodiment of this application;

[0059] Figure 12 This is a performance comparison chart of a traditional p-type gate structure semiconductor device and the semiconductor device provided in the embodiments of this application.

[0060] Explanation of reference numerals in the attached figures:

[0061] Semiconductor Device 10:

[0062] Layered structure 100: substrate 101, insertion layer 102, buffer layer 103, channel layer 104, first barrier layer 105, second barrier layer 106;

[0063] Gate structure 200: high-resistivity nitride epitaxial layer 201, p-cap layer 202, first gate insulating layer 203, second gate insulating layer 204, gate electrode 205; first gate stack 210, second gate stack 220, third gate stack 230; fourth gate stack 240; first cap layer 212, second cap layer 222;

[0064] Source electrode 300; Drain electrode 400. Detailed Implementation

[0065] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0066] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0067] The inventors of this application provide a solution to the technical problem of severe gate leakage in normally off devices.

[0068] The inventors attempted to first form insulating layers such as SiO2 and SiN on the AlGaN barrier layer, and then directly grow p-GaN on top of it. However, the crystal quality and electrical properties of the p-GaN were relatively poor. This is mainly because insulating layers such as SiO2 and SiN are amorphous materials, making it difficult to grow high-quality p-GaN on them. Therefore, it is difficult to form crystal-quality p-GaN using traditional techniques.

[0069] Please see Figure 1 In the first embodiment of this application, the inventors provide a semiconductor device 10 with a high threshold voltage. The semiconductor device 10 can be configured as a high electron mobility transistor. The p-cap layer in the semiconductor device 10 has higher crystal quality.

[0070] The semiconductor device 10 includes a stacked structure 100 and a gate structure 200.

[0071] The stacked structure 100 includes at least a channel layer 104 and a first barrier layer 105. In one embodiment, the stacked structure 100 may include a substrate 101, an insertion layer 102, a buffer layer 103, a channel layer 104, and a first barrier layer 105 stacked sequentially from bottom to top. The substrate 101 may be a silicon substrate. In another embodiment, the stacked structure 100 may include a substrate 101, a channel layer 104, and a first barrier layer 105 stacked sequentially from bottom to top. The substrate 101 may be a sapphire substrate, a GaN substrate, or a SiC substrate. The substrate 101 can be removed after the semiconductor device is fabricated.

[0072] The buffer layer 103 can be a single layer or multiple layers, and can be a GaN buffer layer, an AlGaN buffer layer, or a carbon-doped GaN buffer layer. In one embodiment, the buffer layer 103 can be a single layer or multiple layers, such as multiple AlGaN layers, in which the Al concentration gradually changes.

[0073] Additionally, the stacked structure 100 may further include a pad layer disposed between the channel layer 104 and the first barrier layer 105 to improve channel quality. The stacked structure 100 may also include a gallium nitride cap layer of approximately 2 nm disposed above the first barrier layer 105 to ensure the quality of the barrier layer 105. Furthermore, the stacked structure 100 may include other structural layers for improving film performance.

[0074] The gate structure 200 includes a high-resistivity nitride epitaxial layer 201 and a p-cap layer 202 stacked together, wherein the projected length of the p-cap layer 202 in the stacking direction of the stacked structure 100 is greater than the projected length of the high-resistivity nitride epitaxial layer 201 in the stacking direction of the stacked structure 100.

[0075] The gate structure 200 further includes a first gate insulating layer 203. The first gate insulating layer 203 is disposed on the surface of the first barrier layer 105 away from the channel layer 104, and the thickness of the first gate insulating layer 203 is less than the thickness of the high-resistivity nitride epitaxial layer 201.

[0076] Specifically, for example, the p-cap layer 202 encloses the high-resistivity nitride epitaxial layer 201 exposed outside the first gate insulating layer 203. When the high-resistivity nitride epitaxial layer 201 and the p-cap layer 202 are projected onto the stacking direction of the stacked structure 100, the projected length of the p-cap layer 202 is greater than the projected length of the high-resistivity nitride epitaxial layer 201. Furthermore, the positions where the projected length of the p-cap layer 202 is greater than the projected length of the high-resistivity nitride epitaxial layer 201 are located on the left and right sides of the high-resistivity nitride epitaxial layer 201, respectively. Specifically, the region where the p-cap layer 202 is longer than the high-resistivity nitride epitaxial layer 201 can be set to a longer left side, a longer right side, or the length of the left side being equal to the length of the right side; there is no specific limitation here. Specifically, the positional adjustment between the p-cap layer 202 and the high-resistivity nitride epitaxial layer 201 can be achieved by controlling experimental parameters during the growth process.

[0077] The semiconductor device 10 further includes a source electrode 300 and a drain electrode 400, which are disposed at intervals on the channel layer 104.

[0078] A gate structure 200 is formed between the source electrode 300 and the drain electrode 400 and disposed on the first barrier layer 105. The gate electrode 205 is disposed on the surface of the p-cap layer 202 away from the high-resistivity nitride epitaxial layer 201.

[0079] The semiconductor device 10 provided in this embodiment has a high threshold voltage, which can alleviate gate leakage current, expand the gate voltage operating range, and improve device reliability. Specifically, the high-resistivity nitride epitaxial layer 201 in the gate structure 200 can serve as a nucleation layer for the p-cap layer 202, thereby improving the crystal quality of the p-cap layer 202. The high-resistivity nitride epitaxial layer 201 can prevent Mg diffusion and channel degradation. The high-resistivity nitride epitaxial layer 201 can effectively reduce the leakage current of the gate electrode 205. Therefore, this embodiment reduces gate leakage current by setting a special gate structure 200, enabling the device to have a larger gate voltage operating range and greatly improving device reliability.

[0080] Please see Figure 1 In the first embodiment of this application, the gate structure 200 has: a first gate stack 210 and a second gate stack 220.

[0081] The first gate stack 210 comprises, from top to bottom, the p-cap layer 202, the high-resistivity nitride epitaxial layer 201, the first barrier layer 105, and the channel layer 104 forming a gate stack; the p-cap layer 202 and the first barrier layer 105 in the first gate stack 210 are separated by the high-resistivity nitride epitaxial layer 201, the p-cap layer 202 cannot deplete the two-dimensional electron gas at the interface between the first barrier layer 105 and the channel layer 104, and the first gate stack 210 has a two-dimensional electron gas when the gate voltage is 0V.

[0082] The second gate stack 220 includes a gate stack formed from the p-cap layer 202, the first gate insulating layer 203, the first barrier layer 105, and the channel layer 104 from top to bottom; the p-cap layer 202 in the second gate stack 220 can deplete the two-dimensional electron gas at the interface between the first barrier layer 105 and the channel layer 104, and the two-dimensional electron gas in the second gate stack 220 is depleted when the gate voltage is 0V.

[0083] In this embodiment, when no bias voltage is applied to the gate electrode 205, there is a high-resistivity nitride epitaxial layer 201 between the p-cap layer 202 and the first barrier layer 105 in the first gate stack 210 portion. Since the p-cap layer 202 and the first barrier layer 105 are separated by the high-resistivity nitride epitaxial layer 201, the two-dimensional electron gas in the projection region at the interface of the channel layer 104 / the first barrier layer 105 will not be depleted by the p-cap layer 202. Therefore, the p-cap layer 202 cannot deplete the two-dimensional electron gas at the interface of the first barrier layer 105 / the channel layer 104, so that the two-dimensional electron gas in the first gate stack 210 portion at the interface of the channel layer 104 / the first barrier layer 105 is continuous.

[0084] When no bias voltage is applied to the gate electrode 205, the second gate stack 220 portion will have its two-dimensional electron gas in the projection region at the interface of the channel layer 104 / first barrier layer 105 depleted by the p-cap layer 202 due to the presence of only the first gate insulating layer 203 between the p-cap layer 202 and the first barrier layer 105, resulting in the two-dimensional electron gas in the second gate stack 220 portion at the interface of the channel layer 104 / first barrier layer 105 being discontinuous.

[0085] When a bias voltage greater than a threshold voltage is applied to the gate electrode 205, the two-dimensional electron gas on the second gate stack 220 portion at the interface of the channel layer 104 / the first barrier layer 105 is restored, such that the two-dimensional electron gas on the interface of the channel layer 104 / the first barrier layer 105 forms a continuous whole between the source electrode 300 and the drain electrode 400.

[0086] Thus, by controlling the bias voltage provided by the gate electrode 205, it is possible to control whether the two-dimensional electron gas is a continuous whole between the source electrode 300 and the drain electrode 400, thereby controlling whether the semiconductor device 10 is turned on by controlling the voltage applied to the gate electrode 205.

[0087] In this embodiment, by adding the high-resistivity nitride epitaxial layer 201 to the gate structure 200, the gate structure 200 includes the first gate stack 210 and the second gate stack 220. Furthermore, when no bias voltage is applied to the gate electrode 205, the two-dimensional electron gas at the interface of the channel layer 104 / first barrier layer 105 of the first gate stack 210 is continuous; the two-dimensional electron gas at the interface of the channel layer 104 / first barrier layer 105 of the second gate stack 220 is discontinuous. The high-resistivity nitride epitaxial layer 201, disposed between the first barrier layer 105 and the p-cap layer 202, increases the on-resistance of the PN junction formed by the first barrier layer 105 and the p-cap layer 202. This increased on-resistance effectively reduces the leakage current of the gate electrode 205 after a bias voltage is applied to it.

[0088] Please see Figure 2 , Figure 2 The first embodiment provided in this application is related to Figure 1 The semiconductor device 10 has a different structure from the high-resistivity nitride epitaxial layer 201 described in the previous section. Figure 1 and Figure 2 The different structures of the high-resistivity nitride epitaxial layer 201 described herein are two unavoidable forms during the growth process, and are explicitly illustrated here. It can be understood that the high-resistivity nitride epitaxial layer 201 structures described in the second, third, fourth, and fifth embodiments below can also be different. Figure 2 The structure shown.

[0089] Please see Figure 3 In the second embodiment of this application, the p-cap layer 202 includes a first cap layer 212 with a high doping concentration and a second cap layer 222 with a low doping concentration.

[0090] The second cap layer 222 encloses the first cap layer 212. The first cap layer 212 is in contact with the high-resistivity nitride epitaxial layer 201. The second cap layer 222 is located away from the high-resistivity nitride epitaxial layer 201.

[0091] In this embodiment, the p-cap layer 202 described in the first embodiment is replaced with a p-cap layer containing a high doping concentration. +-GaN (first cap layer 212) and low doping concentration p - -GaN (the second cap layer 222) consists of two parts, and relative to p + -GaN, p - -GaN is closer to the gate electrode 205. Among them, the high doping concentration of p... + -GaN doping concentration can range from 10 18 -10 22 cm -3 low doping concentration p - -GaN doping concentration can range from 10 16 -10 20 cm -3 For example: p with high doping concentration + -GaN doping concentration is 5×10 19 cm -3 low doping concentration p - -GaN doping concentration 5×10 17 cm -3 In this embodiment, p - -GaN (the second cap layer 222) has a relatively low doping concentration, and when depleted, its internal and external electric fields are relatively small, similar to a field plate structure, which can effectively reduce the internal peak electric field.

[0092] Please see Figure 4 In the third embodiment of this application, the semiconductor device 10 further includes a second barrier layer 106.

[0093] The second barrier layer 106 comprises two parts. A first part of the second barrier layer 106 is formed between the first barrier layer 105 and the high-resistivity nitride epitaxial layer 201. A second part of the second barrier layer 106 is formed on the surface of the first gate insulating layer 203 away from the first barrier layer 105. Furthermore, a portion of the surface of the p-cap layer 202 covers the second barrier layer 106.

[0094] In this embodiment, after fabricating the stacked structure 100 and the first gate insulating layer 203, the first gate insulating layer 203 (and the passivation layer) is etched away at a future gate electrode location to expose the first barrier layer 105, and then a second barrier layer 106 of a certain thickness is grown. In the region where the first barrier layer 105 is exposed (without the first gate insulating layer 203 covering it), since the crystal structure of the second barrier layer 106 is similar to that of the first barrier layer 105, single-crystal growth can be achieved in this region, which increases the thickness of the barrier layer and makes the underlying 2DEG have a higher surface charge density. In the region where the first gate insulating layer 203 is retained, since the first gate insulating layer 203 (such as SiN) has a different crystal structure from the second barrier layer 106 (such as AlGaN) or is even amorphous, single-crystal growth of the second barrier layer 106 cannot be achieved there, or it can only be grown as polycrystalline or amorphous. Therefore, in this embodiment, setting the second barrier layer 106 can improve the 2DEG performance of the opening region, while also increasing the on-resistance of the PN junction and reducing leakage current.

[0095] Please see Figure 5 In the fourth embodiment of this application, the semiconductor device 10 further includes a second gate insulating layer 204.

[0096] The second gate insulating layer 204 is disposed on the surface of the first gate insulating layer 203 away from the first barrier layer 105. The thickness of the second gate insulating layer 204 is less than the thickness of the p-cap layer 202, and a portion of the p-cap layer 202 covers the second gate insulating layer 204. It is understood that in other embodiments, a third gate insulating layer or more insulating layer structures may be included to form a multilayer field plate structure.

[0097] In this embodiment, a thick second gate insulating layer 204 is formed on top of the first gate insulating layer 203 in the first embodiment. The presence of the second gate insulating layer 204 results in a larger distance between the p-cap layer 202 located thereon and the underlying two-dimensional electron gas channel. This structure can improve the electric field distribution and avoid the p-cap layer 202 edge ( Figure 5 (The electric field strength at the point indicated by the middle arrow) is too large, so as to avoid electric field spikes at the edge of the p-cap layer 202 and make the electric field distribution more uniform and smooth.

[0098] In a fourth embodiment of this application, the gate structure 200 further includes a third gate stack 230.

[0099] The third gate stack 230 comprises, from top to bottom, the p-cap layer 202, the second gate insulating layer 204, the first gate insulating layer 203, the first barrier layer 105, and the channel layer 104 forming a gate stack. The p-cap layer 202 in the third gate stack 230 cannot deplete the two-dimensional electron gas at the interface between the first barrier layer 105 and the channel layer 104, and the third gate stack 230 contains a two-dimensional electron gas when the gate voltage is 0V.

[0100] In this embodiment, the gate structure 200 further includes the third gate stack 230. The third gate stack 230 expands the coverage area of ​​the p-cap layer 202, improves the electric field distribution, and avoids excessive electric field intensity at the edge of the p-cap layer 202. In other words, the arrangement of the third gate stack 230 minimizes the occurrence of electric field spikes, resulting in a more uniform and smooth electric field distribution.

[0101] Please see Figure 6 This application may also include a fifth embodiment, in which the p-cap layer 202 is further configured to include a first cap layer 212 with a high doping concentration and a second cap layer 222 with a low doping concentration, in addition to the structure of the second gate insulating layer 204 in the fourth embodiment. In this embodiment, the gate structure 200 also has a fourth gate stack structure 240. The fourth gate stack 240 in this embodiment is similar in structure and function to the third gate stack 230 in the fourth embodiment.

[0102] In this embodiment, the third gate stack 230 includes, from top to bottom, the p-cap layer 202 (a second cap layer 222 with low doping concentration), the p-cap layer 202 (a first cap layer 212 with high doping concentration), the second gate insulating layer 204, the first gate insulating layer 203, the first barrier layer 105, and the channel layer 104. The fourth gate stack 240 includes, from top to bottom, the p-cap layer 202 (a second cap layer 222 with low doping concentration), the second gate insulating layer 204, the first gate insulating layer 203, the first barrier layer 105, and the channel layer 104.

[0103] In the third gate stack 230 and the fourth gate stack 240, the p-cap layer 202 cannot deplete the two-dimensional electron gas at the interface between the first barrier layer 105 and the channel layer 104, and the third gate stack 230 has a two-dimensional electron gas when the gate voltage is 0V.

[0104] In this embodiment, the gate structure 200 further includes the third gate stack 230 and the fourth gate stack 240. The third gate stack 230 and the fourth gate stack 240 expand the coverage area of ​​the p-cap layer 202, improve the electric field distribution, and prevent excessive electric field intensity at the edge of the p-cap layer 202. In other words, the arrangement of the third gate stack 230 and the fourth gate stack 240 minimizes the occurrence of electric field spikes, resulting in a more uniform and smooth electric field distribution.

[0105] In the semiconductor device 10 mentioned above in this application, the optional materials and thickness ranges of each film layer can be determined with reference to the following description:

[0106] The substrate 101 can be a silicon substrate, a SiC substrate, a sapphire substrate, or a GaN substrate.

[0107] The insertion layer 102, the buffer layer 103, the channel layer 104, the first barrier layer 105, and the second barrier layer 106 can be prepared using metal-organic chemical vapor deposition or molecular beam epitaxy.

[0108] The insertion layer 102 can be made of AlN material. The thickness of the insertion layer 102 can be 0.05um-0.35um. In one embodiment, the thickness of the insertion layer 102 is set to 0.15um; in another embodiment, the thickness of the insertion layer 102 is set to 0.2um; in yet another embodiment, the thickness of the insertion layer 102 is set to 0.25um.

[0109] The buffer layer 103 can be configured as a GaN buffer layer, an AlGaN buffer layer, or a C-doped gallium nitride buffer layer. In one embodiment, the buffer layer 103 can be one or more layers, such as one or more AlGaN layers. The thickness of the buffer layer 103 can be 0.5µm-4.0µm. For example, the thickness of the buffer layer 103 can be 0.1µm, 0.2µm, 0.25µm, or 4.0µm.

[0110] The channel layer 104 can be GaN. The thickness of the channel layer 104 can be 1.0um-5.0um. In one embodiment, the thickness of the channel layer 104 can be 1.5um, 2.0um, 2.5um, or 3um.

[0111] The first barrier layer 105 and the second barrier layer 106 can be AlGaN, AlInN, or AlInGaN. The thickness of the first barrier layer 105 can be set to 5nm-40nm. For example, the thickness of the first barrier layer 105 can be 10nm, 15nm, 25nm, 30nm, or 35nm. The thickness of the second barrier layer 106 can be set to 0.5nm-25nm. For example, the thickness of the second barrier layer 106 can be set to 1nm, 6nm, 15nm, 18nm, or 20nm.

[0112] In one embodiment, the high-resistivity nitride epitaxial layer 201 can be configured as an unintentionally doped nitride, a carbon-doped nitride, or an iron-doped nitride. Specifically, the high-resistivity nitride epitaxial layer 201 can be unintentionally doped GaN, unintentionally doped AlN, unintentionally doped AlGaN, or other unintentionally doped nitrides. The high-resistivity nitride epitaxial layer 201 can also be carbon-doped GaN, carbon-doped AlN, carbon-doped AlGaN, or other carbon-doped nitrides. The high-resistivity nitride epitaxial layer 201 can also be iron-doped GaN, iron-doped AlN, iron-doped AlGaN, or other iron-doped nitrides.

[0113] In one embodiment, the thickness of the high-resistivity nitride epitaxial layer 201 is greater than 20 nm. For example, the thickness of the high-resistivity nitride epitaxial layer 201 can be 22 nm, 40 nm, 50 nm, 70 nm, 100 nm, or even thicker.

[0114] The p-cap layer 202 can be p-GaN, p-AlGaN, p-InGaN, p-AlInGaN, or other p-type materials. Generally, the p-cap layer 202 can be formed by annealing GaN with Mg doping. The thickness of the p-cap layer 202 can be 0.1µm-0.6µm. In one embodiment, the thickness of the p-cap layer 202 is set to 0.2µm; in another embodiment, the thickness of the p-cap layer 202 is set to 0.25µm; and in yet another embodiment, the thickness of the p-cap layer 202 is set to 0.5µm.

[0115] A gate electrode 205 is also provided on the p-cap layer 202, which can be an ohmic contact or a Schottky contact.

[0116] In another embodiment, the insertion layer 102, the buffer layer 103, the channel layer 104, the first barrier layer 105, and the second barrier layer 106 can be binary arsenides and nitrides such as GaAs, InP, AlN, InN, and GaN, or ternary arsenides and nitrides such as InGaAs, AlGaAs, AlGaN, or InGaN, or even quaternary arsenides and nitrides such as InGaAsP and AlInGaN.

[0117] Please see Figure 7 and Figure 8 This application provides a method for fabricating the semiconductor device 10 described in the first embodiment, comprising the following steps:

[0118] S10, an insertion layer 102, a buffer layer 103, a channel layer 104 and a first barrier layer 105 are sequentially prepared on the first surface of the substrate 101 to form a stacked structure 100.

[0119] S20, a first gate insulating layer 203 is formed on the first barrier layer 105, and the first gate insulating layer 203 is etched to form a first groove exposing the first barrier layer 105. The material of the first barrier layer 105 is a nitride semiconductor.

[0120] S30, using the nitride semiconductor exposed in the first groove as a nucleation layer, a high-resistivity nitride epitaxial layer 201 is selectively grown in the first groove, the thickness of the high-resistivity nitride epitaxial layer 201 being greater than the thickness of the first gate insulating layer 203.

[0121] S40, using the high-resistivity nitride epitaxial layer 201 as the nucleation layer, a p-cap layer 202 is laterally epitaxially grown, wherein the projected length of the p-cap layer 202 in the stacked structure 100 is greater than the projected length of the high-resistivity nitride epitaxial layer 201 in the stacked structure 100.

[0122] After S40, the preparation method may further include:

[0123] The first gate insulating layer 203 and the first barrier layer 105 are etched, and a source electrode 300 and a drain electrode 400 are deposited respectively. The source electrode 300 and the drain electrode 400 are disposed on the channel layer 104 at intervals.

[0124] A gate electrode 205 is further deposited on the p-cap layer 202.

[0125] In this embodiment, the core of the fabrication method lies in the steps of "selectively growing a high-resistivity nitride epitaxial layer 201 in the first groove using the nitride semiconductor exposed in the first groove as the nucleation layer" and "using the high-resistivity nitride epitaxial layer 201 as the nucleation layer to laterally grow a p-cap layer 202." Selective epitaxial growth can effectively prevent dislocations from extending upwards. In this embodiment, selective epitaxy / lateral epitaxy is used, with a high-quality nitride crystal in the gate region (the first barrier layer 105) as the nucleation layer, selectively growing a nitride epitaxial layer (the high-resistivity nitride epitaxial layer 201), and then forming the epitaxial layer (the p-cap layer 202) directly on the first gate insulating layer 203 through lateral epitaxy. This method can obtain a p-cap layer 202 (such as p-GaN) with very good crystal quality on the first gate insulating layer 203.

[0126] During this lateral epitaxy process, by controlling the growth morphology of the epitaxy, no nitride epitaxial layer (the p-cap layer 202) will grow in other regions except on the insulating layer in the gate region and its adjacent regions.

[0127] Another key feature of this preparation method is that, before growing the p-cap layer 202, a high-resistivity nitride epitaxial layer (the high-resistivity nitride epitaxial layer 201) is first epitaxially grown as a gate insulating layer. This high-resistivity epitaxial layer (the high-resistivity nitride epitaxial layer 201) can be achieved in various ways (e.g., doping with elements such as C and Fe during epitaxy).

[0128] In one embodiment, the semiconductor device 10 described in the second embodiment is provided with fabrication steps different from those in the first embodiment:

[0129] The p-cap layer 202 includes: a first cap layer 212 with a high doping concentration and a second cap layer 222 with a low doping concentration. The step of further depositing the p-cap layer 202 in S40 includes:

[0130] S41, using the high-resistivity nitride epitaxial layer 201 as the nucleation layer, a first cap layer 212 with a high doping concentration is deposited;

[0131] S42, a second cap layer 222 is deposited outside the first cap layer 212, the second cap layer 222 encapsulating the first cap layer 212.

[0132] In this embodiment, the p-cap layer 202 in the first embodiment is replaced with p-cap layer containing a high doping concentration. + -GaN (first cap layer 212) and low doping concentration p - -GaN (the second cap layer 222) consists of two parts, and relative to p + -GaN, p --GaN is closer to the gate electrode 205. p - -GaN (the second cap layer 222) has a relatively low doping concentration, and when depleted, its internal and external electric fields are relatively small, similar to a field plate structure, which can effectively reduce the internal peak electric field.

[0133] In one embodiment, a different fabrication step from the first embodiment is provided for the semiconductor device 10 in the third embodiment: the semiconductor device 10 further includes a second barrier layer 106, and step S30 includes:

[0134] S31, deposit the second barrier layer 106 into the first groove and the first gate insulating layer 203, wherein the material of the second barrier layer 106 is a nitride semiconductor.

[0135] S32, depositing the high-resistivity nitride epitaxial layer 201 into the first groove using the nitride semiconductor exposed in the first groove as the nucleation layer, wherein the thickness of the high-resistivity nitride epitaxial layer 201 is greater than the thickness of the first gate insulating layer 203.

[0136] In this embodiment, a thicker second barrier layer 106 is added. Since the crystal structure of the second barrier layer 106 is similar to that of the first barrier layer 105, single-crystal growth can be achieved in this region, resulting in a higher surface charge density for the underlying 2DEG. In the region where the first gate insulating layer 203 is retained, since the first gate insulating layer 203 (e.g., SiN) has a different crystal structure than the second barrier layer 106 (e.g., AlGaN), or is even amorphous, single-crystal growth of the second barrier layer 106 cannot be achieved there, or it can only be grown as polycrystalline or amorphous. Therefore, in this embodiment, a portion of the surface of the p-cap layer 202 is covered by the second barrier layer 106. The main purpose of setting the second barrier layer 106 is to improve the 2DEG performance in the opening region.

[0137] Please see Figures 9 to 11 This application provides a method for fabricating the semiconductor device 10 described in the fourth embodiment, comprising:

[0138] S101, an insertion layer 102, a buffer layer 103, a channel layer 104 and a first barrier layer 105 are sequentially prepared on the first surface of the substrate 101 to form a stacked structure 100.

[0139] S102, a first gate insulating layer 203 and a second gate insulating layer 204 are formed on the first barrier layer 105, and the first gate insulating layer 203 and the second gate insulating layer 204 are etched for the first time to form a first groove exposing the first barrier layer 105. The material of the first barrier layer 105 is a nitride semiconductor.

[0140] S103, the second gate insulating layer 204 is etched a second time to form a second groove that exposes the first gate insulating layer 203;

[0141] S104, using the nitride semiconductor exposed in the first groove as a nucleation layer, a high-resistivity nitride epitaxial layer 201 is selectively grown in the first groove, the thickness of the high-resistivity nitride epitaxial layer 201 being greater than the thickness of the first gate insulating layer 203.

[0142] S105, using the high-resistivity nitride epitaxial layer 201 as the nucleation layer, a p-cap layer 202 is laterally epitaxially grown into the second groove, and a portion of the p-cap layer 202 covers the second gate insulating layer 204, wherein the projected length of the p-cap layer 202 in the stacked structure 100 is greater than the projected length of the high-resistivity nitride epitaxial layer 201 in the stacked structure 100.

[0143] In this embodiment, the core of the fabrication method lies in the steps of "selectively growing a high-resistivity nitride epitaxial layer 201 in the first groove using the nitride semiconductor exposed in the first groove as the nucleation layer" and "using the high-resistivity nitride epitaxial layer 201 as the nucleation layer to laterally grow a p-cap layer 202 in the second groove." Selective epitaxial growth can effectively prevent dislocations from extending upwards. In this embodiment, selective epitaxy / lateral epitaxy is used, with a high-quality nitride crystal in the gate region (the first barrier layer 105) as the nucleation layer, selectively growing a nitride epitaxial layer (the high-resistivity nitride epitaxial layer 201), and then directly forming the epitaxial layer (the p-cap layer 202) on the first gate insulating layer 203 through lateral epitaxy. This method can obtain a p-cap layer 202 (such as p-GaN) with very good crystal quality on the first gate insulating layer 203.

[0144] In this fabrication method, a thicker second gate insulating layer 204 is formed based on the fabrication method of the first embodiment. The presence of the second gate insulating layer 204 results in a larger distance between the p-cap layer 202 located thereon and the two-dimensional electron gas channel below. This structure can improve the electric field distribution and avoid the p-cap layer 202 edge ( Figure 5 (The electric field strength at the point indicated by the middle arrow) is too large, so as to avoid electric field spikes at the edge of the p-cap layer 202 and make the electric field distribution more uniform and smooth.

[0145] Please see Figure 12 , Figure 12 This is a performance comparison diagram between the semiconductor device 10 provided in the embodiments of this application and a traditional p-type gate structure semiconductor device.

[0146] Figure 12This diagram illustrates a comparison of gate leakage currents for a conventional p-type gate semiconductor device, a semiconductor device according to the first embodiment of this application, and a semiconductor device according to the second embodiment of this application. When the same gate voltage is applied to all three, the gate leakage currents of the semiconductor devices in the first and second embodiments of this application are significantly lower than those of the conventional semiconductor device. Furthermore, the gate breakdown voltages of the semiconductor devices in these two embodiments are much higher than those of the conventional solutions.

[0147] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application. It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0148] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: A stacked structure, the stacked structure comprising at least a channel layer and a first barrier layer; A gate structure comprising a high-resistivity nitride epitaxial layer and a p-cap layer stacked thereon, wherein the projection length of the p-cap layer in the stacking direction of the stacked structure is greater than the projection length of the high-resistivity nitride epitaxial layer in the stacked structure; and The gate structure further includes a first gate insulating layer disposed on the surface of the first barrier layer away from the channel layer, and the thickness of the first gate insulating layer is less than the thickness of the high-resistivity nitride epitaxial layer.

2. The semiconductor device according to claim 1, characterized in that, The gate structure has: a first gate stack and a second gate stack; The first gate stack comprises, from top to bottom, the p-cap layer, the high-resistivity nitride epitaxial layer, the first barrier layer, and the channel layer forming a gate stack; the p-cap layer and the first barrier layer in the first gate stack are separated by the high-resistivity nitride epitaxial layer, the p-cap layer cannot deplete the two-dimensional electron gas at the interface between the first barrier layer and the channel layer, and the first gate stack has a two-dimensional electron gas when the gate voltage is 0V; The second gate stack comprises, from top to bottom, the p-cap layer, the first gate insulating layer, the first barrier layer, and the channel layer forming a gate stack; the p-cap layer in the second gate stack can deplete the two-dimensional electron gas at the interface between the first barrier layer and the channel layer, and the two-dimensional electron gas in the second gate stack is depleted when the gate voltage is 0V.

3. The semiconductor device according to claim 2, characterized in that, The p-cap layer comprises: a first cap layer with a high doping concentration and a second cap layer with a low doping concentration; The second cap layer wraps around the first cap layer; The first cap layer is in contact with the high-resistivity nitride epitaxial layer; The second cap layer is located away from the high-resistivity nitride epitaxial layer.

4. The semiconductor device according to claim 2, characterized in that, The semiconductor device further includes: The second barrier layer comprises two parts; The second barrier layer of the first part is formed between the first barrier layer and the high-resistivity nitride epitaxial layer; The second barrier layer of the second portion is formed on the surface of the first gate insulating layer away from the first barrier layer; and a portion of the surface of the p-cap layer covers the second barrier layer.

5. The semiconductor device according to claim 2, characterized in that, The semiconductor device further includes: A second gate insulating layer is disposed on the surface of the first gate insulating layer away from the first barrier layer. The thickness of the second gate insulating layer is less than the thickness of the p-cap layer, and a portion of the p-cap layer covers the second gate insulating layer.

6. The semiconductor device according to claim 5, characterized in that, The gate structure also includes: a third gate stack; The third gate stack comprises, from top to bottom, the p-cap layer, the second gate insulating layer, the first gate insulating layer, the first barrier layer, and the channel layer forming a gate stack; the p-cap layer in the third gate stack cannot deplete the two-dimensional electron gas at the interface between the first barrier layer and the channel layer, and the third gate stack has a two-dimensional electron gas when the gate voltage is 0V.

7. The semiconductor device according to any one of claims 1-6, characterized in that, The high-resistivity nitride epitaxial layer is an unintentionally doped nitride, a carbon-doped nitride, or an iron-doped nitride.

8. The semiconductor device according to claim 7, characterized in that, The thickness of the high-resistivity nitride epitaxial layer is greater than 20 nm.

9. A method for fabricating a semiconductor device, comprising: S10, a stacked structure including at least a channel layer and a first barrier layer is sequentially prepared on the first surface of the substrate; S20, a first gate insulating layer is formed on the first barrier layer, and the first gate insulating layer is etched to form a first groove exposing the first barrier layer, wherein the material of the first barrier layer is a nitride semiconductor. S30, using the nitride semiconductor exposed in the first groove as a nucleation layer, a high-resistivity nitride epitaxial layer is selectively grown in the first groove, the thickness of the high-resistivity nitride epitaxial layer being greater than the thickness of the first gate insulating layer; S40, using the high-resistivity nitride epitaxial layer as the nucleation layer, a p-cap layer is laterally epitaxially grown, wherein the projection length of the p-cap layer in the stacked structure is greater than the projection length of the high-resistivity nitride epitaxial layer in the stacked structure.

10. The preparation method according to claim 9, characterized in that, The p-cap layer comprises: a first cap layer with a high doping concentration and a second cap layer with a low doping concentration, and the step of further depositing the p-cap layer in S40 includes: S41, using the high-resistivity nitride epitaxial layer as the nucleation layer, a first cap layer with a high doping concentration is deposited; S42, deposit a second cap layer outside the first cap layer, the second cap layer enclosing the first cap layer.

11. The preparation method according to claim 9, characterized in that, The semiconductor device further includes a second barrier layer, and S30 includes: S31, deposit the second barrier layer into the first groove and the first gate insulating layer, wherein the material of the second barrier layer is a nitride semiconductor; S32, using the nitride semiconductor exposed in the first groove as a nucleation layer, deposit the high-resistivity nitride epitaxial layer into the first groove, wherein the thickness of the high-resistivity nitride epitaxial layer is greater than the thickness of the first gate insulating layer.

12. A method for fabricating a semiconductor device, comprising: S101, a stacked structure including at least a channel layer and a first barrier layer is sequentially prepared on the first surface of the substrate; S102, a first gate insulating layer and a second gate insulating layer are formed on the first barrier layer and the first gate insulating layer and the second gate insulating layer are etched for the first time to form a first groove exposing the first barrier layer, wherein the material of the first barrier layer is a nitride semiconductor. S103, the second gate insulating layer is etched a second time to form a second groove that exposes the first gate insulating layer; S104, using the nitride semiconductor exposed in the first groove as a nucleation layer, a high-resistivity nitride epitaxial layer is selectively grown in the first groove, the thickness of the high-resistivity nitride epitaxial layer being greater than the thickness of the first gate insulating layer. S105, using the high-resistivity nitride epitaxial layer as the nucleation layer, a p-cap layer is laterally epitaxially grown into the second groove, a portion of the p-cap layer covering the second gate insulating layer, wherein the projection length of the p-cap layer in the stacked structure is greater than the projection length of the high-resistivity nitride epitaxial layer in the stacked structure.

Images