A method for manufacturing a solar cell

Abstract

The application relates to a preparation method of a solar cell, which comprises the following steps: S1, providing an N-type silicon substrate; S2, depositing a tunneling passivation structure on a first surface of the N-type silicon substrate, and depositing a mask layer on the tunneling passivation structure; S3, cleaning a second surface of the N-type silicon substrate; S4, performing boron diffusion treatment on the cleaned second surface of the N-type silicon substrate and annealing treatment on the tunneling passivation structure in the same environment, so that a first emitter layer is formed on the second surface of the N-type silicon substrate and the tunneling passivation structure is crystallized; S5, performing laser patterning treatment on the first emitter layer to form a second emitter region; S6, depositing a passivation anti-reflection film; and S7, forming a first electrode and a second electrode. The solar cell obtained by the method has a selective emitter structure, a large junction depth of a metal contact area, and meets the metallization requirement; and a shallow junction depth of a non-metal contact area, and the optical response is improved.

Description

[0001] This application is a divisional application of Chinese invention patent application filed on February 7, 2023, with application number 202310072596.5 and invention title "A Solar Cell". Technical Field

[0002] This application relates to the field of solar cells. Background Technology

[0003] TOPCon solar cells (Tunnel Oxide Passivated Contact) are a type of solar cell that uses an ultrathin oxide layer as the passivation layer. N-type TOPCon cells entered mass production in 2022, with existing and under-construction capacity exceeding 40GW, and are gradually replacing p-type cells to dominate the market. Currently, N-type TOPCon cells typically use boron doping to form the emitter structure. The emitter usually employs a uniform junction, but its metal contact recombination, short-wavelength response, and recombination rate are often not optimal. To achieve lower metal contact recombination, the junction depth of boron doping generally needs to be above 0.7μm. However, boron atoms are difficult to dope, requiring temperatures above 970 degrees Celsius and time above 3 hours to reach a junction depth of 0.7μm or more. This results in higher power consumption and equipment losses during cell manufacturing, and the long high-temperature and long-time requirements also place higher demands on silicon wafer quality, all of which significantly increase the levelized cost of electricity (LCOE) of solar cells. The electrochemical capacitance-voltage (ECV) doping concentration-depth curve (ECV doping curve) of boron emitters manufactured using this method is shown below. Figure 3 As shown ( Figure 3 The conventional boron emitter is represented by its ECV doping curve. Further optimization of the N-type TOPCon cell structure is needed in this field. Summary of the Invention

[0004] This application provides a solar cell, comprising:

[0005] An N-type silicon substrate having a first surface and a second surface.

[0006] The tunneling passivation structure and the first passivation antireflection film formed on the first surface

[0007] A boron-doped emitter structure layer is formed on the second surface. The emitter structure layer includes a first emitter layer and a second emitter region, wherein the junction depth of the first emitter layer is smaller than the junction depth of the second emitter region, and the total boron doping amount of the first emitter layer is smaller than the total boron doping amount of the second emitter region.

[0008] The second passivation antireflection film formed on the emitter structure layer,

[0009] A first electrode, configured to make electrical contact with the second emitter region;

[0010] The second electrode is configured to make electrical contact with the tunneling passivation structure.

[0011] The solar cell of this application has a selective emitter structure with a large junction depth in the metal contact region to meet the metallization requirements; and a shallow junction depth in the non-metal contact region to improve optical response. At the same time, the total boron doping amount in the first emitter layer is less than that in the second emitter region. This cell structure can meet the photoelectric conversion performance of the solar cell while significantly shortening the high-temperature time of the boron diffusion process during fabrication, thereby reducing the manufacturing cost of the solar cell.

[0012] In one embodiment, the tunneling passivation structure includes a tunneling oxide layer and a passivation contact material layer, wherein the tunneling oxide layer is disposed between the N-type silicon substrate and the passivation contact material layer.

[0013] In one embodiment, the material constituting the passivation contact material layer is selected from one or more of doped amorphous silicon, doped polycrystalline silicon, and silicon carbide.

[0014] In one embodiment, the second electrode is configured to make electrical contact with the passivation contact material layer.

[0015] In one implementation, the junction depth of the first emitter layer is less than or equal to 0.7 μm.

[0016] In one embodiment, the junction depth of the second emitter region is greater than or equal to 0.8 μm.

[0017] In one embodiment, the highest boron doping concentration in the second emitter region is ≤2×10⁻⁶. 19 atm / cm 3 .

[0018] In one embodiment, the highest point in the ECV doping curve of the first emitter layer is located at a depth of 0.05-0.5 μm from the surface of the first emitter layer.

[0019] In one embodiment, within a depth of 0.05-0.7 μm from the surface of the first emitter layer in the ECV doping curve of the first emitter layer, the difference between the highest and lowest boron doping concentrations in the first emitter layer is greater than one order of magnitude.

[0020] In one embodiment, within a depth of 0.05-0.6 μm from the surface of the second emitter layer in the ECV doping curve of the second emitter layer, the difference between the highest and lowest boron doping concentrations in the second emitter region is less than one order of magnitude.

[0021] In one implementation, the sheet resistance of the first emitter layer is greater than the sheet resistance of the second emitter region.

[0022] In one embodiment, the sheet resistance of the first emitter layer is ≥150 ohm / sq, and the sheet resistance of the second emitter region is ≤150 ohm / sq.

[0023] In one embodiment, the width of the first electrode is smaller than the width of the second emitter region.

[0024] In one embodiment, the material of the passivation antireflection film is selected from one or more combinations of alumina, silicon oxide, silicon nitride, and silicon oxynitride.

[0025] This application provides the following implementation methods:

[0026] Item 1. A method for preparing a solar cell, comprising:

[0027] S1 provides an N-type silicon substrate;

[0028] S2 deposits a tunneling passivation structure on the first surface of the N-type silicon substrate, and deposits a mask layer on the tunneling passivation structure;

[0029] S3 cleans the second surface of the N-type silicon substrate;

[0030] S4 performs boron diffusion treatment on the second surface of the cleaned N-type silicon substrate and annealing treatment on the tunneling passivation structure under the same environment, so as to form a first emitter layer on the second surface of the N-type silicon substrate and crystallize the tunneling passivation structure.

[0031] S5 performs laser patterning on the first emitter layer to form the second emitter region;

[0032] S6 deposition passivation antireflection film, and

[0033] S7 forms a first electrode and a second electrode, the first electrode being configured to make electrical contact with the second emitter region, and the second electrode being configured to make electrical contact with the tunneling passivation structure.

[0034] Item 2. The preparation method according to Item 1, wherein the tunneling passivation structure includes a tunneling oxide layer and a passivation contact material layer, wherein the tunneling oxide layer is disposed between the N-type silicon substrate and the passivation contact material layer.

[0035] Item 3. The preparation method according to Item 2, wherein the material constituting the passivation contact material layer is selected from one or more of doped amorphous silicon, doped polycrystalline silicon, and silicon carbide.

[0036] Item 4. The preparation method according to Item 2 or 3, wherein the second electrode is configured to be in electrical contact with the passivated contact material layer.

[0037] Item 5. The preparation method according to Item 1, wherein the temperature of the same environment is 300-970°C, and the treatment time at 800-970°C is less than 3 hours.

[0038] Item 6. The preparation method according to Item 1, wherein the junction depth of the first emitter layer is less than the junction depth of the second emitter region.

[0039] Item 7. The preparation method according to Item 6, wherein the junction depth of the first emitter layer is less than or equal to 0.7 μm, and the junction depth of the second emitter region is greater than or equal to 0.8 μm.

[0040] Item 8. The preparation method according to Item 1, wherein the highest boron doping concentration of the first emitter layer is greater than the highest boron doping concentration of the second emitter region; and the total boron doping amount of the first emitter layer is less than the total boron doping amount of the second emitter region.

[0041] Item 9. The preparation method according to Item 1, wherein the highest point in the ECV doping curve of the first emitter layer is located at an internal position at a depth of 0.05-0.5 μm from the surface of the first emitter layer.

[0042] Item 10. According to the preparation method of Item 1, wherein, in the ECV doping curve of the first emitter layer, within a depth of 0.02-0.6 μm from the surface of the first emitter layer, the difference between the highest boron doping concentration and the lowest boron doping concentration in the first emitter layer is greater than one order of magnitude.

[0043] Item 11. According to the preparation method described in Item 1, wherein, in the ECV doping curve of the second emitter region, within a depth of 0.05-0.7 μm from the surface of the second emitter region, the difference between the highest boron doping concentration and the lowest boron doping concentration in the second emitter region is less than one order of magnitude.

[0044] Item 12. The preparation method according to Item 1, wherein the sheet resistance of the first emitter layer is ≥150 ohm / sq, and the sheet resistance of the second emitter region is ≤150 ohm / sq.

[0045] Item 13. The preparation method according to Item 1, wherein the width of the first electrode is smaller than the width of the second emitter region.

[0046] Item 14. The preparation method according to Item 1, wherein a cleaning step is performed before S6.

[0047] Item 15. The preparation method according to Item 1, wherein the material of the passivation antireflection film is selected from one or more combinations of alumina, silicon oxide, silicon nitride, and silicon oxynitride. Attached Figure Description

[0048] Figure 1 A schematic diagram of the structure of the solar cell disclosed herein is shown.

[0049] Figure 2 A flowchart of the method for preparing the solar cell disclosed herein is shown.

[0050] Figure 3 The ECV doping curves in the first emitter layer and the second emitter region of the solar cell of Example 1 are shown, as well as the ECV doping concentration-depth curve of a conventional boron emitter. Detailed Implementation

[0051] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. Through these descriptions, the features and advantages of the present application will become clearer and more apparent.

[0052] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments. Although various aspects of embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated otherwise.

[0053] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0054] like Figure 1 As shown, this application provides a solar cell, comprising:

[0055] An N-type silicon substrate 1 having a first surface and a second surface,

[0056] The tunneling passivation structure 2 and the first passivation antireflection film 6 are formed on the first surface.

[0057] A boron-doped emitter structure layer is formed on the second surface. The emitter structure layer includes a first emitter layer 3 and a second emitter region 4. The junction depth of the first emitter layer 3 is smaller than the junction depth of the second emitter region 4. The highest boron doping concentration of the first emitter layer is greater than the highest boron doping concentration of the second emitter region. The total boron doping amount of the first emitter layer is less than the total boron doping amount of the second emitter region.

[0058] The second passivation antireflection film 5 is formed on the emitter structure layer.

[0059] A first electrode 7 is configured to make electrical contact with the second emitter region 4;

[0060] The second electrode 8 is configured to make electrical contact with the tunneling passivation structure 2.

[0061] In this application, the front side refers to the side where sunlight enters, while the back side is the side opposite to the side where sunlight enters. Figure 1 In the N-type silicon substrate 1, the upper side is the front side (second surface), and the lower side is the back side (first surface).

[0062] The structure of this solar cell is described below in conjunction with its fabrication process. For example... Figure 2 As shown, this solar cell can be fabricated as follows:

[0063] S1 provides an N-type silicon substrate;

[0064] S2 deposits a tunneling passivation structure on the first surface of the N-type silicon substrate, and deposits a mask layer on the tunneling passivation structure;

[0065] S3 cleans the second surface of the N-type silicon substrate;

[0066] S4 performs boron diffusion treatment on the second surface of the cleaned N-type silicon substrate and annealing treatment on the tunneling passivation structure under the same environment, so as to form a first emitter layer on the second surface of the N-type silicon substrate and crystallize the tunneling passivation structure.

[0067] S5 performs laser patterning on the first emitter layer to form the second emitter region;

[0068] S6 deposition passivation antireflection film, and

[0069] S7 forms a first electrode and a second electrode, wherein the first electrode is configured to make electrical contact with the second emitter region and the second electrode is configured to make electrical contact with the tunneling passivation structure.

[0070] Before preparation, the N-type silicon substrate can be cleaned and polished to facilitate subsequent processes.

[0071] After that, as Figure 1As shown, a tunneling passivation structure 2 is deposited on the first surface (back side) of the N-type silicon substrate 1. This tunneling passivation structure can be any type of tunneling passivation structure that can be used in TOPCon cells, for example, it may include a tunneling oxide layer 21 and a passivation contact material layer 22, wherein the tunneling oxide layer 21 is disposed between the N-type silicon substrate 1 and the passivation contact material layer 22. In one embodiment, the material constituting the tunneling oxide layer can be silicon oxide or similar materials. In one embodiment, the material constituting the passivation contact material layer is selected from one or more of doped amorphous silicon, doped polycrystalline silicon, and silicon carbide (SiCx), such as a phosphorus-doped polycrystalline silicon layer, silicon carbide, etc.

[0072] Next, a cleaning step is performed on the second surface (front side) of the N-type silicon substrate to remove unwanted material layers, such as polysilicon layers, that are deposited around the front side. A texturing step can also be performed after cleaning to form a textured surface, thereby increasing the surface area, reducing surface reflectivity, and removing impurities.

[0073] Subsequently, in the same environment, the second surface of the cleaned N-type silicon substrate undergoes boron diffusion treatment and the tunneling passivation structure undergoes annealing treatment to form a first emitter layer and crystallize the tunneling passivation structure on the second surface of the N-type silicon substrate. Boron diffusion is performed on the second surface (front side) of the N-type silicon substrate 1 to form a p-type silicon layer, i.e., the first emitter layer 3. During the same treatment, in addition to the formation of the p-type silicon layer (first emitter layer 3) by boron diffusion on the second surface (front side) of the N-type silicon substrate, the pre-formed tunneling passivation structure 2 is also annealed simultaneously. This allows the material in the passivation contact material layer to crystallize and redistribute doping elements during the high-temperature boron diffusion process, thereby improving the passivation capability of the passivation contact structure. Therefore, there is no need for a separate annealing treatment of the tunneling passivation structure, avoiding the adverse effects of the high temperature of annealing on the silicon wafer and the layers formed thereon. In one embodiment, the boron source used for the boron diffusion treatment is BCl3, BBr3, etc. In this application, the boron diffusion treatment is performed at a low temperature and for a short time, resulting in a relatively shallow junction depth of the formed p-type silicon layer (first emitter layer). The junction depth of the first emitter layer 3 can be less than or equal to 0.7 μm, which improves optical response. In one embodiment, the ambient temperature is 300-970°C, and the treatment time at 800-970°C is less than 3 hours. In one embodiment, the sheet resistance of the first emitter layer is ≥150 ohm / sq.

[0074] In one embodiment, the junction depth of the first emitter layer 3 can be less than or equal to 0.7 μm, thereby improving the optical response. Figure 1 The junction depth h1 of the first emitter layer is shown, which is equivalent to the thickness of the first emitter layer, and refers to the distance from the surface to where the first emitter layer exists.

[0075] Next, the first emitter layer 3 is laser-patterned to form the second emitter region 4. The conditions for laser patterning are: using one or more wavelengths of laser, such as ultraviolet, green, or infrared, with a pulse width of nanosecond, picosecond, or femtosecond, and an average power of 5-200W; for example, a 532nm green nanosecond laser with a power of 30W can be used. Figure 1 As shown, laser patterning can advance boron doping to form a second emitter region with a different junction depth, doping concentration, and sheet resistance than the first emitter layer. In this application, the junction depth h1 of the first emitter layer is smaller than the junction depth h2 of the second emitter region. Figure 1 The junction depth h2 of the second emitter region is shown, which is equivalent to the thickness of the second emitter region and refers to the distance from the surface to where the second emitter is located. In one embodiment, the junction depth h2 of the second emitter region is greater than or equal to 0.8 μm. However, the junction depth h2 of the second emitter region generally does not exceed 5 μm. As described later, the second emitter region is in electrical contact with the first electrode 7, and the above junction depth h2 meets the metallization requirements. The first emitter layer 3 and the second emitter region 4 together constitute the emitter structure layer.

[0076] For the first emitter layer, the highest point in the ECV doping concentration-depth curve (ECV doping curve) is not on the silicon wafer surface, but rather at a depth of approximately 0.02-0.5 μm from the surface of the first emitter layer. Furthermore, the doping curve of the first emitter layer exhibits a large relative variation, with the doping concentration varying significantly within the 0.02-0.6 μm depth range, and the difference between the highest and lowest boron doping concentrations exceeding one order of magnitude; for example, the boron doping concentration in the first emitter layer is 2 × 10⁻⁶. 19 Up to 1×10 18 atm / cm 3 Or 3×10 19 Up to 5×10 17 atm / cm 3 The steep diffusion junction of the first emitter layer can be achieved using a shorter boron diffusion process time, reducing manufacturing costs;

[0077] For the second emitter region, the ECV doping concentration-depth curve (ECV doping curve) is flatter, and the doping concentration does not change much in the depth range of 0.05-0.7 μm. The difference between the highest and lowest boron doping concentrations is less than one order of magnitude; for example, the boron doping concentration in the second emitter region is 1×10⁻⁶. 19 -1×10 18 atm / cm 3 5×10 18 -5×10 19 atm / cm 3or 1×10 19 -1×10 20 atm / cm 3 Between. A more gently sloping doped junction in the second emitter region is more conducive to forming good metal contacts, reducing contact resistivity, and can also reduce the recombination current density in the metal region, thereby improving the photoelectric conversion efficiency of the solar cell.

[0078] In one embodiment, the sheet resistance of the first emitter layer is greater than the sheet resistance of the second emitter region. In another embodiment, the sheet resistance of the first emitter layer is ≥150 ohm / sq, and the sheet resistance of the second emitter region is ≤150 ohm / sq.

[0079] Next, the silicon wafer surface is cleaned. This cleaning step removes the mask layer on the back side of the tunneling passivation structure, as well as the oxide layer on the front side. The cleaning step can be performed using alkaline washing and / or acid washing. Alkaline washing can use potassium hydroxide solution, sodium hydroxide solution, etc., as detergents, while acid washing can use HF solution, HCl solution, etc., as detergents.

[0080] Next, passivation antireflection films are deposited on both sides of the silicon wafer. Various methods known in the art can be used to deposit the passivation antireflection films, and the material of the passivation antireflection films can be one or more combinations of commonly used passivation antireflection film materials such as alumina, silicon oxide, silicon nitride, and silicon oxynitride. The passivation antireflection films can be composed of a single layer of material or a multilayer structure composed of multiple layers of material. Figure 1 As shown, the second passivation antireflection film 5 is located on the front side, and the first passivation antireflection film 6 is located on the back side.

[0081] Next, the metal electrode portion is deposited. For example... Figure 1 As shown, the metal electrode portion includes a first electrode 7 and a second electrode 8. The first electrode 7 is located on the front side and is configured to make electrical contact with the second emitter region 4. The second electrode 8 is located on the back side and is configured to make electrical contact with the tunneling passivation structure 2, particularly the passivation contact material layer 22. The metal electrode can be deposited using conventional methods such as screen printing.

[0082] In one implementation, such as Figure 1 As shown, the width of the first electrode 7 is smaller than the width of the second emitter region 4. Figure 1 The width w1 of the first electrode 7 and the width w2 of the second emitter region 4 are shown, which are the edge spacings of the first electrode 7 and the second emitter region 4 in the x-direction. This configuration has the following advantages: the first electrode region can completely cover the second emitter region, heavy doping effectively reduces metal recombination under the first electrode region, reduces recombination current density, and increases the open-circuit voltage of the battery.

[0083] Example 1

[0084] The n-type silicon wafer is subjected to wet chemical cleaning to remove surface damage and impurities, and the surface is polished with an alkaline solution to form a surface with high flatness and a reflectivity greater than 30%, which is more suitable for achieving a better passivation effect of the back passivation contact structure.

[0085] A tunneling silicon oxide layer and a doped polysilicon layer are deposited on the back side of a silicon wafer using the PECVD method. The thickness of the tunneling silicon oxide layer is between 0.9-2 nm, and the thickness of the doped polysilicon layer is between 75-150 nm. Then, a silicon oxide mask with a thickness of 10-50 nm is further deposited on the outer layer.

[0086] The polysilicon layer on the front side is removed by wet chemical cleaning, and then alkaline texturing is performed on the front side to form a pyramid structure on the front side of the silicon wafer, while the back side retains its original structure under the protection of a mask.

[0087] A silicon wafer is placed inside a tubular diffusion furnace. BCl3 and oxygen are introduced at temperatures above 800°C, reacting to form boron atoms on the wafer surface. These atoms diffuse into the wafer, forming the first emitter and creating a boron-rich silicon oxide layer, i.e., borosilicate glass (BSG). The boron diffusion conditions are: BCl3 flow rate of 300 sccm, oxygen flow rate of 200 sccm, temperature of 850°C, and time of 15 min during the deposition step; followed by a temperature rise and junction push-off process at 930°C for 30 min. The first emitter sheet resistance is 150-250 ohm / sq, the junction depth is 0.5 μm, and the BSG thickness is 10-150 nm. Simultaneously, under the high temperature and time of boron diffusion, the doped polycrystalline silicon layer on the back side completes crystallization and redistribution of dopants, enhancing the passivation capability of the passivation contact structure.

[0088] Patterning of the borosilicate glass front side was performed using a long-pulse laser or a short-pulse laser with high overlap. The laser power was 30W, the spot width was 60-200μm, and the shape was circular, elliptical, or rectangular. After laser treatment, the sheet resistance decreased to below 150 ohm / sq, the diffusion depth of the second emitter junction increased to above 0.7μm, and the surface doping concentration decreased to 1×10⁻⁶. 19 cm -3 ;

[0089] Wet chemical cleaning is performed on the surface of the silicon wafer to remove the BSG layer on the front side, the laser damage layer, and the mask on the back side.

[0090] Aluminum oxide is deposited on the front side of the silicon wafer using ALD, with a thickness of 2-20nm; then, a combination of one or more of silicon oxynitride and silicon oxide with a thickness of 50-200nm is deposited on the front side using PECVD, thereby forming a second passivation antireflection film.

[0091] A combination of one or more of silicon oxynitride and silicon oxide with a thickness of 30-200nm is deposited on the back side of the silicon wafer by PECVD, thereby forming the first passivation antireflection film.

[0092] The back side uses screen printing to print the fine grid and main grid electrodes, while the front side uses screen printing to print the fine grid electrodes above the second emitter in the laser processing area. The width of the front electrode is less than 50 μm. After high-temperature sintering, the metal electrodes form an ohmic contact with the emitter.

[0093] Figure 3 The ECV doping curves in the first emitter layer and the second emitter region of the solar cell obtained in Example 1 are also shown. Figure 3 In the diagram, the first emitter layer represents the ECV doping curve of the first emitter layer, and the second emitter region represents the ECV doping curve of the second emitter region. This shows that the first emitter layer has a steep diffusion junction, while the second emitter region has a gentler doping junction.

[0094] Compared to the solar cell prepared in Example 1 of CN110299422A, the solar cell obtained in Example 1 of this disclosure has a shallower first emitter depth, a junction depth of less than 0.7 μm, better short-wavelength response, and a higher short-circuit current density, from 40.3 mA / cm². 2 Increased to 40.6 mA / cm 2 ;

[0095] Compared to the solar cell prepared in Example 1 of CN110299422A, the solar cell obtained in Example 1 of this disclosure has a deeper second emitter depth after laser doping, greater than 0.7 μm, and a lower electrode contact resistance, from 1.5 ohm / cm. 2 Decreased to 0.9 ohm / cm 2 .

[0096] In the description of this application, it should be noted that the terms "upper", "lower", "inner", "outer", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship in the working state of this application. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0097] The present application has been described above with reference to preferred embodiments; however, these embodiments are merely exemplary and illustrative. Various substitutions and modifications can be made to the present application based on these embodiments, all of which fall within the protection scope of the present application.

Claims

1. A method for preparing a solar cell, comprising: S1 provides an N-type silicon substrate; S2 deposits a tunneling passivation structure on the first surface of the N-type silicon substrate, and deposits a mask layer on the tunneling passivation structure; S3 Clean the second surface of the N-type silicon substrate; S4. In the same environment, the second surface of the cleaned N-type silicon substrate is subjected to boron diffusion treatment and the tunneling passivation structure is subjected to annealing treatment, so as to form a first emitter layer and crystallize the tunneling passivation structure on the second surface of the N-type silicon substrate; the temperature of the same environment is 300-970℃, and the processing time at 800-970℃ is less than 3 hours. S5 performs laser patterning on the first emitter layer to form a second emitter region, wherein the junction depth of the first emitter layer is less than or equal to 0.7 μm, and the junction depth of the second emitter region is greater than or equal to 0.8 μm; S6 deposited passivation antireflection film, and S7 forms a first electrode and a second electrode, the first electrode being configured to make electrical contact with the second emitter region, and the second electrode being configured to make electrical contact with the tunneling passivation structure; Specifically, in the ECV doping curve of the first emitter layer, within a depth of 0.02-0.6 μm from the surface of the first emitter layer, the difference between the highest and lowest boron doping concentrations in the first emitter layer is greater than one order of magnitude; in the ECV doping curve of the second emitter region, within a depth of 0.05-0.7 μm from the surface of the second emitter region, the difference between the highest and lowest boron doping concentrations in the second emitter region is less than one order of magnitude.

2. The preparation method according to claim 1, wherein, The tunneling passivation structure includes a tunneling oxide layer and a passivation contact material layer, wherein the tunneling oxide layer is disposed between the N-type silicon substrate and the passivation contact material layer.

3. The preparation method according to claim 2, wherein, The material constituting the passivation contact material layer is selected from one or more of doped amorphous silicon, doped polycrystalline silicon, and silicon carbide.

4. The preparation method according to claim 2 or 3, wherein, The second electrode is configured to make electrical contact with the passivated contact material layer.

5. The preparation method according to claim 1, wherein, The junction depth of the first emitter layer is smaller than the junction depth of the second emitter region.

6. The preparation method according to claim 1, wherein, The highest boron doping concentration in the first emitter layer is greater than the highest boron doping concentration in the second emitter region; the total boron doping amount in the first emitter layer is less than the total boron doping amount in the second emitter region.

7. The preparation method according to claim 1, wherein, The highest point in the ECV doping curve of the first emitter layer is located at a depth of 0.05-0.5 μm from the surface of the first emitter layer.

8. The preparation method according to claim 1, wherein, The sheet resistance of the first emitter layer is ≥150 ohm / sq, and the sheet resistance of the second emitter region is ≤150 ohm / sq.

9. The preparation method according to claim 1, wherein, The width of the first electrode is smaller than the width of the second emitter region.

10. The preparation method according to claim 1, wherein, A cleaning step is performed before proceeding with S6.

11. The preparation method according to claim 1, wherein, The material of the passivation antireflection film is selected from one or more combinations of alumina, silicon oxide, silicon nitride, and silicon oxynitride.

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