Light emitting diode and method of manufacturing and transferring the same

Abstract

The present disclosure provides a light emitting diode and a preparation method and a transfer method thereof, and belongs to the technical field of optoelectronic manufacturing. The light emitting diode comprises a substrate, an epitaxial layer and a solder block. The epitaxial layer is located on a bearing surface of the substrate. The solder block is located on a surface of the epitaxial layer away from the substrate, and the solder block is electrically connected with the epitaxial layer. The light emitting diode has a chamfer at at least one of the following: an edge of the bearing surface; and an edge of the surface of the solder block away from the substrate. The embodiment of the present disclosure can stably transfer the light emitting diode to a circuit board during the transfer of the light emitting diode, and improves the transfer precision of the light emitting diode.

Description

Technical Field

[0001] This disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light-emitting diode and its preparation and transfer methods. Background Technology

[0002] Micro LEDs are ultra-small light-emitting diodes with a side length of 10μm to 100μm. Due to their small size, micro LEDs can be arranged more densely to significantly improve resolution. They also have self-emissive properties and are characterized by high brightness, high contrast, high responsiveness, and energy saving.

[0003] In related technologies, a mass transfer method is used to arrange light-emitting diodes (LEDs) on a circuit board. During mass transfer, a large number of LEDs are first adhered to a transfer board, which is then parallel to the circuit board with the electrode side of the LEDs facing the circuit board. After adjusting the position of the transfer board so that the LEDs are aligned with the area to be transferred on the circuit board, the adhesive between the LEDs and the transfer board is broken down by laser, allowing the LEDs to fall onto the circuit board and complete the transfer operation.

[0004] However, during the process of the LED falling onto the circuit board, the LED's falling posture is prone to tilting, which leads to deviations in the LED's installation position after it lands on the circuit board, thus reducing the accuracy of the mass transfer. Summary of the Invention

[0005] This disclosure provides a light-emitting diode (LED) and its fabrication and transfer methods, which enable the LED to be smoothly transferred to a circuit board during the transfer process, improving the transfer accuracy of the LED. The technical solution is as follows:

[0006] This disclosure provides a light-emitting diode (LED) comprising a substrate, an epitaxial layer, and a solder block. The epitaxial layer is located on a bearing surface of the substrate, and the solder block is located on a surface of the epitaxial layer away from the substrate and is electrically connected to the epitaxial layer. The LED has a chamfer at at least one of the following locations: the edge of the bearing surface; and the edge of the solder block on the surface away from the substrate.

[0007] Optionally, the chamfer includes a first chamfer located on opposite sides of the bearing surface.

[0008] Optionally, the chamfer includes a second chamfer located on opposite sides of the surface of the solder block away from the substrate.

[0009] Optionally, the angle between the chamfered surface and the bearing surface is 30° to 70°.

[0010] Optionally, the maximum height of the chamfer in the direction perpendicular to the bearing surface is 3 μm to 10 μm.

[0011] This disclosure provides a method for fabricating a light-emitting diode (LED), the method comprising: providing a substrate; forming an epitaxial layer on a carrier surface of the substrate; forming a solder block on the epitaxial layer, the solder block being electrically connected to the epitaxial layer, the LED having a chamfer at at least one of the following locations: the edge of the carrier surface; the edge of the solder block away from the surface of the substrate.

[0012] Optionally, forming solder joint blocks on the epitaxial layer includes: vapor deposition of solder joint blocks on the epitaxial layer, wherein an evaporation stage with an incident angle of 30° to 70° is used when vapor deposition of the solder joint blocks to form a chamfer at the edge of the surface of the solder joint blocks away from the substrate.

[0013] This disclosure provides a method for transferring light-emitting diodes (LEDs). The method is applicable to transferring LEDs as described above, and includes: providing a plurality of LEDs; fabricating a bonding adhesive on a substrate; exposing the bonding adhesive through a mask structure to form a cured region and a flexible region on the substrate surface, wherein each flexible region corresponds to one of the LEDs; each flexible region includes a first region, a second region, and a third region that surround the substrate from the inside out, with the viscosity of the first region, the second region, and the third region increasing sequentially; and placing the LED on the corresponding flexible region until the LED is embedded in the flexible region.

[0014] Optionally, the viscosity of the first region is 300 CP to 500 CP, the viscosity of the second region is 800 CP to 1000 CP, and the viscosity of the third region is 1500 CP to 2000 CP.

[0015] Optionally, the minimum distance between the outer contour of the first region and the outer contour of the second region is 8 μm to 12 μm, and the minimum distance between the outer contour of the second region and the outer contour of the third region is 15 μm to 25 μm.

[0016] The beneficial effects of the technical solutions provided in this disclosure include at least the following:

[0017] The substrate of the light-emitting diode (LED) provided in this embodiment has a chamfered edge on the surface of the substrate and / or the edge of the solder joint block away from the substrate. Since the side of the LED with the epitaxial layer faces downwards during its descent onto the circuit board, air flows along the chamfered slope. The air exerts a horizontal force on the chamfered slope, thus correcting the LED's descent posture and allowing it to land more smoothly on the circuit board. This effectively prevents positional deviations during the LED's descent, which could affect the LED's transfer accuracy. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the transfer of a light-emitting diode provided by related technologies;

[0020] Figure 2 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure;

[0021] Figure 3 This is a top view of a light-emitting diode provided in an embodiment of this disclosure;

[0022] Figure 4 This is a flowchart of a method for fabricating a light-emitting diode according to an embodiment of this disclosure;

[0023] Figure 5 This is a flowchart of a method for transferring light-emitting diodes according to an embodiment of this disclosure;

[0024] Figure 6 This is a schematic diagram of the distribution of a flexible region provided in an embodiment of this disclosure.

[0025] The markings in the diagram are explained as follows:

[0026] 10. Substrate; 11. Bearing surface; 12. First chamfer;

[0027] 20. Epitaxial layer; 21. First semiconductor layer; 22. Multiple quantum well layer; 23. Second semiconductor layer; 24. Groove;

[0028] 30. Solder joint block; 31. Second chamfer;

[0029] 40. Passivation layer; 41. Electrode;

[0030] 51. Receiving plate; 52. Transfer plate; 53. Circuit board;

[0031] 61. First area; 62. Second area; 63. Third area;

[0032] 70. Solidified area;

[0033] C, LED; X, adhesive. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0035] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0036] Micro LEDs, as ultra-small chips, offer significantly improved display resolution. However, due to their extremely small size, sorting equipment struggles to accurately sort them. Therefore, when transferring a large number of LEDs, a mass transfer method must be used to arrange them on a circuit board.

[0037] Figure 1 This is a schematic diagram of the transfer of a light-emitting diode provided by related technologies. For example... Figure 1As shown, during the transfer process, the LED C is first adhered to the transfer plate 52 by adhesive X, with the side of the LED C having electrodes away from the transfer plate 52. Then, the transfer plate 52 is moved so that it is parallel to the circuit board 53. Next, when the LED C is aligned with the area to be transferred on the circuit board 53, the adhesive X between the LED C and the transfer plate 52 is decomposed by laser. Since the adhesive X is filled with nitrogen gas, after laser decomposition, the nitrogen gas overflows and applies a force to the LED C, causing the LED C to fall quickly onto the circuit board 53, thus completing the transfer operation.

[0038] However, the LEDs are prone to positional deviations during the process of falling onto the circuit board 53, which leads to a decrease in the accuracy of the mass transfer.

[0039] Therefore, this disclosure provides a light-emitting diode. Figure 2 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure. Figure 3 This is a top view of a light-emitting diode provided in an embodiment of this disclosure. Figure 2 , 3 As shown, the light-emitting diode includes a substrate 10, an epitaxial layer 20, and a solder block 30. The epitaxial layer 20 is located on the bearing surface 11 of the substrate 10, and the solder block 30 is located on the surface of the epitaxial layer 20 away from the substrate 10, and the solder block 30 is electrically connected to the epitaxial layer 20.

[0040] like Figure 2 As shown, a chamfer is provided at the edge of the bearing surface 11; a chamfer is provided at the edge of the solder block 30 away from the surface of the substrate 10.

[0041] The substrate 10 of the light-emitting diode provided in this embodiment has a chamfered edge on the bearing surface 11 and / or the solder joint block 30 away from the surface of the substrate 10. Since the side of the light-emitting diode with the epitaxial layer 20 faces downwards during the falling process, air flows along the chamfered slope. The air exerts a horizontal force on the chamfered slope, thus correcting the falling posture of the light-emitting diode and allowing it to fall more smoothly onto the circuit board. This effectively prevents positional deviations during the falling process, thus ensuring the accuracy of the light-emitting diode transfer.

[0042] It should be noted that in some other implementations, the chamfer may be provided only on the edge of the bearing surface 11 or the edge of the solder block 30 away from the substrate 10, and this disclosure does not impose any limitations.

[0043] Optionally, such as Figure 2 As shown, the chamfer includes a first chamfer 12, which is located on opposite sides of the bearing surface 11.

[0044] The first chamfer 12 is located on opposite sides of the bearing surface 11, allowing the first chamfer 12 to be symmetrically distributed on the bearing surface 11. In this way, during the falling process of the light-emitting diode, the light-emitting diode will be subjected to a symmetrical horizontal force, which can make the light-emitting diode fall more smoothly from the transfer plate 52 onto the circuit board 53, effectively preventing positional deviation of the light-emitting diode during the falling process, thus affecting the transfer accuracy of the light-emitting diode.

[0045] For example, such as Figure 3 As shown, all sides of the bearing surface 11 are provided with a first chamfer 12.

[0046] For example, such as Figure 3 As shown, the substrate 10 has a rectangular bearing surface 11. Each of the four sides of the bearing surface 11 is provided with a first chamfer 12, and the ends of two adjacent first chamfers 12 are connected to form a first chamfer 12 on the outer contour of the bearing surface 11.

[0047] In the above implementation, during the falling process of the LED, the air exerts a horizontal component force on the inclined surface of the first chamfer 12. Since the LEDs are distributed around the substrate 10, they are subjected to component forces in all horizontal directions, which allows the LEDs to fall more smoothly from the transfer plate 52 onto the circuit board 53. This effectively prevents positional deviations during the LED's fall, thus avoiding problems that could affect the LED transfer accuracy.

[0048] Optionally, such as Figure 2 , 3 As shown, the chamfer includes a second chamfer 31, which is located on opposite sides of the surface of the solder block 30 away from the substrate 10.

[0049] The second chamfer 31 is located on opposite sides of the surface of the solder block 30 away from the substrate 10, allowing the second chamfer 31 to be symmetrically distributed on the solder block 30. Since the solder block 30 is also facing downwards during the process of the light-emitting diode falling onto the circuit board 53, the symmetrically distributed second chamfer 31 on the surface of the solder block 30 ensures that the solder block 30 is also subjected to a symmetrical horizontal force, further allowing the light-emitting diode to fall more smoothly from the transfer plate 52 onto the circuit board 53.

[0050] For example, such as Figure 3 As shown, all sides of the solder block 30 away from the surface of the substrate 10 are provided with a second chamfer 31.

[0051] For example, such as Figure 3As shown, the surface of the solder block 30 away from the substrate 10 is rectangular, and the four sides of the surface of the solder block 30 away from the substrate 10 are provided with a second chamfer 31, and the ends of two adjacent second chamfers 31 are connected to form a second chamfer 31 on the outer contour of the bearing surface 11.

[0052] Optionally, the angle between the chamfered surface and the bearing surface 11 is 30° to 70°. For example, as Figure 2 , 3 As shown, the angle between the surface of the first chamfer 12 and the bearing surface 11 is 30° to 70°, and the angle between the second chamfer 31 and the surface of the solder block 30 away from the substrate 10 is 30° to 70°.

[0053] By limiting the angle between the surface of the first chamfer 12 and the bearing surface 11, and the angle between the second chamfer 31 and the surface of the solder block 30 away from the substrate 10, the inclination of the chamfered surface relative to the bearing surface 11 can be prevented from being too large or too small, thus failing to guide air to form aerodynamics.

[0054] For example, the angle between the surface of the first chamfer 12 and the bearing surface 11 is 45°, and the angle between the second chamfer 31 and the surface of the solder block 30 away from the substrate 10 is 45°.

[0055] Optionally, the maximum width of the chamfer in the direction parallel to the bearing surface 11 is 3 μm to 10 μm, and the maximum height of the chamfer in the direction perpendicular to the bearing surface 11 is 3 μm to 10 μm.

[0056] Exemplarily, or optionally, as Figure 2 As shown, the maximum width L1 of the first chamfer 12 parallel to the bearing surface 11 is 3μm to 10μm, and the maximum height L2 of the first chamfer 12 perpendicular to the bearing surface 11 is 3μm to 10μm.

[0057] By limiting the maximum width of the first chamfer 12 parallel to the bearing surface 11 and the maximum height of the first chamfer 12 perpendicular to the bearing surface 11 within the aforementioned range, it is possible to avoid the first chamfer 12 being too small and thus failing to guide air to form aerodynamics.

[0058] For example, the first chamfer 12 has a maximum width L1 of 8 μm parallel to the bearing surface 11 and a maximum height L2 of 8 μm perpendicular to the bearing surface 11.

[0059] Optionally, such as Figure 2 As shown, the second chamfer 31 has a maximum width L3 of 3μm to 10μm parallel to the bearing surface 11, and a maximum height L4 of 3μm to 10μm perpendicular to the bearing surface 11.

[0060] By limiting the maximum width of the second chamfer 31 parallel to the bearing surface 11 and the maximum height of the second chamfer 31 perpendicular to the bearing surface 11 within the aforementioned range, it is possible to avoid the second chamfer 31 being too small and thus failing to guide air to form aerodynamics.

[0061] For example, the second chamfer 31 has a maximum width L3 of 5 μm parallel to the bearing surface 11 and a maximum height L4 of 5 μm perpendicular to the bearing surface 11.

[0062] Optionally, the substrate 10 is a sapphire substrate 10. The sapphire substrate 10 has high light transmittance, meaning it is a transparent substrate. Furthermore, sapphire material is relatively hard and chemically stable, giving the light-emitting diode good luminous effect and stability.

[0063] Optionally, such as Figure 2 As shown, the epitaxial layer 20 includes a first semiconductor layer 21, a multiple quantum well layer 22, and a second semiconductor layer 23 sequentially stacked on the substrate 10. The surface of the second semiconductor layer 23 has a groove 24 that exposes the first semiconductor layer 21.

[0064] In this embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.

[0065] As an example, the first semiconductor layer 21 is an n-type layer and the second semiconductor layer 23 is a p-type layer.

[0066] Optionally, the first semiconductor layer 21 is an n-type AlGaInP layer. The thickness of the n-type AlGaInP layer can be from 0.5 μm to 3 μm.

[0067] Optionally, the multiple quantum well layer 22 includes alternating AlGaInP quantum well layers and AlGaInP quantum barrier layers, with different Al contents in the AlGaInP quantum well layers and AlGaInP quantum barrier layers. The multiple quantum well layer 22 may include 3 to 8 alternating stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0068] As an example, in an embodiment of this disclosure, the multi-quantum well layer 22 includes five alternating stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0069] Optionally, the thickness of the multiple quantum well layer 22 can be from 150 nm to 200 nm.

[0070] Optionally, the second semiconductor layer 23 is an indium-doped p-type AlInP layer. The thickness of the p-type AlInP layer can be from 0.5 μm to 3 μm.

[0071] Optionally, such as Figure 2 As shown, the epitaxial layer 20 has a groove 24 exposing the first semiconductor layer 21. An electrode 41 is provided on the surface of the groove 24, and an electrode 41 is also provided on the surface of the second semiconductor layer 23. The electrode located in the groove 24 is an n-type electrode, and the electrode located on the surface of the second semiconductor layer 23 is a p-type electrode.

[0072] Optionally, such as Figure 2 As shown, the light-emitting diode also includes a passivation layer 40, which is located at least on the second semiconductor layer 23, the groove 24, and the electrode. Two solder pads 30 are located on the surface of the passivation layer 40 away from the substrate 10. The passivation layer 40 has two through holes, one of which exposes the electrode on the second semiconductor layer 23, and the other of which exposes the electrode on the surface of the groove 24. The two solder pads 30 are connected to the two electrodes respectively through the two through holes.

[0073] For example, the passivation layer 40 can be a distributed Bragg reflection (DBR layer), which includes multiple periodically alternating layers of SiO2 and TiO2. The number of periods in the DBR layer can be between 20 and 50. For example, the number of periods in the DBR layer is 32.

[0074] The thickness of the SiO2 layer in the DBR layer can be from 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer can be from 500 angstroms to 900 angstroms.

[0075] In addition to its passivation function, the DBR layer also reflects light emitted from the multi-quantum well layer 22 toward the DBR layer back to the substrate 10, thereby improving the light extraction effect.

[0076] Optionally, such as Figure 2 As shown, a protective layer is also provided in the passivation layer 40, and the protective layer extends from the surface of the passivation layer 40 to the substrate 10.

[0077] For example, in this embodiment of the disclosure, the protective layer may be a silicon oxide layer with a thickness of 2000 angstroms.

[0078] Figure 4 This is a flowchart illustrating a method for fabricating a light-emitting diode (LED) according to an embodiment of this disclosure. This method is used to fabricate... Figure 2 The light-emitting diode shown. For example... Figure 4 As shown, the preparation method includes:

[0079] S11: Provide a substrate.

[0080] S12: An epitaxial layer is formed on the bearing surface of the substrate.

[0081] S13: Solder blocks are formed on the epitaxial layer, and the solder blocks are electrically connected to the epitaxial layer.

[0082] The light-emitting diode has a chamfer at at least one of the following locations: the edge of the bearing surface; the edge of the solder block away from the substrate.

[0083] The substrate of the LED fabricated by this method has a chamfered edge on the bearing surface and / or solder joint block away from the substrate surface. Since the side of the LED with the epitaxial layer faces downwards during its descent onto the circuit board, air flows along the chamfered slope. The air exerts a horizontal force on the chamfered slope, thus correcting the LED's descent posture and allowing it to land more smoothly on the circuit board. This effectively prevents positional deviations during the LED's descent, which could affect the LED's transfer accuracy.

[0084] In this embodiment of the disclosure, before the epitaxial layer 20 is formed on the bearing surface 11 of the substrate 10, the following steps may be included:

[0085] The first step is to provide a GaAs chip.

[0086] The second step is to grow an epitaxial layer 20 on the GaAs wafer. The epitaxial layer 20 includes a second semiconductor layer 23, a multiple quantum well layer 22 and a first semiconductor layer 21 stacked sequentially.

[0087] In this embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.

[0088] For example, the first semiconductor layer 21 may be an n-type AlGaInP layer. The thickness of the n-type AlGaInP layer may be from 0.5 μm to 3 μm.

[0089] For example, the second semiconductor layer 23 is an indium-doped p-type AlInP layer. The thickness of the p-type AlInP layer can be from 0.5 μm to 3 μm.

[0090] Optionally, the multiple quantum well layer 22 includes alternating AlGaInP quantum well layers and AlGaInP quantum barrier layers, with different Al contents in the AlGaInP quantum well layers and AlGaInP quantum barrier layers. The multiple quantum well layer 22 may include 3 to 8 alternating stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0091] As an example, in an embodiment of this disclosure, the multi-quantum well layer 22 includes five alternating stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0092] Optionally, the thickness of the multiple quantum well layer 22 can be from 150 nm to 200 nm.

[0093] In the second step, an etching stop layer can be grown before the growth of the second semiconductor layer 23, and an AlInP carrier confinement layer can be grown before the growth of the multi-quantum well layer 22.

[0094] After growing the first semiconductor layer 21, a GaP window layer can be grown, wherein the thickness of the GaP window layer is 10,000 angstroms to 20,000 angstroms.

[0095] For example, the thickness of the GaP window layer is 11,000 angstroms.

[0096] The third step involves forming a bonding layer between the first semiconductor layer 21 and the sapphire substrate 10, bonding the epitaxial layer 20 to the sapphire substrate 10, and removing the GaAs wafer to complete steps S11 to S12.

[0097] Because the sapphire substrate 10 has high light transmittance and the sapphire material is relatively hard and has stable chemical properties, using the sapphire substrate 10 can enable the light-emitting diode to have good light-emitting effect and stability.

[0098] Specifically, this may include: coating the surface of the second semiconductor layer 23 with liquid silicon oxide, placing the sapphire substrate 10 on the surface of the second semiconductor layer 23, and heating the epitaxial wafer to solidify the liquid silicon oxide to form a bonding layer between the second semiconductor layer 23 and the sapphire substrate 10.

[0099] Optionally, the heating temperature of the epitaxial wafer is 250°C to 350°C. For example, the heating temperature can be 300°C.

[0100] The preparation method after forming the epitaxial wafer in step S12 may also include: etching a first chamfer 12 at the scribe line of the sapphire substrate 10 by laser etching, and then cleaning away the residue, so that a light-emitting diode with the first chamfer 12 can be obtained after cleaving.

[0101] In this embodiment of the disclosure, step S13 may include the following steps:

[0102] The first step is to etch the second semiconductor layer 23 to form a groove 24 that exposes the first semiconductor layer 21.

[0103] Specifically, this may include: etching the second semiconductor layer 23 using a dry etching method to expose the first semiconductor layer 21.

[0104] The second step is to form electrodes on the surface of the groove 24 and the surface of the second semiconductor layer 23.

[0105] The electrode located in the groove 24 is an n-type electrode, and the electrode located on the surface of the second semiconductor layer 23 is a p-type electrode.

[0106] The third step is to fabricate a passivation layer 40 on the surface of the epitaxial wafer. The passivation layer 40 is located at least on the second semiconductor layer 23 and the groove 24.

[0107] The passivation layer 40 can be a distributed Bragg mirror layer, which can be a DBR layer comprising multiple periodically alternating SiO2 layers and TiO2 layers. The number of periods in the DBR layer can be between 20 and 50. For example, the number of periods in the DBR layer is 32.

[0108] The thickness of the SiO2 layer in the DBR layer can be from 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer can be from 500 angstroms to 900 angstroms.

[0109] The fourth step is to form two through holes on the passivation layer 40.

[0110] After the passivation layer 40 is formed, two vias are etched on the surface of the passivation layer 40 away from the substrate 10, and the two vias expose the electrodes in the groove 24 and the electrodes in the second semiconductor layer 23, respectively.

[0111] The fifth step is to deposit two solder blocks 30 on the surface of the passivation layer 40 by vapor deposition, and then connect the solder blocks 30 to the semiconductor layer of the epitaxial layer 20 through through holes.

[0112] For example, one solder joint 30 is connected to the electrode of the first semiconductor layer 21 through a through-hole, and another solder joint 30 is connected to the electrode of the second semiconductor layer 23 through a through-hole.

[0113] In this process, an evaporation stage with an incident angle of 30° to 70° is used when evaporating the solder joint block 30 to form a second chamfer 31 on the side of the surface of the solder joint block 30 away from the substrate 10.

[0114] In this embodiment of the disclosure, the solder joint block 30 may include a Ti layer, a first Ni layer, an Au layer, a second Ni layer, and an In layer stacked sequentially.

[0115] For example, the thickness of the Ti layer can be from 500 angstroms to 1500 angstroms, such as 1000 angstroms.

[0116] For example, the thickness of the first Ni layer can be from 500 angstroms to 1500 angstroms, for instance, the thickness of the first Ni layer can be 1000 angstroms.

[0117] For example, the thickness of the Au layer can be from 8,000 angstroms to 12,000 angstroms, such as 5,000 angstroms.

[0118] For example, the thickness of the second Ni layer can be from 2,000 angstroms to 4,000 angstroms, such as 3,000 angstroms.

[0119] For example, the thickness of the In layer can be from 30,000 angstroms to 80,000 angstroms, such as 50,000 angstroms.

[0120] In this embodiment of the present disclosure, after the two solder joint blocks 30 are fabricated, the preparation method may further include: fabricating a protective layer on the surface of the passivation layer 40.

[0121] For example, in this embodiment of the disclosure, the protective layer may be a silicon oxide layer with a thickness of 2000 angstroms.

[0122] It should be noted that after a protective layer is grown on the surface of the passivation layer 40, photolithography can be used to etch vias that expose the electrodes on the surface of the protective layer to facilitate electrical connection.

[0123] Finally, the sapphire can be invisibly cut to reduce brightness loss. Then, the light-emitting diode (LED) can be obtained through testing.

[0124] Figure 5 This is a flowchart illustrating a method for transferring a light-emitting diode (LED) according to an embodiment of this disclosure. This transfer method is applicable to transferring LEDs as described above. Figure 5 As shown, the transfer method includes:

[0125] S21: Provides multiple light-emitting diodes.

[0126] S22: A bonding adhesive is made on the bonding plate 51, and the bonding adhesive is exposed through a mask structure to form a cured area 70 and a flexible area on the bonding surface.

[0127] Figure 6 This is a schematic diagram illustrating the distribution of a flexible region according to an embodiment of this disclosure. For example... Figure 6 As shown, the flexible regions correspond one-to-one with the light-emitting diodes. The flexible regions include a first region 61, a second region 62, and a third region 63 that surround each other from the inside out. The viscosity of the first region 61, the second region 62, and the third region 63 increases sequentially.

[0128] S23: Place the LED on the corresponding flexible area, and let the LED sink into the flexible area.

[0129] Because the viscosity of the first region 61, the second region 62, and the third region 63 increases sequentially, meaning the hardness of each region also gradually increases, the adhesive material surrounding the LED has good flowability. This allows the LED to have a better chance of further positional optimization. When the LED is placed in the flexible region, it will automatically adjust to the first region 61, which has the lowest hardness. Therefore, when transferring the LED to the receiving plate 51, placing it in the flexible region for about 10 minutes will allow the LED to automatically adjust to the first region 61 and sink into the bottom of the adhesive, improving the transfer accuracy and reducing the LED's offset.

[0130] In the above implementation, the different areas of the adhesive hardness change are achieved by exposing the adhesive material. After exposure, the adhesive material will become harder. By selecting mask structures with different exposure amounts, adhesive material areas with different hardness can be obtained. This allows the chip to further improve its positional accuracy after transfer and further reduce the giant rotation offset.

[0131] Optionally, the viscosity of the first region 61 is 300 CP to 500 CP, the viscosity of the second region 62 is 800 CP to 1000 CP, and the viscosity of the third region 63 is 1500 CP to 2000 CP.

[0132] For example, the viscosity of the first region 61 is 300 CP, the viscosity of the second region 62 is 1000 CP, and the viscosity of the third region 63 is 2000 CP.

[0133] Optionally, such as Figure 6 As shown, the minimum distance L5 between the outer contour of the first region 61 and the outer contour of the second region 62 is 8μm to 12μm, and the minimum distance L6 between the outer contour of the second region 62 and the outer contour of the third region 63 is 15μm to 25μm.

[0134] For example, the minimum distance L5 between the outer contour of the first region 61 and the outer contour of the second region 62 is 10 μm, and the minimum distance L6 between the outer contour of the second region 62 and the outer contour of the third region 63 is 20 μm.

[0135] After step S23, the transfer method may also include the following steps:

[0136] The first step is to attach the light-emitting diodes transferred to the receiving plate 51 to the substrate using adhesive. Figure 1 On the transfer plate 52 shown.

[0137] Since the light-emitting diodes can be accurately distributed in the design area on the receiving plate 51 through the flexible area, the arrangement accuracy of the light-emitting diodes on the transfer plate 52 can also be guaranteed when the light-emitting diodes are transferred from the receiving plate 51 to the transfer plate 52.

[0138] The second step involves using a laser to break down the adhesive between the light-emitting diode and the transfer plate 52.

[0139] Since the adhesive is filled with nitrogen, after laser decomposition, the nitrogen overflows and exerts a force on the light-emitting diode, causing the light-emitting diode to fall quickly onto the circuit board 53, thus completing the transfer operation.

[0140] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A light emitting diode, characterized by, The light-emitting diode includes a substrate (10), an epitaxial layer (20), and a solder block (30). The epitaxial layer (20) is located on the bearing surface (11) of the substrate (10), and the solder block (30) is located on the surface of the epitaxial layer (20) away from the substrate (10), and the solder block (30) is electrically connected to the epitaxial layer (20). The bearing surface (11) is rectangular, and each of the four sides of the bearing surface (11) is provided with a first chamfer (12), and the ends of two adjacent first chamfers (12) are connected. The surface of the solder block (30) away from the substrate (10) is rectangular, and the four sides of the surface of the solder block (30) away from the substrate (10) are provided with a second chamfer (31), and the ends of two adjacent second chamfers (31) are connected. The angle between the surface of the first chamfer (12) and the bearing surface (11) is 30° to 70°, and the angle between the second chamfer (31) and the surface of the solder block (30) away from the substrate (10) is 30° to 70°. The first chamfer (12) has a maximum width of 3 μm to 10 μm in the direction parallel to the bearing surface (11), and a maximum height of 3 μm to 10 μm in the direction perpendicular to the bearing surface (11). The second chamfer (31) has a maximum width of 3 μm to 10 μm in the direction parallel to the bearing surface (11), and a maximum height of 3 μm to 10 μm in the direction perpendicular to the bearing surface (11).

2. A method of fabricating a light emitting diode, characterized by, The preparation method includes: Provide a substrate; An epitaxial layer is formed on the bearing surface of the substrate; Solder blocks are formed on the epitaxial layer, and the solder blocks are electrically connected to the epitaxial layer. The bearing surface is rectangular, and each of the four sides of the bearing surface is provided with a first chamfer, with the ends of two adjacent first chamfers connected together; The surface of the solder block away from the substrate is rectangular, and each of the four sides of the surface of the solder block away from the substrate is provided with a second chamfer, with the ends of two adjacent second chamfers connected. The angle between the surface of the first chamfer and the bearing surface is 30° to 70°, and the angle between the second chamfer and the surface of the solder block away from the substrate is 30° to 70°. The first chamfer has a maximum width of 3 μm to 10 μm in the direction parallel to the bearing surface, and a maximum height of 3 μm to 10 μm in the direction perpendicular to the bearing surface. The second chamfer has a maximum width of 3 μm to 10 μm in the direction parallel to the bearing surface, and a maximum height of 3 μm to 10 μm in the direction perpendicular to the bearing surface.

3. The preparation method according to claim 2, characterized in that, The process of forming solder joint blocks on the epitaxial layer includes: Solder blocks are deposited on the epitaxial layer by vapor deposition. An evaporation stage with an incident angle of 30° to 70° is used to deposit the solder blocks to form a chamfer at the edge of the surface of the solder blocks away from the substrate.

4. A method for transferring light-emitting diodes, characterized in that, The transfer method is applicable to transferring the light-emitting diode as described in claim 1, comprising: Provide a plurality of the aforementioned light-emitting diodes; A bonding adhesive is made on the bonding plate, and the bonding adhesive is exposed through a mask structure to form a cured area and a flexible area on the bonding surface. The flexible area corresponds one-to-one with the light-emitting diode. The flexible area includes a first area, a second area and a third area that surround the first area, the second area and the third area in sequence from the inside to the outside. The viscosity of the first area, the second area and the third area increases in sequence. The light-emitting diode is placed on the corresponding flexible region until it is embedded in the flexible region.

5. The transfer method according to claim 4, characterized in that, The viscosity of the first region is 300 CP to 500 CP, the viscosity of the second region is 800 CP to 1000 CP, and the viscosity of the third region is 1500 CP to 2000 CP.

6. The transfer method according to claim 4, characterized by, The minimum distance between the outer contour of the first region and the outer contour of the second region is 8 μm to 12 μm, and the minimum distance between the outer contour of the second region and the outer contour of the third region is 15 μm to 25 μm.

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