A three-level buck-boost converter with flying capacitor voltage balancing circuit

Abstract

The present disclosure relates to a three-level buck-boost converter with flying capacitor voltage balancing circuit, comprising: an inductor connected in series between a switching node and a ground terminal; an output capacitor connected between an output terminal for outputting an output voltage and the ground terminal; a first switch connected between an input terminal for inputting an input voltage and an upper plate node; a second switch connected between the upper plate node and the switching node; a third switch connected between the switching node and a bottom plate node; a fourth switch connected between the bottom plate node and the output terminal; a flying capacitor connected between the upper plate node and the bottom plate node; a balancing switch connected between the switching node and a balancing node; an upper balancing capacitor connected between the input terminal and the balancing node; and a bottom balancing capacitor connected between the balancing node and the output terminal. The converter uses a simple circuit to achieve flying capacitor voltage balancing, thereby improving efficiency, reducing inductor current ripple, and achieving high-speed flying capacitor voltage balancing.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2022-0060667, filed on May 18, 2022, the entire contents of which are incorporated herein by reference. Background Technology

[0003] This disclosure relates to a three-level buck-boost converter with a flying capacitor voltage balancing circuit. More specifically, this disclosure relates to a three-level buck-boost converter with a flying capacitor voltage balancing circuit, which achieves flying capacitor voltage balancing using a simple circuit in the three-level buck-boost converter, thereby uniformly applying the voltage across the switch to improve efficiency and reduce inductor current ripple, and can achieve high-speed flying capacitor voltage balancing.

[0004] Typically, compared to a two-level buck-boost converter, a three-level buck-boost converter can use switches with lower withstand voltage, and even when using inductors with lower inductance values, it can reduce current ripple, thereby improving the converter's efficiency.

[0005] However, in a three-level buck-boost converter, when the flying capacitor voltage is unbalanced, the voltage stress on the switches increases and additional losses occur. Therefore, to maintain the advantages of a three-level buck-boost converter, it is important to keep the flying capacitor voltage balanced, but existing technologies lack an effective method for this. Summary of the Invention

[0006] This disclosure provides a three-level buck-boost converter that achieves cross-capacitor voltage equalization using a simple circuit in the three-level buck-boost converter, thereby uniformly applying the voltage across the switch to improve efficiency and reduce inductor current ripple.

[0007] This disclosure provides a three-level buck-boost converter that can achieve high-speed cross-capacitor voltage balancing.

[0008] According to one embodiment of this disclosure, a three-level buck-boost converter with a flying capacitor voltage balancing circuit includes: an inductor connected in series between a switching node and a ground terminal; an output capacitor connected between an output terminal for output voltage and a ground terminal; a first switch connected between an input terminal for input voltage and an upper plate node; a second switch connected between the upper plate node and the switching node; a third switch connected between the switching node and a bottom plate node; a fourth switch connected between the bottom plate node and the output terminal; a flying capacitor connected between the upper plate node and the bottom plate node; a balancing switch connected between the switching node and the balancing node; an upper balancing capacitor connected between the input terminal and the balancing node; and a bottom balancing capacitor connected between the balancing node and the output terminal.

[0009] In a three-level buck-boost converter according to an embodiment of the present disclosure, the flying capacitor can be connected in parallel with the upper balancing capacitor for a portion of the operation time of the three-level buck-boost converter, and can be connected in parallel with the bottom balancing capacitor for another portion of the operation time of the three-level buck-boost converter.

[0010] In a three-level buck-boost converter according to an embodiment of the present disclosure, the voltage of the flying capacitor, the voltage of the upper balancing capacitor, and the voltage of the bottom balancing capacitor may have the same value.

[0011] In a three-level buck-boost converter according to an embodiment of the present disclosure, the voltage of the flying capacitor, the voltage of the upper balancing capacitor, and the voltage of the bottom balancing capacitor can be maintained at the value obtained by subtracting the output voltage from the input voltage and dividing by 2.

[0012] In a three-level buck-boost converter according to an embodiment of the present disclosure, when the duty cycle D is less than approximately 0.5, during a first time period, the first switch, the third switch, and the balance switch can be turned on, and the second switch and the fourth switch can be turned off, so that the flying capacitor and the upper balance capacitor can be connected in parallel. After the first time period, during a second time period following the first time period, the third switch and the fourth switch can be turned on, and the first switch, the second switch, and the balance switch can be turned off. After the second time period, during a third time period of the same duration as the first time period, the second switch, the fourth switch, and the balance switch can be turned on, and the first switch and the third switch can be turned off, so that the flying capacitor and the bottom balance capacitor can be connected in parallel. After the third time period, during a fourth time period of the same duration as the second time period, the third switch and the fourth switch can be turned on, and the first switch, the second switch, and the balance switch can be turned off.

[0013] In a three-level buck-boost converter according to an embodiment of the present disclosure, when the duty cycle D is approximately 0.5, during a fifth time period, the first switch, the third switch, and the balance switch can be turned on, and the second switch and the fourth switch can be turned off, so that the flying capacitor and the upper balance capacitor can be connected in parallel. After the fifth time period, during a sixth time period that is the same as the fifth time period, the second switch, the fourth switch, and the balance switch can be turned on, and the first switch and the third switch can be turned off, so that the flying capacitor and the bottom balance capacitor can be connected in parallel.

[0014] In a three-level buck-boost converter according to an embodiment of the present disclosure, when the duty cycle D is approximately greater than 0.5, during a seventh time period, the first switch, the third switch, and the balance switch can be turned on, and the second switch and the fourth switch can be turned off, so that the flying capacitor and the upper balance capacitor can be connected in parallel. After the seventh time period, during an eighth time period following the seventh time period, the first switch and the second switch can be turned on, and the third switch, the fourth switch, and the balance switch can be turned off. After the eighth time period, during a ninth time period, which is the same as the seventh time period, the second switch, the fourth switch, and the balance switch can be turned on, and the first switch and the third switch can be turned off, so that the flying capacitor and the bottom balance capacitor can be connected in parallel. After the ninth time period, during a tenth time period, which is the same as the eighth time period, the first switch and the second switch can be turned on, and the third switch, the fourth switch, and the balance switch can be turned off. Attached Figure Description

[0015] The exemplary embodiments can be understood in more detail from the following description taken in conjunction with the accompanying drawings, wherein:

[0016] Figure 1 This is a diagram illustrating a three-level buck-boost converter according to an embodiment of the present invention.

[0017] Figure 2 This is an exemplary timing diagram illustrating an embodiment of the present invention when the duty cycle D is less than approximately 0.5.

[0018] Figure 3 This is a circuit diagram illustrating various operating modes according to an embodiment of the present invention when the duty cycle is less than approximately 0.5.

[0019] Figure 4 This is a simplified circuit diagram illustrating various operating modes according to an embodiment of the present invention when the duty cycle is less than about 0.5.

[0020] Figure 5 This is an exemplary timing diagram illustrating an operation when the duty cycle is approximately 0.5, according to an embodiment of the present invention.

[0021] Figure 6 This is a circuit diagram illustrating various operating modes when the duty cycle is approximately 0.5, according to an embodiment of the present invention.

[0022] Figure 7 This is a simplified circuit diagram illustrating various operating modes when the duty cycle is approximately 0.5, according to an embodiment of the present invention.

[0023] Figure 8 This is an exemplary timing diagram illustrating an operation when the duty cycle D is approximately greater than 0.5, according to an embodiment of the present invention.

[0024] Figure 9 This is a circuit diagram illustrating various operating modes according to an embodiment of the present invention when the duty cycle is approximately greater than 0.5.

[0025] Figure 10 This is a simplified circuit diagram illustrating various operating modes according to an embodiment of the present invention when the duty cycle is approximately greater than 0.5. Detailed Implementation

[0026] The specific structural or functional descriptions of embodiments of the present invention disclosed in this specification are merely illustrative examples for describing embodiments of the present invention, and embodiments of the present invention can be implemented in various forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the inventive concept to those skilled in the art.

[0027] Embodiments of the present invention can have various variations and forms, and therefore are shown in the accompanying drawings and described in detail in this specification. However, this is not to limit the embodiments of the present invention to the specific forms disclosed, but includes all variations, equivalents, or substitutions within the spirit and scope of the invention.

[0028] Unless otherwise defined, terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by one of ordinary skill in the art. Terms typically defined in dictionaries may be understood to have the same or similar meaning as in the context of the prior art. Unless otherwise defined, these terms should not be interpreted as having an ideal or overly formal meaning.

[0029] Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0030] Figure 1 This is a diagram illustrating a three-level buck-boost converter according to an embodiment of the present invention.

[0031] Reference Figure 1 An embodiment of the present invention provides a three-level buck-boost converter with a flying capacitor voltage equalization circuit, configured to include: an inductor L and a first switch Q. A Second switch QB Third switch Q C Fourth switch Q D Flying capacitor C FLY Balance switch Q BAL1 and Q BAL2 Upper balancing capacitor C FLY_BAL_T and bottom balancing capacitor C FLY_BAL_B .

[0032] In the following description, the first switch Q A Second switch Q B Third switch Q C Fourth switch Q D and balance switch Q BAL1 and Q BAL2 It can be a field-effect transistor, but is not limited to this.

[0033] The inductor L is connected in series between the switch node SW and the ground terminal.

[0034] Output capacitor C OUT Connected to the supply and output voltage V OUT Output terminal V OUT Between and the grounding terminal.

[0035] First switch Q A Connected to the input voltage V IN Input terminal V IN Between and the upper board node CP.

[0036] Second switch Q B It connects the upper plate node CP and the switch node SW.

[0037] Third switch Q C It is connected between the switch node SW and the base plate node CN.

[0038] Fourth switch Q D Connected to the base plate node CN and the output terminal V OUT between.

[0039] Flying capacitor C FLY It connects the upper plate node CP and the bottom plate node BA.

[0040] Balance switch Q BAL1 and Q BAL2 It is connected between the switch node SW and the balance node BA.

[0041] Upper balancing capacitor C FLY_BAL_T It is connected between the input terminal and the balance node BA.

[0042] Bottom balancing capacitor C FLY_BAL_BConnected to the balanced node BA and the output terminal V OUT between.

[0043] For example, the flying capacitor C FLY It can be configured to operate with the upper balancing capacitor C for a portion of the time during the operation of the three-level buck-boost converter. FLY_BAL_T In parallel, during another portion of the operation of the three-level buck-boost converter, it is connected with the bottom balancing capacitor C. FLY_BAL_B in parallel.

[0044] For example, the flying capacitor C FLY voltage V CFLY Upper balancing capacitor C FLY_BAL_T The voltage of the bottom balancing capacitor and the voltage C FLY_BAL_B They can be configured to have the same value.

[0045] For example, the flying capacitor C FLY voltage V CFLY Upper balancing capacitor C FLY_BAL_T The voltage of the bottom balancing capacitor and the voltage C FLY_BAL_B It can be configured to retain the value obtained by subtracting the output voltage from the input voltage and then dividing by 2.

[0046] The following describes the specific and exemplary working configuration of a three-level buck-boost converter according to an embodiment of the present invention.

[0047] For example, in a three-level buck-boost converter according to an embodiment of the present invention, when the duty cycle D is approximately less than 0.5, 1) during the first time period, the first switch Q... A Third switch Q C and balance switch Q BAL1 and Q BAL2 The second switch Q is turned on. B and the fourth switch Q D Disconnect, thus bypassing capacitor C FLY and the upper balancing capacitor C FLY_BAL_T Parallel connection, 2) After the first time period, during the second time period following the first time period, the third switch Q C and the fourth switch Q D On, the first switch Q A Second switch Q B and balance switch Q BAL1 and Q BAL2 3) After the second time period, during the third time period (the same as the first time period), the second switch Q is disconnected. B Fourth switch Q D and balance switch Q BAL1 and Q BAL2 On, the first switch Q Aand the third switch Q C Disconnect, thus bypassing capacitor C FLY and bottom balancing capacitor C FLY_BAL_B Parallel connection, 4) After the third time period, during the fourth time period which is the same as the second time period, the third switch Q C and the fourth switch Q D On, the first switch Q A Second switch Q B and balance switch Q BAL1 and Q BAL2 disconnect.

[0048] Such exemplary embodiments will be further referred to Figures 2 to 4 To provide a more detailed description.

[0049] Figure 2 This is an exemplary timing diagram illustrating an embodiment of the present invention when the duty cycle D is approximately less than 0.5. Figure 3 This is a circuit diagram illustrating various operating modes according to an embodiment of the present invention when the duty cycle is approximately less than 0.5. Figure 4 This is a simplified circuit diagram illustrating various operating modes according to an embodiment of the present invention when the duty cycle is less than about 0.5.

[0050] Reference Figures 2 to 4 Priority is given to the first switch Q during the first time period. A Third switch Q C and balance switch Q BAL1 and Q BAL2 The second switch Q is turned on. B and the fourth switch Q D Disconnect, thus bypassing capacitor C FLY and the upper balancing capacitor C FLY_BAL_T When connected in parallel, the voltage at the upper board node CP rises to the input voltage V. IN The voltage V at the switching node SW SW Rise to from input voltage V IN Subtract the flying capacitor C FLY voltage V CFLY The obtained value V IN - V CFLY And the value V IN - V CFLY Approximating by the input voltage V IN Add output voltage V OUT The value obtained by dividing by 2 (V) IN + V OUT These values ​​are actually the same. Furthermore, the voltage V at the base plate node CN... CN Rise to from input voltage V IN Subtract the flying capacitor CFLY voltage V CFLY The obtained value V IN -V CFLY The current I in inductor L L Gradually rising.

[0051] Next, after the first time period, during the second time period following the first time period, the third switch Q... C and the fourth switch Q D On, the first switch Q A Second switch Q B and balance switch Q BAL1 and Q BAL2 When disconnected, the voltage V at the upper plate node CP CP Drop to the flying capacitor C FLY voltage V CFLY Add output voltage V OUT The obtained value V CFLY + V OUT And the value V CFLY +V OUT Approximating by the input voltage V IN Add output voltage V OUT The value obtained by dividing by 2 (V) IN + V OUT These values ​​are actually the same. Furthermore, the voltage V at the switching node SW... SW The voltage V at the base plate node CN CN Drop to output voltage V OUT The current I in inductor L L Gradually decreasing.

[0052] Next, after the second time period, during the third time period which is the same as the first time period, the second switch Q... B Fourth switch Q D and balance switch Q BAL1 and Q BAL2 On, the first switch Q A and the third switch Q C Disconnect, thus bypassing capacitor C FLY and bottom balancing capacitor C FLY_BAL_B When connected in parallel, the voltage V at the upper plate node CP is... CP Maintaining the flying capacitor C FLY voltage V CFLY Add output voltage V OUT The obtained value V CFLY + V OUT The voltage V at the switching node SW SW Rise to the flying capacitor C FLY voltage V CFLYAdd output voltage V OUT The obtained value V CFLY + V OUT The voltage V at node CN on the base plate CN Maintain output voltage V OUT The current I in inductor L L Gradually rising.

[0053] Next, after the third time period, during the fourth time period (the same as the second time period), the third switch Q... C and the fourth switch Q D On, the first switch Q A Second switch Q B and balance switch Q BAL1 and Q BAL2 When disconnected, the voltage V at the upper plate node CP CP Maintaining the flying capacitor C FLY voltage V CFLY Add output voltage V OUT The obtained value V CFLY + V OUT The voltage V at the switching node SW SW Drop to output voltage V OUT The voltage V at node CN on the base plate CN Maintain output voltage V OUT The current I in inductor L L Gradually decreasing.

[0054] For example, in a three-level buck-boost converter according to an embodiment of the present invention, when the duty cycle D is approximately 0.5, 1) during the fifth time period, the first switch Q... A Third switch Q C and balance switch Q BAL1 and Q BAL2 It can conduct, the second switch Q B and the fourth switch Q D Disconnect, thus bypassing capacitor C FLY and the upper balancing capacitor C FLY_BAL_T Parallel connection, 2) After the fifth time period, during the sixth time period which is the same as the fifth time period, the second switch Q B Fourth switch Q D and balance switch Q BAL1 and Q BAL2 On, the first switch Q A and the third switch Q C Disconnect, thus bypassing capacitor C FLY and bottom balancing capacitor C FLY_BAL_B in parallel.

[0055] Such exemplary embodiments will be further referred to Figures 5 to 7To provide a more detailed description.

[0056] Figure 5 This is an exemplary timing diagram illustrating an embodiment of the present invention when the duty cycle is approximately 0.5. Figure 6 This is a circuit diagram illustrating various operating modes according to an embodiment of the present invention when the duty cycle is approximately 0.5. Figure 7 This is a simplified circuit diagram illustrating various operating modes when the duty cycle is approximately 0.5, according to an embodiment of the present invention.

[0057] Reference Figures 5 to 7 Prioritizing the fifth time period, the first switch Q... A Third switch Q C and balance switch Q BAL1 and Q BAL2 The second switch Q is turned on. B and the fourth switch Q D Disconnect, thus bypassing capacitor C FLY and the upper balancing capacitor C FLY_BAL_T When connected in parallel, the voltage V at the upper plate node CP is... CP Rise to input voltage V IN The voltage V at the switching node SW SW Maintain from input voltage V IN Subtract the flying capacitor C FLY voltage V CFLY The obtained value V IN - V CFLY And the value V IN - V CFLY Approximately 0. Furthermore, the voltage V at the base plate node CN... CN Rise to from input voltage V IN Subtract the flying capacitor C FLY voltage V CFLY The obtained value V IN - V CFLY And this value is approximately 0, the current I of inductor L L Maintain a certain value.

[0058] Next, after the fifth time period, during the sixth time period (which is the same as the fifth time period), the second switch Q... B Fourth switch Q D and balance switch Q BAL1 and Q BAL2 On, the first switch Q A and the third switch Q C Disconnect, thus bypassing capacitor C FLY and bottom balancing capacitor C FLY_BAL_B When connected in parallel, the voltage V at the upper plate node CP is... CP The voltage drops to the output voltage VOUT Add flying capacitor C FLY voltage V CFLY The obtained value V OUT + V CFLY This value is approximately 0, and the voltage V at the switching node SW is... SW To achieve the output voltage V OUT Add flying capacitor C FLY voltage V CFLY The obtained value V OUT + V CFLY The value V OUT + V CFLY Approximately 0. The voltage V at the base plate node CN is... CN Drop to output voltage V OUT The current I in inductor L L Maintain a certain value.

[0059] For example, in a three-level buck-boost converter according to an embodiment of the present invention, when the duty cycle D is approximately greater than 0.5, 1) during the seventh time period, the first switch Q... A Third switch Q C and balance switch Q BAL1 and Q BAL2 The second switch Q is turned on. B and the fourth switch Q D Disconnect, thus bypassing capacitor C FLY and the upper balancing capacitor C FLY_BAL_T Parallel connection, 2) After the seventh time period, during the eighth time period following the seventh time period, the first switch Q A Second switch Q B The third switch Q is turned on. C Fourth switch Q D and balance switch Q BAL1 and Q BAL2 3) After the eighth time period, during the ninth time period, which is the same as the seventh time period, the second switch Q is disconnected. B Fourth switch Q D and balance switch Q BAL1 and Q BAL2 On, the first switch Q A and the third switch Q C Disconnect, thus bypassing capacitor C FLY and bottom balancing capacitor C FLY_BAL_B Parallel connection, 4) After the ninth time period, during the tenth time period which is the same as the eighth time period, the first switch Q A Second switch Q B The third switch Q is turned on. C Fourth switch Q D and balance switch Q BAL1and Q BAL2 disconnect.

[0060] Such exemplary embodiments will be further referred to Figures 8 to 10 To provide a more detailed description.

[0061] Figure 8 This is an exemplary timing diagram illustrating an embodiment of the present invention when the duty cycle D is approximately greater than 0.5. Figure 9 This is a circuit diagram illustrating various operating modes according to an embodiment of the present invention when the duty cycle is approximately greater than 0.5. Figure 10 This is a simplified circuit diagram illustrating various operating modes according to an embodiment of the present invention when the duty cycle is approximately greater than 0.5.

[0062] Reference Figures 8 to 10 Priority is given to the first switch Q during the seventh time period. A Third switch Q C and balance switch Q BAL1 and Q BAL2 The second switch Q is turned on. B and the fourth switch Q D Disconnect, thus bypassing capacitor C FLY and the upper balancing capacitor C FLY_BAL_T When connected in parallel, the voltage at the upper plate node remains at the input voltage V. IN The voltage V at the switching node SW SW The voltage drops from the input voltage V IN Subtract the flying capacitor C FLY voltage V CFLY The obtained value V IN - V CFLY And the value V IN - V CFLY Approximating by the input voltage V IN Add output voltage V OUT The value obtained by dividing by 2 (V) IN + V OUT These values ​​are actually the same. Furthermore, the voltage V at the base plate node CN... CN Maintain from input voltage V IN Subtract the flying capacitor C FLY voltage V CFLY The obtained value V IN - V CFLY The current I in inductor L L Gradually decreasing.

[0063] Next, after the seventh time period, during the eighth time period (which is the same as the seventh time period), the first switch Q... A Second switch Q B The third switch Q is turned on.C Fourth switch Q D and balance switch Q BAL1 and Q BAL2 When disconnected, the voltage V at the upper plate node CP CP Maintain input voltage V IN The voltage V at the switching node SW SW Rise to from input voltage V IN The voltage V at node CN on the base plate CN Maintain from input voltage V IN Subtract the flying capacitor C FLY voltage V CFLY The obtained value V IN - V CFLY The current I in inductor L L Gradually rising.

[0064] Next, after the eighth time period, during the ninth time period, which is the same as the seventh time period, the second switch Q... B Fourth switch Q D and balance switch Q BAL1 and Q BAL2 On, the first switch Q A and the third switch Q C Disconnect, thus bypassing capacitor C FLY and bottom balancing capacitor C FLY_BAL_B When connected in parallel, the voltage V at the upper plate node CP is... CP Drop to the flying capacitor C FLY voltage V CFLY The value V obtained by adding the output voltage VOUT CFLY + V OUT The voltage V at the switching node SW SW Drop to the flying capacitor C FLY voltage V CFLY Add output voltage V OUT The obtained value V CFLY + V OUT The value V CFLY + V OUT Approximating by the input voltage V IN Add output voltage V OUT The value obtained by dividing by 2 (V) IN + V OUT These values ​​are actually the same. Furthermore, the voltage V at the base plate node CN... CN Drop to output voltage V OUT The current I in inductor L L Gradually decreasing.

[0065] Next, after the ninth time period, during the tenth time period (the same as the eighth time period), the first switch Q... A Second switch Q B The third switch Q is turned on. C Fourth switch Q D and balance switch Q BAL1 and Q BAL2 When disconnected, the voltage V at the upper plate node CP CP and the voltage V of the switching node SW SW Rise to from input voltage V IN The voltage V at node CN on the base plate CN Rise to from input voltage V IN Subtract the flying capacitor C FLY The value V obtained by VCFLY voltage IN - V CFLY The current I in inductor L L Gradually rising.

[0066] As described above, according to this disclosure, by using a simple circuit in a three-level buck-boost converter to achieve flying capacitor voltage equalization, the voltage across the switch can be applied uniformly, and the inductor current ripple can be reduced to improve efficiency.

[0067] In addition, it has the effect of achieving high-speed capacitor voltage balance.

[0068] According to this disclosure, by using a simple circuit in a three-level buck-boost converter to achieve flying capacitor voltage equalization, the voltage across the switch can be applied uniformly, and the inductor current ripple can be reduced to improve efficiency.

[0069] In addition, it has the effect of achieving high-speed capacitor voltage balance.

[0070] Although a three-level buck-boost converter with a flying capacitor voltage balancing circuit has been described with reference to specific embodiments, the present invention is not limited thereto. Therefore, those skilled in the art will readily understand that various modifications and alterations can be made without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A three-level buck-boost converter, the three-level buck-boost converter comprising a flying capacitor voltage equalization circuit, including: An inductor, wherein the inductor is connected in series between the switching node and the ground terminal; An output capacitor is connected between the output terminal for outputting the output voltage and the ground terminal. The first switch is connected between the input terminal for input voltage input and the node on the upper plate. A second switch is connected between the upper plate node and the switch node; A third switch is connected between the switch node and the base plate node; A fourth switch is connected between the base plate node and the output terminal; A flying capacitor is connected between the upper plate node and the bottom plate node; A balance switch, wherein the balance switch is connected between the switch node and the balance node; Upper balancing capacitor, the upper balancing capacitor being connected between the input terminal and the balancing node; and A bottom balancing capacitor is connected between the balancing node and the output terminal.

2. The three-level buck-boost converter according to claim 1, wherein, The flying capacitor is connected in parallel with the upper balancing capacitor for a portion of the time during the operation of the three-level buck-boost converter, and in parallel with the bottom balancing capacitor for another portion of the time during the operation of the three-level buck-boost converter.

3. The three-level buck-boost converter according to claim 2, wherein, The voltages of the flying capacitor, the upper balancing capacitor, and the bottom balancing capacitor have the same value.

4. The three-level buck-boost converter according to claim 3, wherein, The voltage of the flying capacitor, the voltage of the upper balancing capacitor, and the voltage of the bottom balancing capacitor are maintained at the value obtained by subtracting the output voltage from the input voltage and then dividing by 2.

5. The three-level buck-boost converter according to claim 1, wherein, When the duty cycle D is less than 0.5, During the first period, the first switch, the third switch, and the balancing switch are turned on, while the second switch and the fourth switch are turned off, thereby connecting the flying capacitor and the upper balancing capacitor in parallel. After the first time period, during the second time period following the first time period, the third switch and the fourth switch are turned on, while the first switch, the second switch, and the balance switch are turned off. After the second time period, during a third time period identical to the first time period, the second switch, the fourth switch, and the balance switch are turned on, while the first switch and the third switch are turned off, thereby connecting the flying capacitor and the bottom balance capacitor in parallel. After the third time period, during the fourth time period which is the same as the second time period, the third switch and the fourth switch are turned on, and the first switch, the second switch and the balance switch are turned off.

6. The three-level buck-boost converter according to claim 1, wherein, When the duty cycle D is 0.5, During the fifth time period, the first switch, the third switch, and the balancing switch are turned on, while the second switch and the fourth switch are turned off, thereby connecting the flying capacitor and the upper balancing capacitor in parallel. After the fifth time period, during the sixth time period which is the same as the fifth time period, the second switch, the fourth switch, and the balance switch are turned on, and the first switch and the third switch are turned off, so that the flying capacitor and the bottom balance capacitor are connected in parallel.

7. The three-level buck-boost converter according to claim 1, wherein, When the duty cycle D is greater than 0.5, During the seventh time period, the first switch, the third switch, and the balancing switch are turned on, while the second switch and the fourth switch are turned off, thereby connecting the flying capacitor and the upper balancing capacitor in parallel. After the seventh time period, during the eighth time period following the seventh time period, the first switch and the second switch are turned on, while the third switch, the fourth switch, and the balance switch are turned off. After the eighth time period, during the ninth time period (the same as the seventh time period), the second switch, the fourth switch, and the balance switch are turned on, while the first switch and the third switch are turned off, thereby connecting the flying capacitor and the bottom balance capacitor in parallel. After the ninth time period, during the tenth time period, which is the same as the eighth time period, the first switch and the second switch are turned on, and the third switch, the fourth switch and the balance switch are turned off.

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