Systems and methods for improving power converter efficiency using common-source, cascode power stages

Abstract

The present invention provides a circuit. In one aspect, the circuit includes a first power stage and a second power stage. The first power stage includes a first switch having a first gate terminal, a first drain terminal, and a first source terminal, and a second switch having a second gate terminal, a second drain terminal, and a second source terminal, the first source terminal being coupled to the second drain terminal. The second power stage includes a third switch having a third gate terminal, a third drain terminal, and a third source terminal, and a fourth switch having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, the third source terminal being coupled to the fourth drain terminal. The second power stage is coupled in parallel to the first power stage such that the first drain terminal is coupled to the third drain terminal, and the second source terminal is connected to the fourth source terminal.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 292,359, filed December 21, 2021, entitled “Systems and Methods for Improved Efficiency in a Power Converter Using Cascode Power Stages,” which is incorporated herein by reference in its entirety for all purposes. Technical Field

[0003] The described implementation generally relates to power converters, and more specifically, this implementation relates to systems and methods for improving the efficiency of power converters using common source and common gate power stages. Background Technology

[0004] Today, consumers have access to a wide variety of electronic devices. Many of these devices feature integrated circuits powered by regulated low-voltage DC power supplies. These low-voltage supplies are typically generated by dedicated power converter circuits that use a higher voltage input from a battery or other power source. In some applications, the dedicated power converter circuit can be one of the largest power dissipation components in an electronic device, and sometimes it consumes more space than the integrated circuit that powers it. As electronic devices become more complex and compact, there is a growing need for more efficient power converter circuits. Summary of the Invention

[0005] In some embodiments, a power converter circuit is disclosed. The power converter circuit includes: a first power stage including a first switch having a first gate terminal, a first drain terminal, and a first source terminal, and a second switch having a second gate terminal, a second drain terminal, and a second source terminal, the first source terminal coupled to the second drain terminal; a second power stage including a third switch having a third gate terminal, a third drain terminal, and a third source terminal, and a fourth switch having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, the third source terminal coupled to the fourth drain terminal, wherein the second power stage is coupled in parallel to the first power stage such that the first drain terminal is coupled to the third drain terminal, and the second source terminal is connected to the fourth source terminal; an input terminal coupled to a first terminal of an impedance element; an output terminal coupled to a second terminal of the impedance element and the first drain terminal and the third drain terminal; and a control circuit arranged to couple the first gate terminal to a DC bias during a first state and to the first source terminal during a second state.

[0006] In some implementations, the first power stage and the second power stage control the power transfer from the input terminal to the output terminal.

[0007] In some implementations, the first state is a full-load condition, wherein the first power stage and the second power stage transfer power from the input terminal to the output terminal.

[0008] In some implementations, the second state is a light load condition, in which the second power stage transfers power from the input terminal to the output terminal.

[0009] In some embodiments, the control circuitry is arranged to connect the second gate terminal to the second source terminal during the second state.

[0010] In some implementations, the first power stage and the second power stage are arranged to generate an output voltage at the output terminal that is lower than the voltage at the input terminal.

[0011] In some embodiments, a method of operating a power converter circuit is disclosed. The method includes: providing a first power stage including a first switch having a first gate terminal, a first drain terminal, and a first source terminal, and a second switch having a second gate terminal, a second drain terminal, and a second source terminal, the first source terminal coupled to the second drain terminal; providing a second power stage including a third switch having a third gate terminal, a third drain terminal, and a third source terminal, and a fourth switch having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, the third source terminal coupled to the fourth drain terminal, wherein the second power stage is coupled in parallel to the first power stage such that the first drain terminal is coupled to the third drain terminal, and the second source terminal is connected to the fourth source terminal; providing an input terminal coupled to a first terminal of an impedance element; providing a second terminal coupled to the impedance element and an output terminal coupled to the first drain terminal and the third drain terminal; and using control circuitry to couple the first gate terminal to a DC bias during a first state and to the first source terminal during a second state.

[0012] In some implementations, the method further includes using the first power stage and the second power stage to control power transfer from the input terminal to the output terminal.

[0013] In some implementations, the first state is a full-load condition, wherein the first power stage and the second power stage transfer power from the input terminal to the output terminal.

[0014] In some implementations, the second state is a light load condition, in which the second power stage transfers power from the input terminal to the output terminal.

[0015] In some embodiments, the method further includes, during the second state, using the control circuitry to connect the second gate terminal to the second source terminal.

[0016] In some embodiments, the method further includes using the first power stage and the second power stage to generate an output voltage at the output terminal that is lower than the voltage at the input terminal.

[0017] In some embodiments, a circuit is disclosed. The circuit includes: a first power stage including a first switch having a first gate terminal, a first drain terminal, and a first source terminal, and a second switch having a second gate terminal, a second drain terminal, and a second source terminal, the first source terminal coupled to the second drain terminal; a second power stage including a third switch having a third gate terminal, a third drain terminal, and a third source terminal, and a fourth switch having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, the third source terminal coupled to the fourth drain terminal, wherein the second power stage is coupled in parallel to the first power stage such that the first drain terminal is coupled to the third drain terminal, and the second source terminal is connected to the fourth source terminal; an input terminal coupled to a first terminal of a transistor; an output terminal coupled to a second terminal of the transistor and coupled to the first drain terminal and the third drain terminal; and a control circuit arranged to couple the first gate terminal to a DC bias during a first state and to the first source terminal during a second state.

[0018] In some implementations, the fourth gate terminal is arranged to receive a pulse width modulation (PWM) signal.

[0019] In some implementations, in response to receiving the PWM signal, the fourth switch is arranged to control the power transfer from the input terminal to the output terminal in the second state. Attached Figure Description

[0020] Figure 1 A DC-DC power converter circuit using a common-source, common-gate power stage according to an embodiment of this disclosure is shown; and

[0021] Figure 2 It is shown according to certain implementation schemes Figure 1 The equivalent circuit of a segment of the circuit is shown, illustrating the parasitic capacitance during light-load operating conditions. Detailed Implementation

[0022] The circuits and related techniques disclosed herein generally relate to power converters. More specifically, the circuits, apparatuses, and related techniques disclosed herein relate to systems and methods for improving the efficiency of power converters using cascode power stages. In some embodiments, a power converter, such as a DC-DC converter, may include cascode-connected switches, wherein each switch may be formed of multiple segments, and a portion of each segment may be disabled (or disconnected) to improve the efficiency of the power converter over a range of load currents. In various embodiments, the disclosed methods enable the use of disconnection techniques in power converters with cascode power stages. In some embodiments, the method for disconnecting portions of a switch segment allows for a reduction in the maximum voltage applied to the switch, thereby keeping the switch within its safe operating area (SOA) and improving reliability. The various inventive embodiments described herein include methods, processes, systems, apparatuses, etc.

[0023] Several illustrative embodiments will now be described with reference to the accompanying drawings, which form part of the embodiments. The following description provides embodiments only and is not intended to limit the scope, applicability, or configuration of this disclosure. In fact, the following description of the embodiments will provide an enlightening description for those skilled in the art to implement one or more embodiments. It should be understood that various changes can be made to the function and arrangement of elements without departing from the spirit and scope of this disclosure. In the following description, specific details are set forth for illustrative purposes to provide a thorough understanding of certain inventive embodiments. However, it will be apparent that various embodiments can be practiced without these specific details. The drawings and descriptions are not intended to be restrictive. The terms “example” or “exemplary” are used herein to mean “serving as an example, illustration, or description.” Any embodiment or design described herein as “exemplary” or “example” should not be construed as preferred or advantageous relative to other embodiments or designs.

[0024] Figure 1 A DC-DC power converter circuit 100 using a common-source, common-gate power stage is shown according to an embodiment of this disclosure. Figure 1As shown, a DC-DC power converter circuit 100 may include a first power stage 102 and a second power stage 104 coupled in parallel. In various embodiments, the circuit 100 may include three or more parallel-coupled segments. The first power stage 102 may be coupled to the second power stage 104 at nodes 143 and 141. Each of the first stage 102 and the second stage 104 may include top switches 105 and 115, and bottom switches 110 and 120, respectively. Top switch 105 may have a gate terminal 190, a drain terminal 191, and a source terminal 193. Top switch 115 may have a gate terminal 171, a drain terminal 173, and a source terminal 177. Bottom switch 110 may have a gate terminal 111, a drain terminal 117, and a source terminal 119. Bottom switch 120 has a gate terminal 163, a drain terminal 167, and a source terminal 169.

[0025] Top switch 105 may be coupled to bottom switch 120 in a cascode configuration. Top switch 115 may be coupled to bottom switch 120 in a cascode configuration. In some embodiments, top switches 105 and 115 may be identical in size and other electrical characteristics, while bottom switches 110 and 120 may be identical in size and other electrical characteristics. In various embodiments, the top and bottom switches may have different sizes and different electrical characteristics. Power converter circuit 100 may include input terminal 135 and output terminal 145. Input terminal 135 may be arranged to have a power supply V. dd In some implementations, output terminal 145 may be coupled to an inductor. Node 143 may be coupled to the power supply V via impedance element 130. dd In some implementations, node 143 can be coupled to power supply V via a switch. dd The switch is such as, but not limited to, a metal-oxide-semiconductor field-effect transistor (MOSFET). In various embodiments, the impedance element 130 may be a resistor. Node 141 may be coupled to ground 140. Circuit 100 may provide an output voltage (V) at output terminal 145. out Circuit 100 may further include a first control circuit 106 coupled to the top switch 105 and a second control circuit 108 coupled to the bottom switch 110. In some embodiments, the first control circuit 106 and the second control circuit 108 may be integrated to form a single control circuit. Switch 185 may be coupled to gate terminal 190. Switch 185 may be controlled by a signal high-load 122 and may be arranged to connect gate terminal 190 to node 170 or node 189. Node 170 may have a DC bias voltage. Node 189 may be coupled to node 125, which is connected to source terminal 193.

[0026] During full-load operating conditions, the power converter circuit 100 can generate power at output terminal 145 using both the first power stage 102 and the second power stage 104. Full-load conditions may also be referred to as high-load conditions. During light-load operating conditions, the power converter circuit 100 can disconnect (or disable) one of the first power stage 102 and the second power stage 104 to improve efficiency, since most power loss during light-load conditions is due to switching losses of switches 105, 110, 115, and 120. Disconnecting the stage during light-load operating conditions reduces switching losses, thereby improving the efficiency of the power converter 100. In the first power stage 102, the top switch 105 and the bottom switch 110 can be coupled in a cascode configuration. In this way, the top switch 105 and the bottom switch 110 can be coupled in series, such that each switch supports a portion of the supply voltage from its drain terminal to its source terminal. The sum of the voltages across the drain and source terminals may exceed the voltage that any single switch can withstand; that is, the sum of the voltages across the drain and source terminals may be outside the safe operating area (SOA) of each switch. Prolonged operation outside the SOA may lead to reliability issues and switch damage. Similarly, in the second power stage 104, the top switch 115 and the bottom switch 120 are arranged in a cascode configuration such that each switch supports a portion of the supply voltage across its drain and source terminals.

[0027] Switch 185 can be controlled by a high-load signal 122. The high-load signal 122 can be high when the power converter operates under high-load conditions and low when the power converter operates under light-load conditions. Under high-load operating conditions, gate terminal 190 can be connected to node 170 and has a DC bias voltage. Gate terminal 171 can be connected to node 170 and has a DC bias voltage. Therefore, both gate terminals of the top switch can be connected to the DC bias voltage. The gate of the bottom switch 110 can be connected to the output node of AND gate 150, wherein the first input node 155 of AND gate 150 can be arranged to receive the switch signal 118, and the second input node 160 of AND gate 150 can be arranged to receive the high-load signal 122. In some embodiments, the switch signal 118 can be a pulse-width modulated (PWM) signal.

[0028] During high load conditions, signal high_load 122 can be in a high state. Therefore, AND gate 150 can pass switching signal 118 to gate terminal 111. Thus, bottom switch 110 can switch under high load conditions. Gate terminal 163 can also be coupled to terminal 165, which is arranged to receive switching signal 118, so bottom switch 120 can also switch during high load conditions. Therefore, both bottom switches 110 and 120 can switch during high load conditions. In this way, the effective on-resistance (Rdson) of the bottom switches can be minimized because bottom switches 110 and 120 are arranged in parallel. Furthermore, the maximum voltage across each power stage segment can be divided between its top switch and its bottom switch, i.e., each of switches 105 / 110 and 115 / 120 can not experience a voltage exceeding its rated safe operating area (SOA).

[0029] During light-load operating conditions, the first power stage segment 102 can be disconnected (disabled) to improve the efficiency of the power converter. During light-load conditions, the high-load signal 122 is low, so the switch signal 118 cannot pass through the AND gate 150. With the high-load signal 122 low, switch 185 can disconnect the gate terminal 190 from node 170 and connect the gate terminal 190 to node 125 coupled to the source terminal 193. Therefore, the first power stage segment 102 can be disabled, while segment 104 can continue to operate. By connecting the gate terminal 190 to node 125, the gate terminal 190 is connected to a high-impedance node. The voltage Vx at node 125 can be determined by the relative magnitudes of the drain-to-source leakage currents of the top switch 105 and the bottom switch 110. For example, if the drain-to-source leakage current of the top switch 105 is greater than that of the bottom switch 110, then the voltage at node 125 can be directed towards the power supply Vx. dd The voltage at node 125 increases, causing a decrease in the drain-to-source voltage of the top switch 105, which in turn reduces the drain-to-source leakage current of the top switch 105. Simultaneously, the drain-to-source voltage of the bottom switch 110 increases, resulting in an increase in the leakage current of the bottom switch 110. Therefore, the voltage (Vx) at node 125 decreases and shifts towards the midpoint through this feedback loop until equilibrium is reached. In this way, the equilibrium voltage (Vx) at node 125 can be below the gate-to-drain breakdown voltages of both the top switch 105 and the bottom switch 110.

[0030] During light load conditions, the top switch 105 can be turned off because its gate terminal is connected to its source. Figure 2 The equivalent circuit of the first power stage segment 102 is shown, along with the parasitic capacitance during light load conditions. (See diagram below.) Figure 2As can be seen, during light load conditions, gate terminal 190 can be coupled to node 125, and gate terminal 111 of bottom switch 110 can be connected to its source at ground 140. Because no channel is formed in top switch 105, the drain-to-gate parasitic capacitance 159 of top switch 105 can be relatively small. In this way, the parasitic capacitance at output terminal 145 can be minimized, resulting in improved efficiency of power converter circuit 100. This is because when V out As the circuit oscillates from rail to rail, output terminal 145 is charged and discharged. Therefore, the parasitic capacitance at output terminal 145 significantly affects the efficiency of the power converter circuit 100. The parasitic capacitance at output terminal 145 increases with V... out The energy stored in the parasitic capacitance at output terminal 145 is dissipated as heat as the energy generated by the rail-to-rail oscillation during charging and discharging, directly affecting efficiency. Furthermore, the output voltage V at output terminal 145... out It can repeatedly swing from Vdd to ground, and in the case where the switch is implemented as a MOSFET device, as V... out Grounding, node Vx can be clamped to ground-V diode voltage (V) diode This is the voltage across the parasitic diode between the drain and substrate of the MOSFET (where the substrate is connected to the source). V diode The value can be, for example, 0.7V. Therefore, the voltage V... diode It is maintained across the gate-to-source parasitic capacitance of the top switch 105. When V out When it swings to Vdd, V x It can move towards the equilibrium point, and the voltage across the gate-source capacitor of the top switch 105 becomes V. dd -V x Therefore, in each switching cycle, the voltage change across the gate-source capacitor of the top switch 105 is V. dd -V x -V diode .

[0031] As described above, in some embodiments, during light load conditions, the gate terminal of the top switch 105 is connected to its source. This prevents the formation of a channel in the top switch 105 and makes the parasitic capacitance of the top switch 105 relatively small, thereby improving the efficiency of the power converter 100. Furthermore, the drain-to-source parasitic capacitance 157 of the bottom switch 110 is connected in series with the drain-to-gate parasitic capacitance 159 of the top switch 105, resulting in a smaller total parasitic capacitance of the combined parasitic capacitances of the top switch 105 and the bottom switch 110. In this way, the parasitic capacitance at the output terminal 145 can be minimized.

[0032] Embodiments of this disclosure can also reduce power supply leakage current, thereby improving the efficiency of the power converter. For example, when the bottom switch 110 is off, the leakage current of the power converter can be limited to the maximum leakage current that may be achieved through the combination of the top switch 105 and the bottom switch 110. In some embodiments, the top switch 105 can be implemented with a relatively small size, so that a relatively low leakage current can flow through the top switch 105, thus limiting the leakage current that can flow from the power supply V. dd The leakage current flows to ground 140.

[0033] As will be understood by those skilled in the art who benefit from this disclosure, the gate of the top switch 105 may be connected to its source via, for example, a switching element (such as a MOSFET, resistor, diode, or diode-connected MOSFET) or other active circuitry (such as an amplifier or follower circuitry). In various embodiments, a DC bias voltage may be generated such that it is higher than ground voltage, but not high enough to make the top switch 105 conduct under any circumstances, nor low enough to exceed the gate-to-drain breakdown voltage of the top switch 105.

[0034] While the primary application of the disclosed technology has been shown herein as its use in power stages, the disclosed technology is applicable to any cascode device that will turn off with minimal leakage or in a manner that minimizes parasitic capacitance at the drain node of its switches. Furthermore, different sized switches can be used dynamically to vary the gain of the power stage, the switching speed of the power stage, or to allow for low-current standby modes.

[0035] In some embodiments, the described switch may be formed in silicon or any other semiconductor material. In various embodiments, the described switch may be a transistor. In some embodiments, the described switch may be a metal-oxide-semiconductor field-effect transistor (MOSFET). In some embodiments, the MOSFET may be entirely formed within a single die. In some embodiments, the disclosed power converter may be monolithically integrated onto a single die. In various embodiments, the top switch and bottom switch may be formed on separate individual dies. In some embodiments, the top switch and bottom switch, along with logic and control circuitry, and any combination thereof, may be grouped and formed on separate dies. In various embodiments, the top switch and bottom switch, along with logic and control circuitry, may all be integrated into an electronic package, such as, but not limited to, a quad flat no-lead (QFN) package, a dual flat no-lead (DFN) package, or a ball grid array (BGA) package.

[0036] Although this document describes and illustrates systems and methods for improving the efficiency of power converters using cascode power stages with regard to a specific configuration of DC-DC power converter circuits, embodiments of this disclosure are suitable for use with other configurations of power converters. For example, embodiments of this disclosure can be used in multiphase DC-DC power converter circuits to cut off (disable) a portion of the power stage for more efficient operation.

[0037] In the foregoing description, embodiments of this disclosure have been described with reference to numerous specific details that may vary with particular implementation. Therefore, the description and drawings are to be considered illustrative rather than restrictive. The unique and exclusive measure of the scope of this disclosure, and what the applicant intends to be the scope of this disclosure, is the literal and equivalent scope of the set of claims published in this application, including any subsequent amendments in the specific form of such claim publication. Specific details of particular embodiments may be combined in any suitable manner without departing from the spirit and scope of embodiments of this disclosure.

[0038] Additionally, spatially relative terms such as “bottom” or “top” may be used to describe the relationship of an element and / or feature to another element and / or feature, for example, as shown in the figures. It will be understood that, in addition to the orientation depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use and / or operation. For example, if the device in the figures is flipped, an element described as the “bottom” surface may be oriented “above” other elements or features. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein shall be interpreted accordingly.

[0039] As used herein, the terms “and,” “or,” and “and / or” can have a variety of meanings, which are expected to depend at least in part on the context in which such terms are used. Generally, when used in relation to a list such as A, B, or C, “or” is intended to mean A, B, and C, used herein in an inclusive sense; and A, B, or C, used herein in an exclusive sense. Additionally, the term “one or more” as used herein can be used to describe any feature, structure, or characteristic in the singular, or to describe a combination of features, structures, or characteristics. However, it should be noted that this is merely an illustrative example, and the claimed subject matter is not limited to this example. Furthermore, when used in relation to a list such as A, B, or C, the term “at least one of…” can be interpreted as meaning any combination of A, B, and / or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

[0040] Throughout this specification, references to “an example,” “an instance,” “some instances,” or “exemplary implementation” mean that a particular feature, structure, or characteristic described in connection with a feature and / or instance may be included in at least one feature and / or instance of the claimed subject matter. Therefore, the appearance of the phrases “in one instance,” “an instance,” “in some instances,” or “in some implementations,” or other similar phrases throughout this specification does not necessarily refer to the same feature, instance, and / or limitation. Furthermore, a particular feature, structure, or characteristic may be combined in one or more instances and / or features.

[0041] In the foregoing detailed description, numerous specific details have been set forth to provide a thorough understanding of the claimed subject matter. However, those skilled in the art will understand that the claimed subject matter can be practiced without these specific details. In other instances, methods and apparatus known to those of ordinary skill have not been described in detail to avoid obscuring the claimed subject matter. Therefore, it is intended that the claimed subject matter be limited to the specific examples disclosed, but rather that it may also include all aspects falling within the scope of the appended claims and their equivalents.

Claims

1. A power converter circuit, the power converter circuit comprising: A first power stage, the first power stage including a first switch having a first gate terminal, a first drain terminal and a first source terminal, and a second switch having a second gate terminal, a second drain terminal and a second source terminal, the first source terminal being coupled to the second drain terminal; The second power stage includes a third switch having a third gate terminal, a third drain terminal, and a third source terminal, and a fourth switch having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, the third source terminal being coupled to the fourth drain terminal, wherein the second power stage is coupled in parallel to the first power stage such that the first drain terminal is coupled to the third drain terminal, and the second source terminal is connected to the fourth source terminal. An input terminal, said input terminal being coupled to a first terminal of an impedance element; An output terminal, which is coupled to a second terminal of the impedance element and to the first drain terminal and the third drain terminal; as well as A control circuit is arranged to couple the first gate terminal to a DC bias during a first state and to the first source terminal during a second state.

2. The power converter circuit of claim 1, wherein the first power stage and the second power stage control the power transfer from the input terminal to the output terminal.

3. The power converter circuit of claim 1, wherein the first state is a full load condition, wherein the first power stage and the second power stage transmit power from the input terminal to the output terminal.

4. The power converter circuit of claim 1, wherein the second state is a light load condition, wherein the second power stage transfers power from the input terminal to the output terminal.

5. The power converter circuit of claim 1, wherein the control circuit is arranged to connect the second gate terminal to the second source terminal during the second state.

6. The power converter circuit of claim 1, wherein the first power stage and the second power stage are arranged to generate an output voltage at the output terminal that is lower than the voltage at the input terminal.

7. A method of operating a power converter circuit, the method comprising: A first power stage is provided, the first power stage including a first switch having a first gate terminal, a first drain terminal and a first source terminal, and a second switch having a second gate terminal, a second drain terminal and a second source terminal, the first source terminal being coupled to the second drain terminal; A second power stage is provided, the second power stage including a third switch having a third gate terminal, a third drain terminal and a third source terminal, and a fourth switch having a fourth gate terminal, a fourth drain terminal and a fourth source terminal, the third source terminal being coupled to the fourth drain terminal, wherein the second power stage is coupled in parallel to the first power stage such that the first drain terminal is coupled to the third drain terminal and the second source terminal is connected to the fourth source terminal; Provides an input terminal that is coupled to the first terminal of the impedance element; A second terminal coupled to the impedance element and an output terminal of the first drain terminal and the third drain terminal are provided; as well as Using control circuitry, the first gate terminal is coupled to a DC bias during a first state and to the first source terminal during a second state.

8. The method of claim 7, further comprising using the first power stage and the second power stage to control power transfer from the input terminal to the output terminal.

9. The method of claim 7, wherein the first state is a full load condition, wherein the first power stage and the second power stage transmit power from the input terminal to the output terminal.

10. The method of claim 7, wherein the second state is a light load condition, wherein the second power stage transfers power from the input terminal to the output terminal.

11. The method of claim 7, further comprising, during the second state, using the control circuitry to connect the second gate terminal to the second source terminal.

12. The method of claim 7, further comprising using the first power stage and the second power stage to generate an output voltage at the output terminal that is lower than the voltage at the input terminal.

13. A circuit, the circuit comprising: A first power stage, the first power stage including a first switch having a first gate terminal, a first drain terminal and a first source terminal, and a second switch having a second gate terminal, a second drain terminal and a second source terminal, the first source terminal being coupled to the second drain terminal; The second power stage includes a third switch having a third gate terminal, a third drain terminal, and a third source terminal, and a fourth switch having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, the third source terminal being coupled to the fourth drain terminal, wherein the second power stage is coupled in parallel to the first power stage such that the first drain terminal is coupled to the third drain terminal, and the second source terminal is connected to the fourth source terminal. An input terminal, said input terminal being coupled to a first terminal of the transistor; An output terminal, which is coupled to a second terminal of the transistor and to the first drain terminal and the third drain terminal; as well as A control circuit is arranged to couple the first gate terminal to a DC bias during a first state and to the first source terminal during a second state.

14. The circuit of claim 13, wherein the first power stage and the second power stage control the power transfer from the input terminal to the output terminal.

15. The circuit of claim 13, wherein the first state is a full load condition, wherein the first power stage and the second power stage transfer power from the input terminal to the output terminal.

16. The circuit of claim 13, wherein the second state is a light load condition, wherein the second power stage transfers power from the input terminal to the output terminal.

17. The circuit of claim 13, wherein the control circuit is arranged to connect the second gate terminal to the second source terminal during the second state.

18. The circuit of claim 13, wherein the first power stage and the second power stage are arranged to generate an output voltage at the output terminal that is lower than the voltage at the input terminal.

19. The circuit of claim 13, wherein the fourth gate terminal is arranged to receive a pulse width modulation (PWM) signal.

20. The circuit of claim 19, wherein in response to receiving the PWM signal, the fourth switch is arranged to control power transfer from the input terminal to the output terminal in the second state.

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