Circuit arrangement, communication device and method for biasing a transistor stack

Abstract

The invention relates to a circuit arrangement, a communication device and a method for biasing a transistor stack. The circuit arrangement comprises a transistor stack and a biasing circuit comprising a replica circuit of the transistor stack, the circuit arrangement operating in at least an active mode and a standby mode, during operation in the active mode the biasing circuit generating an input gate bias voltage based on a reference current conducted through the replica circuit, the biasing circuit generating a bias voltage to a cascode transistor of the replica circuit, the bias voltage being substantially equal to a bias voltage to a corresponding cascode transistor of the transistor stack during operation in the active mode and during operation in the standby mode, and the biasing circuit generating a bias voltage to the cascode transistor of the replica circuit during operation in the standby mode, the bias voltage being substantially equal to the bias voltage to the cascode transistor of the replica circuit during operation in the active mode.

Description

[0001] This application is a divisional application of Chinese patent application filed on March 14, 2019, with application number 201780056671.1 and entitled "Standby Voltage Conditions for Fast RF Amplifier Bias Recovery". The international filing date of the parent application is September 8, 2017, the priority date is September 16, 2016, and the international application number is PCT / US2017 / 050839.

[0002] Cross-reference to related applications

[0003] This application claims priority to U.S. nonprovisional application 15 / 268,297, filed September 16, 2016, the entire contents of which are incorporated herein by reference.

[0004] This application may be related to U.S. Patent No. 7,248,120, published July 24, 2007, entitled "Stacked Transistor Method and Apparatus," the entire contents of which are incorporated herein by reference. This application may also be related to U.S. Application No. 2015 / 0270806A1, published September 24, 2015, entitled "Bias Control for Stacked Transistor Configuration," the entire contents of which are incorporated herein by reference. This application may also be related to U.S. Application No. 2014 / 0184336A1, published July 3, 2014, entitled "Amplifier Dynamic Bias Adjustment for Envelope Tracking," the entire contents of which are incorporated herein by reference. This application may also be related to U.S. Patent No. 9,219,445, entitled "Optimization Methods for Amplifiers with Variable Supply Power," published December 22, 2015, the entire contents of which are incorporated herein by reference. This application may also be related to U.S. Patent No. 8,487,706B2, entitled "Stacked Linear Power Amplifier with Capacitor Feedback and Resistor Isolation," published July 16, 2013, the entire contents of which are incorporated herein by reference. This application may also be related to U.S. Patent Application No. 14 / 945,323, entitled "Butted Body Contact for SOI Transistor," filed November 18, 2015, the entire contents of which are incorporated herein by reference. This application may also relate to U.S. Patent Application No. 15 / 078,930, filed March 23, 2016, entitled “Butted Body Contact for SOITransistor,” the entire contents of which are incorporated herein by reference. Technical Field

[0005] This application relates to amplifiers. Specifically, this application relates to gate biasing for an amplifier comprising stacked transistors capable of operating in active mode during RF signal transmission and in standby mode during non-transmission periods. Problems and solutions related to switching from standby mode operation to active mode operation are presented. Background Technology

[0006] In recent years, stacked cascode amplifiers, which use multiple transistors arranged in a stacked manner (stacked transistors) in the amplification stage of amplifiers, have become dominant in radio frequency (RF) applications where high power and high voltage output are desired. Due to the large number of transistors in the stack, the amplifier's voltage handling capability is improved, allowing for high power and high voltage output. Since the stacked transistors include individual low-voltage transistors that can tolerate voltages substantially lower than the amplifier's output voltage, it is important to bias the stacked low-voltage transistors to keep operation within their permissible voltage range. This voltage compliance of the stacked low-voltage transistors must be maintained whether the amplifier is operating in active mode (transmitting a signal) or in standby mode (not transmitting a signal). In cases where a scaled-down replica circuit of the stacked transistors used in the amplification stage is used to generate the bias voltage for the amplification stage, it may be desirable to reduce power consumption through this replica circuit and associated auxiliary circuitry during standby mode. However, there may be conflicting characteristics of the bias circuit that provides bias voltage to the stacked transistors between active mode operation and standby mode operation, such as, for example, the impedance presented to the gate of the stacked transistors during active operation mode, the power consumed in the bias circuit during standby operation mode, and the recovery speed of the bias voltage from standby mode operation to active mode operation. Summary of the Invention

[0007] The various teachings of this disclosure describe a bias circuit for providing a bias voltage for stacked transistors, the bias circuit having different characteristics between active and standby modes, while maintaining the voltage compliance of the stacked low-voltage transistors for safe operation in both operating modes, and enabling the bias voltage to recover quickly from operation in standby mode to operation in active mode.

[0008] According to a first aspect of this disclosure, a circuit arrangement is presented, comprising: a transistor stack configured to operate as an amplifier, the transistor stack including a plurality of stacked transistors including an input transistor and an output transistor, the transistor stack being configured to operate between a first supply voltage coupled to an output transistor and a reference voltage coupled to an input transistor; and a bias circuit including a replication circuit of the transistor stack, the bias circuit being configured to provide an input gate bias voltage to the input transistor and to a corresponding first transistor of the replication circuit, the replication circuit being configured to operate between a second supply voltage coupled to the last transistor in the replication circuit corresponding to the output transistor and a reference voltage coupled to the first transistor. A transistor operates between reference voltages, wherein the circuit arrangement is configured to operate in at least a first mode and a second mode, wherein during operation in the first mode, a bias circuit: couples the last transistor of the replication circuit to a second supply voltage by generating a reference current source, and adjusts the input gate bias voltage to conduct the reference current through the replication circuit, and wherein during operation in the second mode, the bias circuit: sets the input gate bias voltage to a voltage such that substantially no current is conducted through the replication circuit, deactivates the reference current source, and resistively couples the last transistor of the replication circuit to the second supply voltage.

[0009] According to a second aspect of this disclosure, a method for biasing a transistor stack using a replication circuit configured to operate as an amplifier is presented, the method comprising: during a first operating mode of the amplifier: generating a reference current via a current source; coupling a supply voltage to the replication circuit via the current source; adjusting the bias voltage of the input transistors of the transistor stack; and, based on the adjustment, conducting the reference current through the replication circuit; and during a second operating mode of the amplifier: setting the bias voltage to a fixed value such that substantially no current is conducted through the replication circuit; deactivating the current source; and resistively coupling the supply voltage to the replication circuit.

[0010] According to a third aspect of this disclosure, a circuit arrangement is presented comprising: a transistor stack configured to operate as an amplifier, the transistor stack including a plurality of stacked transistors including an input transistor and an output transistor; and a bias circuit including a replication circuit of the transistor stack, the bias circuit being configured to provide an input gate bias voltage to the input transistor and to a corresponding first transistor of the replication circuit, wherein the circuit arrangement is configured to operate in at least an active mode and a standby mode, in which the transistor stack amplifies a radio frequency (RF) signal, and in the standby mode, substantially no current is conducted through the transistor stack and the power consumption of the circuit arrangement is reduced, wherein during operation in the active mode, the bias circuit is configured to generate an input gate bias voltage based on a reference current conducted through the replication circuit, and wherein the bias circuit is configured to generate a bias voltage to the transistor of the replication circuit during both the active operation mode and the standby operation mode, the bias voltage being substantially equal to the bias voltage to the transistor of the transistor stack.

[0011] According to a fourth aspect of this disclosure, a method for biasing a transistor stack using a replication circuit configured to operate as an amplifier is presented, the method comprising: during an active amplification operation mode of the amplifier: adjusting a bias voltage to an input transistor of the transistor stack by conducting a reference current through the replication circuit; and providing a bias voltage to a transistor of the replication circuit substantially equal to the bias voltage provided to the transistor of the transistor stack; and during a standby operation mode of the amplifier: setting the bias voltage to the input transistor to a fixed value such that substantially no current is conducted through the replication circuit; and providing a bias voltage to a transistor of the replication circuit substantially equal to the bias voltage provided to the transistor of the transistor stack. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one or more embodiments of this disclosure and, together with the description of exemplary embodiments, serve to illustrate the principles and implementation of this disclosure.

[0013] Figure 1 A prior art implementation of a stacked transistor amplifier is shown, wherein a resistor ladder network is used to provide a bias voltage to the gate of the stacked transistors.

[0014] Figure 2 It shows the relationship with Figure 1 The prior art implementations depicted are similar to those of stacked transistor amplifiers, in which diode-connected resistors are used to reduce bias voltage variations, and gate capacitors are used so that the voltage at the gate of the stacked transistors can vary with the RF signal at the drain of the transistors.

[0015] Figure 3 An embodiment of a switchable bias circuit according to the present disclosure is shown, which can switch the impedance presented to the gate of a transistor while maintaining proper bias of the transistor.

[0016] Figure 4A and Figure 4B An exemplary embodiment of the source follower transistor circuit used in the switchable bias circuit of this disclosure is shown.

[0017] Figure 5 This demonstrates the use of the content of this disclosure. Figure 4A An exemplary source follower transistor circuit Figure 3 An exemplary implementation of the switchable bias circuitry in the example.

[0018] Figure 6 It shows when coupled to Figure 1 and Figure 2 The prior art implementation described herein is provided Figure 3 The impedance control element is the function of the switchable bias circuit described in this disclosure.

[0019] Figure 7 A switchable bias circuit according to this disclosure is shown, wherein different voltages are used to switch the bias circuit. Figure 6 The impedance control element depicted in the figure is similar to multiple impedance control elements that provide bias voltages to different stacked transistors.

[0020] Figure 8 A switchable bias circuit according to the present disclosure is shown, wherein two separate resistor ladder networks are used to provide different impedances to the gates of stacked transistors while maintaining proper bias of the transistors.

[0021] Figure 9A It shows in Figure 8 The switchable bias circuit uses a resistor ladder network, in which a transistor connected in series is inserted between two resistors in the ladder section.

[0022] Figure 9B It shows in Figure 9A An exemplary implementation of the switch (815) used in the resistive ladder network, wherein the FET transistor M92 is used as the switch.

[0023] Figure 10A A prior art embodiment of a simplified bias circuit for biasing the gate of the input transistor of a stacked transistor used in an amplification stage is shown, wherein a replication circuit is used in the bias circuit.

[0024] Figure 10BAn alternative prior art implementation of a simplified bias circuit for 10A is shown, wherein the number of stacked transistors in the replication circuit differs from the number of stacked transistors used in the amplification stage.

[0025] Figure 10C It shows Figure 10B An alternative to existing technology implementations with simplified bias circuitry, wherein the same supply voltage is provided to both the stacked transistors used in the amplification stage and the stacked transistors used in the replication circuit.

[0026] Figure 11 A simplified bias circuit according to an embodiment of the present disclosure is shown, wherein the voltage across the stacked transistors is maintained during standby operation mode so that the bias voltage to the gate of the input transistor can be quickly restored when switching to active mode.

[0027] Figure 12A and Figure 12B It shows Figure 11 An alternative configuration to the one described in the text, while providing the same functionality.

[0028] The same reference numerals and names in the various figures indicate the same elements. Detailed Implementation

[0029] Throughout this disclosure, embodiments and variations have been described for the purpose of illustrating the use and implementation of the inventive concept. These illustrative descriptions should be understood as examples presenting the inventive concept, and not as limiting the scope of the concept disclosed herein.

[0030] Figure 1 A simplified schematic diagram of a prior art stacked cascode (RF) amplifier (100) is shown. By way of example and not limitation, the stacked cascode amplifier (100) may include a stack of FET transistors (M1, M2, M3, M4) comprising an input transistor M1, a cascode transistor (M4, M3, M2), and an output transistor M4. An input RF signal RF is provided at the input terminal (120) of the amplifier (100). in The signal is transmitted to the gate of the input transistor M1 and amplified by the amplifier (100). The corresponding amplified output RF signal RF out A bypass capacitor (125, 135) is provided at the drain of the output transistor M4 and fed to the output of the amplifier (130). The bypass capacitors can be used to separate the low-frequency (e.g., DC) bias voltage supplied to the stack of transistors (transistor stack) from the RF signal. in Signals and RF out Signal decoupling. Supply voltage V CCThe inductor L supplies power to the drain of the output transistor M4, and a reference voltage (e.g., GND) is connected to the source of the input transistor M1. The bias voltage (V) at the gate of the cascode transistors (M4, M3, M2) is... G4 V G3 V G2 By coupling to the supply voltage V CC A resistor ladder network (R4, R3, R2, R1) is provided between the reference voltage GND and the reference voltage. The node (V) connecting any two resistors in the resistor ladder network (R4, R3, R2, R1) is provided. B4 V B3 V B2 The bias voltage (V) is provided by connecting the corresponding gates of the cascode transistors (M4, M3, M2) via series resistors (R14, R13, R12). G4 V G3 V G2 ).like Figure 1 It can be seen that the gate bias voltage V of the input transistor M1 is not provided by a resistor ladder network (R4, R3, R2, R1). G1 Alternatively, it can be done at node V. B1 A bias voltage is provided to the input transistor M1. For example, various bias circuits for generating such a gate voltage are described in, for example, in the above-cited U.S. Application No. 2015 / 0270806 and U.S. Application No. 2014 / 0184336 A1, which can be referenced... Figure 10A and Figure 11 The teachings described in this disclosure have been further modified.

[0031] Those skilled in the art will recognize that the FET transistors (M1, M2, M3, M4) are configured as a four-stage cascode amplifier. Stacked cascode amplifiers and methods for minimizing output signal distortion by, for example, biasing the individual gates of the transistors within the stack, are also described in other literature, such as the teachings of U.S. Patent No. 8,487,706B2 cited above. Those skilled in the art can apply these teachings to further details of multi-stage stacked transistors in a cascode configuration, wherein the stack of FET transistors comprises multiple transistors, not just four.

[0032] Although Figure 1 The amplifier (100) is shown to be supplied with a fixed voltage V. CCPower supply is provided, but other configurations in which the amplifier (100) has a variable supply voltage are also conceivable. In some exemplary configurations, the supply voltage may be a voltage regulator or a DC-DC converter. In other exemplary configurations, the supply voltage may be varied under the control of an external control signal. In some configurations, the control signal may be the input RF signal RF. in Or output RF signal out The function of the envelope signal. Detailed descriptions of apparatus and biasing methods for stacked transistor amplifiers operating according to a variable supply voltage can be found, for example, in U.S. Application No. 2014 / 0184336 A1, U.S. Application No. 2015 / 0270806A1, and U.S. Patent No. 9,219,445, all of which are incorporated herein by reference. Those skilled in the art will also appreciate that the amplifier's supply is in the form of a current source rather than the exemplary voltage source (e.g., V) discussed in this disclosure. CC The teachings of this disclosure also apply to such different supply configurations. The exemplary cases of fixed supply discussed in this disclosure should not be construed as limiting the scope of what the applicant considers the invention.

[0033] Although N-type MOSFETs are used to describe embodiments in this disclosure, those skilled in the art will recognize that other types of transistors, such as P-type MOSFETs and bipolar junction transistors (BJTs), can be used instead of or in combination with N-type MOSFETs. Furthermore, those skilled in the art will appreciate the advantages that stacking more than two transistors, such as three, four, five, or more transistors, provides for the voltage handling performance of the amplifier. This can be achieved, for example, using non-bulk silicon technologies such as silicon-on-insulator (SMI) technology. Typically, the individual devices in the stack can be constructed using CMOS, silicon germanium (SiGe), gallium arsenide (GaAs), gallium nitride (GaN), bipolar transistors, or any other known feasible semiconductor technologies and architectures. Additionally, different device sizes and types can be used within the stack of devices.

[0034] This disclosure describes apparatus and methods for biasing stacked transistor amplifiers, wherein the amplifier is configured to operate in an active mode for transmitting RF signals and in a standby mode for not transmitting signals. Such amplifiers can be used in mobile phones for current communication systems (e.g., WCMDA, LTE, WiFi, etc.), where amplification of signals with frequency content higher than 100 MHz and power levels higher than 50 mW is required. Such amplifiers can also be used to transfer power at a frequency to loads such as those indicated by: feedback networks used in delivering cable television services to consumers, cables or downstream splitters, the next amplifier in the RF chain at a cellular base station, or beamforming networks in a phased array radar system. Other suitable implementations of this disclosure can be found by those skilled in the art for lower frequency (e.g., audio) systems, such as audio drivers, high-bandwidth laser drivers, and the like. Therefore, it is contemplated that the teachings of this disclosure will also be extended to amplification of signals with frequency content lower than 100 MHz.

[0035] Further reference Figure 1 The amplifier (100) depicted in the figure has a bias voltage (V). G4 V G3 V G2 This allows each transistor in the stack (M4, M3, M2, M1) to be biased according to its voltage compliance. In other words, the voltage across any two ends of the transistor (e.g., gate, source, drain) is within the safe operating range of the transistor. Since transistor failure can be a statistical function of the voltage applied across the transistor, even if such a voltage is within the safe operating range, in some implementations it may be desirable to subject the stacked transistors to the same voltage range to provide the same expected lifetime (e.g., average time before failure) for each transistor in the stack. Therefore, the gate bias voltage (V G4 V G3 V G2 It can be configured to uniformly distribute the voltage V across the transistor stack in the stacked transistors (M4, M3, M2, M1). CC In other words, make the drain-source voltage V of each stacked transistor (M4, M3, M2, M1)... DS Basically equal to the supply voltage V CC One-quarter (1 / 4) of the provided voltage. This can be achieved, for example, as described in the published U.S. Application No. 2015 / 0270806A1 cited above, by biasing the gates of the transistors (M4, M3, M2) to the corresponding bias voltages (V). G4 V G3 V G2 ) equals V CC x 3 / 4+V GS VCC x 2 / 4+V GS and V CC x1 / 4+V GS To complete this, the entire contents of the public information disclosed in this application are incorporated herein by reference.

[0036] Those skilled in the art will understand that during the operation of the amplifier (100), the amplified RF signal at the drain of the output transistor (M4) can be substantially above V. CC The voltage level of the supply voltage. This means that if the gate voltage V of the output transistor M4... G4 Maintain the bias voltage level provided by the resistor ladder network (R4, R3, R2, R1) discussed above, and therefore the source of M4 remains at V. CC x 3 / 4+V GS Then the drain-source voltage V of the output transistor M4 DS It may be subjected to higher voltage offsets than the transistor's permissible voltage range.

[0037] Based on the above, due to the uneven voltage division at the drain of the output transistor M4 across the transistors (M4, M3, M2, M1), any one of the transistors may be subjected to a voltage exceeding the transistor's permissible voltage range (e.g., approaching or exceeding its limiting breakdown voltage). Therefore, it may be desirable to control the stress on the individual transistors in the stack. This can be achieved through methods such as... Figure 2 The stacked transistors (M4, M3, M2) are configured to float by inserting gate capacitors (C4, C3, C2). The values ​​of the gate capacitors are chosen so that the gate voltage can vary (float) with the RF signal at the drain of the respective transistor, thus achieving a change in voltage drop (e.g., V) across the respective transistor. DS The transistor's conduction is controlled by the voltage at its drain, thus enabling more efficient operation. Teachings on this floating technique—also known as a conduction control circuit—can be found in U.S. Patent No. 7,248,120, cited above, the entire contents of which are incorporated herein by reference.

[0038] because Figure 2The gate capacitors (C4, C3, C2) depicted allow RF signals to couple at the gates of transistors (M4, M3, M2). This coupling can negatively impact the operation of the bias circuitry provided by the resistor ladder network (R4, R3, R2, R1) because various harmonics of the RF signal (including those at lower frequencies) can alter the operating bias voltage provided by the bias circuitry. As those skilled in the art will understand, the RF signal and corresponding harmonics coupled at the gates of transistors (e.g., M4, M3, M2) can generate a small current that, when fed to the output impedance of the bias circuitry presented to the gates of the transistors, can generate a corresponding voltage at a frequency substantially lower than the frequency of the RF signal. Specifically, if the output impedance of the bias circuitry is sufficiently large, this small current can generate a sufficiently large low-frequency voltage that, when added to the bias voltage, negatively affects the operation of the amplifier. Since the output impedance of the bias circuitry is a function of the resistance values ​​of the resistors (R4, R3, R2, R1), reducing the frequency can be achieved by selecting such values ​​as small. Figure 2 The effect of RF coupling in the prior art amplifier (200) is depicted. Consequently, such small resistance values ​​of resistors (R4, R3, R2, R1) may require a higher resistance value (and subject to a higher level of RF coupling) compared to choosing a higher resistance value (and subjecting to a higher level of RF coupling). CC A higher bias current is used to provide the desired gate bias voltage for the transistors (M4, M3, M2). According to some embodiments, the impedance (e.g., resistance) of the bias circuit presented to the gate of the transistors (M4, M3, M2) is substantially the same, but other configurations in which the presented impedance is unbalanced are also possible.

[0039] Continue to refer to Figure 2The desire to reduce the coupling between the RF signal and the base circuitry of the generation transistors (M4, M3, M2) gate bias voltages in the amplifier (200) may increase the power consumption of the resistor ladder network (R4, R3, R2, R1). While this increase in power consumption may provide an advantage during the amplifier's active operation mode (due to reduced RF coupling from the higher impedance), it does not provide an advantage during standby operation mode. Since the amplifier (200) does not amplify in standby mode, there is no RF signal in the transistor stack (M4, M3, M2, M1), and therefore no coupling effect between the RF signal and the bias circuitry. However, during the amplifier's (200) standby operation mode, the bias voltage to the gates of the transistors (M4, M3, M2) must be maintained to keep the operation of the stacked transistors (M4, M3, M2, M1) within their permissible voltage range. Therefore, methods and apparatus are provided according to the teachings of this disclosure to reduce RF coupling effects with the bias circuit during the active operation mode of a stacked transistor amplifier and to reduce power consumption in the bias circuit during the standby operation mode of the stacked transistor amplifier, while maintaining the same gate bias voltage to the gates of the stacked transistors (e.g., M4, M3, M2) in both operating modes. Figure 2 As can be seen, the optional diode-connected transistor M10 is added to the resistor ladder network (R4, R3, R3, R1), which allows the node (V) to... B4 V B3 V B2 The voltage at point (V) can track process-dependent changes that may affect the characteristics of transistors (M4, M3, M2, M1). By selecting transistor M10, which connects this diode, to have the same characteristics as transistors (M4, M3, M2, M1), process-dependent changes can similarly affect the current-to-voltage response of transistors (M10, M4, M3, M2, M1), and thus make the node (V) B4 V B3 V B2 The voltage at that point can track such process changes.

[0040] Figure 3 It shows the relationship with Figure 2 The simplified schematic diagram depicts a stacked cascode amplifier (300) similar to the amplifier (200) described in this disclosure. According to embodiments of this disclosure, the stacked cascode amplifier (300) includes switchable biasing circuitry (e.g., R4, R3, R2, R1, 310, 315) capable of switching the impedance presented to the gates of the stacked transistors (M4, M3, M2) while maintaining proper bias of the transistors. It should be noted that, for clarity, in Figure 3The present disclosure describes only one switchable element (310, 315 associated with the gate of transistor M3) of the switchable bias circuit. Similarly, similar switchable elements (310, 315) can be provided for biasing transistors (M4, M2).

[0041] Figure 3 The switchable impedance elements (310, 315) include: an impedance transformation unit (310), which is coupled at its input node to a node V of a resistive ladder network (R4, R3, R2, R1). B3 And optionally, a diode-connected transistor M10. The impedance conversion unit (310) is coupled at its output node to the first switching node of the switch (315). The second switching node of the switch (315) is coupled to node V. B3 The common node of switch (315) is coupled to the gate of transistor M3 via resistor R13. The control signal Ctrl selectively controls the conduction path coupled to the common node of switch (315) between a conduction path including the output node of impedance transformation unit (310) and a conduction path excluding that output node. The same control signal Ctrl can be used to enable and disable the operation of impedance transformation unit (310). According to an exemplary embodiment, when disabled, no current flows through impedance transformation unit (310).

[0042] exist Figure 3 In the exemplary configuration depicted, the position of switch (315) is such that the common node of switch (315) couples the gate of transistor M3 to the output node of impedance switching unit (310), thus presenting the voltage and impedance at the output node of impedance switching unit (310) to the gate of transistor M3. In an alternative position of switch (315) (not shown), the common node of switch (315) couples the gate of transistor M3 to node V of the resistor ladder network (R4, R3, R2, R1). B3 Therefore, node V B3 The voltage and impedance at that point are presented to the gate of transistor M3.

[0043] According to an embodiment of this disclosure, the impedance transformation unit (310) is configured to transform the impedance at node V B3 The impedance of the resistive ladder network (R4, R3, R2, R1) presented at the point is converted to a lower impedance at the output node of the impedance transformation unit (310), while maintaining the impedance at the output node at node V. B3The voltage at the input node (connected to 310) is essentially the same. Therefore, regardless of the position of switch (315), the voltage presented to the gate of transistor M3 at the common node of switch (315) remains constant, while the impedance presented to the gate of transistor M3 at the common node of switch (315) is selectively configured to the node V B3 The lower impedance at the output node of the impedance conversion unit (310).

[0044] Therefore, based on the above, and in accordance with the contents of this disclosure Figure 3 The switchable bias circuit (R4, R3, R2, R1, 310, 315) depicted in the diagram enables the bias voltage to the gate of transistor M3 to remain the same even when the impedance of the resistive ladder network (R4, R3, R2, R1) is selectively coupled to / decoupled from the gate.

[0045] Further reference Figure 3 According to embodiments of the present disclosure, the control signal Ctrl of the amplifier (300) can be a digital control signal for controlling the amplifier (300) to operate in one of an active mode and a standby mode. Therefore, in order to operate the amplifier (300) in active operation mode, the control signal Ctrl can control the position of the switch (315) to connect the output node of the impedance switching unit (310) to the resistor R13, thereby presenting a low impedance and a desired bias voltage to the gate of the transistor M3. Alternatively, in order to operate the amplifier (300) in standby operation mode, the control signal Ctrl can control the position of the switch (315) to connect node V... B3 Connecting to resistor R13 presents a higher impedance and the same desired bias voltage to the gate of transistor M3. Those skilled in the art will appreciate many methods for controlling a cascode stack to operate in one of active or standby modes. According to an exemplary embodiment, the control signal Ctrl can control the generation at node V... B1 A bias circuit for biasing the gate of the input transistor M1 is used to turn off the input transistor to operate in standby mode. As described above, the entire contents of its disclosure, which are incorporated herein by reference, describe various biasing methods and apparatus for the input transistor M1.

[0046] Because in Figure 3 During the active operation mode of the amplifier (300), the gate of the transistor is connected to node V. B3 Isolation, therefore node V B3The impedance at the gate of transistor M3 will not affect the coupling of the RF signal. This allows the resistor values ​​in the resistor ladder network (R4, R3, R2, R1) to be chosen high enough to reduce the standby current (power consumption during standby mode) in the resistors, while (through node V) B3 The voltage at that point provides the desired gate bias voltage for transistor M3. Therefore, Figure 3 The switchable bias circuitry (R4, R3, R2, R1, 310, 315) of the stacked amplifier (300) depicted enables the maintenance of a desired bias voltage at the gate of transistor M3 during both operating modes of the amplifier (300), while presenting a low impedance to the gate during active operating mode to reduce RF coupling effects with the bias voltage and to reduce standby power consumption in the resistor ladder network. The same effect can be achieved by similar switching impedance elements (310, 315) providing bias for the gates of transistors (M2, M4), such as those described later. Figure 7 As depicted in the text.

[0047] Further reference Figure 3 The impedance transformation unit (310) is configured to connect to node V. B3 The input node provides high isolation between itself and its output node connected to the switch (315). Furthermore, as described above, the impedance transformation unit (310) is configured to present a low impedance at its output node and output at its output node the voltage (V) at its input node. B3 Equal voltage. Those skilled in the art will know of many ways to implement such a circuit. According to one exemplary embodiment, such as... Figure 4A and Figure 4B As shown, the source follower can be used as an impedance transformation unit (310).

[0048] Further reference Figure 4A Impedance conversion unit (310A) and Figure 4B The impedance transformation unit (310B) and the source follower circuit can be used to provide the function of a buffer circuit that buffers the node (V) connected at the input node (410). B4 V B3 V B2 Simultaneously, it transforms its impedance at the output node (420). Transistor M40 is configured as a source follower, wherein the drain of transistor M40 is connected to the supply voltage V. REG Furthermore, the source of transistor M40 is connected to current sink elements (R40, 425) via switch (415). Figure 4AIn an exemplary embodiment, the current sink element is a resistor (R40), the size of which is selected to obtain the desired current through the transistor M40, which determines the output impedance of the transistor M40, and thus the output impedance at the output node (420). Furthermore, according to the exemplary embodiment, the transistor M40 can have a low threshold voltage that is substantially equal to 0V, so the gate-source voltage drop of the transistor M40 is substantially equal to 0V (i.e., V0). GS =0V). In Figure 4A During the active operation mode of the impedance conversion unit (310A), switch (415) is closed to allow current to flow through resistor R40, and during the standby operation mode, switch (415) is opened to stop the current flow, and thus stop the power consumption through the impedance conversion unit (310A). The operation of the exemplary impedance conversion unit (310B) is similar to that of the element (310A), except that a current source (425) is used instead of resistor R40 as a means of absorbing the current through transistor M40. Since the current source (425) is inherently smaller in physical size than a resistor (e.g., R40), the current source allows the overall size of the circuit (310B) to be reduced compared to the circuit (310A).

[0049] Further reference Figure 4A Impedance conversion unit (310A) and Figure 4B The impedance conversion unit (310B) supplies voltage V. REG It can be related to the supply voltage V CC The voltage level is independent of the regulated voltage, or alternatively, it can be the supply voltage V. CC Functions, including V CC Those skilled in the art will recognize V REG The voltage level must conform to the voltage compliance of transistor M40 so that the transistor can operate within its permissible voltage range. This is due to the nodes (V) of the resistor ladder network (R4, R3, R2, R1). B4 V B3 V B2 The voltage at the input node (410) can be different, and therefore depends on the node (V) of the input node (410) coupled to the impedance transformation unit (310A, 310B). B4 V B3 V B2 ), supply voltage V REG The corresponding levels can be different, as described later. Figure 7 As shown.

[0050] Figure 5 It shows the use of Figure 4AA simplified schematic diagram of a stacked cascode amplifier (500) with an impedance transformation unit (310A). Those skilled in the art will recognize that the bias of the amplifier (500) is based on... Figure 3 The switchable bias discussed for the amplifier (300), wherein, Figure 3 The impedance transformation unit (310) is composed of about Figure 4A The source follower configuration (310A) discussed is used instead. As mentioned above, for clarity, Figure 5 The diagram shows only one such component (310A), which can similarly be supplied with different voltages V. REG A similar power supply component (310A) can also be coupled to the nodes (V) of the resistor ladder network (R4, R3, R2, R1). B4 V B3 V B2 Each node of the gate resistor is connected to its corresponding gate resistor (R14, R13, R12). As mentioned earlier, Figure 5 The four-level common source cascode configuration is merely an exemplary implementation of the present disclosure and should not be considered as limiting the scope of what the applicant considers to be the content of the present invention, as the teachings are equally applicable to configurations with different levels (e.g., 2, 3, 4, 5 and higher).

[0051] Further reference Figure 3 The switchable bias circuit (R4, R3, R2, R1, 310, 315) of this disclosure, coupled to the impedance transformation unit (310) of the switch (315), can be considered as follows: Figure 6The impedance control element (600) is depicted above. According to the above description, the impedance control element (600) has the function of coupling the voltage at its input node (410) to its output node (620) while selectively changing the impedance at its output node under the control of the control signal Ctrl. In other words, during a first operating mode (e.g., standby mode), the voltage at the output node (620) is equal to the voltage at the input node (410), and the impedance at the output node (620) is equal to the impedance at the input node (410). During a second operating mode (e.g., active mode), the voltage at the output node (620) is equal to the voltage at the input node (410), and the impedance at the output node (620) is lower than the impedance at the input node (410). Furthermore, during the first operating mode, no current flows through the impedance control element (600), and during the second operating mode, the isolation between the output node (620) and the input node (410) is high. Given such functionality, circuitry designed for the switchable bias circuitry of this disclosure is entirely within the capabilities of those skilled in the art. Such a circuit can use, for example, an operational amplifier or discrete transistors to provide buffering of the voltage at the input node (410) while presenting a different impedance at the output node (620). In other words, the impedance transformation unit (310) of the impedance control element (600) can include any one or a combination of a transistor and an operational amplifier (with or without feedback).

[0052] Figure 7 A simplified schematic diagram of a stacked cascode amplifier (700) including switchable bias circuitry (R4, R3, R2, R1, 602, 603, 604) according to this teaching is shown. Each of the components (602, 603, 604) is based on the following... Figure 6 The impedance control element (600) is described. As previously mentioned, each of the impedance control elements (602, 603, 604) can be supplied with different (or the same) supply voltages (V). REG2 V REG3 V REG4 Power is supplied to meet the voltage compliance requirements of the electronic components (e.g., transistors, operational amplifiers). Due to the node (V... B4 V B3 V B2 The voltage at point V can follow the expression V. B4 >V B3 >V B2 According to an exemplary embodiment of this disclosure, the supply voltage (V) REG2 V REG3 V REG4 It can also follow the V in it. REG4 >V REG3 >VREG2 Similar expressions. Figure 7 The operation of the stacked cascode amplifier (700) is as follows: Figure 3 The operation of the amplifier (300) is described. According to an exemplary embodiment, during the active operation mode of the amplifier (700), the impedance control elements (602, 603, 604) present the same impedance value to the gates of the transistors (M4, M3, M2). Other exemplary embodiments in which the impedance control elements (602, 603, 604) present different impedance values ​​to the gates of the transistors (M4, M3, M2) during the active operation mode of the amplifier (700) are feasible.

[0053] Further reference Figure 7 The amplifier (700) depicted in the image, with optional capacitors (C) 64 C 63 C 62 This can be used to further connect the bias circuit to the gate (V) of the transistors (M4, M3, M2). G4 V G3 V G2 The coupling RF signal is isolated at the point ( ). The combination of these capacitors with series-connected resistors (R14, R13, R12) can form a low-pass filter, the cutoff frequency of which can be selected according to the operating frequency of the RF signal amplified by the amplifier (700). Although not shown in other figures of this disclosure, similar capacitors can be used in any of the presented embodiments.

[0054] The switchable bias circuits discussed above according to this disclosure can use, for example, the following: Figure 4A , Figure 4B and Figure 5 The active components of the transistor M40 depicted herein, or other active components such as the operational amplifier described above. An alternative switchable bias circuit according to another embodiment may primarily use passive components, such as... Figure 8 The resistors described herein provide a simpler bias configuration while offering the same operating principle as those discussed above, namely, reducing RF coupling with the bias circuitry during the active operating mode of the stacked transistor amplifier and reducing power consumption in the bias circuitry during the standby operating mode of the stacked transistor amplifier, while maintaining the same gate bias voltage to the gates of the stacked transistors (e.g., M4, M3, M2) in both operating modes.

[0055] Further reference Figure 8 The amplifier (800) uses two separate resistor ladder networks (R4, R3, R2, R1) and (R84, R83, R82, R81) to pass the node voltage (V). B4V B3 V B2 ) and (V' B4 V' B3 V' B2 The same bias voltage is provided to the gates of the transistors (M4, M3, M2, M1), respectively. As described above, each ladder section may have an optional diode-connected transistor (e.g., M10, M81) so that the voltage at the node of the ladder section can track process-related changes in the stacked transistors (M4, M3, M2, M1). An optional switch (815) can be used to control the current conduction path across the resistive ladder network.

[0056] The preceding figures (e.g.) Figure 3 ) describes Figure 8 A resistor ladder network (R4, R3, R2, R1) is constructed, and the resistor ladder network (R4, R3, R2, R1) can include sufficiently high resistance values ​​to reduce the standby current through the ladder. Therefore, it may not be necessary for a switch (such as switch 815) to completely remove the current path through the ladder during active operation mode, since the current expected to conduct through the ladder is very small. In some exemplary embodiments, the resistance values ​​of the resistors (R4, R3, R2, R1) can be high enough that the current conducted through the ladder is as small as 3 μA. As described above, during the standby operation mode of the amplifier (800), the nodes (V) of the resistor ladder network (R4, R3, R2, R1) B4 V B3 V B2 A bias voltage is provided to the gate of the transistors (M4, M3, M2, M1), wherein each such node presents a high impedance to the gate of the transistor. As described above, the selection of these nodes is provided by the switch (315).

[0057] Figure 8 The resistive ladder network (R84, R83, R82, R81) is sensitive to the voltage across the ladder section (e.g., as shown in the figure). Figure 8 V shown in CC The partition is performed to divide the data at the corresponding node (V'). B4 V' B3 V' B2 The value generated at point (V) is essentially equal to that of node (V). B4 V B3 V B2 The voltage at point (V') is different in that the voltage at node ... B4 V' B3 V' B2 Each of the transistors in the series presents a gate that is substantially lower than the corresponding node (V) of the resistor ladder network (R4, R3, R2, R1).B4 V B3 V B2 The impedance presented is the impedance of the transistor (M4, M3, M2, M1). As mentioned above, this makes it possible to reduce the RF signal conducted through the transistors (M4, M3, M2, M1) and the node (V'). B4 V' B3 V' B2 The coupling effect of the bias voltage at node (V'). B4 V' B3 V' B2 The lower impedance presented is provided by choosing smaller resistance values ​​for the resistors (R84, R83, R82, R81), which in turn allows a considerable current to flow through the resistor ladder network (R84, R83, R82, R81). Therefore, in Figure 8 During the standby operation mode of the amplifier (800), the switch (815) removes the current conduction path in the ladder. In some exemplary embodiments, the resistance values ​​of the resistors (R84, R83, R82, R81) can be low enough that the current conducted through the ladder is as high as 0.8mA.

[0058] Figure 9A It shows Figure 8 An alternative implementation of the resistor ladder network (R84, R83, R82, R81) is provided, wherein an additional transistor M91 connected in series between resistors R82 and R81 can be used at node V' of the resistor ladder network. B2 Apply the desired voltage at the point.

[0059] Figure 9B It shows according to Figure 9A The same resistive ladder network is used, wherein, according to an exemplary embodiment, the switch (815) is implemented via a FET transistor M92. Those skilled in the art will recognize many different ways to implement the switch (815), therefore... Figure 9B The exemplary embodiments described herein should not be construed as limiting the scope of what the applicant considers to be the content of the invention.

[0060] The above description primarily discusses the biasing of transistors other than the input transistor M1 in the stack. Those skilled in the art will recognize that this biasing of the input transistors can determine the bias current through the transistors (M4, M3, M2, M1), and thus can indicate the gain of the amplifier using the stacked transistors (M4, M3, M2, M1). Figure 10A A simplified schematic diagram of a prior art stacked cascode amplifier device (1000A) is depicted, wherein a replication circuit (1010) is used to generate the gate bias voltage V of the input transistor M1. G1The bias circuit that generates the gate bias voltage for the stacked upper transistors (M4, M3, M2) Figure 10A (Not shown) can be any bias circuit known in the art, including the bias circuits described in U.S. Patent No. 7,248,120, U.S. Application No. 2015 / 0270806A1, and U.S. Application No. 2014 / 0184336A1—the entire contents of which are incorporated herein by reference—or as described above, for example, Figure 3 , Figure 5 , Figure 7 and Figure 8 The bias circuit is discussed.

[0061] Figure 10A The replication stack circuit (1010) may include a stack of transistors (M'4, M'3, M'2, M'1), wherein each of the transistors (M'4, M'3, M'2, M'1) is a scaled-down version (e.g., scaled down to a factor N, where N can be, for example, 100 to 1000) of the corresponding transistor (M4, M3, M2, M1) used in the amplification stage of the stacked cascode amplifier (1000A). The input transistor M'1 of the replication circuit (1010) is biased according to the same bias voltage used in the biasing of the input transistor M1 in the main amplification stage, and the gate bias voltage provided to transistor M'1 is adjusted to allow the reference current I... REF Conducted through the replica stack (1010), if the input transistor M1 is set with the same regulated gate bias voltage, the reference current N x I is multiplied. REF It can conduct through stacked transistors. This is in Figure 10A As shown, the input transistor M'1 of the replicated stack (1010) is provided with the same gate bias voltage V as the input transistor M1 provided to the amplification stage. G1 And among them, voltage V G1 via including V G1 The closed-loop system regulation of the bias control module (1020) conducts the current I generated by the current source (1030) through the replica stack circuit (1010). REF Although in Figure 10A In the exemplary prior art implementation described herein, V G1 The bias control module (1020) is shown as sensing the voltage at the drain of transistor M'4 of the replica stack (1010), but other implementations sensing other voltages in the replica stack (1010) are also feasible. These voltages can be used as part of a closed-loop system that regulates voltage V. G1 To make the current I REFThe transmission is achieved through a stack of copies (1010). Therefore, it equals N x I. REF The current is conducted through the transistors (M4, M3, M2, M1) of the amplification stage, where N is a size factor between the size of the transistors in the amplification stage and the size of the transistors in the replication circuit. Regarding... Figure 10A Further details of circuit implementation examples of bias circuits similar to the bias circuit described herein can be found, for example, in U.S. Patent No. 7,248,120 and U.S. Application No. 2015 / 0270806A1, published above, the entire contents of which are incorporated herein by reference. Based on this description, it will be clear to those skilled in the art that the corresponding current source (1030) and V can be implemented in various ways. G1 The bias control module (1010) includes auxiliary circuitry used around the operational amplifier and / or current mirror.

[0062] Further reference Figure 10A It should be noted that although the figure shows the same number of stacked transistors in the replication circuit as in the amplification stage, the number of stacked transistors (M'1, M'2, M'3) used in the replication circuit differs from other configurations of the number of stacked transistors (M1, M2, M3, M4) used in the amplification stage, for example... Figure 10B The exemplary configuration depicted is feasible. Such a configuration can be similarly achieved by adjusting the voltage V shared by the two stacks. G1 To generate the reference current I through the replication circuit REF Therefore, and as stated above, the current N'x I REF Conducted through transistors (M4, M3, M2, M1) in the amplification stage, where N' is a size factor between the size of the transistors in the amplification stage and the size of the transistors in the replication circuit. Furthermore, as... Figure 10C As illustrated in the exemplary case, the supply voltage to the replication circuit can be the same as the supply voltage V provided to the amplification stage. CC Same. (Refer to...) Figure 10A , Figure 10B and Figure 10C The gate bias voltage (V') of the transistors in the replication circuit (excluding the input transistor). G4 V' G3 V' G2 ) or (V' Gn V' Gk This can be used with the gate bias voltage (V) of the transistor supplied to the amplification stage. G4 V G3 V G2 The bias voltage may be the same or different because such a bias voltage can depend on the height of each stack and the supply voltage to the stack (e.g., V). CC VDD Therefore, the exemplary embodiments described in this application that use the same number of stacked transistors in the replication circuit and the amplification stage should not be considered as limiting the scope of the teachings of this disclosure.

[0063] Reference Figure 10A The multi-stage cascode amplifier device (1000A) depicted in the figure can be expected to enable such an amplifier to achieve RF at its input (120). in The signal is amplified (and transmitted) in an active mode and in a standby mode where virtually no current is conducted through the transistor stack (M4, M3, M2, M1). As discussed above with reference to the other accompanying figures, the voltage compliance of the transistors (M4, M3, M2, M1) must be maintained during both operating modes to ensure safe operation of the transistors, and as with, for example... Figure 3 , Figure 5 , Figure 7 and Figure 8 The foregoing teachings of this disclosure describe methods and devices for reducing standby mode power consumption in bias circuits used to generate transistors (M4, M3, M2) by presenting a low-impedance bias node to the gate of transistors (M4, M3, M2) during active mode to reduce RF signal coupling with the bias circuit. However, during either operating mode, the replication circuit (1010) is not coupled to RF signals, and therefore increased flexibility can be gained in the design of the bias circuit for the replication circuit (1010).

[0064] According to an exemplary prior art implementation, during standby operation mode... Figure 10A The current source (1030) and corresponding auxiliary circuitry are disabled to reduce power consumption (power supply is removed from the circuit), while V G1 The bias control module (1020) grounds the gates of transistors M1 and M'1, thereby removing current conduction through the two transistor stacks (M4, M3, M2, M1) and (M'4, M'3, M'2, M'1). During standby operation mode, the gate bias voltage (V') can also be removed. G4 V' G3 V' G2 Alternatively, set it to 0V. Note that, if... Figure 10A As shown, the operation in standby mode and active mode can be controlled via the control signal Ctrl. The control signal Ctrl can be generated within the controller unit, such as within the transceiver unit that is aware of the overall communication protocol contributed by the amplifier device (1000A).

[0065] Further reference Figure 10AThe amplifier device (1000A), (during standby operation mode) disables the current source (1030) and optionally grounds the gate of transistor M'1 (e.g., sets it to 0V or a reference potential). It may also dangle the drains of transistors M'4, M'3, M'2, and M'1 to ground, while the drain of output transistor M4 remains at V. CC The drains of M3, M2, and M1 are visible across the Vt (as described above by biasing transistors M4, M3, and M2). CC The voltage corresponding to the voltage division. Those skilled in the art will recognize that if the bodies of transistors (M4, M3, M2, M1) and (M'4, M'3, M'2, M'1) are floating (e.g., buoyant), then the potential of the transistor body is between the drain and source potentials of the transistor. Therefore, in Figure 10A In the case of the replication circuit (1010) and the transistor stack (M4, M3, M2, M1) of the amplification stage, the body potentials of the corresponding transistors may be at completely different potentials when operating in standby mode. As those skilled in the art know, the body potential of a transistor, as a function of its body potential, can affect the transistor's response, particularly its current-to-voltage characteristics. Furthermore, the body potential of a transistor has a time constant that prevents rapid changes in body potential, for example, due to changes in the drain / source potential of the transistor. Therefore, when the amplifier device (1000A) switches operation from standby mode to active mode, the body potentials of transistors (M4, M3, M2, M1) are at normal operating levels (because the transistor bias remains unchanged), while the body potentials of transistors (M'4, M'3, M'2, M'1) are at different operating levels and due to the applied V DD The charging process begins and gradually increases to normal operating levels. Based on... Figure 10A During the charging rise time of the body potential of the transistors (M'4, M'3, M'2, M'1) in the prior art embodiments depicted, the replication circuit (1010) cannot be considered to operate as a "replication" circuit because the reference current I is applied to transistor M'1. REF The gate bias voltage changes and only stabilizes after the body potential stabilizes. Therefore, during the charging rise time of the body potential of the transistors (M'4, M'3, M'2, M'1) in the replication circuit (1010), the changing bias current (e.g., DC current) conducted in the transistor stack (M4, M3, M2, M1) is not based on the desired current (e.g., N x I). REFThis can lead to a non-ideal output response from the amplifier device (1000A). This non-ideal output response can then cause corruption of data transmitted by a communication system using the amplifier device (1000A). For example, a transceiver might send a control signal Crt1 to the amplifier device (1000A) to switch to active operation mode and begin transmitting RF signals to be amplified by the amplifier device (1000A) within a fraction of a microsecond of the control signal Ctrl. in In response to the control signal Ctrl, the amplifier device (1000A) can activate the current source (1030) and provide a bias voltage to the replication circuit (1010) within a fraction of a microsecond. However, the settling time of the body potentials of the transistors (M'4, M'3, M'2, M'1) may be on the order of 100 microseconds. During this period, due to the non-ideal output response of the amplifier device (1000A), the amplifier device (1000A) operates in a suboptimal mode, which may damage its RF. out The data included in the signal. During the (post-switching) transition time from standby mode to active mode, a similar effect on the stability of the body potential can be expected relative to the stability of the gate voltage of the transistors (M'4, M'3, M'2, M'1), since such a gate voltage charges through the drain-gate capacitance of such transistors, and thus can further affect the (transient) response of the replication circuit during the post-switching transition time.

[0066] Those skilled in the art may consider using body-connected transistors as transistors (M4, M3, M2, M1) and (M'4, M'3, M'2, M'1) to reduce or eliminate the aforementioned considerations. Figure 10AThe prior art activation and deactivation of the current source (1030) exhibits body effects. Those skilled in the art will recognize various methods and devices for providing such body contact in transistors, some examples of which can be found, for example, in U.S. Patent Application No. 14 / 945,323 and U.S. Patent Application No. 15 / 078,930, both entitled "Butted Body Contact for SOI Transistor" and cited above, the entire disclosure of which is incorporated herein by reference. It should be noted that, according to some exemplary embodiments, the transistors in each of the stacks (M4, M3, M2, M1) and (M'4, M'3, M'2, M'1) may comprise a combination of floating body transistors and body-connected transistors, as described, for example, in U.S. Patent Application No. ____ (Attorney's File No.: PER-199-PAP), entitled "Body Tie Optimization for Stacked Transistor Amplifier" and cited above, the entire disclosure of which is incorporated herein by reference. The applicant of this disclosure has discovered that, in the case of RF circuits, particularly RF amplifiers, the contact length of the body (e.g., to the bias voltage, the source of the transistor) used to connect the transistor body can negatively affect the amplifier's performance, and therefore the contact length is reduced to maintain the desired performance. On the other hand, reducing this length can reduce the efficiency of the body connection in addressing the aforementioned body effect. This contradictory requirement for the length of the body connection makes this body connection a solution to the problem arising from... Figure 10A This presents a less feasible solution to the prior art problem of activating and deactivating the current source (1030) during the active and standby operating modes of the amplifier device (1000A). Therefore, according to embodiments of this disclosure, during both the standby and active modes of the amplifier device (1000A), the body potentials of the transistors (M'4, M'3, M'2, M'1) are maintained at normal operating levels, while power consumption in the bias circuit of the replication circuit is reduced by deactivating the current source (1030) and the corresponding circuitry. Figure 11 One configuration for providing this functionality is described. This implementation can be used regardless of whether a body-connected transistor or a floating transistor is used.

[0067] Figure 11 Exemplary modifications to the bias circuitry (1020, 1030) for providing bias to the replication circuitry (1010) according to this disclosure are depicted. Figure 11 In the amplifier device (1100), a switch (1140) is used to connect the drain of transistor M'4 to the supply voltage V under the control of the Ctrl signal. DDSelective coupling and decoupling. Therefore, during standby mode, the current source (1030) (and auxiliary circuitry) are deactivated and the switch (1140) is activated (switch on) to maintain the drain of transistor M'4 at voltage V. DD Meanwhile, V G1 The bias control module (1020) grounds the gate of transistor M'1 to remove the current conducting through the replication stack circuit (1010), while the gate bias voltage V' G4 V' G3 V' G2 The voltage V distributed across the transistors in the replication stack circuit (1010) DD During active mode, the current source (1030) (and auxiliary circuitry) are activated to bias the drain of transistor M'4 to V through the current source (1030). DD And the switch (1140) is deactivated (switch off). Therefore, during both standby and active modes, the stacks (M4, M3, M2, M1) and (M'4, M'3, M'2, M'1) are both equally biased, and thus the bodies of the corresponding transistors are at the same potential. Those skilled in the art will understand that when the current source (1030) is activated, the corresponding device / circuit (e.g., transistor) can be connected to the drain of transistor M'4 with the supply voltage V. DD This provides a low-resistance path while controlling the current through the device / circuit to effectively set the drain of M'4 to be substantially equal to V. DD The voltage. On the other hand, when the current source (1030) is deactivated, the device / circuit can be turned off, effectively removing the supply voltage V. DD The conduction path between the drain of M'4 and the drain of M'4. As mentioned earlier, the drain of M'4 is not connected to the supply voltage (e.g., connected to V via switch 1140). DD In the case of the current source (1030) being deactivated, the natural conduction current (from drain to source) discharges the voltage at the drain of M'4 and all drains of subsequent transistors M'3, M'2 and M'1, ultimately causing the drains of transistors (M'4, M'3, M'2, M'1) to be grounded.

[0068] Continue to refer to Figure 11 According to some embodiments of this disclosure, as described above, the gate bias voltage V' of the gates of the transistors (M'4, M'3, M'2) of the replication circuit (1010) can be increased. G4 V' G3 V' G2 The operation is identical (equal) in both standby and active operation modes. According to an alternative embodiment of this disclosure, the gate bias voltage V' can be... G4 V'G3 V' G2 The voltages are substantially equal in both operating modes. For example, in standby mode, the voltage division at the drain of transistor M'4 across the stack (1010) provides the voltage at the common source-drain node of the transistors (M'4, M'3, M'2, M'1) in the stack (1010), which is within 0.5V of the corresponding common source-drain node voltage in active mode. In other words, for V' Gn | 待机 ≈V' Gn | 有源 + / -0.5V for n = 2, 3, 4. According to other embodiments of this disclosure, the gate bias voltage V' provided to the replication circuit (1010) can be... G4 V' G3 V' G2 Essentially equal to the corresponding gate bias voltage V provided to the transistor in the amplification stage. G4 V G3 V G2 .

[0069] Further reference Figure 11 The amplifier device (1100) described in this disclosure achieves reduced power consumption in standby mode compared to active mode because the current source (1030) and auxiliary circuitry are deactivated and no current is conducted through the replication circuit (1010) during standby mode. Furthermore, the bulk effect discussed above is eliminated, resulting in… Figure 11 The amplifier device (1100) is capable of switching operation between standby and active modes without being affected by long settling times of the body potential during periods when the amplifier does not perform as expected. The applicant of this disclosure has measured settling times equal to or less than 200 nanoseconds, relative to a standard timing window. Figure 11 The amplifier device (1100) provides a large operating margin, and the controller (e.g., a transceiver unit) can begin RF switching after a settling time of equal to or less than 200 nanoseconds following a request to switch operation from standby mode to active mode. in The signal is output to the amplifier device (1100).

[0070] Although Figure 11 The exemplary embodiment depicted in this disclosure illustrates a simple switch (1140) independent of the current source (1030) as a selective biasing of the drain of transistor M'4 to voltage V. DDThe device is described, but those skilled in the art will recognize other devices that provide the same function when using the teachings of this disclosure. For example, considering the entire current source (1030) and the corresponding auxiliary circuitry (not shown, but described, for example, in U.S. Application No. 2015 / 0270806A1, the entire disclosure of which is incorporated herein by reference), such as Figure 12A As described herein, those skilled in the art can integrate the same function of the switch (1140) into this current source (1030) and auxiliary circuitry.

[0071] Further reference Figure 12A The description illustrates embodiments based on this disclosure that can provide the same functionality as those referenced above. Figure 11 The amplifier device (1100) discussed is an amplifier device (1200A) with the same function. Specifically, a drain biasing module (1230) is used to selectively couple the drain of transistor M'4 to a voltage that remains constant (e.g., V) during the first and second operating modes. DD At the node, during the first operating mode (e.g., active mode), the current source of the drain bias module is controlled to the reference current (e.g., I0). REF ), and during the second operating mode (e.g., standby mode), the current source of the drain bias module is not controlled. See above for reference. Figure 11 As discussed, this functionality can be achieved using a current source (e.g., 1030), a switch (e.g., 1140), and corresponding auxiliary circuitry. Furthermore, during standby operation, the function of limiting the current to a reference current I in the drain bias module (1230) can be disabled. REF It is part of the circuit designed to reduce power consumption.

[0072] Figure 12B Another embodiment according to this disclosure can provide the same as the one described above. Figure 11 Another exemplary implementation of the amplifier device (1200B) having the same function as the discussed amplifier device (1100). Specifically, a switch (1240) is used to switch the supply voltage V. DD The drain node of transistor M'4 in the current source (1030) is coupled to the replication circuit (1010). As described above, those skilled in the art will understand how to modify the replication circuit (e.g., using the teachings of this disclosure) to achieve the desired effect. Figure 10A and Figure 10BVarious methods are used to bias the circuitry to maintain the body potential of the replication circuitry at the same level as the body potential of the main amplification stage during both standby and active operation modes, while reducing power consumption during standby mode. As noted throughout this disclosure, the stacked transistor configuration depicted as having four stacked transistors is merely exemplary in nature, as the teachings of this disclosure are equally applicable to configurations with different numbers of stacked transistors, such as 2, 3, 4, 5, 6, 7, and more.

[0073] The term "MOSFET" technically refers to a metal-oxide-semiconductor semiconductor; another synonym for MOSFET is "MISFET," used for metal-insulator-semiconductor FETs. However, "MOSFET" has become the common label for most types of insulated-gate FETs ("IGFETs"). Nevertheless, it is well known that the term "metal" in the names MOSFET and MISFET is now generally misused because the previously used metal gate material is now typically a polycrystalline silicon layer (polysilicon). Similarly, "oxide" in the name MOSFET may be misused because different dielectric materials are used for the purpose of obtaining a strong channel at a lower applied voltage. Therefore, the term "MOSFET" as used herein should not be taken literally as limited to metal-oxide-semiconductor semiconductors, but rather generally includes IGFETs instead.

[0074] As will be apparent to those skilled in the art, various embodiments of the present invention can be implemented to meet a wide range of specifications. Unless otherwise stated above, the selection of appropriate component values ​​is a matter of design choice, and various embodiments of the present invention can be implemented using any suitable IC technology (including, but not limited to, MOSFET and IGFET structures) or in hybrid or discrete circuit form. Integrated circuit implementations can be fabricated using any suitable substrate and process—including, but not limited to, standard bulk silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), GaN HEMT, GaAs pHEMT, and MESFET technologies. However, the inventive concepts described above are particularly useful for SOI-based fabrication processes (including SOS) and for fabrication processes with similar characteristics. Fabrication in CMOS on SOI or SOS enables low power consumption, good linearity, and high-frequency operation (above approximately 10 GHz, particularly above approximately 20 GHz) due to the ability of the FET stack to withstand high-power signals during operation. Monolithic IC implementations are particularly useful because, with careful design, parasitic capacitances can generally be kept low (or minimal, consistent across all cells, allowing them to be compensated).

[0075] Depending on specific specifications and / or implementation technology (e.g., NMOS, PMOS, or CMOS, and enhancement-mode transistor devices or depletion-mode transistor devices), voltage levels can be adjusted or voltage and / or logic signal polarity can be reversed. The voltage, current, and power handling capabilities of components can be adaptively adjusted as needed, for example, by adjusting device size, "stacking" components (especially FETs) in series to withstand higher voltages, and / or using multiple components in parallel to handle larger currents. Additional circuit components can be added to enhance the capabilities of the disclosed circuit and / or provide additional functionality without significantly altering the function of the disclosed circuit.

[0076] The examples provided above are intended to offer a complete disclosure and description to those skilled in the art of how to manufacture and use embodiments of the fast RF amplifier bias recovery standby voltage conditions of this disclosure, and are not intended to limit the scope of what the applicant considers the invention. Such embodiments can be used, for example, in mobile phones used in current communication systems (e.g., WCMDA, LTE, WiFi, etc.), where amplification of signals with frequency content higher than 100 MHz and power levels higher than 50 mW may be required. Other suitable implementations of the presented embodiments will be available to those skilled in the art.

[0077] Modifications to the above-described patterns for performing the methods and systems disclosed herein that will be obvious to those skilled in the art are intended to fall within the scope of the appended claims. All patents and disclosures referenced in this specification represent the skill level of a person skilled in the art to which this disclosure pertains. All references cited in this disclosure are incorporated by reference to the same extent that the entire contents of each reference have been individually incorporated by reference.

[0078] It should be understood that this disclosure is not limited to any particular method or system, which can of course vary. It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in this specification and the appended claims, unless expressly specified otherwise, the singular forms (“a”, “an”, and “the”) include a plural of indicators. Unless expressly specified otherwise, the term “a plurality” includes two or more indicators. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains.

[0079] Many embodiments of this disclosure have been described. However, it should be understood that various modifications can be made without departing from the spirit and scope of this disclosure. Therefore, other embodiments are within the scope of the appended claims.

Claims

1. A circuit device, comprising: A transistor stack configured to operate as an amplifier, the transistor stack comprising an input transistor and one or more cascode transistors including an output transistor; A bias circuit, including a replication circuit for the transistor stack, is configured to provide an input gate bias voltage to the input transistor and to a corresponding first transistor of the replication circuit. The circuit device is configured to operate in at least an active mode and a standby mode, wherein in the active mode, radio frequency signals are amplified through the transistor stack, and in the standby mode, substantially no current is conducted through the transistor stack and the power consumption of the circuit device is reduced. During operation in the active mode, the bias circuit generates the input gate bias voltage based on the reference current conducted through the replication circuit. The bias circuit generates a bias voltage to one or more cascode transistors of the replication circuit, the bias voltage being substantially equal to the bias voltage to the corresponding one or more cascode transistors of the transistor stack during operation in the active mode and during operation in the standby mode. The bias circuit generates a bias voltage to the one or more cascode transistors of the replication circuit during operation in the standby mode, the bias voltage being substantially equal to the bias voltage to the one or more cascode transistors of the replication circuit during operation in the active mode.

2. The circuit device according to claim 1, wherein: The transistor stack is configured to operate between a first supply voltage coupled to the output transistor and a reference voltage coupled to the input transistor, and The replication circuit is configured to operate between a second supply voltage of the last transistor corresponding to the output transistor coupled to the replication circuit and a reference voltage coupled to the first transistor.

3. The circuit arrangement according to any one of claims 1 to 2, wherein, During operation in the active mode, the voltage at the common source-drain node of the replication circuit is within 0.5 V of the corresponding voltage during operation in the standby mode.

4. The circuit device according to any one of claims 1 to 2, wherein, The transistor stack is configured to amplify radio frequency signals used for WiFi communication.

5. The circuit device according to claim 4, wherein, The circuit device is used in electronic devices for WiFi communication.

6. The circuit arrangement according to any one of claims 1 to 2, wherein, The gates of the transistors in the replication circuit and the gates of the stacked transistors in the transistor stack are provided with the same bias voltage.

7. The circuit arrangement according to any one of claims 1 to 2, wherein, The gates of the transistors in the replication circuit and the gates of the transistors in the transistor stack are provided with different bias voltages.

8. The circuit arrangement according to any one of claims 1 to 2, wherein, The height of the transistor stack in the replication circuit is equal to the height of the transistor stack configured to operate as an amplifier.

9. The circuit arrangement according to any one of claims 1 to 2, wherein, The height of the transistor stack in the replication circuit is different from the height of the transistor stack configured to operate as an amplifier.

10. The circuit arrangement according to any one of claims 1 to 2, wherein, The transistors in the replication circuit and the transistor stack are floating transistors.

11. The circuit arrangement according to any one of claims 1 to 2, wherein, The transistors in the replication circuit and the transistor stack are body-connected transistors.

12. The circuit arrangement according to any one of claims 1 to 2, wherein, The transistors of the replication circuit and / or the transistor stack include a combination of body-connected transistors and floating transistors.

13. The circuit arrangement according to any one of claims 1 to 2, further comprising one or more gate capacitors, each gate capacitor connected between the gates of the one or more common-source cascode transistors in the transistor stack, wherein, Each gate capacitor is configured to allow the gate voltage at the gate to vary with the radio frequency voltage at the drain of the transistor.

14. The circuit arrangement according to claim 13, wherein, The one or more gate capacitors are configured to substantially equalize the output RF voltage at the drain of the output transistor across the transistor stack configured to operate as an amplifier.

15. The circuit device according to claim 2, wherein, During operation in the standby mode, the input gate bias voltage is substantially equal to the reference voltage.

16. The circuit arrangement according to any one of claims 1, 2, and 15, wherein, The transistors in the replication circuit are the scaled-down versions of the corresponding transistors in the transistor stack configured to operate as amplifiers, reaching a factor of 1. N The version, where N is in the range of 100 to 1000.

17. A communication device for WiFi communication, the communication device comprising the circuit arrangement according to claim 1.

18. The communication device according to claim 17, wherein, The communication device is a mobile phone.

19. A method for biasing a transistor stack using a replication circuit configured to operate as an amplifier, the method comprising: During the active amplification operation mode of the amplifier: The bias voltage of the input transistors in the transistor stack is adjusted by conducting a reference current through the replication circuit. as well as A bias voltage is provided to the cascode transistors of the replication circuit, the bias voltage being substantially equal to the bias voltage provided to the cascode transistors of the transistor stack; as well as During the amplifier's standby operation mode: The bias voltage to the input transistor is set to a fixed value so that virtually no current is conducted through the replication circuit. as well as A bias voltage is provided to the cascode transistors of the replication circuit, the bias voltage being substantially equal to the bias voltage provided to the cascode transistors of the transistor stack. During operation in the standby mode, the bias voltage supplied to the cascode transistor of the replication circuit is substantially equal to the bias voltage supplied to the cascode transistor of the replication circuit during operation in the active amplification mode.

20. The method of claim 19, wherein: The transistor stack is configured to operate between a first supply voltage coupled to the output transistors of the transistor stack and a reference voltage coupled to the input transistors, and The replication circuit is configured to operate between a second supply voltage of the last transistor corresponding to the output transistor in the replication circuit and a reference voltage of the first transistor corresponding to the input transistor in the replication circuit.

21. A circuit device, comprising: A transistor stack, configured to operate as an amplifier, the transistor stack comprising a plurality of stacked transistors including input transistors and output transistors; A bias circuit, including a replication circuit for the transistor stack, is configured to provide an input gate bias voltage to the input transistor and to a corresponding first transistor of the replication circuit. The circuit device is configured to operate in at least an active mode and a standby mode, wherein in the active mode the radio frequency signal is amplified by the transistor stack, and in the standby mode the power consumption of the circuit device is reduced. During operation in the active mode, the bias circuit generates the input gate bias voltage based on the reference current conducted through the replication circuit. During operation in the standby mode, the bias circuit generates the input gate bias voltage, which is substantially equal to the reference voltage coupled to the source of the input transistor and the corresponding input transistor of the replication circuit. During the active mode and the standby mode, the bias circuit generates a bias voltage to the transistors of the replication circuit, the bias voltage being substantially equal to the bias voltage to the transistors of the transistor stack. During operation in the active mode, the voltage at the drain of the last transistor in the replication circuit corresponding to the output transistor is substantially equal to the voltage at the drain of the last transistor during operation in the standby mode.

22. The circuit arrangement according to claim 21, wherein: The transistor stack is configured to operate between a first supply voltage coupled to the output transistor and a reference voltage coupled to the input transistor, and The replication circuit is configured to operate between a second supply voltage of the last transistor corresponding to the output transistor coupled to the replication circuit and a reference voltage coupled to the first transistor.

23. The circuit device according to claim 22, wherein, The first supply voltage is equal to the second supply voltage.

24. The circuit arrangement according to claim 22, wherein, The first supply voltage is different from the second supply voltage.

25. The circuit arrangement according to any one of claims 22 to 24, in, During the active mode, the drain of the last transistor in the replication circuit is coupled to the second supply voltage via a current source, and During the standby mode, the drain of the last transistor in the replication circuit is coupled to the second supply voltage by the closed state of the switch.

26. The circuit arrangement according to any one of claims 21 to 24, wherein, During operation in the active mode, the voltage at the common source-drain node of the replication circuit is within 0.5 V of the corresponding voltage during operation in the standby mode.

27. The circuit arrangement according to any one of claims 21 to 24, wherein, The gates of the transistors in the replication circuit and the gates of the plurality of stacked transistors in the transistor stack are provided with the same bias voltage.

28. The circuit arrangement according to any one of claims 21 to 24, wherein, The gates of the transistors in the replication circuit and the gates of the plurality of stacked transistors in the transistor stack are provided with different bias voltages.

29. The circuit arrangement according to any one of claims 21 to 24, wherein, The height of the transistor stack in the replication circuit is equal to the height of the transistor stack configured to operate as an amplifier.

30. The circuit arrangement according to any one of claims 21 to 24, wherein, The height of the transistor stack in the replication circuit is different from the height of the transistor stack configured to operate as an amplifier.

31. The circuit arrangement according to any one of claims 21 to 24, wherein, The transistors in the replication circuit and the plurality of stacked transistors in the transistor stack are floating transistors.

32. The circuit arrangement according to any one of claims 21 to 24, wherein, The transistors in the replication circuit and the plurality of stacked transistors in the transistor stack are body-connected transistors.

33. The circuit arrangement according to any one of claims 21 to 24, wherein, The transistors of the replication circuit and / or the plurality of stacked transistors of the transistor stack include a combination of body-connected transistors and floating transistors.

34. The circuit arrangement according to any one of claims 21 to 24, further comprising one or more gate capacitors, each gate capacitor being connected between the gates of the transistors other than the input transistor in the plurality of stacked transistors, wherein, Each gate capacitor is configured to allow the gate voltage at the gate to vary with the radio frequency voltage at the drain of the transistor.

35. The circuit arrangement according to claim 34, wherein, The one or more gate capacitors are configured to substantially equalize the output RF voltage at the drain of the output transistor across the plurality of stacked transistors.

36. The circuit arrangement according to any one of claims 21 to 24, wherein, The plurality of stacked transistors of the transistor stack and the corresponding transistors of the replication circuit include metal-oxide-semiconductor MOS field-effect transistors (FETs), which are manufactured using one of the following: a) silicon-on-insulator (SOI) technology; b) silicon-on-sapphire (SOS) technology; and c) bulk silicon (Si) technology.

37. A communication device for WiFi communication, the communication device comprising a circuit arrangement according to any one of claims 21 to 36.

38. The communication device according to claim 37, wherein, The communication device is a mobile phone.

39. A method for biasing a transistor stack using a replication circuit configured to operate as an amplifier, the method comprising: During the active amplification mode of the amplifier: The bias voltage of the input transistors in the transistor stack is adjusted by conducting a reference current through the replication circuit. as well as A bias voltage is provided to the transistors of the replication circuit, the bias voltage being substantially equal to the bias voltage provided to the transistors of the transistor stack; as well as During the amplifier's standby mode: The bias voltage to the input transistor is set to a fixed value, which is substantially equal to the reference voltage coupled to the source of the input transistor and the corresponding input transistor of the replication circuit; as well as A bias voltage is provided to the transistors of the replication circuit, the bias voltage being substantially equal to the bias voltage provided to the transistors of the transistor stack. During operation in the active amplification mode, the voltage at the drain of the last transistor in the replication circuit corresponding to the output transistor of the transistor stack is substantially equal to the voltage at the drain of the last transistor during operation in the standby mode.

40. A circuit device, comprising: A transistor stack, configured to operate as an amplifier, the transistor stack comprising a plurality of stacked transistors including input transistors and output transistors; as well as A bias circuit, including a replication circuit for the transistor stack, is configured to provide an input gate bias voltage to the input transistor and to a corresponding first transistor of the replication circuit. The circuit device is configured to operate in at least an active mode and a standby mode, wherein in the active mode the radio frequency signal is amplified by the transistor stack, and in the standby mode the power consumption of the circuit device is reduced. During operation in the active mode, the drain of the last transistor of the replication circuit is coupled to a first supply voltage via a reference current source, and the bias circuit generates the input gate bias voltage based on a reference current conducted through the reference current source of the replication circuit. During operation in the standby mode, the drain of the last transistor of the replication circuit is coupled to the first supply voltage by the closed state of the switch, and the bias circuit generates the input gate bias voltage, which is substantially equal to the reference voltage coupled to the source of the input transistor and the corresponding first transistor of the replication circuit.

41. The circuit arrangement according to claim 40, wherein, The switch is a transistor switch.

42. The circuit arrangement according to claim 40 or 41, wherein, During operation in the active mode, the switch is in the open state.

43. The circuit arrangement according to any one of claims 40 to 41, wherein, During operation in the active mode, the voltage at the drain of the last transistor of the replication circuit is substantially equal to the voltage at the drain of the last transistor during operation in the standby mode.

44. The circuit arrangement according to any one of claims 40 to 41, wherein: During operation in the active mode, the reference current source provides a low-resistance conduction path between the first supply voltage and the drain of the last transistor of the replication circuit for conducting the reference current, and During operation in the standby mode, the reference current source removes the low-resistance conduction path.

45. The circuit arrangement according to any one of claims 40 to 41, wherein, During operation in the active mode, the bias voltage to the gate of the transistor in the replication circuit is substantially equal to the corresponding bias voltage to the gate of the transistor in the replication circuit during operation in the standby mode.

46. ​​The circuit arrangement according to any one of claims 40 to 41, wherein, During operation in the active mode, the bias voltage to the gates of the plurality of stacked transistors (excluding the input transistor) of the transistor stack is substantially equal to the corresponding bias voltage to the gates of the plurality of stacked transistors (excluding the input transistor) of the transistor stack during operation in the standby mode.

47. The circuit arrangement according to any one of claims 40 to 41, wherein: The transistor stack is configured to operate between a second supply voltage coupled to the output transistor and a reference voltage coupled to the input transistor, and The first supply voltage is equal to the second supply voltage.

48. The circuit arrangement according to any one of claims 40 to 41, wherein: The transistor stack is configured to operate between a second supply voltage coupled to the output transistor and a reference voltage coupled to the input transistor, and The first supply voltage is different from the second supply voltage.

49. The circuit arrangement according to any one of claims 40 to 41, wherein, During operation in the active mode, the voltage at the common source-drain node of the replication circuit is within 0.5 V of the corresponding voltage during operation in the standby mode.

50. The circuit arrangement according to any one of claims 40 to 41, wherein, The gates of the transistors in the replication circuit and the gates of the plurality of stacked transistors in the transistor stack are provided with the same bias voltage.

51. The circuit arrangement according to any one of claims 40 to 41, wherein, The gates of the transistors in the replication circuit and the gates of the plurality of stacked transistors in the transistor stack are provided with different bias voltages.

52. The circuit arrangement according to any one of claims 40 to 41, wherein, The height of the transistor stack in the replication circuit is equal to the height of the transistor stack configured to operate as an amplifier.

53. The circuit arrangement according to any one of claims 40 to 41, wherein, The height of the transistor stack in the replication circuit is different from the height of the transistor stack configured to operate as an amplifier.

54. The circuit arrangement according to any one of claims 40 to 41, wherein, The transistors in the replication circuit and the plurality of stacked transistors in the transistor stack are floating transistors.

55. The circuit arrangement according to any one of claims 40 to 41, wherein, The transistors in the replication circuit and the plurality of stacked transistors in the transistor stack are body-connected transistors.

56. The circuit arrangement according to any one of claims 40 to 41, wherein, The transistors of the replication circuit and / or the plurality of stacked transistors of the transistor stack include a combination of body-connected transistors and floating transistors.

57. The circuit arrangement according to any one of claims 40 to 41, further comprising one or more gate capacitors, each gate capacitor being connected between the gates of the transistors other than the input transistor in the plurality of stacked transistors.

58. The circuit arrangement according to claim 57, wherein, The one or more gate capacitors are configured to substantially equalize the output RF voltage at the drain of the output transistor across the plurality of stacked transistors.

59. A method for biasing a transistor stack using a replication circuit configured to operate as an amplifier, the method comprising: During the active amplification mode of the amplifier: The replication circuit is coupled to the supply voltage via a reference current source; The reference current based on the reference current source is conducted through the replication circuit to generate the input gate bias voltage; as well as The input gate bias voltage is provided to the gate of the input transistor of the transistor stack and the gate of the corresponding first transistor of the replication circuit; as well as During the amplifier's standby mode: The replication circuit is coupled to the supply voltage by the closed state of the switch; The input gate bias voltage is generated, which is substantially equal to the reference voltage coupled to the source of the input transistor and the corresponding first transistor of the replication circuit; as well as The input gate bias voltage is provided to the gate of the input transistor of the transistor stack and the gate of the corresponding first transistor of the replication circuit.

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