A switched capacitor amplifier
By introducing a pre-charge circuit into the switched capacitor amplifier to achieve charge self-balancing, high-speed capacitor charging and discharging is realized, which improves the settling speed and reduces power consumption, thus resolving the contradiction between speed and power consumption in the prior art.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHINA MICRO SEMICON (SHENZHEN) CO LTD
- Filing Date
- 2023-03-20
- Publication Date
- 2026-07-21
AI Technical Summary
Existing switched-capacitor amplifiers struggle to simultaneously achieve higher settling speeds and lower power consumption.
A pre-charging circuit is used after the sampling phase to connect the in-phase and out-of-phase branches of the fully differential amplifier to achieve charge self-balancing between capacitors. The law of conservation of charge is used to realize high-speed capacitor charging and discharging, and the remaining charge is transferred by the fully differential amplifier in the amplification phase.
This improves the settling speed of switched-capacitor amplifiers and reduces the power consumption of fully differential amplifiers, solving the problem that settling speed and low power consumption cannot be satisfied simultaneously in existing technologies.
Smart Images
Figure CN116317982B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic technology, and more particularly to a switched capacitor amplifier. Background Technology
[0002] Switched-capacitor amplifiers and integrators are widely used in integrated circuit systems due to their high precision and energy efficiency. The circuit samples the input signal by controlling a sampling capacitor with a switch, and then transfers the charge from the sampling capacitor to the feedback or integrating capacitor via a switching switch, thereby amplifying or integrating the input signal. This charge transfer process causes the amplifier to undergo a small-signal to large-signal setup process. Currently, switched-capacitor amplifiers, with their higher setup speed and lower power consumption, are more popular.
[0003] Traditional switched-capacitor amplifiers typically require a sufficiently high slew rate and gain bandwidth to ensure good settling accuracy and high settling speed. A higher slew rate and gain bandwidth mean higher power consumption. Current switched-capacitor amplifiers suffer from the problem of not being able to simultaneously achieve both high settling speed and low power consumption. Summary of the Invention
[0004] To address the shortcomings of existing technologies, this invention provides a switched-capacitor amplifier that solves the problem that existing switched-capacitor amplifiers cannot simultaneously achieve higher settling speed and lower power consumption.
[0005] According to an embodiment of the present invention, a switched-capacitor amplifier includes: a first switched-capacitor network, a second switched-capacitor network, a third switched-capacitor network, a pre-charge circuit, a switching network, and a fully differential amplifier; a first input terminal of the first switched-capacitor network is connected to a first input voltage signal, a second input terminal of the first switched-capacitor network is connected to a second input voltage signal, a first output terminal of the first switched-capacitor network is connected to the non-inverting input terminal of the fully differential amplifier, and a second output terminal of the first switched-capacitor network is connected to the inverting input terminal of the fully differential amplifier, wherein the first switched-capacitor network is used to sample the input voltage signal; an input terminal of the second switched-capacitor network is connected to the first output terminal of the first switched-capacitor network, and an output terminal of the second switched-capacitor network is connected to the first input terminal of the switching network, wherein the second switched-capacitor network is used to receive the sampling from the first switched-capacitor network. Charge; the input terminal of the third switched capacitor network is connected to the second output terminal of the first switched capacitor network, and the output terminal of the third switched capacitor network is connected to the second input terminal of the switching network. The third switched capacitor network is used to receive the sampled charge of the first switched capacitor network; the first output terminal of the switching network is connected to the non-inverting output terminal of the fully differential amplifier, the second output terminal of the switching network is connected to the inverting output terminal of the fully differential amplifier, the third output terminal of the switching network is connected to the input terminal of the pre-charge circuit, and the fourth output terminal of the switching network is connected to the output terminal of the pre-charge circuit. The switching network is used to connect the second switched capacitor network and the third switched capacitor network to the pre-charge circuit via a switching switch, or to connect the second switched capacitor network and the third switched capacitor network to the fully differential amplifier via a switching switch. The pre-charge circuit is used to connect the in-phase and out-of-phase branches of the fully differential amplifier after the sampling time ends, so as to perform charge self-balancing between capacitors; the fully differential amplifier is used to transfer the remaining charge of the first switched capacitor network to the second switched capacitor network and the third switched capacitor network after the pre-charge circuit pre-charges.
[0006] Optionally, the pre-charge circuit includes a first pre-charge capacitor, a second pre-charge capacitor, a first switch, and a second switch. The first terminal of the first pre-charge capacitor is connected to the first input voltage signal through the first switch. The first terminal of the first pre-charge capacitor is also connected to the third output terminal of the switching network. The second terminal of the first pre-charge capacitor is connected to a reference common-mode voltage signal. The first terminal of the second pre-charge capacitor is connected to the second input voltage signal through the second switch. The second terminal of the second pre-charge capacitor is also connected to the fourth output terminal of the switching network. The second terminal of the second pre-charge capacitor is also connected to the reference common-mode voltage signal.
[0007] Optionally, the pre-charging circuit is a wire, with the first end of the wire connected to the third output terminal of the switching network and the second end of the wire connected to the fourth output terminal of the switching network.
[0008] Optionally, the first switched capacitor network includes a first sampling capacitor, a second sampling capacitor, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch, and a tenth switch. The first terminal of the first sampling capacitor is connected to the first input voltage signal through the third switch, and the first terminal of the first sampling capacitor is also connected to a reference common-mode voltage through the fifth switch. The second terminal of the first sampling capacitor is connected to the input terminal of the second switched capacitor network through the ninth switch, and the second terminal of the first sampling capacitor is also connected to the reference common-mode voltage through the seventh switch. The first terminal of the second sampling capacitor is connected to the second input voltage signal through the fourth switch, and the first terminal of the second sampling capacitor is also connected to the reference common-mode voltage through the sixth switch. The second terminal of the second sampling capacitor is connected to the input terminal of the third switched capacitor network through the tenth switch, and the second terminal of the second sampling capacitor is also connected to the reference common-mode voltage through the eighth switch.
[0009] Optionally, the first switched capacitor network further includes an eleventh switch and a twelfth switch, wherein the eleventh switch is connected in parallel with the ninth switch, the twelfth switch is connected in parallel with the tenth switch, and the eleventh switch turns off later than the ninth switch, and the twelfth switch turns off later than the tenth switch.
[0010] Optionally, the eleventh switch is smaller than the ninth switch, and the twelfth switch is smaller than the tenth switch.
[0011] Optionally, the second switched capacitor network includes a first feedback capacitor and a thirteenth switch, the thirteenth switch being connected in parallel with the first feedback capacitor, the first end of the first feedback capacitor being connected to the first output terminal of the first switched capacitor network, and the second end of the first feedback capacitor being connected to the first input terminal of the switching network.
[0012] Optionally, the third switched capacitor network includes a second feedback capacitor and a fourteenth switch, the fourteenth switch being connected in parallel with the second feedback capacitor, the first terminal of the second feedback capacitor being connected to the second output terminal of the first switched capacitor network, and the second terminal of the second feedback capacitor being connected to the second input terminal of the switching network.
[0013] Optionally, the switching network includes a fifteenth switch, a sixteenth switch, a seventeenth switch, and an eighteenth switch. The output of the second switched capacitor network is connected to the input of the pre-charge circuit through the fifteenth switch. The output of the second switched capacitor network is connected to the non-inverting output of the fully differential amplifier through the sixteenth switch. The output of the third switched capacitor network is connected to the output of the pre-charge circuit through the seventeenth switch. The output of the third switched capacitor network is connected to the inverting output of the fully differential amplifier through the eighteenth switch.
[0014] According to an embodiment of the present invention, an analog-to-digital converter includes the aforementioned switched-capacitor amplifier.
[0015] The technical principle of this invention is as follows: By introducing a pre-charge phase after the sampling phase and before the amplification phase, the in-phase and out-of-phase branches of the fully differential amplifier are connected using a pre-charge circuit to achieve charge self-balancing between capacitors. According to the law of conservation of charge, the capacitors are charged and discharged. At this time, the fully differential amplifier is not connected to the second and third switched capacitor networks. Finally, in the amplification phase, the second and third switched capacitor networks are connected to the fully differential amplifier, and the connection with the pre-charge circuit is disconnected. The remaining sampling charge on the first switched capacitor network is transferred by the fully differential amplifier.
[0016] Compared with the prior art, the present invention has the following beneficial effects: Since the capacitor charge self-balance is achieved in the pre-charging phase according to the law of charge conservation, the charging and discharging speed of the capacitor is very high, which improves the settling speed of the switched capacitor amplifier. Furthermore, since partial charge transfer is performed in the pre-charging phase first, and the remaining charge is transferred by the fully differential amplifier, the operation of the fully differential amplifier is reduced, and the power consumption of the fully differential amplifier is lowered. This solves the technical problem in the prior art that the switched capacitor amplifier cannot simultaneously achieve higher settling speed and lower power consumption, and produces the technical effect of improving the settling speed of the switched capacitor amplifier while reducing the power consumption of the amplifier. Attached Figure Description
[0017] Figure 1 This is a circuit diagram of a switched capacitor amplifier according to an embodiment of the present invention;
[0018] Figure 2 This is a switching timing diagram of a switched capacitor amplifier according to an embodiment of the present invention;
[0019] Figure 3 This is a pre-charging circuit diagram according to an embodiment of the present invention. Detailed Implementation
[0020] The technical solutions of the present invention will be further described below with reference to the accompanying drawings and embodiments.
[0021] like Figure 1 and Figure 2 As shown in the figure, this embodiment of the invention proposes a switched-capacitor amplifier, including a first switched-capacitor network 1, a second switched-capacitor network 2, a third switched-capacitor network 3, a pre-charge circuit 6, a switching network 5, and a fully differential amplifier 4. The first input terminal of the first switched-capacitor network 1 is connected to a first input voltage signal, the second input terminal of the first switched-capacitor network 1 is connected to a second input voltage signal, the first output terminal of the first switched-capacitor network 1 is connected to the non-inverting input terminal of the fully differential amplifier 4, and the second output terminal of the first switched-capacitor network 1 is connected to the inverting input terminal of the fully differential amplifier 4. The first switched-capacitor network 1 is used to sample the input voltage signal. The input terminal of the second switched-capacitor network 2 is connected to the first output terminal of the first switched-capacitor network 1, and the output terminal of the second switched-capacitor network 2 is connected to the first input terminal of the switching network 5. The second switched-capacitor network 2 is used to receive the first switched-capacitor signal. The sampling charge of capacitor network 1; the input terminal of the third switched capacitor network 3 is connected to the second output terminal of the first switched capacitor network 1, and the output terminal of the third switched capacitor network 3 is connected to the second input terminal of the switching network 5. The third switched capacitor network 3 is used to receive the sampling charge of the first switched capacitor network 1; the first output terminal of the switching network 5 is connected to the non-inverting output terminal of the fully differential amplifier 4, the second output terminal of the switching network 5 is connected to the inverting output terminal of the fully differential amplifier 4, the third output terminal of the switching network 5 is connected to the input terminal of the pre-charge circuit 6, and the fourth output terminal of the switching network 5 is connected to the output terminal of the pre-charge circuit 6. The switching network 5 is used to connect the second switched capacitor network 2 and the third switched capacitor network 3 to the pre-charge circuit 6 through a switching switch, or to connect the second switched capacitor network 2 and the third switched capacitor network 3 to the fully differential amplifier 4 through a switching switch. The pre-charge circuit 6 is used to connect the in-phase and out-of-phase branches of the fully differential amplifier 4 after the sampling time ends, so as to perform charge self-balancing between capacitors; the fully differential amplifier 4 is used to transfer the remaining charge of the first switched capacitor network 1 to the second switched capacitor network 2 and the third switched capacitor network 3 after pre-charging by the pre-charge circuit 6. Figure 2 This is the switching timing diagram for a switched-capacitor amplifier. The switched-capacitor amplifier is divided into three phases: sampling phase 1, pre-charging phase 2, and amplification phase 3. The high level corresponds to the sampling phase of the amplifier, which samples the magnitude of the input signal onto the sampling capacitor C. s ; The high level corresponds to the amplification phase (or integration phase), which is then amplified by a fully differential amplifier. s The collected charge is transferred to C fb When the input signal amplitude is large, the amplifier needs more settling time to complete the charge transfer, that is, to complete the charging and discharging of the capacitor.
[0022] The detailed working process of this embodiment is as follows: In the sampling phase, the first switched capacitor network 1 samples the first input voltage signal and the second input voltage signal, and disconnects from the second switched capacitor network 2, the third switched capacitor network 3, and the fully differential amplifier 4. After the sampling phase ends, the pre-charging phase begins. At this time, the first switched capacitor network 1 is connected to the second switched capacitor network 2, and the first switched capacitor network 1 is also connected to the third switched capacitor network 3. The pre-charging circuit 6 is connected to the second switched capacitor network through the switching network 5, and the pre-charging circuit 6 is also connected to the third switched capacitor network 3 through the switching network 5. This forms a closed-loop circuit composed of the first switched capacitor network 1, the second switched capacitor network 2, the pre-charging circuit, and the third switched capacitor network. The capacitors in the switched capacitor networks of this closed-loop circuit will perform self-balancing of capacitor charge according to the law of conservation of charge, realizing the charging and discharging of the capacitors. Through self-balancing of charge, part of the sampled charge on the first switched capacitor network 1 is transferred to the second switched capacitor network 2 and the third switched capacitor network 3. After the pre-charging phase ends, the amplification phase begins. The pre-charging circuit 6 on the closed-loop circuit is disconnected from the main circuit, and the fully differential amplifier 4 is connected to the closed-loop circuit through the switching network 5. The fully differential amplifier 4 transfers the remaining sampling charge on the first switching network 1. Because the capacitor charge self-balances according to the law of charge conservation during the pre-charging phase, the charging and discharging speed of the capacitor is very high, improving the settling speed of the switched-capacitor amplifier. Furthermore, by first performing partial charge transfer in the pre-charging phase and then transferring the remaining charge using the fully differential amplifier, the workload of the fully differential amplifier is reduced, thus lowering its power consumption. This solves the technical problem in existing technologies where higher settling speed and lower power consumption cannot be simultaneously achieved in switched-capacitor amplifiers, resulting in a technical effect of improving the settling speed of the switched-capacitor amplifier while reducing its power consumption.
[0023] Preferably, combined with Figure 3 As shown, the pre-charge circuit 6 includes a first pre-charge capacitor C. pre Second pre-charge capacitor C pre First switch SW 9a Second switch SW 9b The first pre-charge capacitor C pre The first end is connected to the first switch SW 9a With the first input voltage signal V ip Connected, the first pre-charge capacitor C pre The first terminal is also connected to the third output terminal of the switching network, and the first pre-charge capacitor C pre The second terminal is connected to the reference common-mode voltage signal V. cm Connected, the second pre-charge capacitor C pre The first end is connected to the second switch SW 9b With the second input voltage signal V inConnected, the second pre-charge capacitor C pre The second terminal is also connected to the fourth output terminal of the switching network 5, and the second pre-charge capacitor C pre The second terminal is connected to the reference common-mode voltage signal V. cm Connected. First switch SW 9a Timing and second switch SW 9b The timing sequence is Timing. In the sampling phase, The first switch SW is at a high level. 9a Second switch SW 9b All are on, the first input voltage signal V ip Give the first pre-charge capacitor C pre Charging, second input voltage signal V in Give the second pre-charge capacitor C pre Charging. During the pre-charge phase and the amplification phase, The first switch SW is at a low level. 9a Second switch SW 9b All are disconnected. By pre-charging the pre-charged capacitor in the sampling phase, the charged pre-charged capacitor is connected to the closed-loop circuit in the pre-charged phase to achieve charge self-balancing between capacitors.
[0024] The differential input voltage signal V at the last moment of the sampling phase ip -V in Noted as V in The differential voltage V at the last moment of the sampling phase op -V on Noted as V fb (For switched capacitor amplifiers, V) fb =0), the differential voltage across the non-inverting and inverting input terminals of the fully differential amplifier at the end of the pre-charge phase is denoted as V. x Traditional switched-capacitor amplifiers do not have a pre-charge phase; the amplifier immediately processes a voltage of -V at the initial moment of the amplification phase. in The signal. It is clear that as long as V... x Compared to -V in With the same sign and a sufficiently small amplitude, pre-charging is achieved, accelerating the settling speed of the switched-capacitor amplifier. It can be deduced that:
[0025]
[0026] For a switched-capacitor amplifier, V fb It is always 0V. As can be seen from formula (1), compared to traditional timing, V... x Attenuation was achieved; for example, choosing C. pre =C s =2*C fb hour,
[0027]
[0028] For switched-capacitor integrators used in feedforward Delta-Sigma ADCs, V fb It can be designed to operate at no more than half the power supply voltage. If C is selected... pre =C s =0.2*C fb ,
[0029]
[0030] The working process of a traditional circuit is as follows: at the start of the amplification phase, V x Instantly becomes -V in Then, a fully differential amplifier is used to establish the voltage until V. x Established to near 0V (corresponding to the virtual short of the fully differential amplifier), if V x After the pre-charge is complete, its absolute value can be greater than |V. in The smaller the amplitude, the smaller the amplifier's setup amplitude, resulting in a faster setup speed. In the pre-charge phase, the capacitors self-balance their charges according to the law of charge conservation, and then the remaining charge is transferred by the fully differential amplifier in the amplification phase. It is evident that the invented pre-charge circuit significantly reduces the amplifier's load, whether for switched-capacitor amplifiers or switched-capacitor integrators, thereby improving the amplifier's setup speed while reducing its overall power consumption.
[0031] Optionally, the pre-charge circuit is a single wire, with its first end connected to the third output terminal of the switching network 5 and its second end connected to the fourth output terminal of the switching network 5. Directly connecting the non-inverting and inverting branches of the fully differential amplifier with a wire can also achieve charge self-balancing between capacitors according to the law of conservation of charge. In this case, V x It can be represented as:
[0032]
[0033] For a switched-capacitor amplifier, V fb It is always 0V. If C is selected... s =2*C fb ,
[0034]
[0035] For switched-capacitor integrators used in feedforward Delta-Sigma ADCs, V fb It can be designed to operate at no more than half the power supply voltage. If C is selected... s =0.2*C fb ,
[0036]
[0037] At the final moment of the sampling phase, before the pre-charging phase, a stable charge is stored on the sampling capacitor, and the amount of charge is V. in and V fb The decision is made that, until the pre-charge phase, capacitor C... s C fb Neither of the common positive electrodes has other pathways, C fb There are no other pathways at the negative electrode, meaning that the charge is conserved before and after the pre-charge phase; there is no net inflow or outflow. Using this conservation law, an equation can be derived, which in turn leads to the value of V after the pre-charge phase is complete. x That is, formula (2). It can be seen that whether it is a switched capacitor amplifier or a switched capacitor integrator, the invented pre-charge circuit can reduce the burden of the amplifier, thereby improving the amplifier's settling speed while reducing the overall power consumption of the amplifier. Moreover, the selected pre-charge circuit has a simple and effective structure.
[0038] Optionally, the first switched capacitor network 1 includes a first sampling capacitor C. s Second sampling capacitor C s Third switch SW 1a Fourth switch SW 1b Fifth switch SW 3a Sixth switch SW 3b Seventh switch SW 2a Eighth switch SW 2b Ninth switch SW 4a and the tenth switch SW 4b The first sampling capacitor C s The first end is connected to the third switch SW 1a With the first input voltage signal V ip Connected, the first sampling capacitor C s The first end is also connected to the fifth switch SW 3a The first sampling capacitor C is connected to the reference common-mode voltage. s The second end is connected to the ninth switch SW 4a The first sampling capacitor C is connected to the input terminal of the second switched capacitor network 2. s The second end is also connected to the seventh switch SW 2a With reference common-mode voltage V cm Connected, the second sampling capacitor C s The first end is connected to the fourth switch SW 1b With the second input voltage signal V in Connected, the second sampling capacitor C s The first end is also connected to the sixth switch SW 3b With reference common-mode voltage V cmConnected, the second sampling capacitor C s The second end is connected to the tenth switch SW 4b The second sampling capacitor C is connected to the input terminal of the third switched capacitor network 3. s The second end is also connected to the eighth switch SW 2b With reference common-mode voltage V cm Connected. Third switch SW 1a Fourth switch SW 1b Seventh switch SW 2a and the eighth switch SW 2b The timing is the same, for Timing, fifth switch SW 3a and the sixth switch SW 3b The timing is the same, for Timing, Ninth Switch SW 4a and the tenth switch SW 4b The timing is the same, for Timing. In the sampling phase, A high level indicates the corresponding switch is in the ON state, timing... and timing A low level corresponds to an off switch; in the pre-charge and amplification phases, the timing... and timing A high level indicates the corresponding switch is in the ON state, timing... When the signal is low, the corresponding switch is in the off state.
[0039] Optionally, the first switched capacitor network 1 further includes an eleventh switch SW. 8a and the twelfth switch SW 8b Eleventh switch SW 8a With the ninth switch SW 4a Parallel connection, twelfth switch SW 8b With the tenth switch SW 4b Parallel connection, and the eleventh switch SW 8a Compared to the ninth switch SW 4a Delayed shutdown, twelfth switch SW 8b Compared to the tenth switch SW 4b Delayed shutdown. In the amplified phase, The eleventh switch SW is at a high level. 8a and the twelfth switch SW 8b In the on state, The ninth switch SW is at a high level. 4a and the tenth switch SW 4b In the on state, when the amplification phase is about to end, Compare First, it goes low, i.e., the eleventh switch SW. 8aand the twelfth switch SW 8b Compared to the ninth switch SW 4a and the tenth switch SW 4b Delayed shutdown reduces the clock feedthrough effect of switched-capacitor amplifiers without sacrificing their settling speed.
[0040] Optionally, the eleventh switch SW 8a The size is larger than the ninth switch SW 4a Small size, twelfth switch SW 8b The size is larger than the tenth switch SW 4b Small in size. Eleventh switch SW 8a The size is much smaller than the ninth switch SW 4a Size, Twelfth switch SW 8b The size is much smaller than the tenth switch SW 4b Regarding the size, in the final stage of the magnification phase: first turn off the ninth switch SW. 4a and the tenth switch SW 4b (correspond (falling edge), at this time the clock feedthrough will be activated by the still-conducting eleventh switch SW. 8a and the twelfth switch SW 8b Absorbed; finally, turn off the small eleventh switch SW. 8a and the twelfth switch SW 8b In this way, using parallel large and small switches can help reduce clock feedthrough effects.
[0041] Optionally, the second switched capacitor network 2 includes a first feedback capacitor C. fb and the thirteenth switch SW 5a 13th switch SW 5a With the first feedback capacitor C fb Parallel connection, first feedback capacitor C fb The first terminal is connected to the first output terminal of the first switched capacitor network 1, and the first feedback capacitor C fb The second terminal is connected to the first input terminal of the switching network 5.
[0042] Optionally, the third switched capacitor network 3 includes a second feedback capacitor C. fb and the fourteenth switch SW 5b Fourteenth switch SW 5b With the second feedback capacitor C fb Parallel connection, second feedback capacitor C fb The first terminal is connected to the second output terminal of the first switched capacitor network 1, and the second feedback capacitor C fb The second terminal is connected to the second input terminal of the switching network 5.
[0043] In some embodiments, the difference between the amplifier and the integrator is that the amplifier periodically adjusts the feedback capacitor C. fb A reset is performed, but the integrator is not reset again after the initial reset and until the end of the operation. Timing diagram... The timing of the corresponding amplifier, and The timing is the same. When the signal is high, the feedback capacitor is shorted and thus reset; when used as an integrator, the feedback capacitor C... fb Called the integrating capacitor C fb , The timing sequence corresponding to the integrator is used to adjust the integrating capacitor C during initial operation. fb Perform a reset. When it is high, the integrating capacitor C fb It is shorted and thus reset.
[0044] Optionally, the switching network 5 includes a fifteenth switch SW. 7a Sixteenth switch SW 6a Seventeenth switch SW 7b and the eighteenth switch SW 6b The output of the second switched capacitor network 2 is connected to the fifteenth switch SW. 7a Connected to the input of the pre-charging circuit 6, the output of the second switched capacitor network 2 is connected to the sixteenth switch SW. 6a The output of the third switched capacitor network 3 is connected to the non-inverting output of the fully differential amplifier 4, and the output of the third switched capacitor network 3 is connected to the seventeenth switch SW. 7b The output of the pre-charging circuit 6 is connected to the output of the third switched capacitor network 3, which is connected to the eighteenth switch SW. 6b Connected to the inverting output of the fully differential amplifier 4. Fifteenth switch SW 7a and the seventeenth switch SW 7b The timing is the same, both are Timing, Sixteenth Switch SW 6a and the eighteenth switch SW 6b The timing is the same, both are Timing. In the sampling phase, and All are low level; in the pre-charge phase, Low level, It is at a high level; in the amplification phase, High level It is a low level.
[0045] This invention provides an analog-to-digital converter including the aforementioned switched-capacitor amplifier.
[0046] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.
Claims
1. A switched-capacitor amplifier, characterized in that, The switched capacitor amplifier includes: The system comprises a first switched capacitor network, a second switched capacitor network, a third switched capacitor network, a pre-charge circuit, a switching network, and a fully differential amplifier. The first input terminal of the first switched capacitor network is connected to the first input voltage signal, the second input terminal of the first switched capacitor network is connected to the second input voltage signal, the first output terminal of the first switched capacitor network is connected to the non-inverting input terminal of the fully differential amplifier, and the second output terminal of the first switched capacitor network is connected to the inverting input terminal of the fully differential amplifier. The first switched capacitor network is used to sample the input voltage signal. The input terminal of the second switched capacitor network is connected to the first output terminal of the first switched capacitor network, and the output terminal of the second switched capacitor network is connected to the first input terminal of the switching network. The second switched capacitor network is used to receive the sampled charge of the first switched capacitor network. The input terminal of the third switched capacitor network is connected to the second output terminal of the first switched capacitor network, and the output terminal of the third switched capacitor network is connected to the second input terminal of the switching network. The third switched capacitor network is used to receive the sampled charge of the first switched capacitor network. The first output terminal of the switching network is connected to the non-inverting output terminal of the fully differential amplifier, the second output terminal of the switching network is connected to the inverting output terminal of the fully differential amplifier, the third output terminal of the switching network is connected to the input terminal of the pre-charge circuit, and the fourth output terminal of the switching network is connected to the output terminal of the pre-charge circuit. The switching network is used to connect the second switched capacitor network and the third switched capacitor network to the pre-charge circuit or to the fully differential amplifier via a switching switch. The pre-charge circuit is used to connect the in-phase and out-of-phase branches of the fully differential amplifier after the sampling time ends, so as to perform charge self-balancing between capacitors. The fully differential amplifier is used to transfer the remaining charge of the first switched capacitor network to the second switched capacitor network and the third switched capacitor network after the pre-charging circuit has pre-charged.
2. A switched-capacitor amplifier as described in claim 1, characterized in that, The pre-charge circuit includes a first pre-charge capacitor, a second pre-charge capacitor, a first switch, and a second switch. The first terminal of the first pre-charge capacitor is connected to the first input voltage signal through the first switch. The first terminal of the first pre-charge capacitor is also connected to the third output terminal of the switching network. The second terminal of the first pre-charge capacitor is connected to a reference common-mode voltage signal. The first terminal of the second pre-charge capacitor is connected to the second input voltage signal through the second switch. The second terminal of the second pre-charge capacitor is also connected to the fourth output terminal of the switching network. The second terminal of the second pre-charge capacitor is also connected to the reference common-mode voltage signal.
3. A switched-capacitor amplifier as described in claim 1, characterized in that, The pre-charging circuit is a wire, the first end of which is connected to the third output terminal of the switching network, and the second end of which is connected to the fourth output terminal of the switching network.
4. A switched-capacitor amplifier as described in claim 1, characterized in that, The first switched capacitor network includes a first sampling capacitor, a second sampling capacitor, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch, and a tenth switch. The first terminal of the first sampling capacitor is connected to the first input voltage signal via the third switch. The first terminal of the first sampling capacitor is also connected to a reference common-mode voltage via the fifth switch. The second terminal of the first sampling capacitor is connected to the input terminal of the second switched capacitor network via the ninth switch. The second terminal of the first sampling capacitor is also connected to the reference common-mode voltage via the seventh switch. The first terminal of the second sampling capacitor is connected to the second input voltage signal via the fourth switch. The first terminal of the second sampling capacitor is also connected to the reference common-mode voltage via the sixth switch. The second terminal of the second sampling capacitor is connected to the input terminal of the third switched capacitor network via the tenth switch. The second terminal of the second sampling capacitor is also connected to the reference common-mode voltage via the eighth switch.
5. A switched-capacitor amplifier as described in claim 4, characterized in that, The first switched capacitor network further includes an eleventh switch and a twelfth switch. The eleventh switch is connected in parallel with the ninth switch, and the twelfth switch is connected in parallel with the tenth switch. The eleventh switch turns off later than the ninth switch, and the twelfth switch turns off later than the tenth switch.
6. A switched-capacitor amplifier as described in claim 5, characterized in that, The eleventh switch is smaller than the ninth switch, and the twelfth switch is smaller than the tenth switch.
7. A switched-capacitor amplifier as described in claim 1, characterized in that, The second switched capacitor network includes a first feedback capacitor and a thirteenth switch. The thirteenth switch is connected in parallel with the first feedback capacitor. The first end of the first feedback capacitor is connected to the first output end of the first switched capacitor network, and the second end of the first feedback capacitor is connected to the first input end of the switching network.
8. A switched-capacitor amplifier as described in claim 1, characterized in that, The third switched capacitor network includes a second feedback capacitor and a fourteenth switch. The fourteenth switch is connected in parallel with the second feedback capacitor. The first end of the second feedback capacitor is connected to the second output end of the first switched capacitor network, and the second end of the second feedback capacitor is connected to the second input end of the switching network.
9. A switched-capacitor amplifier as described in claim 1, characterized in that, The switching network includes a fifteenth switch, a sixteenth switch, a seventeenth switch, and an eighteenth switch. The output of the second switched capacitor network is connected to the input of the pre-charge circuit through the fifteenth switch. The output of the second switched capacitor network is connected to the non-inverting output of the fully differential amplifier through the sixteenth switch. The output of the third switched capacitor network is connected to the output of the pre-charge circuit through the seventeenth switch. The output of the third switched capacitor network is connected to the inverting output of the fully differential amplifier through the eighteenth switch.
10. An analog-to-digital converter, characterized in that, Including a switched capacitor amplifier as described in any one of claims 1-9.