Half-encapsulation structure with sealed air cavity, module and electronic device

Abstract

This invention discloses a semi-encapsulated structure, module, and electronic device with a sealed air resonant cavity. The semi-encapsulated structure includes: a chip body having an electrode surface, a back surface opposite to the electrode surface, and a side surface connecting the electrode surface and the back surface; multiple electrodes formed on the electrode surface; a dielectric layer having a surface, forming a cavity between the surface and the electrode surface to accommodate the multiple electrodes; multiple bumps located within the cavity, surrounding the outer periphery of the electrodes and connecting the surface and the electrode surface; a near-sealing ring, the inner side of which is located within the outline of the chip body, forming an overlapping area; and a substrate solder resist layer covering the surface, side surface, and back surface, and connecting the electrode surface and the near-sealing ring. This invention offers high production efficiency, a simple process, and lower cost.

Description

Technical Field

[0001] This invention relates to a semi-encapsulated structure with a sealed air resonant cavity, and also to modules and electronic devices incorporating the semi-encapsulated structure, belonging to the field of semiconductor packaging technology. Background Technology

[0002] Currently, surface acoustic wave (SAW) filters are widely used in radio frequency (RF) front-end modules. SAW filters have many advantages, including high operating frequency, wide bandwidth, good frequency selectivity, small size and light weight. Moreover, they can be manufactured using the same processes as integrated circuits, making them simple to manufacture, low in cost, and with good frequency response consistency.

[0003] SAW filters are made by evaporating a metal film onto a piezoelectric material substrate, followed by photolithography to form a pair of interdigital transducers (IDTs) at each end. Therefore, the packaging of SAW filters must ensure that the surface of the IDTs cannot come into contact with other materials; that is, the chip surface must be a cavity structure, otherwise signal transmission will be affected.

[0004] Currently, the most common packaging method for SAW filters is to solder the filter onto a substrate, then coat, encapsulate, and dice it, followed by a second packaging onto the substrate. Alternatively, the capping and barrier are fabricated at the wafer end before packaging into the module. This process is relatively complex and costly. Summary of the Invention

[0005] The primary technical problem to be solved by this invention is to provide a semi-encapsulated structure with an air resonant cavity.

[0006] Another technical problem to be solved by the present invention is to provide a module including the above-mentioned semi-encapsulated structure.

[0007] Another technical problem to be solved by the present invention is to provide an electronic device including the above-described semi-encapsulated structure.

[0008] To achieve the above-mentioned technical objectives, the present invention adopts the following technical solution:

[0009] According to a first aspect of the present invention, a semi-encapsulated structure having a sealed air resonant cavity is provided, comprising:

[0010] The chip body has an electrode surface, a back surface opposite to the electrode surface, and a side surface connecting the electrode surface and the back surface, and a plurality of electrodes are formed on the electrode surface;

[0011] A dielectric layer having a surface, with a cavity formed between the surface and the electrode surface for accommodating multiple electrodes;

[0012] Multiple protrusions located within the cavity surround the outer periphery of the electrode and connect the surface and the electrode face;

[0013] The near-sealing ring has its inner side located within the area enclosed by the outer contour line of the chip body, forming an overlapping area;

[0014] A substrate solder resist layer covers the surface, the side surface, and the back surface, and the substrate solder resist layer connects the electrode surface and the near-sealing ring.

[0015] Preferably, the near-sealing ring extends into the overlapping area and is located between the surfaces of the chip body and the near-sealing ring to seal the gap between the chip body and the near-sealing ring.

[0016] Preferably, the near-sealing ring is a discontinuous metal or insulating barrier with gaps.

[0017] Preferably, the semi-encapsulation structure further includes a blind via located in the dielectric layer, and a height difference is formed between the surface of the dielectric layer and the bottom of the blind via.

[0018] A portion of the bump is confined within the blind hole.

[0019] Preferably, the near-sealing ring is composed of a copper pillar and a second dielectric layer.

[0020] Preferably, the second dielectric layer is a photocurable or photothermal hybrid curable dry film material, sandwiched between the surface of the substrate solder resist layer and the dielectric layer, and located on the outer periphery of the bump.

[0021] Preferably, the second dielectric layer surrounds the copper pillar and fills the area between the copper pillar and the bump.

[0022] Preferably, the semi-encapsulated structure further includes a shielding layer.

[0023] The surface of the near-sealing ring is electrically connected to the shielding layer through a through hole, so that the shielding layer, the through hole and the near-sealing ring can be used together to achieve shielding.

[0024] According to a second aspect of the present invention, a module is provided, comprising a semi-encapsulated structure having a sealed air resonant cavity as described above.

[0025] According to a third aspect of the present invention, an electronic device is provided, comprising a semi-encapsulated structure having a sealed air resonant cavity as described above.

[0026] Compared with existing technologies, this invention has the following technical features: 1) It utilizes a panel-level cavity for fabrication, resulting in high production efficiency; since the filter soldering is completed before the conventional substrate solder mask process, and the solder mask lamination forms a cavity, the process is simple and the cost is lower; 2) It uses discontinuous near-sealing rings to ensure that welding impurities can pass through the gaps during the cleaning process after filter soldering, thus ensuring filter performance; 3) It uses the substrate solder mask layer to seal the gaps formed between the near-sealing ring and the chip body, ensuring that the solder mask material will not overflow onto the interdigitated electrode surface during the solder mask lamination process, thus ensuring filter performance; 4) It can use conventional substrate processes and set a shielding layer to avoid signal interference; 5) It is suitable for single bare chip packaging structures and can be directly coated and shipped. Attached Figure Description

[0027] Figure 1 This is a cross-sectional schematic diagram of a semi-encapsulated structure with a sealed air resonant cavity in the first embodiment of the present invention.

[0028] Figure 2 for Figure 1 A top view of the semi-encapsulated structure shown.

[0029] Figure 3 This is a cross-sectional schematic diagram of a semi-encapsulated structure with a sealed air resonant cavity in the second embodiment of the present invention;

[0030] Figure 4 for Figure 3 A top view of the semi-encapsulated structure shown.

[0031] Figure 5 This is a cross-sectional schematic diagram of a semi-encapsulated structure with a sealed air resonant cavity in the third embodiment of the present invention.

[0032] Figure 6 for Figure 5 A top view of the semi-encapsulated structure shown.

[0033] Figure 7 This is a cross-sectional schematic diagram of a semi-encapsulated structure with a sealed air resonant cavity in the fourth embodiment of the present invention.

[0034] Figure 8 for Figure 7 A top view of the semi-encapsulated structure is shown. Detailed Implementation

[0035] The technical content of the present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0036] (First Embodiment)

[0037] like Figure 1As shown, the semi-encapsulated structure provided in this embodiment of the invention includes a chip body 1, a dielectric layer 2, and multiple bumps 4 located in a cavity 3.

[0038] The chip body 1, as described below using a SAW filter chip as an example, is made of a wafer and has an electrode surface 10A, a back surface 10B opposite to the electrode surface 10A, and a side surface 10C connecting the electrode surface 10A and the back surface 10B. Multiple electrodes (e.g., interdigitated electrodes) 12 and multiple bumps 4 are formed on the electrode surface 10A.

[0039] The cavity contains multiple bumps 4, which can be copper pillars or solder, etc. The height of the bumps 4 (the height after reflow soldering) may be higher or lower than the height of the cavity. The bumps 4 are arranged around the outer periphery of the electrode 2 to form a cavity 3 covering the electrode 2 between the chip body 1 and the dielectric layer 2. If copper bumps 4 are used to surround the electrode 2, then the bumps 4 can provide both support and conductivity.

[0040] A substrate solder resist layer 11 is applied to the back surface 10B and side surface 10C of the chip body 1, as well as to the surface 20 of the dielectric layer 2 adjacent to the side surface 10C. The substrate solder resist layer 11 is a continuous cover layer formed by coating solder resist material onto the back surface 10B, side surface 10C, and surface 20. Conductive pads 21 are provided on the surface 20, and their positions correspond to the bumps 4. The bumps 4 connect the surface 20 and the electrode surface 10A.

[0041] Combination Figure 1 and Figure 2 As shown, a near-sealing ring 31 is formed around the cavity 3. The near-sealing ring 31 is made of copper or an insulating material. The near-sealing ring 31 can also be made of the same dielectric material as the dielectric layer 2. The inner side 312 of the near-sealing ring 31 is located within the area enclosed by the outline of the chip body 1. In other words, the inner side 312 of the near-sealing ring 31 is located within the area of ​​the projection of the outline of the chip body 1 onto the surface 20 of the dielectric layer 2. Here, "inner" refers to the direction towards the geometric center point of the chip; "outer" refers to the direction away from the geometric center of the chip. In other words, the inner side 312 of the near-sealing ring 31 is located within the projection line of the side surface 10C of the chip body 1 onto the dielectric layer 2. Figure 2 Inside (as shown by the dashed line). That is, within Figure 2 The projection of the side surface 10C of the chip body 1 in the vertical direction shown (as shown) Figure 2 The area shown in the dashed box overlaps with the near-sealing ring 31, forming a shape as shown in the image. Figure 1 The overlapping area 100 is indicated by the dashed circle in the middle.

[0042] Furthermore, the near-sealing ring 31 surrounds the outer periphery of the protrusion 4, therefore, in Figure 1In the cross-sectional view shown, the horizontal distance from the near-sealing ring 31 to the electrode 2 is greater than the horizontal distance from the bump 4 to the electrode 2. This ensures that during the solder mask lamination process, the solder mask material is blocked by the near-sealing ring 31 and will not overflow onto the surface of the electrode 2, thus guaranteeing the stable performance of the filter.

[0043] like Figure 2 As shown, the near-sealing ring 31 is a discontinuous barrier made of metal or insulating material, meaning that the near-sealing ring 31 has a gap 310. Therefore, after the chip body 1 is soldered, during the chip cleaning process, the residue in the cavity 3 can be discharged through the gap 310.

[0044] Dielectric layer 2, serving as a substrate, is used to support the chip 1. Metal pads 21 are formed on the surface 20 of dielectric layer 2. For example... Figure 2 As shown, the connecting pad 21 connects to the bump 4 to achieve electrical connection between the chip body 1 (filter chip) and the dielectric layer 2. The connecting pad 21 can correspond one-to-one with the bump 4, located on the side 10C of the chip body 1, projected onto the dielectric layer 2. Figure 2 (shown within the dashed box). Therefore, the connecting pad 21 is located inside the area enclosed by the sealing ring 31, but outside the projection of the electrode 2 onto the surface 20.

[0045] On the surface of dielectric layer 2 away from the chip body 1, there is solder resist (SR) 23 and pads 29. Pads 29 are used for electrical connection with the circuit board. Optionally, solder resist 23 may be omitted. Pads 29 may be embedded in dielectric layer 2 or on the surface of dielectric layer 2.

[0046] In this embodiment, the substrate solder resist layer 11 extends into the overlap region 100 and is located between the chip body 1 and the surface 311 of the near-sealing ring 31 to seal the gap between the chip body 1 and the near-sealing ring 31, thereby ensuring the airtightness of the cavity 3. The substrate solder resist layer 11 is formed of a dry film material, which can be an organic, inorganic, or resin-based dry film material. Therefore, it can be rapidly cured when pressed into the overlap region 100, thus being confined within the overlap region and preventing it from flowing into the inside of the near-sealing ring 31.

[0047] (Second Embodiment)

[0048] like Figure 3 and Figure 4As shown, the semi-encapsulated structure with a sealed air resonant cavity provided in this embodiment differs from the first embodiment. In this embodiment, the metal bump 4 is located inside the blind via (VIA) 25 formed in the dielectric layer 2. A height difference is formed between the surface 20 of the dielectric layer 2 and the bottom of the blind via 25. Between the bump 4 and the connecting pad 21, there is also a bump connecting pad 24. The connecting pad 21 and the bump connecting pad 24 are completely disposed inside the blind via 25, and there is a height difference between the bump connecting pad 24 and the surface 20 of the dielectric layer, so that a portion of the bump 4 can be confined within the blind via 25. This height difference design is similar to a Solder Mask Defined (SMD) structure, which is beneficial for fixing the soldering shape of the bump 4, thereby reducing stress and lowering the risk of bump failure.

[0049] The height difference between the surface 20 of the dielectric layer 2 and the bottom of the blind hole 25 can be formed by partially etching the dielectric support 2 at the blind hole 25, or by laminating the dielectric layer with through holes or through grooves onto the substrate and then filling the holes with electroplating.

[0050] (Third Embodiment)

[0051] like Figure 5 and Figure 6 As shown, unlike the first embodiment, the semi-encapsulated structure with a sealed air resonant cavity in this embodiment adds a second dielectric layer 5. The second dielectric layer 5 is a photocurable or photothermal hybrid curable dry film material, sandwiched between the substrate solder resist layer 11 and the surface 20 of the dielectric layer 2, and located on the outer periphery of the bump 4. The space between the bump 4 and the second dielectric layer 5 should be empty, and the solder from the bump will flow and fill it during soldering.

[0052] Furthermore, in this embodiment, the near-sealing ring 3 is composed of a copper pillar 34 and a second dielectric layer 5. The second dielectric layer 5 surrounds the copper pillar and fills the area between the copper pillar 34 and the bump 4. Similar to the first embodiment, the near-sealing ring 33 is also a discontinuous annular structure (e.g., Figure 6 As shown), the substrate solder resist 11 fills the overlapping area between the second dielectric layer 5 and the chip body 1 to ensure that the solder resist does not flow into the surface of the electrode (interdigital transducer) 12 during lamination, thereby ensuring the stable performance of the filter chip. Similar to the first embodiment, overlap refers to the projection of the side surface 10C of the chip body onto the dielectric layer 2 (as shown). Figure 6 As shown in the dashed box in the image, it overlaps with the projection of the second dielectric layer 5 onto the dielectric layer, but does not overlap with the projection of the copper pillar 34 onto the dielectric layer (the copper pillar 34 is shown in the image). Figure 6 (Outside the dashed box in the middle).

[0053] The lower surface of the bump 4 is interconnected with the internal connection pad 21 of the dielectric layer 2; the copper pillar 34 is interconnected with the external connection pad 21A of the dielectric layer 2. The external connection pad 21A surrounds the internal connection pad 21 on the horizontal plane.

[0054] (Fourth Embodiment)

[0055] like Figure 7 and Figure 8 As shown, compared with the first embodiment, this embodiment adds a shielding layer 6 to the outer surface of the substrate solder resist layer 11 to achieve shielding between chips. The shielding layer 6 can be a single-component metal such as copper, titanium, nickel, tin, or cobalt, or a composite material formed by arbitrary stacking. The shielding layer 6 can be formed by electroplating, sputtering, or stacking.

[0056] Furthermore, in this embodiment, a through-hole (or solid hole) 111 is formed on the solder resist layer 11 of the substrate. The near-sealing ring 35 is made of a metallic material and is wider than the near-sealing ring 31 in the first embodiment. That is, the surface 311 of the near-sealing ring 35 is large enough to be electrically connected to the shielding layer 6 through the through-hole 111, thereby achieving shielding by utilizing the shielding layer 6, the through-hole 111, and the near-sealing ring 35 together.

[0057] Furthermore, a shielding wall 28 is formed in the dielectric layer 2 below the near-sealing ring 35. The shielding wall 28 is a metal-plated hole penetrating the dielectric layer 2 to electrically connect the near-sealing ring 35 to the pad 29. Thus, the shielding layer 6, the through-hole 111, the near-sealing ring 35, and the shielding wall 28 together form a shielding path to further improve the shielding effect.

[0058] This invention provides a method for soldering filter chips and forming an air resonant cavity during substrate processing. The method involves creating a cavity in the dielectric layer within a panel-level system, forming a barrier with copper or substrate material (copper bonded to substrate), and simultaneously forming the solder mask layer (roof) on the substrate. Therefore, utilizing the panel-level cavity fabrication results in high production efficiency; and because filter soldering is completed before the conventional substrate solder mask process, and the solder mask lamination forms the cavity, the process is simple and cost-effective.

[0059] This invention can be applied to single bare chip packaging structures and can be directly coated and shipped.

[0060] A discontinuous sealing ring formed by copper pillars or dielectric layers under the solder resist is used to ensure that welding impurities can pass through the gaps during the cleaning process after the filter is soldered, thus ensuring the filter performance.

[0061] The gap formed between the copper pillars or dielectric layer and the chip body ensures that the solder resist material will not overflow onto the surface of the interdigitated electrodes during the solder resist lamination process, forming a sealed air resonant cavity and ensuring the performance of filters such as SAW or BAW.

[0062] Conventional substrate processes can be used to create a shielding layer on the solder resist layer of the substrate, which can prevent signal interference between the filter chip and other chips during module packaging.

[0063] This invention also provides a module comprising a semi-encapsulated structure with a sealed air resonant cavity as described above. This invention is applicable to module packaging such as frequency converter modules, where a film is deposited in the chip body area, and conventional packaging processes are used in other areas. For example, this invention can employ an IDT on Cap Wafer to solder a cap wafer with interdigitated electrodes to a carrier wafer using Cu / Sn / Cu or similar bonding agents, or to bond them together with an adhesive, to prefabricate the cavity, thereby enabling the module packaging containing the filter die to be completed using conventional packaging processes.

[0064] The present invention also provides an electronic device comprising a semi-encapsulated structure having a sealed air resonant cavity as described above. This electronic product can be a smartphone, tablet computer, wearable electronic device, intelligent connected vehicle, etc.

[0065] The foregoing has provided a detailed description of the semi-encapsulated structure, module, and electronic device with a sealed air resonant cavity provided by this invention. Any obvious modifications made by those skilled in the art without departing from the essence of this invention will constitute an infringement of the patent rights of this invention and will incur corresponding legal liability.

Claims

1. A semi-hermetic structure with a sealed air cavity, characterized in that include: The chip body has an electrode surface, a back surface opposite to the electrode surface, and a side surface connecting the electrode surface and the back surface, and a plurality of electrodes are formed on the electrode surface; The dielectric layer, as a substrate, has a surface, and a cavity is formed between the surface and the electrode surface to accommodate multiple electrodes. Multiple protrusions located within the cavity surround the outer periphery of the electrode and connect the surface and the electrode face; The near-sealing ring has its inner side located within the area enclosed by the outer contour line of the chip body, forming an overlapping area; A substrate solder resist layer, formed of a dry film material, covers the surface, the side surface, and the back surface, and the substrate solder resist layer connects the electrode surface and the near-sealing ring. The substrate solder mask extends into the overlapping area and is located between the chip body and the surface of the near-sealing ring to seal the gap between the chip body and the near-sealing ring.

2. The semi-encapsulated structure with a sealed air resonant cavity as described in claim 1, characterized in that: The near-sealing ring is a discontinuous metal or insulating barrier with gaps.

3. The semi-hermetic structure with a sealed air resonator according to claim 2, characterized in that It includes a blind via located in the dielectric layer, with a height difference between the surface of the dielectric layer and the bottom of the blind via, and a portion of the bump is confined within the blind via.

4. The semi-encapsulated structure with a sealed air resonant cavity as described in claim 2, characterized in that: The near-sealing ring consists of a copper pillar and a second dielectric layer.

5. The semi-encapsulated structure with a sealed air resonant cavity as described in claim 4, characterized in that: The second dielectric layer is a photocurable or photothermal hybrid curable dry film material, sandwiched between the surface of the substrate solder resist layer and the dielectric layer, and located on the outer periphery of the bump.

6. The semi-encapsulated structure with a sealed air resonant cavity as described in claim 5, characterized in that: The second dielectric layer surrounds the copper pillar and fills the area between the copper pillar and the bump.

7. The semi-hermetic structure with a sealed air resonator according to claim 1, characterized in that It also includes a shielding layer, the surface of which is electrically connected to the shielding layer through a through hole, so that the shielding layer, the through hole and the near-sealing ring can be used together to achieve shielding.

8. A module characterized in that A semi-encapsulated structure comprising any one of claims 1 to 7 having a sealed air resonant cavity.

9. An electronic device, characterized in that... A semi-encapsulated structure comprising any one of claims 1 to 7 having a sealed air resonant cavity.

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