Superconducting pulse counter and method for increasing operating frequency of superconducting circuits

Abstract

Provided are a superconducting pulse counter and a method for increasing the operating frequency of a superconducting circuit, the counter comprising: n TFFE devices, p TFFO devices, and m superconducting devices with clock ports, wherein n and m are positive integers, and p is an integer greater than or equal to 0; the n+m+p devices are connected in series, wherein the input of the first device is the input of the superconducting pulse counter, the output of each of the n+m+p devices is connected to the input of the next device, and the output of the last device is the output of the superconducting pulse counter; the clock ports of the m superconducting devices with clock ports are connected to the clock port of the superconducting pulse counter; and wherein the superconducting pulses input to the input and clock port of the superconducting pulse counter have the same frequency.

Description

Technical Field

[0001] This invention relates to the field of superconducting electronic circuits, and in particular to a superconducting pulse counter and a method for increasing the operating frequency of superconducting circuits. Background Technology

[0002] There is a simple and convenient counter in the superconducting RSFQ circuit, which is composed of the even-two divider (TFFE) logic device in the superconducting RSFQ circuit. Figure 1A A schematic diagram of a prior art TFFE device is shown. Figure 1B The state transition diagram of a prior art TFFE device is shown. (Example) Figure 1A and Figure 1B As shown, the TFFE device includes an input terminal din for receiving superconducting pulses and an output terminal dout for outputting superconducting pulses. Assuming the initial state of the TFFE device is 0, if no superconducting pulse is input, the TFFE device remains in state 0, and no superconducting pulse is output. After the first superconducting pulse is input, the TFFE device changes to state 1, and no superconducting pulse is output. After the second superconducting pulse is input, the TFFE device changes to state 0, and the output terminal dout will output a superconducting pulse. That is, when an even number of superconducting pulses are input to the input terminal din of the TFFE device, the output terminal dout of the TFFE device will output a superconducting pulse.

[0003] Figure 2 A schematic diagram of a prior art superconducting pulse counter is shown. (For example...) Figure 2 As shown, the superconducting pulse counter includes an input terminal din for receiving superconducting pulses and an output terminal dout for outputting superconducting pulses. The superconducting pulse counter includes n TFFE devices, TFFE1, TFFE2…TFFEn, where n is a positive integer. The number of countable devices N of the superconducting pulse counter is... cnt =2 n When superconducting pulses are continuously input to the input terminal din of the superconducting pulse counter, every 2 inputs... n A superconducting pulse will be output at the output terminal dout of the superconducting pulse counter, thereby realizing its counting function.

[0004] However, existing superconducting pulse counters suffer from drawbacks such as high delay and poor scalability. On the one hand, the delay t of existing counters... cnt =n*t TFFE +t wire (where n*t) TFFE t is the total delay of n TFFEs in the counter; wire(where n is the delay of all connections in the counter). Therefore, it is evident that the larger n is, i.e., the larger the counting capacity of the counter, the higher the counter delay will be. Counters are widely used in digital systems, and in many cases, especially in feedback loops, the counter delay becomes a key factor limiting the system frequency. On the other hand, existing counters can only generate 2... n The counting range is poorly scalable. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention proposes a superconducting pulse counter, comprising:

[0006] There are n TFFE devices, p TFFO devices, and m superconducting devices with clock ports, where n and m are positive integers, and p is an integer greater than or equal to 0;

[0007] The n+m+p devices are linearly connected in series, wherein the input terminal of the first device is the input terminal of the superconducting pulse counter, the output terminal of each of the n+m+p devices is connected to the input terminal of the next device, and the output terminal of the last device is the output terminal of the superconducting pulse counter; the clock terminals of the m superconducting devices with clock ports are connected to the clock terminal of the superconducting pulse counter; and

[0008] The superconducting pulses input to the input terminal and the clock terminal of the superconducting pulse counter have the same frequency.

[0009] In one embodiment, the m superconducting devices with clock ports are not connected adjacent to each other.

[0010] In one embodiment, the counting capacity of the superconducting pulse counter is:

[0011] N cnt =2 n+p +m-∑ i∈S1 2 i-1

[0012] Where i is the position number of all TFFE and TFFO devices from the input to the output of the superconducting pulse counter, and the m superconducting devices with clock ports are not included in the numbering; S1 is the set of position numbers of TFFO devices.

[0013] In one embodiment, when the initial state of the superconducting device with clock port is state 0 and a superconducting pulse is input, the superconducting device with clock port will change from state 0 to state 1. In this state, when the clock signal arrives at its clock terminal, a superconducting pulse will be output at the output terminal, and the superconducting device with clock port will change to state 0.

[0014] In one embodiment, the superconducting device with a clock port is a DFF device, an RDFF device with its output terminal connected to a reset terminal, or an NDRO device with its output terminal connected to a reset terminal.

[0015] In one embodiment, the superconducting pulse counter further includes an SPL device, which includes an input terminal for receiving a clock signal and m output terminals for outputting the clock signal to the clock terminals of the m superconducting devices with clock ports.

[0016] In one embodiment, all superconducting devices are reset after one count is completed.

[0017] In one embodiment, each of the n+m+p devices has a reset terminal, and the output terminal of the superconducting pulse counter is connected to the reset terminals of the n+m+p devices.

[0018] The present invention also provides a method for increasing the operating frequency of a superconducting circuit, comprising:

[0019] Insert m superconducting devices with clock ports into a superconducting circuit that includes n superconducting devices, where n and m are positive integers;

[0020] The n+m devices are connected in linear series, wherein the input terminal of the first device is the input terminal of the superconducting circuit, the output terminal of each of the n+m devices is connected to the input terminal of the next device, and the output terminal of the last device is the output terminal of the superconducting circuit; the clock terminals of the m superconducting devices with clock ports are connected to the clock terminal of the superconducting circuit.

[0021] The n superconducting devices do not have clock ports, and the superconducting pulses input to the input and clock terminals of the superconducting circuit have the same frequency.

[0022] In one embodiment, the m superconducting devices with clock ports are not connected adjacently to each other. In another embodiment, the n superconducting devices include TFFE devices and / or TFFO devices.

[0023] The superconducting pulse counter and method for increasing the operating frequency of a superconducting circuit in this invention increase the upper limit of the superconducting circuit's operating frequency by inserting a superconducting device with a clock port into the circuit and dividing it into more pipeline stages. The superconducting pulse counter in this invention effectively prevents the counter's operating frequency from decreasing due to increased counting capacity, significantly increasing the upper limit of the operating frequency to tens of GHz, enabling its application in superconducting digital circuit systems with higher frequencies. Furthermore, based on the division of pipeline stages, the superconducting pulse counter in this invention replaces the TFFE at corresponding positions with TFFO, simplifying the full count rather than being limited to 2 stages. n count. Attached Figure Description

[0024] Figure 1A A schematic diagram of a prior art TFFE device is shown.

[0025] Figure 1B The state transition diagram of a prior art TFFE device is shown.

[0026] Figure 2 A schematic diagram of a prior art superconducting pulse counter is shown.

[0027] Figure 3A A schematic diagram of a prior art DFF device is shown.

[0028] Figure 3B The state transition diagram of a prior art DFF device is shown.

[0029] Figure 3C A schematic diagram of a prior art RDFF trigger is shown.

[0030] Figure 4A A schematic diagram of a prior art NDRO device is shown.

[0031] Figure 4B The state transition diagram of a prior art NDRO device is shown.

[0032] Figure 5 A schematic diagram of a prior art SPL2 device is shown.

[0033] Figure 6A A schematic diagram of a prior art TFFO device is shown.

[0034] Figure 6B The state transition diagram of a prior art TFFO device is shown.

[0035] Figure 6C A schematic diagram of a TFFEC device according to an embodiment of the present invention is shown.

[0036] Figure 6D A schematic diagram of a TFFEC device according to an embodiment of the present invention is shown.

[0037] Figure 6E A schematic diagram of a TFOC device according to an embodiment of the present invention is shown.

[0038] Figure 6F A schematic diagram of the structure of a TFOC device according to an embodiment of the present invention is shown.

[0039] Figure 7 A schematic diagram of a superconducting pulse counter according to an embodiment of the present invention is shown.

[0040] Figure 8A A schematic diagram of a superconducting pulse counter according to another embodiment of the present invention is shown.

[0041] Figure 8B A schematic diagram of a superconducting pulse counter according to yet another embodiment of the present invention is shown.

[0042] Figure 9A A schematic diagram of a prior art high-frequency clock generator is shown.

[0043] Figure 9B A schematic diagram of a high-frequency clock generator according to an embodiment of the present invention is shown. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the embodiments given in this invention are for illustrative purposes only and do not limit the scope of protection of this invention.

[0045] This invention relates to superconducting RSFQ circuits. In superconducting RSFQ circuits, the binary information is not represented by DC voltage as in conventional digital circuits, but rather by the presence or absence of a superconducting pulse between two adjacent clock pulses to represent the logic values ​​"1" and "0". For ease of explanation, this invention uses states 0, 1, and 2 to distinguish the states of the superconducting device. These states are used only to illustrate the state transitions of the superconducting device and are independent of the presence or absence of a superconducting pulse.

[0046] The superconducting pulse counter in this invention relates to existing D flip-flops (DFF), D flip-flops with reset terminals (RDFF), nondestructive readout registers (NDRO), splitters (SPL), even-two dividers (TFFE), and odd-two dividers (TFFO). The superconducting devices described above are described in detail below with reference to the accompanying drawings.

[0047] Figure 3A A schematic diagram of a prior art DFF device is shown. Figure 3B The state transition diagram of a prior art DFF device is shown. For example... Figure 3A and Figure 3BAs shown, the DFF device includes an input terminal din for receiving superconducting pulses, a clock terminal clk for receiving clock signals, and an output terminal dout for outputting superconducting pulses. The initial state of the DFF device is 0. If there is no superconducting pulse input, the device remains in the 0 state, and there will be no superconducting pulse output. When the DFF device receives a superconducting pulse input, it changes from the 0 state to the 1 state. In this state, when the clock signal arrives at the clock terminal clk, the output terminal dout will output a superconducting pulse, and the DFF device will return to the 0 state.

[0048] Figure 3C A schematic diagram of a prior art RDFF flip-flop is shown, which includes an input terminal din for receiving input data, a clock terminal clk for receiving clock signals, an output terminal dout for outputting data, and a reset terminal reset for receiving reset signals. The RDFF flip-flop is a D flip-flop with a reset terminal reset. Its operating mode is basically the same as that of a DFF, the difference being that when a pulse signal is input to the reset terminal reset, the RDFF flip-flop clears its internal state, and after a subsequent clock signal arrives, the output terminal dout does not output a pulse signal.

[0049] Figure 4A A schematic diagram of a prior art NDRO device is shown. Figure 4B The state transition diagram of a prior art NDRO device is shown. (Example) Figure 4A and Figure 4B As shown, the NDRO device includes an input terminal din for receiving superconducting pulses, a clock terminal clk for receiving clock signals, a reset terminal reset for receiving reset signals, and an output terminal dout for outputting superconducting pulses. The initial state is 0. If no superconducting pulse is input, the device remains in state 0. In this state, when the clock signal reaches the clock terminal clk, there will be no superconducting pulse output at the dout terminal. When a superconducting pulse is input, the NDRO device changes from state 0 to state 1, and there will be no superconducting pulse output at this time. In this state, when the clock signal reaches the clock terminal clk, there will be a superconducting pulse output at the dout terminal, but the device state remains unchanged (i.e., it remains in state 1). If another clock signal reaches the clock terminal clk at this time, there will be a superconducting pulse output at the dout terminal. When the reset signal reaches the reset terminal reset of the NDRO device, regardless of the current state, the device will be cleared and return to state 0.

[0050] Figure 5 A schematic diagram of a prior art SPL2 device is shown; the SPL2 device does not require a clock input. For example... Figure 5As shown, the SPL2 device includes an input terminal din for receiving input data and a first output terminal dout1 and a second output terminal dout2 for outputting data. When the SPL2 device receives a superconducting pulse input, it will directly output two identical superconducting pulses. Similarly, the SPL3 device may include three output terminals, and when a superconducting pulse input is received, it will directly output three identical superconducting pulses (not shown in the figure). For ease of explanation, the SPL device in this invention may include a tree structure composed of SPL2 and SPL3 devices, that is, the SPL device in this invention may include any number of output terminals.

[0051] Figure 6A A schematic diagram of a prior art TFFO device is shown. Figure 6B The state transition diagram of a prior art TFFO device is shown. Figure 6A and Figure 6B As shown, the TFFO device includes an input terminal din for receiving superconducting pulses and an output terminal dout for outputting superconducting pulses. Assuming the initial state of the TFFO device is 0, if no superconducting pulse is input, the TFFO device remains in state 0, and no superconducting pulse is output. When the first superconducting pulse is input, the TFFO device changes to state 1, and the output terminal dout will output a superconducting pulse. When the second superconducting pulse is input, the TFFO device changes to state 0, and no superconducting pulse is output. That is, when an odd number of superconducting pulses are input to the input terminal din of the TFFO device, the output terminal dout of the TFFO device will output a superconducting pulse.

[0052] Based on existing TFFE and TFFO devices, this invention also provides a clocked even-divider (TFFEC) and a clocked odd-divider (TFFOC). Figure 6C A schematic diagram of a TFFEC device according to an embodiment of the present invention is shown. The TFFEC device includes an input terminal din for receiving superconducting pulses, a clock terminal clk for receiving clock signals, and an output terminal dout for outputting superconducting pulses. Assuming the initial state of the TFFEC device is state 0, if no superconducting pulse is input at this time, the TFFEC device remains in state 0, and no superconducting pulse is output. When the first superconducting pulse is input, the TFFEC device changes to state 1, and no superconducting pulse is output. When the second superconducting pulse is input, the TFFEC device changes to state 2. In this state, when the clock signal reaches the clock terminal clk, the output terminal dout will output a superconducting pulse, and the TFFEC device will return to state 0. That is, when an even number of superconducting pulses are input to the input terminal din of the TFFEC device, and the clock signal reaches the clock terminal clk, the output terminal dout of the TFFEC device will output a superconducting pulse. Figure 6DA schematic diagram of a TFFEC device according to an embodiment of the present invention is shown. Figure 6D As shown, the TFFEC device can be composed of a TFFE device and a DFF device. The output terminal of the TFFE device is connected to the input terminal of the DFF device. The input terminal of the TFFE device is used as the input terminal din of the TFFEC device. The clock terminal of the DFF device is used as the clock terminal clk of the TFFEC device. The output terminal of the DFF device is used as the output terminal dout of the TFFEC device. The superconducting signals input to the input terminal din and the clock terminal clk of the TFFEC device are of the same frequency.

[0053] Figure 6E A schematic diagram of a TFOC device according to an embodiment of the present invention is shown. The TFOC device includes an input terminal din for receiving superconducting pulses, a clock terminal clk for receiving clock signals, and an output terminal dout for outputting superconducting pulses. Assuming the initial state of the TFOC device is state 0, if no superconducting pulse is input at this time, the TFOC device remains in state 0, and no superconducting pulse is output. When the first superconducting pulse is input, the TFOC device becomes state 1. In this state, when the clock signal reaches the clock terminal clk, the output terminal dout will output a superconducting pulse, and the TFOC device becomes state 2. When the second superconducting pulse is input, the TFOC device becomes state 0, and no superconducting pulse is output. That is, when an odd number of superconducting pulses are input to the input terminal din of the TFOC device, and the clock signal reaches the clock terminal clk, the output terminal dout of the TFOC device will output a superconducting pulse. Figure 6F A schematic diagram of the structure of a TFOC device according to an embodiment of the present invention is shown. Figure 6F As shown, the TFOC device can be composed of a TFFO device and a DFF device. The output terminal of the TFFO device is connected to the input terminal of the DFF device. The input terminal of the TFFO device is used as the input terminal din of the TFOC device. The clock terminal of the DFF device is used as the clock terminal clk of the TFOC device. The output terminal of the DFF device is used as the output terminal dout of the TFOC device. The superconducting signals input to the input terminal din and the clock terminal clk of the TFOC device are of the same frequency.

[0054] Figure 7 A schematic diagram of a superconducting pulse counter according to an embodiment of the present invention is shown. In this embodiment, two DFF devices are inserted among three TFFE devices. Figure 7As shown, counter 700 includes an input terminal din for receiving superconducting pulses, an output terminal dou for outputting superconducting pulses, and a clock terminal clk for receiving clock signals. Counter 700 includes three even-division multiplexers TFFE, namely TFFE 701, TFFE 702, and TFFE 703 from the input terminal din to the output terminal dou; two D flip-flops, namely DFF 704 and DFF 705 from the input terminal din to the output terminal dou; and an SPL 706 for receiving clock signals and outputting clock signals to the clock terminals clk of DFF 704 and DFF 705.

[0055] Specifically, the input terminal din of TFFE 701 is used as the input terminal din of counter 700, and the output terminal dou of DFF 705 is used as the output terminal dou of counter 700. Specifically, TFFE 701 includes an input terminal din for receiving a superconducting signal and an output terminal dou for outputting the superconducting signal. DFF 704 includes an input terminal din for receiving the output signal from TFFE 701, a clock terminal clk for receiving a clock signal, and an output terminal dou for outputting the superconducting signal. TFFE 702 includes an input terminal din for receiving the output signal from DFF 704 and an output terminal dou for outputting the superconducting signal. TFFE 703 includes an input terminal din for receiving the output signal from TFFE 702 and an output terminal dou for outputting the superconducting signal. DFF 705 includes an input terminal din for receiving the output signal from TFFE 703, a clock terminal clk for receiving a clock signal, and an output terminal dou for outputting the superconducting signal. SPL 706 includes an input terminal din for receiving a clock signal, a first output terminal out1 for outputting a clock signal to the clock terminal clk of DFF 704, and a second output terminal out2 for outputting a clock signal to the clock terminal clk of DFF 705.

[0056] The clock signal can have the same frequency as the input superconducting pulse of the counter 700, or it can be higher or lower than the input superconducting pulse, depending on the design requirements. Preferably, the clock signal is the same as the input superconducting pulse of the counter 700.

[0057] The following text will use the example of a clock signal that is the same as the input superconducting pulse of counter 700 for detailed explanation. Table 1 shows the input of counter 700 and the output of each device.

[0058] Table 1: Inputs and Outputs of Counter 700

[0059]

[0060]

[0061] In this counter 700, when the first superconducting pulse 1 arrives at TFFE 701, TFFE 701 has no signal output, that is, it outputs "0". TFFE 702-703 and DFF 704-705 also have no signal output, that is, they output "0". Therefore, the output terminal dou of this counter 700 is "0".

[0062] When the second superconducting pulse 2 arrives at TFFE 701, the output terminal of TFFE 701 generates an output, i.e., output "1". This signal is transmitted to the input terminal of DFF 704, causing DFF 704 to change from state 0 to state 1. Since the clock signal is the same as the input superconducting pulse of counter 700, the clock signal arrives at DFF 704 before the second superconducting pulse 2. Therefore, DFF 704 has no signal output, i.e., output "0". TFFE 702-703 and DFF 705 also have no signal output, i.e., output "0". Therefore, the output terminal dout of counter 700 is "0".

[0063] When the third superconducting pulse 3 arrives at TFFE 701, TFFE 701 has no signal output, i.e., outputs "0"; at the same time, the clock signal arrives at the clock terminal of DFF 704, and the output terminal of DFF 704 generates an output, i.e., outputs "1", and DFF 704 changes from state 1 to state 0. This output signal is transmitted to the input terminal of TFFE 702, and TFFE 702 has no signal output, i.e., outputs "0". TFFE 703 and DFF 705 also have no signal output, i.e., outputs "0". Therefore, the output terminal dou of the counter 700 is "0".

[0064] When the fourth superconducting pulse 4 arrives at TFFE 701, the output terminal of TFFE 701 generates an output, namely, output "1". This signal is transmitted to the input terminal of DFF 704, causing DFF 704 to change from state 0 to state 1. Since the clock signal is the same as the input superconducting pulse of counter 700, the clock signal arrives at DFF 704 before the fourth superconducting pulse 4. Therefore, DFF 704 has no signal output, namely, output "0". TFFE 702-703 and DFF 705 also have no signal output, namely, output "0". Therefore, the output terminal dout of counter 700 is "0".

[0065] When the fifth superconducting pulse 5 arrives at TFFE 701, TFFE 701 has no signal output, i.e., outputs "0"; at the same time, the clock signal arrives at the clock terminal of DFF 704, and the output terminal of DFF 704 generates an output, i.e., outputs "1", and DFF 704 changes from state 1 to state 0. This output signal is transmitted to the input terminal of TFFE 702, and TFFE 702 has a signal output, i.e., outputs "1". TFFE 703 and DFF 705 have no signal output, i.e., outputs "0". Therefore, the output terminal dou of the counter 700 is "0".

[0066] When the sixth superconducting pulse 6 arrives at TFFE 701, the output terminal of TFFE 701 generates an output, i.e., output "1". This signal is transmitted to the input terminal of DFF 704, causing DFF 704 to change from state 0 to state 1. Since the clock signal is the same as the input superconducting pulse of counter 700, the clock signal arrives at DFF 704 before the sixth superconducting pulse 6. Therefore, DFF 704 has no signal output, i.e., output "0". TFFE 702-703 and DFF 705 also have no signal output, i.e., output "0". Therefore, the output terminal dout of counter 700 is "0".

[0067] When the seventh superconducting pulse 7 arrives at TFFE 701, TFFE 701 has no signal output, i.e., outputs "0"; at the same time, the clock signal arrives at the clock terminal of DFF 704, and the output terminal of DFF 704 generates an output, i.e., outputs "1", and DFF 704 changes from state 1 to state 0. This output signal is transmitted to the input terminal of TFFE 702, and TFFE 702 has no signal output, i.e., outputs "0". TFFE 703 and DFF 705 also have no signal output, i.e., outputs "0". Therefore, the output terminal dou of the counter 700 is "0".

[0068] When the eighth superconducting pulse 8 arrives at TFFE 701, the output terminal of TFFE 701 generates an output, namely, output "1". This signal is transmitted to the input terminal of DFF 704, causing DFF 704 to change from state 0 to state 1. Since the clock signal is the same as the input superconducting pulse of counter 700, the clock signal arrives at DFF 704 before the eighth superconducting pulse 8. Therefore, DFF 704 has no signal output, namely, output "0". TFFE 702-703 and DFF 705 also have no signal output, namely, output "0". Therefore, the output terminal dout of counter 700 is "0".

[0069] When the ninth superconducting pulse 9 arrives at TFFE 701, TFFE 701 has no signal output, i.e., outputs "0". At the same time, the clock signal arrives at the clock terminal of DFF 704, and the output terminal of DFF 704 generates an output, i.e., outputs "1", and DFF 704 changes from state 1 to state 0. This output signal is transmitted to the input terminal of TFFE 702, and TFFE 702 has a signal output, i.e., outputs "1". TFFE 703 has a signal output, i.e., outputs "1", and this signal is transmitted to the input terminal of DFF 705, causing DFF 705 to change from state 0 to state 1. Since the clock signal is the same as the input superconducting pulse of counter 700, and the clock signal arrives at DFF 705 before the ninth superconducting pulse 9, DFF 705 has no signal output, i.e., outputs "0".

[0070] When the tenth superconducting pulse 10 arrives at TFFE 701, the output terminal of TFFE 701 generates an output, i.e., output "1". This signal is transmitted to the input terminal of DFF 704, causing DFF 704 to change from state 0 to state 1. Since the clock signal is the same as the input superconducting pulse of counter 700, the clock signal arrives at DFF 704 before the tenth superconducting pulse 10. Therefore, DFF 704 has no signal output, i.e., output "0". TFFE 702-703 also have no signal output, i.e., output "0". At the same time, the clock signal arrives at the clock terminal of DFF 705, and the output terminal of DFF 705 generates an output, i.e., output "1". Therefore, the output terminal dout of counter 700 is "1". In this process, the clock terminal clk of the inserted DFF 705 can directly generate an output after receiving the tenth superconducting pulse 10, saving the delay on TFFE701-TFF 703 and DFF 704 as well as the delay of the connection from TFFE 701 to DFF 705.

[0071] exist Figure 7 In one embodiment, the frequency-limiting factor is the longest delay segment in the counter, which determines the counter's operating frequency. For example... Figure 7 The longest latency segment is likely from DFF 704 to DFF 705, which includes one DFF delay, two TFFE delays, and the latency of the connection.

[0072] As can be seen from the above embodiments, after inserting DFF devices into the superconducting pulse counter, more pipeline stages are divided, which greatly reduces the counter delay, increases the upper limit of the counter's operating frequency, and effectively prevents the counter's operating frequency from decreasing due to the increase in counting capacity, enabling it to be applied in superconducting digital circuit systems with higher frequencies.

[0073] In the above embodiment, after inserting m (m is a positive integer) DFF devices, the counting capacity becomes N.cnt =2 n +m (n is the number of TFFE devices, which is an integer greater than or equal to 1). To ensure the original counting capacity (i.e., 2^n). n (The original text appears to be incomplete and contains several errors. A more accurate translation would require the full context.) i-1 Where i is the position number of the TFFE device from the input to the output of the counter, excluding intermediate DFF devices. Figure 7 For example, TFFE 701 is numbered 1, TFFE 702 is numbered 2, and so on. The replaced counting capacity becomes:

[0074] N cnt =2 n +m-∑ i∈S1 2 i-1 (1)

[0075] Where S1 is the set of position numbers of the replaced TFFEs. Theoretically, the replaced superconducting pulse counter can achieve arbitrary counting. Figure 7 The superconducting pulse counter in the image can be re-achieved by replacing the TFFE 702 (i.e., i=2) with a TFFO device, thus restoring the counting capacity N. cnt =2 n .

[0076] Although the above embodiments use the insertion of a DFF device as an example, the present invention is not limited to this. Other superconducting devices with clock ports can also be inserted, including but not limited to RDFF devices and NDRO devices. The output terminals of the RDFF and NDRO devices are connected to a reset terminal to satisfy the state transition of the superconducting device with a clock port. The superconducting device with a clock port may include an input terminal din for receiving superconducting pulses, a clock terminal clk for receiving clock signals, and an output terminal dout for outputting superconducting pulses. When the initial state is 0 and a superconducting pulse is input, the superconducting device with a clock port will change from state 0 to state 1. In this state, when the clock signal reaches its clock terminal clk, the output terminal dout will output a superconducting pulse, and the superconducting device with a clock port will return to state 0. When the initial state is 0 and there is no superconducting pulse input, the superconducting device with a clock port will not output a superconducting pulse.

[0077] The superconducting pulse counter in this invention uses... Figure 2The superconducting pulse counter shown inserts m superconducting devices with clock ports into the n TFFE devices to create finer pipelines, reducing circuit delay and increasing system frequency. The number of TFFE devices and clock-ported superconducting devices is unlimited, and the clock-ported superconducting devices can be inserted at any position.

[0078] In one embodiment, a TFFEC device can be used instead of a TFFE and a superconducting device with a clock port, and a TFFOC device can be used instead of a TFFEC device. Figure 8A A schematic diagram of a superconducting pulse counter according to another embodiment of the present invention is shown. The TFFEC device can be considered as a TFFE device + DFF device; therefore, in this embodiment, n = 3, m = 2, and the counting capacity is N. cnt =2 3 +2 = 10. Figure 8B It shows Figure 8A A schematic diagram showing the superconducting pulse counter after replacing the TFFE device. After replacing the second TFFE device with a TFFO device, the counting capacity becomes N. cnt =2 3 +2-2 2-1 =8.

[0079] In one embodiment, after one count, all superconducting devices are reset to facilitate continuous target counting. For example, all superconducting devices are devices with reset ports, such as RDFF devices, TFFE devices with reset terminals (RTFFE), and TFFO devices with reset terminals (RTFFO). The reset terminals of all devices with reset ports are connected to the output of a superconducting pulse counter. After one count, the counter outputs a superconducting signal, causing all devices with reset ports to be reset.

[0080] Figure 9A A schematic diagram of a prior art high-frequency clock generator is shown. High-frequency clock generators are typically used to generate high-frequency clocks of the desired frequency for system use. For example... Figure 9A As shown, the high-frequency clock generator 900 consists of a superconducting pulse counter 907 and an NDRO 906. The NDRO 906 includes an input terminal din for receiving a trigger signal trg, a clock terminal clk for receiving the trigger signal trg and data from the output terminal dou, an output terminal dou for outputting an external clock signal clk_out, and a reset terminal reset for receiving data from the output terminal dou of the counter 907. The counter 907 includes an input terminal din for receiving data from the output terminal dou of the NDRO 906 and an output terminal dou for outputting the counting result.

[0081] When a trigger signal trg is input, the high-frequency clock generator 900 will operate at a frequency of 1 / T. clk_out Output the external clock signal clk_out, and simultaneously, counter 907 starts counting, where T clk_out The delay in the clock loop from the output of the NDRO 906 to its clock input, as well as the delay of the NDRO 906 itself, can be adjusted according to the clock frequency requirements. From the time the NDRO 906 is triggered until it receives the 8th signal at its clock input, after a delay of t... rst =t ndro +3*t TFFE +t wire It was then reset, stopping the count, where t ndro The delay between the clock and output terminals of the NDRO 906 is 3*t. TFFE The total delay of the three TFFEs in the counter; t wire This represents the delay of all connections in the feedback loop where the counter resides. Therefore, the effect of the high-frequency clock generator is to generate a clock frequency of 1 / T. clk_out After continuously outputting 8 clock signals clk_out, it is reset and stops working.

[0082] Therefore, when t rst <T clk_out -t reset-clk For a high-frequency clock generator to function properly, t... reset-clk This is the setup time for the NDRO 906 reset pin. Otherwise, the number of output clock signals clk_out will be greater than the expected value (8). Therefore, the excessive delay of counter 907 will severely limit the operating frequency of the high-frequency clock generator.

[0083] Figure 9B A schematic diagram of a high-frequency clock generator according to an embodiment of the present invention is shown. Figure 9B High-frequency clock generator and Figure 9A The difference lies in the addition of two superconducting devices, DFF 904 and 905, with clock ports. The clock ports of DFF 904 and 905 are used to receive data from the output of NDRO, and the second TFFE is replaced with a TFFO device.

[0084] In this embodiment, two DFF devices are inserted into counter 907, sharing a clock signal with NDRO 906 to form a synchronous timing circuit. This transforms the frequency limiting factor into the segment with the largest delay between each adjacent NDRO and DFF or between DFFs. Therefore, the delay can be significantly reduced, increasing the frequency of the clock signal clk_out output to the external system. Since the two DFFs are inserted, the counting capacity increases by 2; therefore, replacing the second TFFE with a TFFO reduces the counting capacity by 2. 2-1=2, reimplementing the 8-counting mechanism.

[0085] The superconducting pulse counter in this invention, by inserting a superconducting device with a clock port, divides the counter into more pipeline stages, thereby increasing the upper limit of the counter's operating frequency and effectively preventing the counter's operating frequency from decreasing due to the increase in counting capacity. This allows it to be applied in superconducting digital circuit systems with higher frequencies. Based on the division of pipeline stages, replacing the TFFE at the corresponding positions with TFFO simplifies the implementation of full counting, rather than being limited to 2 stages. n The superconducting pulse counter in this invention has a significantly increased upper limit on its operating frequency, reaching tens of GHz, which helps existing superconducting RSFQ microprocessors overcome frequency bottlenecks.

[0086] Although the superconducting pulse counter was used as an example in the above embodiments, the present invention is not limited thereto. The method of increasing the upper limit of the operating frequency of a superconducting circuit by inserting a superconducting device with a clock port and dividing it into more pipeline stages can be applied to any other superconducting circuit, such as a high-delay circuit that does not include a superconducting device with a clock port.

[0087] The present invention also provides a method for increasing the operating frequency of a superconducting circuit, the method comprising: inserting a superconducting device with a clock port into a superconducting circuit that does not include a superconducting device with a clock port, in order to divide the circuit into more pipeline stages.

[0088] While the present invention has been described through preferred embodiments, it is not limited to the embodiments described herein, and various changes and modifications are made without departing from the scope of the invention.

Claims

1. A superconducting pulse counter, comprising: There are n TFFE devices, p TFFO devices, and m superconducting devices with clock ports, where n and m are positive integers, and p is an integer greater than or equal to 0; n+m+p devices are linearly connected in series, wherein the input terminal of the first device is the input terminal of the superconducting pulse counter, the output terminal of each of the n+m+p devices is connected to the input terminal of the next device, and the output terminal of the last device is the output terminal of the superconducting pulse counter; the clock terminals of the m superconducting devices with clock ports are connected to the clock terminal of the superconducting pulse counter; and The superconducting pulses input to the input terminal and the clock terminal of the superconducting pulse counter have the same frequency; Among them, the m superconducting devices with clock ports are not connected adjacent to each other; The superconducting device with a clock port is a superconducting device with the following characteristics: when the initial state of the superconducting device with a clock port is state 0, and there is a superconducting pulse input, the superconducting device with a clock port will change from state 0 to state 1. In this state, when the clock signal reaches its clock terminal, there will be a superconducting pulse output at the output terminal, and the superconducting device with a clock port will change to state 0.

2. The superconducting pulse counter according to claim 1, wherein, The counting capacity of the superconducting pulse counter is: N cnt =2 n+p +m-∑ i∈S1 2 i-1 Where i is the position number of all TFFE and TFFO devices from the input to the output of the superconducting pulse counter, and the m superconducting devices with clock ports are not included in the numbering; S1 is the set of position numbers of TFFO devices.

3. The superconducting pulse counter according to claim 1, wherein, The superconducting device with a clock port is a DFF device, an RDFF device with its output terminal connected to the reset terminal, or an NDRO device with its output terminal connected to the reset terminal.

4. The superconducting pulse counter according to claim 1, wherein, The superconducting pulse counter also includes an SPL device, which includes an input terminal for receiving a clock signal and m output terminals for outputting the clock signal to the clock terminals of the m superconducting devices with clock ports.

5. The superconducting pulse counter according to any one of claims 1-4, wherein, After one count, all superconducting devices are reset.

6. The superconducting pulse counter according to claim 5, wherein, Each of the n+m+p devices has a reset terminal, and the output terminal of the superconducting pulse counter is connected to the reset terminals of the n+m+p devices.

7. A method for increasing the operating frequency of a superconducting circuit, comprising: Insert m superconducting devices with clock ports into a superconducting circuit that includes n superconducting devices, where n and m are positive integers; n+m devices are connected in linear series, wherein the input terminal of the first device is the input terminal of the superconducting circuit, the output terminal of each of the n+m devices is connected to the input terminal of the next device, and the output terminal of the last device is the output terminal of the superconducting circuit; the clock terminals of the m superconducting devices with clock ports are connected to the clock terminal of the superconducting circuit. Among them, the n superconducting devices do not have clock ports, and the superconducting pulses input to the input terminal and clock terminal of the superconducting circuit have the same frequency; Among them, the m superconducting devices with clock ports are not connected adjacent to each other; The superconducting device with a clock port is a superconducting device with the following characteristics: when the initial state of the superconducting device with a clock port is state 0, and there is a superconducting pulse input, the superconducting device with a clock port will change from state 0 to state 1. In this state, when the clock signal reaches its clock terminal, there will be a superconducting pulse output at the output terminal, and the superconducting device with a clock port will change to state 0.

8. The method for increasing the operating frequency of a superconducting circuit according to claim 7, wherein, The n superconducting devices include TFFE devices and / or TFFO devices.

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