Error calibration circuit for high-speed digital-to-analog converters

Abstract

The application discloses an error calibration circuit of a high-speed digital-to-analog converter. The error calibration circuit comprises sequentially connected transmitting end circuit, serial-to-parallel conversion circuit, digital-to-analog converter (DAC), analog-to-digital converter (ADC), calibration circuit and reference clock generation circuit, the reference clock generation circuit outputs a reference clock to the analog-to-digital converter, the calibration circuit controls data types according to error calibration types, for different error calibration types, the calibration circuit calculates an error calibration word according to the output of the analog-to-digital converter and outputs the error calibration word to the digital-to-analog converter to perform corresponding error calibration, the calibration circuit obtains a reference clock calibration word according to the sampling result of the analog-to-digital converter on the rising edge of the output waveform of the digital-to-analog converter and outputs the reference clock calibration word to the reference clock generation circuit, and the error calibration circuit further comprises a sub-digital-to-analog converter sequential positioning process between the reference clock calibration and phase delay error calibration. The application realizes a high-precision digital-to-analog conversion circuit by combining the ADC and the DAC, utilizing reasonable reference clock frequency and multiple calibration methods.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an error calibration circuit for a high-speed digital-to-analog converter. Background Technology

[0002] Digital-to-analog converters (DACs) are widely used in electronic systems. Digital circuit systems process and generate discrete digital signals. To transmit information through a channel, these discrete digital signals need to be converted into continuous analog signals, processed by analog circuits, and then sent. A DAC takes a discrete digital signal as input and generates a summed voltage signal based on the value (0 or 1) and weight of each bit. High-speed DACs are essential components of high-speed serial interface chips and incoherent / coherent optical chips, and their sampling accuracy directly determines the overall performance of the chip. Currently, the demand for chip speeds is increasing; however, high-speed DACs suffer from various errors that severely degrade chip performance. Current research in academia and industry focuses on optimizing the DAC itself, using superior materials or optimized processes, but this also introduces difficulties in engineering implementation and increases costs. In general, there is currently no effective technology for calibrating the various errors of high-speed DACs. Summary of the Invention

[0003] The purpose of this application is to provide an error calibration circuit for a high-speed digital-to-analog converter. By combining an analog-to-digital converter (ADC) and a DAC, and utilizing a reasonable reference clock frequency and multiple calibration methods, a high-precision digital-to-analog conversion circuit can be achieved.

[0004] This application discloses an error calibration circuit for a high-speed digital-to-analog converter (DAC), comprising: a transmitter circuit, a serial-to-parallel conversion circuit, a DAC, an analog-to-digital converter (ADC), a calibration circuit, and a reference clock generation circuit connected in sequence. The reference clock generation circuit outputs a reference clock to the ADC. The DAC includes several sub-DACs, wherein the division ratio of the reference clock is equal to the number of sub-DACs. any integer The transmitting circuit uses a sequence length +0.5. The calibration circuit sends a control signal to the transmitting circuit according to the error calibration type and controls the transmitting circuit to send the data type to the serial-to-parallel conversion circuit. For different error calibration types, the calibration circuit calculates the error calibration word according to the output of the analog-to-digital converter and outputs it to the digital-to-analog converter for corresponding error calibration. The calibration circuit obtains the reference clock calibration word according to the sampling result of the rising edge of the output waveform of the digital-to-analog converter by the analog-to-digital converter and outputs it to the reference clock generation circuit. The calibration circuit performs the following calibration processes on the digital-to-analog converter: bias error calibration, proportional error calibration, reference clock calibration, phase delay error calibration, and unit delay error calibration. The reference clock calibration and the phase delay error calibration are further separated by a sub-digital-to-analog converter sequential positioning process.

[0005] In a preferred embodiment, the transmitting circuit uses a PRBS3, PRBS7, or PRBS9 sequence. The length of the PRBS3 sequence is 7. When the transmitting circuit uses a PRBS3 sequence, the number of sub-digital-to-analog converters is 4. The arbitrary integer value is 4. The frequency division ratio of the reference clock is 112.5T.

[0006] In a preferred embodiment, when the error calibration type is bias error, the data type transmitted by the transmitting circuit is: the input of the currently calibrated sub-digital-to-analog converter is data that cycles between positive maximum and negative maximum, while the inputs of other sub-digital-to-analog converters are all 0. The bias error calibration process of the calibration circuit includes: calculating the target value based on the positive maximum and negative maximum or register configuration; calculating the bias error; and updating the bias error control word.

[0007] In a preferred embodiment, when the error calibration type is proportional error, the data type transmitted by the transmitting circuit is: the input of the currently calibrated sub-digital-to-analog converter is data that cycles between positive maximum and negative maximum, while the inputs of other sub-digital-to-analog converters are all 0. The proportional error calibration process of the calibration circuit includes: calculating the target value based on the positive maximum and negative maximum or register configuration; calculating the proportional error; and updating the proportional error control word.

[0008] In a preferred embodiment, the process by which the calibration circuit determines whether the data output by the analog-to-digital converter is positive maximum or negative maximum includes: determining that there is one and only one value greater than a positive threshold / less than a negative threshold, and if this value is positive maximum / negative maximum; determining that there are two or more values ​​greater than a positive threshold / less than a negative threshold, and if this is satisfied, incrementing the positive threshold by 1 or decrementing the negative threshold by 1; determining that there is no value greater than a positive threshold / less than a negative threshold, and if this is satisfied, incrementing the counter by 1; if the counter reaches the counting threshold, decrementing the positive threshold by 1 or incrementing the negative threshold by 1.

[0009] In a preferred embodiment, when the error calibration type is reference clock calibration, the data type transmitted by the transmitting circuit is: the input of the currently calibrated sub-digital-to-analog converter is the largest positive data, and the inputs of other sub-digital-to-analog converters are all the largest negative data; the calibration circuit uses a binary search method or a scanning method to process the sampling results of the rising edge of the output waveform of the analog-to-digital converter to the digital-to-analog converter to obtain the reference clock calibration word.

[0010] In a preferred embodiment, when the calibration circuit performs the sequential positioning process of the sub-digital-to-analog converters, the data type sent by the transmitting circuit is: the input of the currently calibrated sub-digital-to-analog converter is the PRBS3 sequence, and the inputs of other sub-digital-to-analog converters are all the largest negative data. The sequential positioning process of the sub-digital-to-analog converters includes: determining that the first 1 has been found, and sequentially judging whether subsequent 1s have been found after 16, 8, 8, and 24 data. If so, locking which sub-digital-to-analog converter these 1s come from and which bit of PRBS3 data they are, and representing them as dac_idx and prbs_idx respectively.

[0011] In a preferred embodiment, when the calibration circuit performs phase delay error calibration, the data type transmitted by the transmitting circuit is a PRBS3 sequence. The phase delay error calibration process of the calibration circuit includes: determining the position of the rising edge based on dac_idx and prbs_idx obtained during the sequential positioning process of the sub-digital-to-analog converter, and applying the formula hr(n+1)=hr(n)+ g (Dr(n)-Vth) calculates the phase delay control word, where hr(n+1) and hr(n) are the phase delay control words at time n+1 and time n, respectively, g is the adjustment rate, Dr(n) is the sampled value of the rising edge at time n, and Vth is the offset value configured in the register.

[0012] In a preferred embodiment, when the calibration circuit performs unit delay error calibration, the data type transmitted by the transmitting circuit is a PRBS3 sequence. The unit delay error calibration process of the calibration circuit includes: determining the position of the falling edge based on dac_idx and prbs_idx obtained during the sequential positioning process of the sub-digital-to-analog converter, and applying the formula hf(n+1)=hf(n)+g (Df(n)-Vth) calculates the unit delay control word, where hf(n+1) and hf(n) are the unit delay control words at time n+1 and time n, respectively, g is the adjustment rate, Df(n) is the sampled value at the falling edge at time n, and Vth is the offset value configured in the register.

[0013] In a preferred embodiment, the circuit further includes: a positioning failure protection circuit, such as a phase delay control word or a unit delay control word that is all 1 or all 0, gradually incrementing dac_idx obtained during the sequential positioning process of the sub-digital-to-analog converters by 1, keeping prbs_idx unchanged, and calculating the phase delay control word or unit delay control word corresponding to each sub-digital-to-analog converter in turn. If each of the several sub-digital-to-analog converters obtained in each calculation has a saturated phase delay control word or unit delay control word, then the group of phase delay control words or unit delay control words with the fewest number of saturated phase delay control words or unit delay control words is selected.

[0014] The embodiments of this application have the following beneficial effects: 1. A DAC calibration circuit was designed using a combination of DAC and ADC, employing a suitable reference clock frequency, resulting in high calibration accuracy. Pre-processing calibration (performing calibration before the chip officially begins operation) has no impact on power consumption. Only a low-speed ADC and digital circuitry need to be added, resulting in minimal area impact.

[0015] 2. The sampling circuit samples the DAC output signal. The digital circuit performs DAC error calibration according to calibration methods, including calibration methods for bias error, proportional error, phase delay error and unit delay error, as well as calibration methods for reference clock and sub-DAC sequence positioning. It has comprehensive error type calibration and greatly improves DAC performance.

[0016] 3. A protection circuit for sub-DAC positioning failure was designed, which improved the stability and robustness of the system.

[0017] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which should be considered as described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the error calibration circuit of a high-speed digital-to-analog converter according to one embodiment of this application.

[0019] Figure 2 This refers to the DAC output waveform and ADC sampling points according to one embodiment of this application.

[0020] Figure 3 This refers to the sampling relationship between the ADC and DAC according to one embodiment of this application.

[0021] Figure 4This is a schematic diagram of a DAC calibration process according to one embodiment of this application.

[0022] Figure 5 This is a schematic diagram of a bias error calibration process according to one embodiment of this application.

[0023] Figure 6 This is a schematic diagram of a proportional error calibration process according to one embodiment of this application.

[0024] Figure 7 This is a flowchart illustrating a method for determining the positive maximum value according to one embodiment of this application.

[0025] Figure 8 This is a schematic flowchart of a reference clock calibration method according to one embodiment of this application.

[0026] Figure 9 This is a flowchart illustrating the sub-DAC sequential positioning method according to one embodiment of this application. Detailed Implementation

[0027] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0029] One embodiment of this application relates to an error calibration circuit for a high-speed digital-to-analog converter, the structure of which is as follows: Figure 1 As shown, the circuit includes: a sequentially coupled transmitting circuit 101, a serial-to-parallel conversion circuit 102, a digital-to-analog converter (DAC) 103, an analog-to-digital converter (ADC) 104, a DAC calibration circuit 105, and a reference clock generation circuit 106. It can be understood that the DAC 104 is responsible for converting discrete digital signals into continuous analog signals and sending them to subsequent analog circuits for processing, or directly transmitting them to the receiving circuit via the channel. To achieve error calibration of the high-speed DAC, this application designs a calibration circuit that combines a high-speed DAC and a high-speed analog-to-digital converter (ADC).

[0030] Specifically, the transmitting circuit 101 sends different data types according to the control signals of the calibration circuit. Different data types are suitable for calibrating different errors. The data transmitted by the transmitting circuit 101 is sent to the digital-to-analog converter (DAC) 103 after passing through the serial-to-parallel conversion circuit 102. After being converted into an analog signal, it is sent to the analog-to-digital converter (ADC) 104, then converted into a digital signal and sent to the calibration circuit 105 for calibration. The output data of the ADC 104 is converted into parallel data (parallelism 4, not limited to 4) by the register and sent to the calibration circuit 105. The reference clock generation circuit 106 generates a reference clock and sends it to the ADC 104 as the sampling trigger signal of the ADC 104. The ADC calibration circuit 105 analyzes the input data to obtain the reference clock calibration word and sends it to the reference clock generation circuit 106. It also obtains the calibration words for bias error, proportional error, phase delay error, and unit delay error and sends them to the DAC 103 for calibration.

[0031] In one embodiment, DAC 103 consists of multiple sub-digital-to-analog converters (sub-DACs) (e.g., it may consist of four sub-DACs: sub-DAC1, sub-DAC2, sub-DAC3, and sub-DAC4). The multiple sub-DACs sample sequentially, thereby achieving a high-speed DAC using low-speed sub-DACs.

[0032] Wherein, the division ratio of the reference clock is equal to the number of sub-digital-to-analog converters. any integer The transmitting circuit uses a sequence length + 0.5. In one embodiment, the transmitting circuit uses a PRBS3, PRBS7, or PRBS9 sequence.

[0033] By designing appropriate transmitter data types, the number of sub-DACs, and the reference clock frequency, it is possible to achieve, for example... Figure 2 and Figure 3 The sampling order is shown. In practice, the relationship between the reference clock frequency and the number of sub-DACs must satisfy: Reference clock division ratio = Number of sub-DACs. Length of data sequence in the transmitting circuit M + 0.5, where M is any integer. For example, the transmitter uses a PRBS3 sequence (a pseudo-random sequence with a period of 7, 0010111 or 0100111), the number of sub-DACs is 4, and the reference clock frequency is 112.5T. Then, every 112.5T interval, ADC 104 can sample the output of DAC 103. Assuming the input of DAC 103 is 1011 (each bit corresponds to the input of sub-DAC1, sub-DAC2, sub-DAC3, and sub-DAC4 respectively), then the analog voltage waveform of the output of DAC 103 is as follows. Figure 2 As shown in the curve, each sampling point of the ADC 104 shifts forward by 0.5 UI on the curve, as... Figure 2 The dots in the image are shown. Figure 3 The sampling relationship between the ADC and DAC is further given. The ADC can completely sample the PRBS3 sequence points as well as the points between sequences at 0.5 UI.

[0034] Figure 4 This is a schematic diagram of a DAC calibration process according to one embodiment of this application. The calibration circuit performs the following calibration processes on the digital-to-analog converter: bias error calibration, proportional error calibration, reference clock calibration, phase delay error calibration, and unit delay error calibration. Between the reference clock calibration and the phase delay error calibration, a sub-digital-to-analog converter sequential positioning process is also included. Figure 5 This is a schematic diagram of a bias error calibration process according to one embodiment of this application. In order to calibrate different errors, the transmitting end needs to send different types of data, as shown in Table 1. Table 1. Data types transmitted by the transmitting circuit in different calibration procedures In one embodiment, when the error calibration type is bias error, the data type transmitted by the transmitting circuit is: the input of the currently calibrated sub-DAC is data that cycles sequentially from positive maximum to negative maximum, while the inputs of other sub-DACs are all 0. The bias error calibration process of the calibration circuit includes: calculating the target value based on the positive maximum and negative maximum or register configuration; calculating the bias error; updating the bias error control word; determining whether all sub-DACs have been calibrated; if so, ending the calibration; otherwise, switching the sub-DACs and transmitting data. Figure 5 This is a schematic diagram of a bias error calibration process according to one embodiment of this application.

[0035] In one embodiment, when the error calibration type is proportional error, the data type transmitted by the transmitting circuit is: the input of the currently calibrated sub-digital-to-analog converter is data that cycles sequentially from positive maximum to negative maximum, while the inputs of other sub-digital-to-analog converters are all 0. The proportional error calibration process of the calibration circuit includes: calculating the target value based on the positive maximum and negative maximum or register configuration; calculating the proportional error; updating the proportional error control word; determining whether all sub-DACs have been calibrated; if so, ending the calibration; otherwise, switching the sub-DACs and transmitting data. Figure 6 This is a schematic diagram of a proportional error calibration process according to one embodiment of this application.

[0036] In fact, as mentioned above, determining the positive and negative maximum values ​​requires an algorithm to identify whether any of the four data points received in each frame contain a positive or negative maximum value. Figure 7 As shown. Figure 7A method for determining whether there is a positive maximum value in each frame using a positive threshold is given. Similarly, the negative threshold can be obtained using the same method, or it can be obtained by adding the register configuration value to the positive threshold.

[0037] Specifically, the process by which the calibration circuit determines whether the data output by the analog-to-digital converter is positive maximum or negative maximum includes: determining that there is one and only one value greater than the positive threshold / less than the negative threshold, and if this value is positive maximum / negative maximum; determining that there are two or more values ​​greater than the positive threshold / less than the negative threshold, and if this is satisfied, incrementing the positive threshold by 1 or decrementing the negative threshold by 1; determining that there is no value greater than the positive threshold / less than the negative threshold, and if this is satisfied, incrementing the counter by 1; if the counter reaches the counting threshold, decrementing the positive threshold by 1 or incrementing the negative threshold by 1.

[0038] The reference clock is used to trigger the ADC 104 to sample. If the reference clock deviates too far from the data center point, the ADC 104 will fail to sample an accurate signal, which is equivalent to a large delay error in the DAC 103. The reference clock calibration method finds the optimal control word by sampling the rising edge using a binary search or scanning method.

[0039] In one embodiment, when the error calibration type is reference clock calibration, the data type transmitted by the transmitting circuit is: the input of the currently calibrated sub-digital-to-analog converter is the largest positive data, and the inputs of all other sub-digital-to-analog converters are the largest negative data. The calibration circuit uses a binary search method or a scanning method to process the sampling results of the rising edge of the output waveform of the analog-to-digital converter to the digital-to-analog converter to obtain the reference clock calibration word.

[0040] Figure 8 This is a flowchart illustrating a reference clock calibration method according to one embodiment of this application. Specifically, the maximum value is first found, the rising edge value is obtained, multiple samples are taken to obtain the average value, and it is determined whether all sub-DACs have been calibrated. If not, the sub-DACs and transmitting data are switched. If so, the current state is determined, and the control word is found using a binary search method or a scanning method. It is then determined whether the stopping condition has been met. If so, the process ends; otherwise, the control word is switched.

[0041] In one embodiment, when the calibration circuit performs the sequential positioning process of the sub-digital-to-analog converters (ADCs), the data type transmitted by the transmitting circuit is: the input of the currently calibrated ADC is the PRBS3 sequence, and the inputs of other ADCs are all the largest negative data. The sequential positioning process of the ADCs includes: determining that the first 1 has been found, and then sequentially determining whether subsequent 1s have been found after 16, 8, 8, and 24 data points. If so, the ADC from which these 1s came and which bit of the PRBS3 sequence they belong to are identified and represented as dac_idx and prbs_idx, respectively.

[0042] As mentioned above, unless a special data type is used (where only one sub-DAC has a value), under a normal PRBS3 sequence, we cannot know which sub-DAC the first data received in the calibration circuit originates from; therefore, sub-DAC sequence positioning is required. Figure 9 As shown, the data type transmitted by the transmitting circuit at this time is PRBS3 data from one sub-DAC, while all other sub-DACs are negative maximum values. Therefore, we judge the received data: values ​​greater than the positive threshold are 1, and values ​​less than the positive threshold are 0. Thus, the data received by a sub-DAC with a value should be in the order of 0010111 or 0100111. Taking 0010111 as an example, the circuit starts counting when it receives the first 1. If the received data is the first 1 in 0010111, then when the 16th data is received (for example, from 4 sub-DACs), the data should be the second 1 in 0010111, and so on. The counting thresholds are 16, 8, 8, 24, 16, 8, 8, ... Figure 9 The design shown considers the sequence locked once the fifth 1 is found. At this point, the circuit can determine which of the four data points fed into the calibration circuit was sampled by which sub-DAC and which bit in the PRBS3 sequence it belongs to. The results are named dac_idx and prbs_idx, respectively, and will be used in phase delay error and unit delay error calibration.

[0043] In one embodiment, when the calibration circuit performs phase delay error calibration, the data type transmitted by the transmitting circuit is a PRBS3 sequence. The phase delay error calibration process of the calibration circuit includes: determining the position of the rising edge based on dac_idx and prbs_idx obtained during the sequential positioning process of the sub-digital-to-analog converter, and applying the formula hr(n+1)=hr(n)+ g (Dr(n)-Vth) calculates the phase delay control word, where hr(n+1) and hr(n) are the phase delay control words at time n+1 and time n, respectively, g is the adjustment rate, Dr(n) is the sampled value of the rising edge at time n, and Vth is the offset value configured in the register.

[0044] In one embodiment, when the calibration circuit performs unit delay error calibration, the data type transmitted by the transmitting circuit is a PRBS3 sequence. The unit delay error calibration process of the calibration circuit includes: determining the position of the falling edge based on dac_idx and prbs_idx obtained during the sequential positioning process of the sub-digital-to-analog converter, and applying the formula hf(n+1)=hf(n)+g (Df(n)-Vth) calculates the unit delay control word, where hf(n+1) and hf(n) are the unit delay control words at time n+1 and time n, respectively, g is the adjustment rate, Df(n) is the sampled value at the falling edge at time n, and Vth is the offset value configured in the register.

[0045] Each time the calibration circuit receives data (from the ADC), it uses two values ​​(dac_idx, prbs_idx) to label it. dac_idx indicates which sub-DAC sampled the data, and prbs_idx indicates which data point in the PRBS3 sequence it belongs to. When prbs_idx corresponds to the rising edge (between the second and third numbers, and between the fourth and fifth numbers) or falling edge (between the third and fourth numbers, and between the seventh and first numbers) of the known PRBS3 sequence (0010111), this number is the one we are looking for. The calibration circuit calculates the error based on this number and then updates the control word of the corresponding sub-DAC (each sub-DAC has an independent control word) based on dac_idx. The calibration errors for phase delay and unit delay are obtained by sampling the values ​​of the rising and falling edges, and the errors are sent to the update circuit to obtain the error control word using the LMS algorithm. Meanwhile, the positions of the rising and falling edges are directly obtained using the results from the sub-DAC sequential positioning method. Since the phase delay and unit delay affect the values ​​of both the rising and falling edges simultaneously, but in opposite directions, and the output control word actually controls both the rising and falling edges, the calculation methods for the two control words are shown in formulas (1) and (2): Rising edge: hr(n+1) = hr(n) + g (Dr(n)-Vth) (1) Falling edge: hf(n+1) = hf(n) + g (Df(n)-Vth) (2) Where hr(n+1) and hr(n) are the rising edge control words at time n+1 and time n, respectively, and hf(n+1) and hf(n) are the falling edge control words at time n+1 and time n, respectively. g is the adjustment rate, which can be adaptively adjusted according to the duration. Dr(n) and Df(n) are the sampled values ​​of the rising and falling edges at time n, respectively, and Vth is the offset value configured in the register.

[0046] In one embodiment, the calibration circuit further includes: a positioning failure protection circuit, such as a phase delay control word or a unit delay control word that is all 1 or all 0, gradually incrementing dac_idx obtained during the sequential positioning process of the sub-digital-to-analog converters by 1, keeping prbs_idx unchanged, and calculating the phase delay control word or unit delay control word corresponding to each sub-digital-to-analog converter in turn. If each of the several sub-digital-to-analog converters obtained in each calculation has a saturated phase delay control word or unit delay control word, then the group of phase delay control words or unit delay control words with the fewest number of saturated phase delay control words or unit delay control words is selected.

[0047] The order of sub-DAC positioning determines the results of phase delay calibration and unit delay calibration. Therefore, a protection circuit needs to be designed to ensure that subsequent processes can still be completed correctly even if sub-DAC positioning fails. When skew saturation is detected, the dac_idx obtained by the sub-DAC positioning method is incremented by 1, while prbs_idx (i.e., the order of PRBS) remains unchanged. The phase delay error and unit delay error calibration are then performed again. This process is repeated a maximum of 4 times (number of sub-DACs). If saturation occurs in all 4 iterations, the result with the fewest saturation values ​​is selected as the final output.

[0048] It should be noted that in this patent application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0049] The term “coupled to” and its derivatives may be used in this document. “Coupled” can mean two or more elements in direct physical or electrical contact. However, “coupled” can also mean two or more elements in indirect contact with each other, but still cooperating or interacting with each other, and can mean one or more other elements coupled or connected between elements referred to as being coupled to each other.

[0050] This specification includes combinations of various embodiments described herein. Individual references to embodiments (e.g., “one embodiment”, “some embodiments”, or “preferred embodiments”) do not necessarily refer to the same embodiment; however, these embodiments are not mutually exclusive unless indicated to be mutually exclusive or are readily apparent to those skilled in the art. It should be noted that the word “or” is used in a non-exclusive sense throughout this specification unless the context explicitly indicates or requires it.

[0051] All references to this specification are considered to be incorporated integrally into the disclosure of this application so that they can serve as the basis for modifications if necessary. Furthermore, it should be understood that the above descriptions are merely preferred embodiments of this specification and are not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of one or more embodiments of this specification.

Claims

1. An error calibration circuit for a high-speed digital-to-analog converter, characterized in that, include: The circuit consists of a transmitter circuit, a serial-to-parallel converter, a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), a calibration circuit, and a reference clock generator circuit, connected in sequence. The reference clock generator circuit outputs a reference clock to the ADC. The ADC includes several sub-ADCs, wherein the frequency division ratio of the reference clock is equal to the number of sub-ADCs. any integer The transmitting circuit uses a sequence length +0.

5. The calibration circuit sends a control signal to the transmitting circuit according to the error calibration type and controls the transmitting circuit to send the data type to the serial-to-parallel conversion circuit. For different error calibration types, the calibration circuit calculates the error calibration word according to the output of the analog-to-digital converter and outputs it to the digital-to-analog converter for corresponding error calibration. The calibration circuit obtains the reference clock calibration word according to the sampling result of the rising edge of the output waveform of the digital-to-analog converter by the analog-to-digital converter and outputs it to the reference clock generation circuit. The calibration circuit performs the following calibration processes on the digital-to-analog converter: bias error calibration, proportional error calibration, reference clock calibration, phase delay error calibration, and unit delay error calibration. The reference clock calibration and the phase delay error calibration are further separated by a sub-digital-to-analog converter sequential positioning process.

2. The circuit as described in claim 1, characterized in that, The transmitting circuit uses a PRBS3, PRBS7, or PRBS9 sequence. The length of the PRBS3 sequence is 7. When the transmitting circuit uses the PRBS3 sequence, the number of sub-digital-to-analog converters is 4. The arbitrary integer value is 4. The frequency division ratio of the reference clock is 112.5T.

3. The circuit as described in claim 1, characterized in that, When the error calibration type is bias error, the data type sent by the transmitting circuit is: the input of the currently calibrated sub-digital-to-analog converter is data that cycles between positive maximum and negative maximum, and the input of other sub-digital-to-analog converters is all 0. The bias error calibration process of the calibration circuit includes: calculating the target value based on the positive maximum and negative maximum or register configuration; calculating the bias error; and updating the bias error control word.

4. The circuit as described in claim 1, characterized in that, When the error calibration type is proportional error, the data type sent by the transmitting circuit is: the input of the currently calibrated sub-digital-to-analog converter is data that cycles between positive maximum and negative maximum, and the input of other sub-digital-to-analog converters is all 0. The proportional error calibration process of the calibration circuit includes: calculating the target value based on the positive maximum and negative maximum or register configuration; calculating the proportional error; and updating the proportional error control word.

5. The circuit as described in claim 3 or 4, characterized in that: The process by which the calibration circuit determines that the data output by the analog-to-digital converter is the largest positive value includes: Determine if there is one and only one value greater than the positive threshold, and if so, the value is positive and maximum. If not satisfied: Determine if there are two or more values ​​greater than the positive threshold. If satisfied, increment the positive threshold by 1. If not satisfied, determine if there are no values ​​greater than the positive threshold. If satisfied, increment the counter by 1. If the counter reaches the counting threshold, decrement the positive threshold by 1. The process by which the calibration circuit determines that the data output by the analog-to-digital converter is the most negative includes: Determine if there is one and only one value less than the negative threshold, and if so, the value is the maximum negative value. If not satisfied: Determine if there are two or more values ​​less than the negative threshold. If satisfied, decrement the negative threshold by 1. If not satisfied, determine if there are no values ​​less than the negative threshold. If satisfied, increment the counter by 1. If the counter reaches the counting threshold, increment the negative threshold by 1.

6. The circuit as described in claim 1, characterized in that, When the error calibration type is reference clock calibration, the data type sent by the transmitting circuit is: the input of the currently calibrated sub-digital-to-analog converter is the largest positive data, and the inputs of other sub-digital-to-analog converters are all the largest negative data; the calibration circuit uses a binary search method or a scanning method to process the sampling results of the rising edge of the output waveform of the analog-to-digital converter to the digital-to-analog converter to obtain the reference clock calibration word.

7. The circuit as described in claim 1, characterized in that, When the calibration circuit performs the sequential positioning process of the sub-digital-to-analog converters, the data type sent by the transmitting circuit is: the input of the currently calibrated sub-digital-to-analog converter is the PRBS3 sequence, and the inputs of other sub-digital-to-analog converters are all the largest negative data. The sequential positioning process of the sub-digital-to-analog converters includes: determining that the first 1 is found, and sequentially judging whether subsequent 1s are found after 16, 8, 8, and 24 data. If so, locking which sub-digital-to-analog converter these 1s come from and which bit of PRBS3 data they are, and representing them as dac_idx and prbs_idx respectively.

8. The circuit as described in claim 7, characterized in that, When the calibration circuit performs phase delay error calibration, the data type transmitted by the transmitting circuit is a PRBS3 sequence. The phase delay error calibration process of the calibration circuit includes: determining the position of the rising edge based on dac_idx and prbs_idx obtained during the sequential positioning process of the sub-digital-to-analog converter, and applying the formula hr(n+1)=hr(n)+ g (Dr(n)-Vth) calculates the phase delay control word, where hr(n+1) and hr(n) are the phase delay control words at time n+1 and time n, respectively, g is the adjustment rate, Dr(n) is the sampled value of the rising edge at time n, and Vth is the offset value configured in the register.

9. The circuit as described in claim 7, characterized in that, When the calibration circuit performs unit delay error calibration, the data type transmitted by the transmitting circuit is a PRBS3 sequence. The unit delay error calibration process of the calibration circuit includes: determining the position of the falling edge based on dac_idx and prbs_idx obtained during the sequential positioning process of the sub-digital-to-analog converter, and applying the formula hf(n+1)=hf(n)+g (Df(n)-Vth) calculates the unit delay control word, where hf(n+1) and hf(n) are the unit delay control words at time n+1 and time n, respectively, g is the adjustment rate, Df(n) is the sampled value at the falling edge at time n, and Vth is the offset value configured in the register.

10. The circuit as described in claim 8 or 9, characterized in that, Also includes: The positioning failure protection circuit, such as when the phase delay control word or unit delay control word is all 1 or all 0, gradually increments dac_idx obtained during the sequential positioning process of the sub-digital-to-analog converters by 1, while keeping prbs_idx unchanged, and calculates the phase delay control word or unit delay control word corresponding to each sub-digital-to-analog converter in turn. If each of the sub-digital-to-analog converters obtained in each calculation has a saturated phase delay control word or unit delay control word, then selects the group of phase delay control words or unit delay control words with the fewest number of saturated phase delay control words or unit delay control words.

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