A method and apparatus for determining a transmission time stamp

Abstract

The application discloses a method and device for determining a sending timestamp, which adjusts all serial-parallel conversion channel buffers (lane FIFO) in an optical channel transmission unit to reduce time delay deviation caused by inconsistent pipeline values of different lane FIFO, and sets a virtual frame header (VFP) on a predetermined logical channel of the optical channel transmission unit to indicate a frame header (FP) timing position, generates a sending timestamp for determining path time delay based on a time stamp of VFP reaching a serial-parallel conversion interface, fixes the sending timestamp to a single logical lane, solves the problem of path time delay jitter caused by sending timestamp jitter due to non-fixed logical lane number of the sending timestamp, effectively suppresses the sending timestamp jitter and the path time delay jitter, and the method is not limited by the number of channels and is suitable for various scenes where the channel of the sending timestamp stamping point is not fixed.

Description

Technical Field

[0001] This application relates to the field of time synchronization technology for optical communication networks, and in particular to a method and apparatus for determining a transmission timestamp. Background Technology

[0002] like Figure 1 As shown, the Optical Channel Transmission Unit (OTU4) has 20 logical channels (logical lanes) and multiple physical channels (physical lanes) connected to the parallel interface of the SerDes serial deserializer (hereinafter referred to as the serial deserialization parallel interface). Lanefifo refers to the SerDes channel buffer, i.e., the serial deserialization channel buffer. The Lanefifo input is the system clock domain, and the output is the SerDes clock domain. The Lanefifo converts data from the system clock domain to the SerDes clock domain. The Frame Header Indicator (FP) appears cyclically on the 20 logical lanes in a round-robin scheduling manner. In OTU4, every 256 frames form a multiframe. The Multiframe Indicator (MFP) also appears on different logical lanes, and the OTU4's transmission timestamp is placed in the first bit of the MFP.

[0003] In related technologies, when OTU4 is working, the timestamp position (MFP) in the transmission direction is carried to the area near the serial-to-deserial parallel interface. When analyzing path delay, from a single-channel perspective, when the timestamp point is in the SerDes clock domain, it has already passed through the clock-domain buffered lane FIFO. Therefore, the lane FIFO waterline level and the processing delay of the preceding circuit have no impact on path delay. However, in scenarios where the logical lane number of the timestamp point on the MFP is not fixed, the delay deviation between multiple logical lanes will cause timestamp jitter, thus affecting path delay. Assuming multiple logical lanes are perfectly aligned during transmission, in actual circuits, multiple physical lanes correspond to different SerDes, the SerDes phase cannot be completely consistent, and there is cross-clock domain processing at the SerDes. Therefore, there is a certain delay deviation between multiple physical lanes. The protocol defines the logical lane with the longest received delay, i.e., the latest logical lane, as the reference lane. In the receiving direction, the path delay is calculated by subtracting the MFP transmission timestamp carried in the PTP message from the receive timestamp at the MFP position on the latest logical lane. In the transmitting direction, the MFP appears in different logical lanes, resulting in the logical lane corresponding to the transmission timestamp being variable. Therefore, the delay deviation between multiple logical lanes in the transmitting direction will exacerbate path delay jitter.

[0004] With the development of 5G and the continuous evolution of network technology, the clock synchronization accuracy requirement has reached the nanosecond level, which also puts forward higher requirements for the jitter of the transmitted timestamp. Therefore, how to reduce the jitter of the transmitted timestamp and thus reduce the path delay jitter is a technical problem to be solved. Summary of the Invention

[0005] The main objective of this application is to provide a method and apparatus for determining the suppression of transmission timestamp jitter, aiming to solve the technical problem of path delay jitter caused by transmission timestamp jitter due to transmission timestamps appearing on different logical lanes in optical channel transmission units.

[0006] Firstly, this application provides a method for determining a transmission timestamp, the method comprising the following steps: Align and adjust all serial-to-deserial channel buffers (lane FIFO) in the optical channel transmission unit; A virtual frame header (VFP) is set on a predetermined logical channel of the optical channel transmission unit to indicate the timing position of the frame header (FP). A transmission timestamp for determining path delay is generated based on the timestamp of arrival at the serial-to-deserial parallel interface using VFP.

[0007] In some embodiments, the alignment adjustment of all serial-to-deserial channel buffer lane FIFOs in the optical channel transmission unit includes: The system clock of the optical channel transmission unit generates timing pulses; Lock the waterline value of each lane FIFO at the timed pulse; Determine whether the difference between the maximum and minimum lane FIFO waterline values ​​is greater than a preset first threshold value; If so, all lane FIFOs are reset simultaneously to align and adjust them; otherwise, no lane FIFOs are reset.

[0008] In some embodiments, the simultaneous reset of all lane FIFOs to align and adjust all lane FIFOs includes: Clear all lane FIFOs and set the read function read preparation signal of all lane FIFOs to low level; When the real-time waterline value of each lane FIFO reaches the preset second threshold value, the read function preparation signal of the corresponding lane FIFO is set to a high level to respond to the corresponding read request.

[0009] In some embodiments, before determining whether the difference between the largest and smallest lane FIFO waterline value is greater than a preset first threshold value, the method further includes: The waterline values ​​of each lane FIFO locked at the timed pulse are sorted using the bubble sort method. The period of the timing pulse is greater than or equal to the number of beats required to sort the waterline values ​​of each lane FIFO.

[0010] In some embodiments, a virtual frame header (VFP) for indicating the timing position of the frame header (FP) is set on a predetermined logical channel of the optical channel transmission unit, including: Select one logical channel of the optical channel transmission unit as the predetermined logical channel; When an FP appears on any logical channel of the optical channel transmission unit, the VFP is generated at the same time position as the FP on the predetermined logical channel; Wherein, VFP is a sideband signal.

[0011] In some embodiments, the generation of a transmission timestamp for determining path delay based on the timestamp of arrival at the VFP serial-to-deserial parallel interface includes: Based on the timestamp of the VFP arriving at the serial-to-deserial parallel interface and the offset of the VFP in a single data cycle after data bit width conversion, a transmission timestamp for determining path delay is generated.

[0012] In some embodiments, generating a transmission timestamp for determining path delay based on the timestamp of the VFP arriving at the serial-to-deserial parallel interface and the offset of the VFP in a data clock cycle after data bit width conversion includes: The transmission time compensation value is determined based on the offset of the VFP in one frame of data after data bit width conversion and the transmission rate of the optical channel transmission unit. The timestamp of the VFP arriving at the serial-to-deserial parallel interface is compensated according to the transmission time compensation value; The compensated VFP timestamp is used as the MFP transmission timestamp for determining path delay and is loaded into the PTP message.

[0013] In some embodiments, before generating a transmission timestamp for determining path delay based on the timestamp of the VFP arriving at the serial-to-deserial parallel interface and the offset of the VFP in a data clock after data bit width conversion, the method further includes: When any lane FIFO detects a multiframe indicator (MFP), after a preset delay, it acquires the offset of the VFP in one data cycle after data bit width conversion and the timestamp of the VFP arriving at the serial-to-deserial parallel interface; The preset time is greater than the time required to transmit the amount of data corresponding to the first threshold value.

[0014] In some embodiments, the method further includes: Set the timestamp of the next VFP arriving at the serial deserialization parallel interface to overwrite the timestamp of the previous VFP arriving at the serial deserialization parallel interface.

[0015] Secondly, this application also provides a device for determining a transmission timestamp, the device comprising: The alignment module is used to align and adjust all serial-to-deserial channel buffer lane FIFOs in the optical channel transmission unit. The setting module is used to set a virtual frame header (VFP) on a predetermined logical channel of the optical channel transmission unit to indicate the timing position of the frame header (FP). The generation module is used to generate a transmission timestamp to determine the path delay based on the timestamp of the VFP arriving at the serial-to-deserial parallel interface.

[0016] In some embodiments, the alignment module is further configured to: The system clock of the optical channel transmission unit generates timing pulses; Lock the waterline value of each lane FIFO at the timed pulse; Determine whether the difference between the maximum and minimum lane FIFO waterline values ​​is greater than a preset first threshold value; If so, all lane FIFOs are reset simultaneously to align and adjust them; otherwise, no lane FIFOs are reset.

[0017] In some embodiments, the alignment module is further configured to: Clear all lane FIFOs and set the read function read preparation signal of all lane FIFOs to low level; When the real-time waterline value of each lane FIFO reaches the preset second threshold value, the read function preparation signal of the corresponding lane FIFO is set to a high level to respond to the corresponding read request.

[0018] In some embodiments, the alignment module is further configured to: The waterline values ​​of each lane FIFO locked at the timed pulse are sorted using the bubble sort method. The period of the timing pulse is greater than or equal to the number of beats required to sort the waterline values ​​of each lane FIFO.

[0019] In some embodiments, the setting module is further configured to: Select one logical channel of the optical channel transmission unit as the predetermined logical channel; When an FP appears on any logical channel of the optical channel transmission unit, the VFP is generated at the same time position as the FP on the predetermined logical channel; Wherein, VFP is a sideband signal.

[0020] In some embodiments, the generation module is further configured to: Based on the timestamp of the VFP arriving at the serial-to-deserial parallel interface and the offset of the VFP in a single data cycle after data bit width conversion, a transmission timestamp for determining path delay is generated.

[0021] In some embodiments, the generation module is further configured to: The transmission time compensation value is determined based on the offset of the VFP in one frame of data after data bit width conversion and the transmission rate of the optical channel transmission unit. The timestamp of the VFP arriving at the serial-to-deserial parallel interface is compensated according to the transmission time compensation value; The compensated VFP timestamp is used as the MFP transmission timestamp for determining path delay and is loaded into the PTP message.

[0022] In some embodiments, the generation module is further configured to: When any lane FIFO detects a multiframe indicator (MFP), after a preset delay, it acquires the offset of the VFP in one data cycle after data bit width conversion and the timestamp of the VFP arriving at the serial-to-deserial parallel interface; The preset time is greater than the time required to transmit the amount of data corresponding to the first threshold value.

[0023] In some embodiments, the device is also used for: Set the timestamp of the next VFP arriving at the serial deserialization parallel interface to overwrite the timestamp of the previous VFP arriving at the serial deserialization parallel interface.

[0024] This application provides a method and apparatus for determining a transmission timestamp. By aligning and adjusting the FIFOs of all serial deserialization channel buffers in an optical channel transmission unit, delay deviations caused by inconsistent watermark values ​​in different lane FIFOs are reduced. A virtual frame header (VFP) is set on a predetermined logical channel of the optical channel transmission unit to indicate the timing position of the frame header (FP). A transmission timestamp for determining path delay is generated based on the timestamp of the VFP arriving at the serial deserialization parallel interface. This fixes the transmission timestamp to a single logical lane, solving the problem of path delay jitter caused by transmission timestamp jitter due to the non-fixed logical lane number of the transmission timestamp. It effectively suppresses transmission timestamp jitter and path delay jitter. Furthermore, this method is not limited by the number of channels and is applicable to scenarios where the channel where the transmission timestamp is located is not fixed. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the OTU4 unit. Figure 2 A flowchart illustrating a method for determining a transmission timestamp provided in an embodiment of this application; Figure 3 This is a logical diagram of the lane FIFO waterline consistency comparison and alignment method; Figure 4 A schematic diagram illustrating the specific process for determining the sending timestamp; Figure 5 This is a schematic diagram showing the timing relationship between the MFP and the corresponding VFP.

[0027] Figure 6 A schematic block diagram of a device for determining a transmission timestamp provided in an embodiment of this application; The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0030] This application provides a method and apparatus for determining a transmission timestamp, which can be applied to computer devices.

[0031] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0032] It is worth noting that the method for determining the transmission timestamp in this application can be applied to scenarios where the logical lane where the transmission timestamp stamping point of the MFP is not fixed, such as in optical channel transmission units like OTU4. ​​This application will illustrate the implementation of this method in OTU4 through its embodiments.

[0033] It's important to understand that on the OTU4 transmitting side, multiple logical lanes are distributed and become either OTL4.4 or OTL4.10. OTL4.4 has 4 physical lanes, and OTL4.10 has 10 physical lanes. This embodiment uses OTL4.4 as an example. Figure 1 As shown, there are multiple parallel FIFO lanes at the serial-to-deserial parallel interface. The write side of the FIFO is the system clock domain clk_sys, and the four logical lanes for writing are aligned. The read side is the SerDes clock domain. The four physical lanes on the read side are from the same source but have instantaneous phase deviations, which causes the waterlines of the four lane FIFOs to be not completely consistent. The delay of the OTU4 multiframe indicator MFP sending from different lane FIFOs is deviated, which causes jitter in the transmission timestamp of the multiframe indicator MFP, and thus jitter in the path delay.

[0034] Please refer to Figure 2 , Figure 2 This is a flowchart illustrating a method for determining a sending timestamp, provided as an embodiment of this application.

[0035] like Figure 2 As shown, the method includes steps S1 to S3.

[0036] Step S1: Align and adjust all serial-to-deserial channel buffer lanes and FIFOs in the optical channel transmission unit.

[0037] Specifically, the step of aligning and adjusting all serial-to-deserial channel buffer lane FIFOs in the optical channel transmission unit includes: generating a timing pulse based on the system clock of the optical channel transmission unit; locking the waterline value of each lane FIFO at the timing pulse; determining whether the waterline difference between the largest and smallest lane FIFO waterline values ​​is greater than a preset first threshold value; if so, resetting all lane FIFOs simultaneously to align and adjust all lane FIFOs; otherwise, not resetting any lane FIFOs.

[0038] Exemplary, such as Figure 3 As shown, the system clock clk_sys of OTU4 generates a timing pulse chk_point. At the same timing pulse chk_point, the waterline values ​​of all lane FIFOs are locked. In this embodiment, OTU4.4 has four lane FIFOs, so the waterline values ​​of all four lane FIFOs are locked. Then, the waterline values ​​of the four lane FIFOs are sorted, and the largest lane FIFO waterline value Wmax and the smallest lane FIFO waterline value Wmin are found. The consistency of all lane FIFOs is determined by whether the difference between the largest lane FIFO waterline value Wmax and the smallest lane FIFO waterline value Wmin is greater than a preset first threshold value Wt. If the waterline difference is greater than the preset first threshold value Wt, it indicates that the consistency of each lane FIFO is poor, which will lead to a large deviation in transmission delay, and alignment processing is required. If the waterline difference is less than or equal to the preset first threshold value Wt, it indicates that each lane FIFO has good consistency, and no processing is required.

[0039] It's worth noting that the write enable alignment of the lane FIFO is based on the read enable derived from the SerDes clock. The configuration of the first threshold value Wt needs to consider the clock synchronization status of the SerDes clocks among the multiple physical lanes on the read side. If it's a local clock, the first threshold value Wt is configured to a smaller value; if it's a clock recovered by each lane through a phase-locked loop, the first threshold value Wt is configured to a larger value. Furthermore, the first threshold can be configured to a range based on the fluctuation range of the lane FIFO waterline deviation, ensuring that consistency protection is not frequently triggered during normal operation of the lane FIFO.

[0040] Furthermore, resetting all lane FIFOs simultaneously to align and adjust them includes the following steps: clearing all lane FIFOs and setting the read preparation signal of all lane FIFOs to low level. At this time, the lane FIFOs do not send data but can write data. Setting the same second threshold value Ws for each lane FIFO. When the real-time waterline value Wr of each lane FIFO reaches the preset second threshold value Ws, setting the read preparation signal of the corresponding lane FIFO to high level to respond to the corresponding read request. In this way, all lane FIFOs on the same OTU4 port have the same starting waterline. After all lane FIFOs are reset simultaneously, they are ready simultaneously and start reading simultaneously, effectively reducing the time delay deviation caused by inconsistent waterline values ​​of different lane FIFOs. After consistency protection, the deviation of the waterline values ​​of each lane FIFO is small, approximately Ws.

[0041] Preferably, in this embodiment, the waterline values ​​of each lane FIFO locked at the same timing pulse are sorted using bubble sort to determine the order of the waterline values ​​of each lane FIFO. It can be understood that the waterline value of a lane FIFO refers to the amount of data currently stored in the lane FIFO; for example, if a lane FIFO stores 10 clock cycles of data, then the waterline value is 10. Furthermore, in this embodiment, the period of the timing pulse is configured according to the speed of lane FIFO consistency detection. It is necessary to ensure that the period of the timing pulse is greater than or equal to the number of clock cycles required for waterline sorting of multiple lane FIFOs. Therefore, if the bubble sort method is used, the period of the timing pulse must be at least the total number of entries in the physical lane equal to the number of clk_sys clock cycles.

[0042] It's worth noting that in the actual circuit, all lane FIFOs share the same write-side clock, which is the system clock. However, the read-side clocks belong to their respective SerDes lane clock domains, resulting in a certain phase deviation. Therefore, even after lane FIFO consistency checks and corrections, different lane FIFO lines will still exhibit some deviation, requiring further processing to reduce this deviation.

[0043] Step S2: Set a virtual frame header (VFP) on the predetermined logical channel of the optical channel transmission unit to indicate the timing position of the frame header (FP).

[0044] Specifically, setting a virtual frame header (VFP) on a predetermined logical channel of the optical channel transmission unit to indicate the timing position of the frame header (FP) includes: selecting one logical channel of the optical channel transmission unit as the predetermined logical channel; when an FP appears on any logical channel of the optical channel transmission unit, generating the VFP at the same timing position as the FP on the predetermined logical channel; wherein the VFP is a sideband signal.

[0045] Exemplary, such as Figure 4 As shown, cfg_en[19:0] is configured with 20 bits to correspond to logical lanes #0~19 respectively. If cfg_en[i] is set to 1, then lane #i generates a virtual frame header VFP. Only one logical lane can be selected from the 20 logical lanes as the predetermined logical lane. The 20-bit configuration is for the flexible selection of any lane as the reference lane. The selected lane #i is set with a 1-bit sideband signal, i.e., the virtual frame header VFP. When multiple lanes are distributed for each OTU4 frame header, regardless of whether the real FP falls on the predetermined logical lane during the rotation of the OTU4 frame header, a virtual frame header pulse VFP is generated at the same position as the FP timing position on the predetermined logical lane. VFP corresponds to the first bit position of FP. Therefore, it can be understood that when generating MFP, there must be a corresponding VFP generated on the predetermined logical lane.

[0046] Step S3: Generate a transmission timestamp to determine the path delay based on the timestamp of VFP arriving at the serial-to-deserial parallel interface.

[0047] Specifically, generating a transmission timestamp for determining path delay based on the timestamp of VFP arriving at the serial-to-deserial parallel interface includes: generating a transmission timestamp for determining path delay based on the timestamp of VFP arriving at the serial-to-deserial parallel interface and the offset of VFP in one data cycle after data bit width conversion.

[0048] Furthermore, a transmission timestamp for determining path delay is generated based on the timestamp of the VFP arriving at the serial-to-deserial parallel interface and the offset of the VFP in a single data frame after data bit width conversion. This includes: determining a transmission time compensation value based on the offset of the VFP in a single data frame after data bit width conversion and the transmission rate of the optical channel transmission unit; compensating the timestamp of the VFP arriving at the serial-to-deserial parallel interface based on the transmission time compensation value; and using the compensated VFP timestamp as the transmission timestamp of the multiframe indicator MFP for determining path delay, and loading it into the PTP message.

[0049] It's worth noting that when the 20 logic lanes of the OTU4 are bit-interleaved to OTL4.4 or OTL4.10, the VFP is input into 4 or 10 logic lanes via an OR operation. The VFP, as a sideband signal, undergoes clock domain buffering and bit-width conversion along with the data stream, ultimately reaching the SerDes clock domain at the serial-to-deserial parallel interface. During data bit-width conversion, the offset indicates the bit position of the VFP within the current data frame. This offset refers to the position of the corresponding bit in the VFP within the data frame after bit-width conversion. For example, if the serial-to-deserial parallel interface has a bit width of 40 bits, the data needs to be converted to 40 bits per frame before being written to the lane FIFO. The VFP might correspond to bit 15, in which case the offset would be 15.

[0050] Then, when each VFP reaches the serial-to-deserial parallel interface, a timestamp Ts corresponding to the current time is added to the position indicated by the VFP, and the timestamp Ts of the VFP arriving at the serial-to-deserial parallel interface is acquired. The timestamp of the next VFP arriving at the serial-to-deserial parallel interface will overwrite the timestamp of the previous VFP arriving at the serial-to-deserial parallel interface. Simultaneously, the acquired Ts and the corresponding offset are latched. After the timestamp Ts corresponding to the current time is added to the position indicated by the VFP, signal demodulation can be performed to eliminate the 1-bit sideband signal of the VFP.

[0051] In some embodiments, before generating a transmission timestamp for determining path delay based on the timestamp of the VFP arriving at the serial-to-deserial parallel interface and the offset of the VFP in a single data frame after data width conversion, the method further includes: when any lane FIFO detects a multiframe indicator MFP, obtaining the offset of the VFP in a single data frame after data width conversion and the timestamp of the VFP arriving at the serial-to-deserial parallel interface after a preset time. The preset time is greater than the time required to transmit the data amount corresponding to the first threshold value.

[0052] It is necessary to understand that, such as Figure 5As shown, since the frequency of MFP occurrence is lower than that of VFP, to save computation, after an MFP is detected on any lane FIFO read side, a preset time Td is delayed, and the VFP timestamp Ts and corresponding offset collected at the VFP are obtained to calculate the MFP transmission timestamp. After lane FIFO consistency checks and corrections, it is ensured that the deviation between lane FIFOs does not exceed the first threshold value Wt of the waterline difference. The first threshold value Wt is several SerDes clock cycles, which is much smaller than the OTU4 frame period. The preset time Td of the delay is slightly longer than the time required to transmit the amount of data corresponding to the first threshold value Wt, ensuring that when the MFP arrives at the serial-to-deserial parallel interface, the latched VFP timestamp is the timestamp of the corresponding VFP, not the timestamp of the previous VFP. Since the actual timestamp used is the timestamp value of the VFP position on the predetermined logical lane, a deviation of one or two clock cycles before or after the MFP position has no impact on the result. Therefore, the MFP only needs to be checked for presence or absence in the current clock cycle, and does not need to record the bit offset position within the current clock cycle.

[0053] The transmission timestamp corresponding to the MFP position is calculated based on Ts and offset to determine the path delay. The transmission time compensation value is determined based on the VFP offset in one data cycle after data bit width conversion and the transmission rate of the optical channel transmission unit. The single-lane rate of OTL4.4 is 255 / 227*99.5328 / 4Gb / s. Therefore, the time compensation value for each UI (UnitInterval, the time for 1 bit of data transmission) in OTL4.4 is 1 / (255 / 227*99.5328 / 4) ≈ 35.775 picoseconds. Thus, taking a VFP offset of 15 as an example, the transmission time compensation value can be calculated as 15*35.775 picoseconds. The calculated transmission time compensation value is used to compensate the timestamp of the VFP arriving at the serial-to-deserial parallel interface to obtain the transmission timestamp corresponding to the MFP position. The compensated VFP timestamp is then used as the MFP transmission timestamp and loaded into the PTP message, which is then inserted into the OTN overhead. The path delay can be obtained by subtracting the corresponding compensated VFP timestamp from the received timestamp at the MFP location.

[0054] In this embodiment, the latency deviation caused by inconsistent watermark values ​​of different lane FIFOs is reduced by aligning and adjusting all serial deserialization channel buffer lane FIFOs in the optical channel transmission unit. A virtual frame header (VFP) is set on a predetermined logical channel of the optical channel transmission unit to indicate the timing position of the frame header (FP). A transmission timestamp for determining the path latency is generated based on the timestamp of the VFP arriving at the serial deserialization parallel interface. This fixes the transmission timestamp to a single logical lane, solving the problem of path latency jitter caused by transmission timestamp jitter due to the non-fixed logical lane number of the transmission timestamp. It effectively suppresses transmission timestamp jitter and path latency jitter. Furthermore, this method is not limited by the number of channels and is applicable to scenarios where the channel where the transmission timestamp stamping point is not fixed.

[0055] Please refer to Figure 6 , Figure 6 This is a schematic block diagram of a device for determining a transmission timestamp, provided as an embodiment of this application.

[0056] like Figure 6 As shown, the device includes: The alignment module is used to align and adjust all serial-to-deserial channel buffer lane FIFOs in the optical channel transmission unit. The setting module is used to set a virtual frame header (VFP) on a predetermined logical channel of the optical channel transmission unit to indicate the timing position of the frame header (FP). The generation module is used to generate a transmission timestamp to determine the path delay based on the timestamp of the VFP arriving at the serial-to-deserial parallel interface.

[0057] The alignment module is further used for: The system clock of the optical channel transmission unit generates timing pulses; Lock the waterline value of each lane FIFO at the timed pulse; Determine whether the difference between the maximum and minimum lane FIFO waterline values ​​is greater than a preset first threshold value; If so, all lane FIFOs are reset simultaneously to align and adjust them; otherwise, no lane FIFOs are reset.

[0058] The alignment module is further used for: Clear all lane FIFOs and set the read function read preparation signal of all lane FIFOs to low level; When the real-time waterline value of each lane FIFO reaches the preset second threshold value, the read function preparation signal of the corresponding lane FIFO is set to a high level to respond to the corresponding read request.

[0059] The alignment module is further used for: The waterline values ​​of each lane FIFO locked at the timed pulse are sorted using the bubble sort method. The period of the timing pulse is greater than or equal to the number of beats required to sort the waterline values ​​of each lane FIFO.

[0060] The setting module is further configured to: When distributing each frame header FP of the optical channel transmission unit to multiple logical channels, a virtual frame header VFP is set on a predetermined logical channel.

[0061] The generation module is further configured to: Select one logical channel of the optical channel transmission unit as the predetermined logical channel; When an FP appears on any logical channel of the optical channel transmission unit, the VFP is generated at the same time position as the FP on the predetermined logical channel; Wherein, VFP is a sideband signal.

[0062] The generation module is further configured to: The transmission time compensation value is determined based on the offset of the VFP in one frame of data after data bit width conversion and the transmission rate of the optical channel transmission unit. The timestamp of the VFP arriving at the serial-to-deserial parallel interface is compensated according to the transmission time compensation value; The compensated VFP timestamp is used as the MFP transmission timestamp for determining path delay and is loaded into the PTP message.

[0063] The generation module is further configured to: When any lane FIFO detects a multiframe indicator (MFP), after a preset delay, it acquires the offset of the VFP in one data cycle after data bit width conversion and the timestamp of the VFP arriving at the serial-to-deserial parallel interface; The preset time is greater than the time required to transmit the amount of data corresponding to the first threshold value.

[0064] The device is also used for: Set the timestamp of the next VFP arriving at the serial deserialization parallel interface to overwrite the timestamp of the previous VFP arriving at the serial deserialization parallel interface.

[0065] It should be noted that those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the above-described device and its modules and units can be referred to the corresponding processes in the foregoing embodiments, and will not be repeated here.

[0066] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0067] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The above descriptions are merely specific implementations of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for determining a transmission timestamp, characterized in that, include: Align and adjust all serial-to-deserial channel buffers (lane FIFO) in the optical channel transmission unit; A virtual frame header (VFP) is set on a predetermined logical channel of the optical channel transmission unit to indicate the timing position of the frame header (FP). A transmission timestamp for determining path delay is generated based on the timestamp of VFP arrival at the serial-to-deserial parallel interface. The provision of a virtual frame header (VFP) on a predetermined logical channel of the optical channel transmission unit to indicate the timing position of the frame header (FP) includes: Select one logical channel of the optical channel transmission unit as the predetermined logical channel; When an FP appears on any logical channel of the optical channel transmission unit, the VFP is generated at the same time position as the FP on the predetermined logical channel; Wherein, VFP is a sideband signal; The step of generating a transmission timestamp for determining path delay based on the timestamp of arrival at the VFP serial-to-deserial parallel interface includes: Based on the timestamp of the VFP arriving at the serial-to-deserial parallel interface and the offset of the VFP in a single data cycle after data bit width conversion, a transmission timestamp for determining path delay is generated.

2. The method for determining the transmission timestamp according to claim 1, characterized in that, The step of aligning and adjusting all serial-to-deserial channel buffer lane FIFOs in the optical channel transmission unit includes: The system clock of the optical channel transmission unit generates timing pulses; Lock the waterline value of each lane FIFO at the timed pulse; Determine whether the difference between the maximum and minimum lane FIFO waterline values ​​is greater than a preset first threshold value; If so, all lane FIFOs are reset simultaneously to align and adjust them; otherwise, no lane FIFOs are reset.

3. The method for determining the transmission timestamp according to claim 2, characterized in that, The simultaneous reset of all lane FIFOs to align and adjust all lane FIFOs includes: Clear all lane FIFOs and set the read function read preparation signal of all lane FIFOs to low level; When the real-time waterline value of each lane FIFO reaches the preset second threshold value, the read function preparation signal of the corresponding lane FIFO is set to a high level to respond to the corresponding read request.

4. The method for determining the transmission timestamp according to claim 2, characterized in that, Before determining whether the difference between the maximum and minimum lane FIFO waterline values ​​exceeds a preset first threshold, the process also includes... The waterline values ​​of each lane FIFO locked at the timed pulse are sorted using the bubble sort method. The period of the timing pulse is greater than or equal to the number of beats required to sort the waterline values ​​of each lane FIFO.

5. The method for determining the transmission timestamp according to claim 1, characterized in that, The step of generating a transmission timestamp for determining path delay based on the timestamp of the VFP arriving at the serial-to-deserial-parallel interface and the offset of the VFP in a data clock cycle after data bit width conversion includes: The transmission time compensation value is determined based on the offset of the VFP in one frame of data after data bit width conversion and the transmission rate of the optical channel transmission unit. The timestamp of the VFP arriving at the serial-to-deserial parallel interface is compensated according to the transmission time compensation value; The compensated VFP timestamp is used as the MFP transmission timestamp for determining path delay and is loaded into the PTP message.

6. The method for determining the transmission timestamp according to claim 1, characterized in that, Before generating a transmission timestamp for determining path delay based on the VFP's offset in a data clock cycle after the VFP arrives at the serial-to-deserial-parallel interface and the data bit width conversion, the process further includes: When any lane FIFO detects a multiframe indicator (MFP), after a preset delay, it acquires the offset of the VFP in one data cycle after data bit width conversion and the timestamp of the VFP arriving at the serial-to-deserial parallel interface; The preset time is greater than the time required to transmit the data corresponding to the first threshold value.

7. The method for determining the transmission timestamp according to claim 1, characterized in that, Also includes: Set the timestamp of the next VFP arriving at the serial deserialization parallel interface to overwrite the timestamp of the previous VFP arriving at the serial deserialization parallel interface.

8. A device for determining a transmission timestamp, characterized in that, include: The alignment module is used to align and adjust all serial-to-deserial channel buffer lane FIFOs in the optical channel transmission unit. The setting module is used to set a virtual frame header (VFP) on a predetermined logical channel of the optical channel transmission unit to indicate the timing position of the frame header (FP). The generation module is used to generate a transmission timestamp to determine the path delay based on the timestamp of the VFP arriving at the serial-to-deserial parallel interface. The setting module is further configured to: Select one logical channel of the optical channel transmission unit as the predetermined logical channel; When an FP appears on any logical channel of the optical channel transmission unit, the VFP is generated at the same time position as the FP on the predetermined logical channel; Wherein, VFP is a sideband signal; The generation module is further configured to: Based on the timestamp of the VFP arriving at the serial-to-deserial parallel interface and the offset of the VFP in a single data cycle after data bit width conversion, a transmission timestamp for determining path delay is generated.

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