Instruction extension method for high-reliability real-time network device scheduling

Abstract

This invention provides a highly reliable real-time network device scheduling instruction extension method, comprising: defining an extended instruction set based on a general instruction set, using the general instruction set for flow control, and using the extended instruction set for scheduling configuration. The extended instruction set includes idle instructions, best-effort transmission instructions, frame synchronization instructions, doorbell instructions, time-triggered packet sending instructions, rate control packet sending instructions, time-triggered packet receiving instructions, rate control packet receiving instructions, composite window start instructions, and composite window end instructions for switching devices and end nodes. The scheduling instructions are synchronized with the global time. The scheduling instruction executor receives and executes the next scheduling instruction only after completing the execution of one scheduling instruction. If a general-purpose processor provides a scheduling instruction in advance, the execution of the general-purpose processor's scheduling instruction is blocked. This invention can effectively schedule network devices, achieve highly reliable network switching functions, and significantly improve the real-time performance of network device scheduling.

Description

Technical Field

[0001] This invention relates to the field of network technology, and more specifically, to an instruction extension method for scheduling highly reliable real-time network devices. Background Technology

[0002] Time-triggered Ethernet (TTE) is a new type of real-time industrial control Ethernet characterized by high real-time performance, high resource utilization, and high fault tolerance, and it has been widely used in the aerospace field. As a distributed network, TTE boasts communication rates exceeding 1Gbps and incorporates time attributes and various fault-tolerant designs to ensure reliable transmission of time-critical messages, exhibiting numerous superior characteristics such as high determinism and high real-time performance.

[0003] In the aerospace field, achieving highly reliable real-time data exchange is particularly important. However, current technology does not yet offer a highly reliable solution to achieve this. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the purpose of this invention is to provide a highly reliable real-time network device scheduling instruction extension method.

[0005] This application provides an instruction extension method for scheduling highly reliable real-time network devices, including:

[0006] Construct an extended instruction set; wherein, the scheduling instructions in the extended instruction set include: idle instruction, best-effort transmission instruction, frame synchronization instruction, doorbell instruction, time-triggered packet transmission instruction, rate control packet transmission instruction, time-triggered packet reception instruction, rate control packet reception instruction, composite window start instruction, and composite window end instruction.

[0007] The execution flow of network devices is controlled by various scheduling instructions in the extended instruction set, wherein the scheduling instructions are kept synchronized with the global time.

[0008] Optionally, before controlling the execution flow of the network device through the various scheduling instructions in the extended instruction set, the method further includes:

[0009] The duration or end time of each scheduling instruction is set by register parameters; wherein: when the highest bit of the register parameter is 0, the remaining bits of the register parameter are used to represent the duration of the scheduling instruction; when the highest bit of the register parameter is 1, the remaining bits of the register parameter are used to represent the end time of the scheduling instruction.

[0010] Optionally, the idle instruction, when used to instruct a switching device, is used to instruct all ports on the switching device to be in a closed state;

[0011] When the idle command is on the end node device, it is used to instruct all external ports on the end node device to be closed, while retaining the reception and buffering functions of internal ports.

[0012] Optionally, when the best-effort transmission command is used on the switching device, it is used to instruct the switching device to open all ports except the synchronization port;

[0013] When the best-effort transmission instruction is on the end node device, it is used to instruct the end node device to open all ports except the synchronization port and to notify the internal ports to send the previously cached data.

[0014] Optionally, the frame synchronization instruction uses an immediate value or register transmission to specify the synchronization period number;

[0015] When the frame synchronization command is on the switching device, it is used to instruct the synchronization port and data port on the switching device to be in the open state, and to notify the synchronization controller to complete the synchronization according to the synchronization cycle number.

[0016] When the frame synchronization command is on the end node device, it is used to indicate that the synchronization port and data port on the end node device are in the open state, and to notify the synchronization controller to complete the synchronization according to the synchronization cycle number.

[0017] Optionally, the doorbell command uses an immediate number or register to transmit the specified doorbell number;

[0018] When the doorbell command is on the switching device, it is used to instruct all ports on the switching device to be in a closed state, and an interrupt is used to notify the switching device manager.

[0019] When the doorbell command is on the end node device, it is used to instruct all ports on the end node device to be in a closed state, and uses an interrupt to notify the end node's manager and host.

[0020] Optionally, the time-triggered packet sending instruction uses register parameters to specify the message backup waiting time;

[0021] When the time-triggered packet sending instruction is sent on the switching device, the enable bitmap of the input port is specified using an immediate value or register parameter, and the corresponding input port is enabled.

[0022] When the time-triggered packet sending instruction is sent on the end node device, the virtual link number is specified using an immediate value or register parameter, and all data ports are opened; and the host port and management port are notified to send the cached virtual link data.

[0023] Optionally, the rate control packet sending instruction uses an immediate value or register parameter to specify the number of rate control bytes in the message;

[0024] When the rate control packet is sent to the switching device, the enable bitmap of the input port is specified using an immediate value or register parameter, and the corresponding input port is enabled.

[0025] When the rate control packet is sent to the end node device, it uses an immediate value or register parameter to specify the virtual link number, opens all data ports, and notifies the host port and management port to send the cached virtual link data.

[0026] Optionally, when the time-triggered packet receiving instruction is received on the switching device, an immediate value or register parameter is used to specify the enable bitmap of the output port, and the corresponding output port is enabled;

[0027] When the time-triggered packet receiving instruction is received on the end node device, the virtual link number is specified using an immediate value or register parameter, all data ports are opened, and the host port and management port are notified to prepare to receive the corresponding virtual link data.

[0028] When the rate control packet receives the instruction on the switching device, it uses an immediate value or register parameter to specify the enable bitmap of the output port and enables the corresponding output port.

[0029] When the rate control packet receives the instruction on the end node device, it uses an immediate value or register parameter to specify the virtual link number and notifies the host port and management port to prepare to receive the corresponding virtual link data.

[0030] The composite window start instruction and the composite window end instruction constitute a composite window instruction pair;

[0031] When the composite window instruction is applied to a switching device, it combines the enable bitmaps of multiple send and receive instructions' input ports and output ports, and uses them as a single instruction to complete the scheduling and configuration of the switching device.

[0032] When the composite window instruction pair is on the end node device, the backup waiting time and rate control byte number of multiple sending instruction messages are combined for verification configuration; wherein, the execution duration of the composite window instruction pair is provided by the composite window end instruction.

[0033] Optionally, the method further includes:

[0034] The scheduling instruction executor must complete the execution of one scheduling instruction before receiving and executing the next scheduling instruction;

[0035] If the general-purpose processor provides scheduling instructions in advance, the scheduling instruction executor blocks the execution of the scheduling instructions of the general-purpose processor.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] This application primarily addresses the complexity of high-reliability real-time network requirements by designing a special extended instruction set based on the open instruction set RISC-V. This effectively ensures the execution of time-triggered traffic scheduling tables. Furthermore, in the embodiments of this application, the extended instruction set is combined with the general RISC-V instruction set. The general instruction set is used for process control, while the extended instruction set is used for scheduling configuration, and synchronization with global time is achieved, realizing highly reliable network switching and improving the real-time performance of network device scheduling. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort. Other features, objects, and advantages of the present invention will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0039] Figure 1 This application provides a flowchart of an instruction extension method for highly reliable real-time network device scheduling.

[0040] Figure 2 A schematic diagram of a certain instruction format of an extended instruction set for scheduling high-reliability real-time network devices provided in an embodiment of this application;

[0041] Figure 3 This application provides a schematic diagram of the execution mechanism of an extended instruction set for highly reliable real-time network device scheduling;

[0042] Figure 4 This application provides a flowchart of the configuration file development process for an extended instruction set for highly reliable real-time network device scheduling. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0044] It should be noted that when a component is said to be "fixed" to another component, it can be directly on the other component or it can be in a middle component. When a component is said to be "connected" to another component, it can be directly connected to the other component or it may be in a middle component.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0046] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0047] The technical solutions of the present invention and how they solve the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0048] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0049] Figure 1 A flowchart of an instruction extension method for highly reliable real-time network device scheduling is provided in this application embodiment, as shown below. Figure 1 As shown, the method in this embodiment may include the following steps:

[0050] Step S101: Construct an extended instruction set.

[0051] In this embodiment, the scheduling instructions in the extended instruction set include: idle instruction, best-effort transmission instruction, frame synchronization instruction, doorbell instruction, time-triggered packet transmission instruction, rate control packet transmission instruction, time-triggered packet reception instruction, rate control packet reception instruction, composite window start instruction, and composite window end instruction.

[0052] Specifically, this embodiment extends the RISC-V general instruction set to obtain an extended instruction set. RISC-V provides a unified and open ecosystem for system development, as well as an open-source and well-designed SoC development framework. The extended instruction set includes 10 instruction categories: Idle, Best Effort (BE), Frame Synchronization (FRAME), Doorbell, Time Triggered Packet Transmission (XMITTT), Rate Control Packet Transmission (XMITRC), Time Triggered Packet Receive (RECVTT), Rate Control Packet Receive (RECVRC), Composite Window Start (WBEGIN), and Composite Window End (WEND). The RISC-V general instruction set and the custom extended instruction set control the execution flow of time-triggered Ethernet, with the general instruction set handling flow control and the extended instruction set handling scheduling and configuration.

[0053] For example, the IDLE instruction, when used on a switching device, indicates that all ports on the switching device are closed; when used on an end node device, the IDLE instruction indicates that all external ports on the end node device are closed, while retaining the receive and buffering functions of internal ports.

[0054] Specifically, the IDLE command requires specifying the command duration. This command shuts down all ports (P1~Pn, PSYNC, PMGMT) on the switching device. This command shuts down all external ports (P1~Pn, PSYNC) on the end node, but still retains the receive and buffering function for internal ports (PHOST, PMGMT).

[0055] For example, when the best-effort transmission (BE) instruction is on a switching device, it is used to instruct the switching device to open all ports except the synchronization port; when the best-effort transmission instruction is on an end node device, it is used to instruct the end node device to open all ports except the synchronization port and to notify the internal ports to send previously cached data.

[0056] Specifically, the Best Effort Transmission (BE) command requires specifying the command duration. This command opens all ports (P1-Pn, PMGMT) on the switching device except for the synchronization port (PSYNC). This command opens all ports (P1-Pn, PHOST, PMGMT) on the end node device except for the synchronization port (PSYNC) and instructs the internal ports (PHOST, PMGMT) to send the previously buffered BE data.

[0057] For example, the FRAME instruction uses an immediate value or register to transmit a specified synchronization period number; when the FRAME instruction is on a switching device, it is used to instruct the synchronization port and data port on the switching device to be in the open state and to notify the synchronization controller to complete synchronization according to the synchronization period number; when the FRAME instruction is on an end node device, it is used to instruct the synchronization port and data port on the end node device to be in the open state and to notify the synchronization controller to complete synchronization according to the synchronization period number.

[0058] Specifically, the FRAME instruction, in addition to specifying the instruction duration, also uses an immediate value or register parameter to specify the synchronization period number. This instruction opens the synchronization port (PSYNC) and data ports (P1~Pn) on the switching device and notifies the synchronization controller to complete synchronization according to the synchronization period number. This instruction also opens the synchronization port and data port on the end node device and notifies the synchronization controller to complete synchronization according to the synchronization period number.

[0059] For example, the doorbell instruction uses an immediate value or register to transmit the specified doorbell number; when the doorbell instruction is on a switching device, it is used to instruct all ports on the switching device to be closed and uses an interrupt to notify the switching device manager; when the doorbell instruction is on an end node device, it is used to instruct all ports on the end node device to be closed and uses an interrupt to notify the end node manager and the host.

[0060] Specifically, the doorbell command (DOORBELL), besides specifying the command duration, also uses an immediate value or register parameter to specify the doorbell number. This command shuts down all ports on the switching device and uses an interrupt to notify the switching management module. This command shuts down all ports on the end node and uses an interrupt to notify both the management module and the host module.

[0061] For example, the time-triggered packet transmission (XMITTT) instruction uses register parameters to specify the message backup wait time; when the time-triggered packet transmission instruction is on a switching device, it uses an immediate value or register parameter to specify the enable bitmap of the input port and opens the corresponding input port; when the time-triggered packet transmission instruction is on an end node device, it uses an immediate value or register parameter to specify the virtual link number and opens all data ports; and it notifies the host port and management port to send the buffered virtual link data.

[0062] Specifically, the Time-Triggered Packet Sending (XMITTT) instruction, in addition to specifying the instruction duration, uses register parameters to specify the message backup wait time (DELTA). On switching devices, this instruction uses immediate or register parameters to specify the enable bitmap of the input port and opens the corresponding input port. Because the enable bitmap of the output port also needs to be specified, this instruction is generally used inside a compound window instruction. On end-node devices, this instruction uses immediate or register parameters to specify the virtual link number, opens all data ports (P1~Pn), and notifies the host port and management port to send buffered virtual link data.

[0063] For example, the XMITRC (Extreme Rate Control Packet Sending) instruction uses an immediate value or register parameter to specify the number of rate control bytes in the message. When the XMITRC instruction is on a switching device, it uses an immediate value or register parameter to specify the enable bitmap of the input port and enables the corresponding input port. When the XMITRC instruction is on an end node device, it uses an immediate value or register parameter to specify the virtual link number, enables all data ports, and notifies the host port and management port to send buffered virtual link data.

[0064] Specifically, the XMITRC (Rate Control Packet Send) instruction, in addition to specifying the instruction duration, uses register parameters to specify the number of rate control bytes (QUOTA) for the message. On switching devices, this instruction uses immediate or register parameters to specify the enable bitmap of the input port and opens the corresponding input port. Because the enable bitmap of the output port also needs to be specified, this instruction is generally used inside a compound window instruction. On end-node devices, this instruction uses immediate or register parameters to specify the virtual link number, opens all data ports (P1 to Pn), and instructs the host port and management port to send buffered virtual link data.

[0065] For example, when the Time Triggered Packet Receive (RECVTT) instruction is on a switching device, it uses an immediate value or register parameter to specify the enable bitmap of the output port and opens the corresponding output port; when the Time Triggered Packet Receive instruction is on an end node device, it uses an immediate value or register parameter to specify the virtual link number, opens all data ports, and notifies the host port and management port to prepare to receive the corresponding virtual link data.

[0066] Specifically, the Time-Triggered Packet Receive (RECVTT) instruction requires specifying the instruction duration. On switching devices, this instruction uses immediate or register parameters to specify the enable bitmap of the output port and opens the corresponding output port. Because the enable bitmap of the input port also needs to be specified, this instruction is generally used inside a compound window instruction. On end-node devices, this instruction uses immediate or register parameters to specify the virtual link number, opens all data ports (P1 to Pn), and notifies the host port and management port to be ready to receive data from the corresponding virtual link.

[0067] For example, when the Rate Control Packet Receive (RECVRC) command is executed on a switching device, an immediate value or register parameter is used to specify the enable bitmap of the output port, and the corresponding output port is enabled. When the Rate Control Packet Receive command is executed on an end node device, an immediate value or register parameter is used to specify the virtual link number, and the host port and management port are notified to prepare to receive the corresponding virtual link data.

[0068] Specifically, the Rate Control Packet Receive (RECVRC) instruction requires specifying the instruction duration. On switching equipment, this instruction uses immediate or register parameters to specify the enable bitmap of the output port and opens the corresponding output port. Because the enable bitmap of the input port also needs to be specified, this instruction is generally used inside a compound window instruction. On end-node equipment, this instruction uses immediate or register parameters to specify the virtual link number and notifies the host port and management port to prepare to receive data from the corresponding virtual link.

[0069] For example, the composite window start (WBEGIN) instruction and the composite window end (WEND) instruction constitute a composite window instruction pair. When on a switching device, the composite window instruction pair combines the enable bitmaps of multiple send and receive instructions' input and output ports, and uses this as a single instruction to complete the scheduling and configuration of the switching device. When on an end node device, the composite window instruction pair combines the backup wait time and rate control byte count of multiple send instructions' messages for verification and configuration; the execution duration of the composite window instruction pair is provided by the composite window end instruction.

[0070] Specifically, the composite window start (WBEGIN) and composite window end (WEND) commands constitute a composite window instruction pair, and the instruction duration needs to be specified. On switching equipment, the composite window instruction pair is used to combine the input and output port enable bitmaps of multiple send and receive commands, and complete the scheduling and configuration of the switching equipment as a single instruction. On end-node equipment, the composite window instruction is used to combine the DELTA and QUOTA of multiple send commands for verification configuration. The execution duration of the composite window instruction pair is provided by the composite window end (WEND) instruction.

[0071] Step S102: Control the execution flow of network devices through various scheduling instructions in the extended instruction set, wherein the scheduling instructions are kept synchronized with the global time.

[0072] In this embodiment, by embedding the RISC-V instruction set into the switching IP (Internet Protocol Address) core and the end-node IP core, RISC-V instructions are read from DDR (Double Data Rate) according to the process sequence, and the execution flow of network port data on the entire switching and end-node is controlled according to the instruction content. Controlling the execution flow of the TTE (Time-Triggered Ethernet) network through the RISC-V instruction set improves the efficiency of front-end logic design.

[0073] Optionally, before controlling the execution flow of network devices through various scheduling instructions in the extended instruction set, the method further includes:

[0074] Step S103: Set the duration or end time of each scheduling instruction through register parameters; wherein: when the highest bit of the register parameter is 0, the remaining bits of the register parameter are used to represent the duration of the scheduling instruction; when the highest bit of the register parameter is 1, the remaining bits of the register parameter are used to represent the end time of the scheduling instruction.

[0075] Optionally, the method further includes:

[0076] Step S104: The scheduling instruction executor must receive and execute the next scheduling instruction only after completing the execution of one scheduling instruction.

[0077] Step S105: If the general-purpose processor provides scheduling instructions in advance, the scheduling instruction executor blocks the execution of the general-purpose processor's scheduling instructions.

[0078] In this embodiment, the scheduling instructions are synchronized with the global time. The scheduling instruction executor always receives the next scheduling instruction only after completing the execution of the previous one. If the general-purpose processor provides the scheduling instruction in advance, the scheduling instruction executor will block the instruction execution of the general-purpose processor.

[0079] This embodiment primarily addresses the complexity of high-reliability real-time network requirements by designing a special extended instruction set based on the open instruction set RISC-V. This effectively ensures the execution of time-triggered traffic scheduling tables. Furthermore, this embodiment combines the extended instruction set with the general-purpose RISC-V instruction set. The general-purpose instruction set is used for process control, while the extended instruction set is used for scheduling configuration, all synchronized with global time. This achieves highly reliable network switching and improves the real-time performance of network device scheduling.

[0080] The present invention will be further described in detail below through embodiments and with reference to the accompanying drawings. The described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention.

[0081] The first embodiment of this invention provides an extended instruction set for highly reliable real-time network device scheduling. This instruction set consists of a general RSIC-V instruction set and a custom extended instruction set, used to control the execution process of time-triggered Ethernet. By combining the custom extended instruction set with the general instruction set, highly reliable network switching can be achieved, improving the real-time performance of network device scheduling. The format of the instruction set is as follows: Figure 2 As shown.

[0082] In this embodiment, the extended instruction set for high-reliability real-time network device scheduling can be used for data transmission and reception management of network switching devices to realize the execution of time-triggered traffic scheduling tables. As shown in Table 1, some instructions from embodiments of this disclosure are listed.

[0083] Table 1 IP Switching Command Set

[0084]

[0085] This IP switching command set includes 10 categories of commands: Idle, Best Effort (BE), Frame Synchronization (FRAME), Doorbell, Time Triggered Transmission (XMITTT), Rate Control Transmission (XMITRC), Time Triggered Reception (RECVTT), Rate Control Reception (RECVRC), Composite Window Start (WBEGIN), and Composite Window End (WEND). The definitions of the IP switching commands are as follows:

[0086] idle <rd> ， <rs1>,x0 / idlei <rd> ， <rs1>0: Idle window command, neither sending nor receiving data. The command starts from... <rs1>The end time of the read or the total duration of the instruction. If <rs1>If it's a positive number, it indicates the end time. If <rs1>It is a negative number, and its absolute value represents the total instruction duration. The end time point is generally used for the direct instruction list, while the total instruction duration is used for the instruction list in a subroutine. After the instruction begins execution, [the text abruptly ends here]. <rd>Write the start time point.

[0087] be <rd> ， <rs1>,x0 / at <rd> ， <rs1>0: Best-effort transmit / receive window command, allowing the transmission and reception of BE frames. The command originates from... <rs1>Read the end time point or total instruction duration. After the instruction begins execution, [the text abruptly ends here]. <rd>Write the start time point.

[0088] frame <rd> ， <rs1> ， <rs2> / frame <rd> ， <rs1> ， <imm>: Synchronize message window command. Enables the transmission and reception of AS6802 PCF frames. In the frame command, use... <rs2>Specifies the synchronization period for PCF frames. In the `framei` directive, an immediate value is used. <imm>Specifies the synchronization period for PCF frames. The instruction originates from... <rs1>Read the end time point or total instruction duration. After the instruction begins execution, [the text abruptly ends here]. <rd>Write the start time point. It should be noted that the frame instruction generally starts execution when local_clock is relatively large, and its end time point is relatively small, covering the moment when local_clock returns to zero.

[0089] doorbell <rd> ， <rs1> ， <rs2> / doorbell <rd> ， <rs1> , <imm>: Doorbell window instruction. Allows direct sending of register number '(')' to the application processor from the dispatch instruction table. <rs2>Content or immediate number <imm>The doorbell stopped ringing. The instruction came from... <rs1>Read the end time point or total instruction duration. After the instruction begins execution, [the text abruptly ends here]. <rd>Write the start time point.

[0090] recvtt <rd> ， <rs1> ， <rs2> / recvtti <rd> ， <rs1> ， <imm>TT message receive instruction. Notification send gating enable register. <rs2>Content or immediate number <imm>Send data packets to the specified port. The command originates from... <rs1>Read the end time point or total instruction duration. After the instruction begins execution, [the text abruptly ends here]. <rd>Write the start time point.

[0091] recvrc <rd> ， <rs1> ， <rs2> / recvrci <rd> , <rs1> ， <imm>RC message receive instruction. Notification send gating enable register. <rs2>Content or immediate number <imm>Send data packets to the specified port. The command originates from... <rs1>Read the end time point or total instruction duration. After the instruction begins execution, [the text abruptly ends here]. <rd>Write the start time point.

[0092] xmittt <rs3 rd> ， <rs1> ， <rs2> / xmitt <rs3 rd> ， <rs1> ， <imm>:TT message send command. Notification receive gate enable register <rs2>Content or immediate number <imm>Data packets are sent to the specified port. The command is executed... <rs3>Specify the DELTA (Message Backup Wait Time) value for this window. This means that if no TT message is sent from this port within a DELTA period, then TT messages are allowed to be sent into this port. Using the DELTA mechanism, Master / Shadow mode backups of the host can be implemented. For the same TT message, the Master's DELTA is 0, and the Backup's DELTA is set to the transmission delay from the Master to the Backup. This allows the Backup to send critical commands when the Master experiences a downtime. Commands are sent from... <rs1>Read the end time point or total instruction duration. After the instruction begins execution, [the text abruptly ends here]. <rd>Write the start time. Because... <rs3>and <rd>Sharing a single encoding field, after the instruction begins execution, the original encoding field... <rs3>The DELTA in the data is overwritten by the start time point.

[0093] xmitrc <rs3 rd> ， <rs1> ， <rs2> / xmitrci <rs3 rd> ， <rs1> ， <imm>RC message send instruction. Notification receive gate enable register. <rs2>Content or immediate number <imm>Data packets are sent to the specified port. The command is executed... <rs3>Specifying the QUOTA (rate control bytes) value for this window allows only QUOTA bytes to be sent to this port, thus implementing rate limiting at the sending end. The command originates from... <rs1>Read the end time point or total instruction duration. After the instruction begins execution, [the text abruptly ends here]. <rd>Write the start time. Because... <rs3>and <rd>Sharing a single encoding field, after the instruction begins execution, the original encoding field... <rs3>The QUOTA in the file was overwritten by the start time point.

[0094] The `wbegin` and `wend` commands are used to combine multiple data send / receive commands into a single compound command for execution. Currently, on switches, `xmittt / recvtt` and `xmitrc / recvrc` need to be executed as a compound command, specifying both the inbound and outbound ports of the switch within that window.

[0095] Another embodiment of the present invention provides an extended instruction set for highly reliable real-time network device scheduling of end-node devices. This instruction set consists of a general RSIC-V instruction set and a custom extended instruction set, used to control time-triggered Ethernet execution processes. By combining the custom extended instruction set with the general instruction set, highly reliable network switching can be achieved, improving the real-time performance of network device scheduling.

[0096] In this embodiment, the extended instruction set for high-reliability real-time network device scheduling can be used for data transmission and reception management of end-node devices to realize the execution of time-triggered traffic scheduling tables. As shown in Table 2, some instructions from embodiments of this disclosure are listed.

[0097] Table 2 End Node IP Command Set

[0098]

[0099]

[0100] This end-node IP command set includes 10 categories of commands: Idle, Best Effort (BE), Frame Synchronization (FRAME), Doorbell, Time Triggered Transmission (XMITTT), Rate Control Transmission (XMITRC), Time Triggered Reception (RECVTT), Rate Control Reception (RECVRC), Composite Window Start (WBEGIN), and Composite Window End (WEND). The definitions of the end-node IP commands are as follows:

[0101] idle <rd> ， <rs1>,x0 / idlei <rd> ， <rs1>0: Idle window command, neither sending nor receiving data. The command starts from... <rs1>The end time of the read or the total duration of the instruction. If <rs1>If it's a positive number, it indicates the end time. If <rs1>It is a negative number, and its absolute value represents the total instruction duration. The end time point is generally used for the direct instruction list, while the total instruction duration is used for the instruction list in a subroutine. After the instruction begins execution, [the text abruptly ends here]. <rd>Write the start time point.

[0102] be <rd> ， <rs1>,x0 / at <rd> ， <rs1>0: Best-effort transmit / receive window command, allowing the transmission and reception of BE frames. The command originates from... <rs1>Read the end time point or total instruction duration. After the instruction begins execution, [the text abruptly ends here]. <rd>Write the start time point.

[0103] frame <rd> ， <rs1> ， <rs2> / frame <rd> ， <rs1> ， <imm>: Synchronize message window command. Enables the transmission and reception of AS6802 PCF frames. In the frame command, use... <rs2>Specifies the synchronization period for PCF frames. In the `framei` directive, an immediate value is used. <imm>Specifies the synchronization period for PCF frames. The instruction originates from... <rs1>Read the end time point or total instruction duration. After the instruction begins execution, [the text abruptly ends here]. <rd>Write the start time point. It should be noted that the frame instruction generally starts execution when local_clock is relatively large, and its end time point is relatively small, covering the moment when local_clock returns to zero.

[0104] doorbell <rd> ， <rs1> ， <rs2> / doorbell <rd> ， <rs1> , <imm>: Doorbell window instruction. Allows direct sending of register number '(')' to the application processor from the dispatch instruction table. <rs2>Content or immediate number <imm>The doorbell stopped ringing. The instruction came from... <rs1>Read the end time point or total instruction duration. After the instruction begins execution, [the text abruptly ends here]. <rd>Write the start time point.

[0105] recvtt <rd> ， <rs1> ， <rs2> / recvtti <rd> ， <rs1> ， <imm>TT message receive instruction. Notification send gating enable register. <rs2>Content or immediate number <imm>Send data packets to the specified port. The command originates from... <rs1>Read the end time point or total instruction duration. After the instruction begins execution, [the text abruptly ends here]. <rd>Write the start time point.

[0106] recvrc <rd> ， <rs1> ， <rs2> / recvrci <rd> , <rs1> ， <imm>RC message receive instruction. Notification send gating enable register. <rs2>Content or immediate number <imm>Send data packets to the specified port. The command originates from... <rs1>Read the end time point or total instruction duration. After the instruction begins execution, [the text abruptly ends here]. <rd>Write the start time point.

[0107] xmittt <rs3 rd> ， <rs1> ， <rs2> / xmitt <rs3 rd> ， <rs1> ， <imm>:TT message send command. Notification receive gate enable register <rs2>Content or immediate number <imm>Data packets are sent to the specified port. The command is executed... <rs3>Specify the DELTA value for this window; if no TT message is sent from this port within a DELTA period, then TT messages are allowed to be sent into this port. Using the DELTA mechanism, Master / Shadow mode backups of the host can be implemented. For the same TT message, the DELTA for the master is 0, and the DELTA for the backup is set to the transmission delay from the master to the backup. This allows the backup to send critical commands when the master experiences a downtime. Commands are sent from... <rs1>Read the end time point or total instruction duration. After the instruction begins execution, [the text abruptly ends here]. <rd>Write the start time. Because... <rs3>and <rd>Sharing a single encoding field, after the instruction begins execution, the original encoding field... <rs3>The DELTA in the data is overwritten by the start time point.

[0108] xmitrc <rs3 rd> ， <rs1> ， <rs2> / xmitrci <rs3 rd> ， <rs1> ， <imm>RC message send instruction. Notification receive gate enable register. <rs2>Content or immediate number <imm>Data packets are sent to the specified port. The command is executed... <rs3>Specifying the QUOTA value for this window allows only QUOTA bytes to be sent to this port, thus implementing sender-side rate limiting. The command originates from... <rs1>Read the end time point or total instruction duration. After the instruction begins execution, [the text abruptly ends here]. <rd>Write the start time. Because... <rs3>and <rd>Sharing a single encoding field, after the instruction begins execution, the original encoding field... <rs3>The QUOTA in the file was overwritten by the start time point.

[0109] The `wbegin` and `wend` commands are used to combine multiple data send / receive commands into a single compound command for execution. Currently, on switches, `xmittt / recvtt` and `xmitrc / recvrc` need to be executed as a compound command, specifying both the inbound and outbound ports of the switch within that window.

[0110] Furthermore, to implement the above instructions, the Control and Status Register (CSR) defined in the RISC-V architecture is used to configure or record some operational states. The CSR register is an internal register of the processor core, using a dedicated 12-bit address encoding space.

[0111] Access to the CSR register uses dedicated CSR instructions, including CSRRW, CSRRS, CSRRC, CSRRWI, CSRRSI, and CSRRCI.

[0112] The standard RISC-V ISA allocates a 12-bit encoding space (csr[11:0]) for 4096 CSRs. By convention, the high 4 bits of the CSR address (csr[11:8]) are used to encode the accessibility of the CSR based on privilege level. The highest 2 bits (csr[11:10]) indicate whether the register is readable / writable (00, 01, or 10) or read-only (11). The last 2 bits (csr[9:8]) indicate the minimum privilege level required to access the CSR (00 for user level, 01 for administrator level).

[0113] Furthermore, one embodiment of the present invention provides an execution mechanism for highly reliable real-time network device scheduling instructions, such as... Figure 3 As shown, scheduling instructions utilize the network-wide synchronized local clock for synchronized execution. When the RISC-V kernel delivers scheduling instruction B to the scheduling instruction executor, if the previous scheduling instruction A has not yet finished executing, the executor will block the RISC-V kernel from executing scheduling instruction B and subsequent instructions. Conversely, after the executor completes scheduling instruction A, the RISC-V kernel should have already completed other tasks and placed scheduling instruction B at the scheduling instruction executor entry point. Using this mechanism, the RISC-V kernel can run a small number of ordinary instructions after the start of each window to set or collect the state of other parts of the end system, synchronizing it with the overall network state.

[0114] Furthermore, to achieve compatibility with TTTech products, one embodiment of the present invention provides an instruction development process, such as... Figure 4 As shown, the development of the RISC-V instruction set is based on the TTTech product configuration file. The configuration file is converted into an assembly file using a configuration file conversion tool, and then configuration modifications and subsequent processes are performed.

[0115] Furthermore, embodiments of this application also provide a computer-readable storage medium storing computer-executable instructions, wherein when at least one processor of a user device executes the computer-executable instructions, the user device performs the various possible methods described above.

[0116] Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of computer programs from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an ASIC. Alternatively, the ASIC can reside in a user device. Of course, the processor and storage medium can also exist as discrete components in a communication device.

[0117] This application also provides a program product including a computer program stored in a readable storage medium. At least one processor of the server can read the computer program from the readable storage medium, and the at least one processor executes the computer program to cause the server to implement any of the methods described in the embodiments of the present invention.

[0118] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0119] It can employ a portable compact disc read-only memory (CD-ROM) and include program code, and can run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, the readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0120] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0121] Computer-readable storage media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable storage medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0122] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0123] The various embodiments described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0124] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention. < / rd> < / rd> < / imm> < / imm> < / rs1> < / rs3> < / rs1> < / rs3> < / rd> < / rd> < / imm> < / imm> < / rs1> < / rs3> < / rs1> < / rs3> < / rd> < / imm> < / imm> < / rs1> < / rd> < / rs1> < / rd> < / rd> < / imm> < / imm> < / rs1> < / rd> < / rs1> < / rd> < / rd> < / imm> < / imm> < / rs1> < / rd> < / rs1> < / rd> < / rd> < / imm> < / imm> < / rs1> < / rd> < / rs1> < / rd> < / rd> < / rd> < / rd> < / rd> < / rd> < / rd> < / rd> < / rd> < / imm> < / imm> < / rs1> < / rs3> < / rs1> < / rs3> < / rd> < / rd> < / imm> < / imm> < / rs1> < / rs3> < / rs1> < / rs3> < / rd> < / imm> < / imm> < / rs1> < / rd> < / rs1> < / rd> < / rd> < / imm> < / imm> < / rs1> < / rd> < / rs1> < / rd> < / rd> < / imm> < / imm> < / rs1> < / rd> < / rs1> < / rd> < / rd> < / imm> < / imm> < / rs1> < / rd> < / rs1> < / rd> < / rd> < / rd> < / rd> < / rd> < / rd> < / rd>

Claims

1. A method for instruction extension of high-reliability real-time network device scheduling, characterized in that, include: An extended instruction set is constructed; wherein the scheduling instructions in the extended instruction set include: idle instruction, best-effort transmission instruction, frame synchronization instruction, doorbell instruction, time-triggered packet transmission instruction, rate control packet transmission instruction, time-triggered packet reception instruction, rate control packet reception instruction, composite window start instruction, and composite window end instruction; the idle instruction, when on a network device, is used to instruct all ports on the network device to be in a closed state; the idle instruction, when on an end node device, is used to instruct all external ports on the end node device to be in a closed state, while retaining the reception and buffering functions of internal ports; When the best-effort transmission instruction is on a network device, it is used to instruct the network device to open all ports except the synchronization port; when the best-effort transmission instruction is on an end node device, it is used to instruct the end node device to open all ports except the synchronization port and to notify the internal ports to send the previously cached data. The frame synchronization instruction uses an immediate value or register to transmit a specified synchronization period number; when the frame synchronization instruction is on a network device, it is used to indicate that the synchronization port and data port on the network device are in an open state, and to notify the synchronization controller to complete synchronization according to the synchronization period number; when the frame synchronization instruction is on an end node device, it is used to indicate that the synchronization port and data port on the end node device are in an open state, and to notify the synchronization controller to complete synchronization according to the synchronization period number. The doorbell command uses an immediate number or register transmission to specify the doorbell number; when the doorbell command is on a network device, it is used to instruct all ports on the network device to be in a closed state, and uses an interrupt to notify the network device manager; when the doorbell command is on an end node device, it is used to instruct all ports on the end node device to be in a closed state, and uses an interrupt to notify the end node manager and the host; the time-triggered packet sending command uses register parameters to specify the message backup waiting time; When the time-triggered packet sending instruction is sent on a network device, it uses an immediate value or register parameter to specify the enable bitmap of the input port and opens the corresponding input port; when the time-triggered packet sending instruction is sent on an end node device, it uses an immediate value or register parameter to specify the virtual link number and opens all data ports; and notifies the host port and management port to send buffered virtual link data; the time-triggered packet sending instruction uses register parameters to specify the message backup waiting time; when the time-triggered packet sending instruction is sent on a network device, it uses an immediate value or register parameter to specify the enable bitmap of the input port and opens the corresponding input port; when the time-triggered packet sending instruction is sent on an end node device, it uses an immediate value or register parameter to specify the virtual link number and opens all data ports; and notifies the host port and management port to send buffered virtual link data; The rate control packet sending instruction uses an immediate value or register parameter to specify the number of rate control bytes in the message; when the rate control packet sending instruction is on a network device, it uses an immediate value or register parameter to specify the enable bitmap of the input port and opens the corresponding input port; when the rate control packet sending instruction is on an end node device, it uses an immediate value or register parameter to specify the virtual link number, opens all data ports, and notifies the host port and management port to send the buffered virtual link data. When the time-triggered packet receiving instruction is received on a network device, an immediate value or register parameter is used to specify the enable bitmap of the output port, and the corresponding output port is opened; when the time-triggered packet receiving instruction is received on an end node device, an immediate value or register parameter is used to specify the virtual link number, all data ports are opened, and the host port and management port are notified to prepare to receive the corresponding virtual link data. When the rate control packet receiving instruction is received on the network device, the enable bitmap of the output port is specified using an immediate value or register parameter, and the corresponding output port is opened; when the rate control packet receiving instruction is received on the end node device, the virtual link number is specified using an immediate value or register parameter, and the host port and management port are notified to prepare to receive the corresponding virtual link data. The composite window start instruction and the composite window end instruction constitute a composite window instruction pair. When the composite window instruction pair is on a network device, it combines the enable bitmaps of multiple send and receive instructions' input ports and output ports, and uses them as a single instruction to complete the scheduling and configuration of the network device. When the composite window instruction pair is on an end node device, it combines the backup waiting time and rate control byte number of multiple send instructions' messages for composite configuration. The execution duration of the composite window instruction pair is provided by the composite window end instruction. The execution flow of network devices is controlled by various scheduling instructions in the extended instruction set, wherein the scheduling instructions are kept synchronized with the global time.

2. The instruction extension method for high-reliability real-time network device scheduling according to claim 1, characterized in that, Before controlling the execution flow of network devices through the various scheduling instructions in the extended instruction set, the method further includes: The duration or end time of each scheduling instruction is set by register parameters; wherein: when the highest bit of the register parameter is 0, the remaining bits of the register parameter are used to represent the duration of the scheduling instruction; when the highest bit of the register parameter is 1, the remaining bits of the register parameter are used to represent the end time of the scheduling instruction.

3. The instruction extension method of claim 1 or 2, wherein, The method further includes: The scheduling instruction executor must complete the execution of one scheduling instruction before receiving and executing the next scheduling instruction; If the general-purpose processor provides scheduling instructions in advance, the scheduling instruction executor blocks the execution of the scheduling instructions of the general-purpose processor.

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