A semiconductor structure and a method of fabricating the same

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a preparation method thereof, which are used to solve the problem of chip reliability decline caused by the increasing density of semiconductor memory cells. The semiconductor structure comprises: a substrate comprising a plurality of transistors arranged in an array; an isolation structure located inside the substrate, the isolation structure being located between any two adjacent rows of the transistors; wherein the isolation structure comprises a first sub-portion, a second sub-portion and a third sub-portion, the first sub-portion and the third sub-portion being located on two sides of the second sub-portion, wherein the lower surface of the first sub-portion and the lower surface of the third sub-portion are lower than the lower surface of the second sub-portion. By using the above-mentioned isolation structure between the transistors, the mutual influence between the memory cells can be effectively reduced, and the reliability of the semiconductor structure can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for preparing the same. Background Technology

[0002] In recent years, with the continuous increase in the density of semiconductor structural units, the interaction between structural units in semiconductor structures has easily led to phenomena such as capacitor leakage, electrical coupling, and row hammer effect, resulting in a decline in the performance of semiconductor structures such as DRAM.

[0003] Therefore, how to reduce the capacitive coupling effect inside the semiconductor structure, thereby improving the performance of the semiconductor structure, is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] This disclosure provides a method for fabricating a semiconductor structure, including: The substrate includes multiple transistors arranged in an array; An isolation structure located inside the substrate, the isolation structure being situated between any two adjacent rows of transistors; The isolation structure includes a first sub-part, a second sub-part, and a third sub-part. The first sub-part and the third sub-part are located on both sides of the second sub-part. The lower surfaces of the first sub-part and the third sub-part are lower than the lower surface of the second sub-part.

[0005] In some embodiments, the substrate includes a plurality of word lines, wherein the lower surfaces of the first sub-part and the third sub-part are lower than the lower surfaces of the word lines. In some embodiments, along the direction in which the word line extends, the length of the isolation structure is greater than the length of the word line, or the length of the isolation structure is less than the length of the word line.

[0006] In some embodiments, the material of the isolation structure includes a conductive material.

[0007] In some embodiments, the device further includes: a via located on the back side of the substrate, through which the first sub-part or the third sub-part is exposed; and an isolation lead-out structure located at least partially within the via, the isolation lead-out structure being electrically connected to the first sub-part or the third sub-part.

[0008] In some embodiments, the substrate includes a dummy transistor, and the isolation lead structure is also connected to the conductive channels of the dummy transistor on adjacent sides.

[0009] In some embodiments, the isolation lead-out structure is grounded or connected to an external power supply.

[0010] In some embodiments, the isolation structure and the isolation lead-out structure are made of the same conductive material.

[0011] This disclosure also provides a method for fabricating a semiconductor structure, including: A substrate is provided, the substrate comprising a plurality of transistors arranged in an array; An isolation structure is formed inside the substrate, the isolation structure being located between any two adjacent rows of transistors; wherein the isolation structure includes a first sub-section, a second sub-section, and a third sub-section, the first sub-section and the third sub-section being located on both sides of the second sub-section, wherein the lower surface of the first sub-section and the lower surface of the third sub-section are lower than the lower surface of the second sub-section.

[0012] In some embodiments, after forming the isolation structure, the method further includes: A through-hole is formed by etching the back side of the substrate, and the first sub-part or the third sub-part is exposed from the through-hole; The through-hole is filled to form the isolation lead-out structure, which is electrically connected to the first sub-part or the third sub-part.

[0013] In this embodiment of the disclosure, an isolation structure disposed between transistors is used to isolate adjacent transistors, and an isolation lead-out structure is used to lead the coupled charge between adjacent transistors out of the semiconductor structure. This can effectively reduce the mutual influence between memory cells, reduce the probability of row hammer effect and electrical coupling, and improve the reliability of the semiconductor structure.

[0014] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a top view of a semiconductor structure according to an embodiment of the present disclosure; Figure 2 This is a schematic diagram of the isolation structure according to an embodiment of the present disclosure; Figures 3 to 5 This is a detailed schematic diagram of a semiconductor structure according to an embodiment of the present disclosure, wherein, Figure 3 For along Figure 1A schematic diagram of the vertical cross-section of line b-b' in the diagram. Figure 4 For along Figure 1 A schematic diagram of the vertical cross-section of line a-a' in the diagram. Figure 5 For along Figure 1 A schematic diagram of the vertical cross-section of line c-c' in the diagram; Figure 6 This is a flowchart illustrating the manufacturing process of a semiconductor structure according to an embodiment of the present disclosure; Figures 7 to 12 This is a schematic diagram of the semiconductor structure according to an embodiment of the present disclosure during the manufacturing process, wherein, Figure 7 This is a top view of a semiconductor structure according to an embodiment of the present disclosure during the manufacturing process. Figures 8 to 10 Figure (2) shows the route along Figure 1 A schematic diagram of the vertical cross-section of line b-b' in the diagram. Figures 8 to 10 (1) Figure in Figure 11 , Figure 12 For along Figure 1 A schematic diagram of the vertical cross-section of line a-a' in the diagram. Detailed Implementation

[0017] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0018] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0019] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0020] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0021] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0023] In recent years, as semiconductor chips have continued to develop towards higher integration, the density of memory cells in semiconductor structures has been increasing. This has led to a situation where, when the same row of memory cells is read many times in a short period of time (a behavior known as "hammering"), the charge in that row of memory cells can easily leak to adjacent rows, changing the values ​​of the memory cells in those adjacent rows. This phenomenon is called bit flipping, which in turn causes information errors in the memory chip. This phenomenon not only affects the reliability of the semiconductor structure but also the performance and value of the semiconductor memory chip.

[0024] Based on this, embodiments of this disclosure provide a semiconductor structure, such as... Figure 1-2 As shown, it includes: The substrate 100 includes a plurality of transistors 101 arranged in an array; An isolation structure 110 is located inside the substrate 100, and the isolation structure 110 is located between any two adjacent rows of transistors 101; The isolation structure 110 includes a first sub-part 111, a second sub-part 112, and a third sub-part 113. The first sub-part 111 and the third sub-part 113 are located on both sides of the second sub-part 112, as shown in the attached diagram. Figure 2 As shown, the lower surface of the first sub-part 111 and the lower surface of the third sub-part 113 are lower than the lower surface of the second sub-part 112.

[0025] In this embodiment of the disclosure, the isolation structure 110 disposed between transistors 101 isolates adjacent transistors 101, which can effectively reduce the mutual influence between memory cells. The first sub-part 111 and the third sub-part 113 in the isolation structure 110 can facilitate the subsequent lead-out of the isolation structure 110, thereby reducing the probability of row hammer effect and coupling phenomenon, and improving the reliability of semiconductor structure.

[0026] The semiconductor structure provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings.

[0027] As attached Figure 1 As shown, the semiconductor structure includes a substrate 100, in which a plurality of transistors 101 are arranged in an array. The plurality of transistors 101 are arranged in an array on the substrate 100 at intervals in the column direction and the row direction. Here, the plurality of transistors 101 can be as shown in the attached figure. Figure 3 The vertical gate transistor (VGT) shown can also be a planar transistor, a buried channel array transistor (BCAT), etc.

[0028] The substrate 100 may be a semiconductor substrate, specifically including at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate 100 is a silicon substrate.

[0029] along Figure 1 The b-b' line in the diagram forms a vertical cross-section. Figure 3 ,along Figure 1 The a-a' line in the diagram forms a vertical cross-section. Figure 4 .

[0030] See appendix Figure 3-4 In this embodiment, a vertical gate transistor is used. This structure can reduce the area of ​​the transistor structure, thereby increasing the storage density of the semiconductor device.

[0031] Each transistor 101 includes a conductive channel 102, and the conductive channels 102 of each transistor 101 are arranged in an array (as shown in the attached figure). Figure 1 As shown), the channel extends in a direction perpendicular to the substrate 100. The gate oxide layer 103 and the gate conductive layer 104 of the transistor 101 are located on one side of the conductive channel 102, and the gate oxide layer 103 is located between the conductive channel 102 and the gate conductive layer 104. Each conductive channel 102 has a source 106 and a drain 107 at both ends of its extension direction. The drain 107 can be led out from the back side 100a of the substrate to form a bit line (not shown in the figure).

[0032] The gate oxide layer 103 may be made of silicon oxide, a high-k dielectric material, or a combination thereof. The material of the gate conductive layer 104 may include polysilicon and / or a metal electrode (such as tungsten). The material of the conductive channel 102 may include, but is not limited to, one or more of silicon, silicon carbide, gallium nitride, and IGZO.

[0033] See appendix for further details. Figure 1 An isolation structure 110 is provided inside the substrate 100. The isolation structure 110 is located between any two adjacent rows of transistors 101. This isolation structure 110 can separate adjacent transistors 101, prevent leakage charges in transistors 101 from affecting each other, and improve the performance of semiconductor chips.

[0034] It should be noted that, as Figure 3As shown, in this embodiment, the transistors 101 are symmetrically distributed, with two symmetrical transistors 101 separated by a substrate 100 or an insulating material, and adjacent pairs of transistors 101 are separated by an isolation structure 110 (i.e., an additional layer of insulating material). Figure 3 The second sub-section 112 of the structure is electrically insulated from any transistor 101. In actual operation, the isolation structure 110 can be located between any two transistors 101.

[0035] Among them, such as Figure 2 As shown, the isolation structure 110 includes a first sub-part 111, a second sub-part 112, and a third sub-part 113. The first sub-part 111 and the third sub-part 113 are located on both sides of the second sub-part 112. The lower surfaces of the first sub-part 111 and the third sub-part 113 are lower than the lower surface of the second sub-part 112. The material of the isolation structure 110 may include a conductive material, such as a metallic material or a metal silicide material. The isolation structure 110 is configured as shown in the attached figure. Figure 2 The "π" shape shown helps to reduce the process difficulty when setting up the subsequent isolation lead-out structure 122, facilitates the lead-out of the isolation structure 110, and allows the position of the isolation lead-out structure 122 to be planned in advance, making it easier to connect with the subsequent isolation lead-out structure 122.

[0036] Specifically, the size range of the lower surface of the first sub-part 111 and the lower surface of the third sub-part 113 being lower than the lower surface of the second sub-part 112 is not specifically limited. The size is based on the isolation effect achieved between adjacent transistors in actual operation.

[0037] In one embodiment, see Appendix Figure 1 Appendix Figure 5 The semiconductor structure also includes a via 121 located on the back side of the substrate 100a. A first sub-part 111 or a third sub-part 113 is exposed through the via 121. An isolation lead-out structure 122, at least partially located within the via 121, is electrically connected to the first sub-part 111 or the third sub-part 113. Typically, the substrate 100 has two opposing surfaces. The front side of the substrate 100b can be used to form semiconductor devices, and the back side of the substrate 100a is a plane relative to the front side of the substrate 100b. The isolation lead-out structure 122 is disposed within the via 121 on the back side of the substrate 100a. One end is electrically connected to the isolation structure 110, and the other end can be grounded or connected to an external power supply (not shown in the figure), thereby realizing the lead-out of the isolation structure 110.

[0038] Of course, the isolation lead-out structure 122 can be electrically connected to the first sub-part 111 and the third sub-part 113 at the same time, that is, each isolation structure 110 is connected to two isolation lead-out structures 122.

[0039] It should be noted that the appendix Figure 1The isolation lead-out structure 122 is actually located on the back side of the substrate 100a, and the isolation structure 110 is located inside the substrate 100. The accompanying drawings are only for better illustration of the contents of the embodiments of this disclosure.

[0040] In summary, the semiconductor structure in this embodiment isolates adjacent transistors 101 through the isolation structure 110, and leads out the coupled charge or leakage charge between adjacent transistors 101 through the isolation lead-out structure 122 which is electrically connected to the isolation structure 110. In this way, the mutual influence between memory cells can be reduced, the probability of horizontal hammer effect or electrical interference can be reduced, and the reliability of the semiconductor structure can be improved.

[0041] In one embodiment, as shown in the appendix Figure 1 Appendix Figure 4 As shown, the substrate 100 includes a plurality of word lines 105, the word lines 105 being perpendicular to the substrate. Figure 4 Extending in a planar direction, and formed by the interconnection of gate conductive layers 104 of multiple transistors 101, the lower surfaces of the first sub-section 111 and the third sub-section 113 are lower than the lower surface of the word line 105, i.e. Figure 4 As shown, the lower surface of the third sub-section 113 is lower than the lower surface of the gate conductive layer 104 of the transistor 101. The structure of the first sub-section 111 is similar, so as to facilitate the subsequent setting of the isolation lead-out structure 122 and prevent damage to the word line 105 of the transistor 101 when setting the isolation lead-out structure 122.

[0042] In one specific embodiment, see Appendix Figure 1 Along the direction of word line 105, the length of isolation structure 110 is greater than the length of word line 105. At this time, isolation structure 110 can extend to the edge or peripheral area of ​​substrate 100 (not shown in the figure). Isolation lead-out structure 122 can be located at the edge or peripheral area of ​​substrate 100, away from transistor 101, thereby preventing the setting of isolation lead-out structure 122 from damaging transistor 101, reducing electrical interference between transistor 101 and isolation lead-out structure 122, and improving the performance of semiconductor structure.

[0043] Optional, as shown in the appendix Figure 1 As shown, along the direction of extension of the word line 105, the length of the isolation structure 110 can be less than the length of the word line 105. The length of the isolation structure 110 does not affect the isolation effect of the isolation structure 110 in this embodiment. The length of the isolation structure 110 is less than the length of the word line 105, which can reduce the process difficulty of forming the isolation structure 110.

[0044] In one embodiment, as shown in the appendix Figure 12As shown, the substrate 100 includes a dummy transistor 108. The isolation lead structure 122 is connected to the conductive channel 102 of the dummy transistor 108 on both sides. The dummy transistor 108 can be located at the edge of the substrate 100, that is, the edge of the transistor array.

[0045] The aforementioned semiconductor structure includes multiple transistors 101, which can be categorized according to their function into storage transistors 101 and dummy transistors 108 for support. The conductive channel 102 of the dummy transistor 108 has no free charge available for storage. Therefore, an isolation lead structure 122 can be provided in the adjacent region of the dummy transistor 108, and the isolation lead structure 122 can be connected to the conductive channel 102 of the dummy transistor 108. This increases the space available for the isolation lead structure 122 and reduces the manufacturing complexity of its installation.

[0046] It is understandable that at this time, the first sub-part 111 or the third sub-part 113 of the isolation structure 110 is also located in the adjacent area of ​​the dummy transistor 108, so that the isolation lead-out structure 122 can be electrically connected to the isolation structure 110.

[0047] In some embodiments, the isolation lead-out structure 122 and the isolation structure 110 are made of the same conductive material, such as a metal, alloy, or other conductive material. Because the isolation lead-out structure 122 and the isolation structure 110 are made of the same conductive material, electrical interference caused by different conductive materials can be reduced when leading charges out of the semiconductor structure, thereby effectively improving the stability of the semiconductor structure.

[0048] like Figure 6 As shown, this embodiment also provides a method for fabricating a semiconductor structure, including: Step S101: Provide a substrate 100, the substrate 100 including a plurality of transistors 101 arranged in an array; In step S102, an isolation structure 110 is formed inside the substrate 100. The isolation structure 110 is located between any two adjacent rows of transistors 101. The isolation structure 110 includes a first sub-part 111, a second sub-part 112, and a third sub-part 113. The first sub-part 111 and the third sub-part 113 are located on both sides of the second sub-part 112. The lower surface of the first sub-part 111 and the lower surface of the third sub-part 113 are lower than the lower surface of the second sub-part 112.

[0049] The method for manufacturing the semiconductor structure provided in this disclosure will be further described in detail below with reference to specific embodiments.

[0050] First, see appendix Figure 7Step S101 is executed, providing a substrate 100, the substrate 100 including a plurality of transistors 101 arranged in an array, the plurality of transistors 101 being spaced apart in the row direction and column direction to form a transistor array.

[0051] In practice, as shown in the appendix Figure 8 As shown, transistor 101 can be any type of transistor 101 fabricated using known semiconductor manufacturing processes. Forming transistor 101 may include forming multiple gate conductive layers 104, multiple gate oxide layers 103, source 106, and drain 107 in or on substrate 100. In practice, interlayer dielectric (ILD) layers, interconnect wiring layers, capacitors, or inductors may also be formed on substrate 100.

[0052] The formation of the gate conductive layer 104 and the gate oxide layer 103 both involve etching, deposition and other processes. The formation of the source 106 and the drain 107 also involves ion implantation and other processes, which will not be elaborated here.

[0053] See appendix Figure 1 In step S102, an isolation structure 110 is formed inside the substrate 100. The isolation structure 110 is located between any two adjacent rows of transistors 101. The isolation structure 110 includes a first sub-section 111, a second sub-section 112, and a third sub-section 113. The first sub-section 111 and the third sub-section 113 are located on either side of the second sub-section 112. (See attached diagram.) Figure 2 As shown, the lower surface of the first sub-part 111 and the lower surface of the third sub-part 113 are lower than the lower surface of the second sub-part 112.

[0054] In one embodiment, as shown in the appendix Figure 8-10 As shown, the method for forming the isolation structure 110 includes: First, a first trench 132 is etched between any two adjacent rows of transistors 101; Next, a second trench 133 is formed by etching on both sides of the first trench 132, and the lower surface of the second trench 133 is deeper than the lower surface of the first trench 132. Finally, the first trench 132 and the second trench 133 are filled to form the isolation structure 110.

[0055] It should be noted that, as shown in the attached document... Figure 8 As shown, there is a certain depth difference between the second trench 133 and the first trench 132. This depth difference can be a depth difference that is naturally formed during the manufacturing process, or it can be formed through a specific process.

[0056] The following is in conjunction with the appendix Figure 8-10 The process of forming the isolation structure 110 through a specific process will be further explained in detail. Specifically, as follows... Figure 8 As shown in Figure (2), the method of etching to form the first trench 132 includes: forming a first mask layer (not shown in the figure) on a semiconductor substrate 100, wherein the first mask layer has a plurality of first mask openings distributed in parallel; using the first mask layer as a mask, etching the semiconductor substrate 100 along the first mask openings to a certain depth to form the first trench 132. The formation of the first trench 132 can be achieved by anisotropic etching process, such as plasma etching process.

[0057] As attached Figure 7 As shown, a second trench 133 is formed by etching on both sides of the first trench 132. The lower surface of the second trench 133 is deeper than the lower surface of the first trench 132, as shown in the attached figure. Figure 8 As shown.

[0058] In one embodiment, see Appendix Figure 9 The method for etching to form the second trench 133 includes: The two sides of the first trench 132 are etched to be flush with the lower surface of the first trench 132 to form a transition groove (not shown in the figure). Then, a second mask layer 142 is formed on the semiconductor substrate 100, the second mask layer 142 covering the remaining area except for the transition trench, including the first trench 132; Next, using the second mask layer 142 as a mask, the transition groove is etched along the second mask opening 142a to form the second trench 133, the lower surface of the second trench 133 being deeper than the lower surface of the first trench 132.

[0059] Here, the formation of the transition groove and the formation of the second trench 133 can be achieved using anisotropic etching processes, such as plasma etching.

[0060] In practice, the formation of the first trench 132 and the formation of the transition trench are carried out in the same process step. This not only simplifies the semiconductor manufacturing process, but also reduces the frequency of mask use, thereby reducing costs.

[0061] In another embodiment, the method of etching to form the second trench 133 includes: after forming the first trench 132, forming a third mask layer (not shown in the figure) on the semiconductor substrate 100, the third mask layer having a plurality of third mask openings distributed in parallel; using the third mask layer as a mask, etching the semiconductor substrate 100 along the third mask openings on both sides of the first trench 132 until the etching depth is deeper than the lower surface of the first trench 132 to form the second trench 133.

[0062] Finally, as attached Figure 10As shown, the first trench 132 and the second trench 133 are filled to form an isolation structure 110. The process for forming the isolation structure 110 may include chemical vapor deposition, sputtering, electroplating, or other suitable processes.

[0063] In practice, as shown in the appendix Figure 7 As shown, the substrate 100 includes a plurality of word lines 105, which are formed by connecting the gate conductive layers 104 of a plurality of transistors 101, as shown. Figure 8 As shown, in order to prevent damage to the gate conductive layer 104 of transistor 101 when the isolation lead-out structure 122 is set, the lower surfaces of the first sub-part 111 and the third sub-part 113 must be lower than the lower surface of word line 105. That is, when etching to form the second trench 133, it is necessary to ensure that the lower surface of the second trench 133 is lower than the lower surface of word line 105.

[0064] Additionally, see appendix. Figure 7 Along the direction of extension of the word line 105, the length of the isolation structure 110 can be greater than or less than the length of the word line 105. That is, when etching to form the first trench 132 and the second trench 133, along the direction of extension of the word line 105, the total length of the first trench 132 and the second trench 133 can be greater than or less than the length of the word line 105. The specific length can be adjusted according to the process parameters in actual operation, etc., and no specific restrictions are made here.

[0065] It should be noted that after forming the isolation structure 110, the method also includes forming an insulating layer 145, which can embed the isolation structure 110 within an insulating material, as shown in the attached figure. Figure 10 As shown. The material of the insulating layer 145 may include any one or any combination of two or more of silicon nitride (SiN), silicon oxide (SiO2), and aluminum oxide (Al2O3). In a specific embodiment, the material of the insulating layer 145 may be the same as the material of the substrate 100.

[0066] The insulating layer 145 can be formed using one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) processes. If necessary, surface planarization (CMP) can be performed after filling the insulating material to form the insulating layer 145, so that the upper surface of the filled insulating layer 145 is flush with the surface of the front side 100b of the substrate.

[0067] In one embodiment, as shown in the appendix Figure 11 As shown, after forming the isolation structure 110, the method further includes: First, the back side of the substrate 100a is etched to form a via 121. The first sub-part 111 (not shown in the figure, its structure is the same as the third sub-part 113) or the third sub-part 113 is exposed from the via 121. Forming the via 121 requires first forming a fourth mask layer (not shown in the figure) on the back side of the substrate 100a. The fourth mask layer has a plurality of fourth mask openings distributed in parallel. The projection of the fourth mask openings in the direction perpendicular to the substrate 100 should cover a portion of the first sub-part 111 or a portion of the third sub-part 113 of the isolation structure 110. Then, the semiconductor substrate 100 is etched along the fourth mask openings until the first sub-part 111 or the third sub-part 113 is exposed to form the via 121.

[0068] The via 121 formed by etching on the back side 100a of the substrate can be formed by one or more of plasma etching, reactive ion etching, laser ablation, wet etching, or photolithography.

[0069] Next, as attached Figure 4 As shown, the via 121 is filled to form an isolation lead-out structure 122. The isolation lead-out structure 122 is electrically connected to the first sub-part 111 (not shown in the figure, with the same structure as the third sub-part 113) or the third sub-part 113. The process for filling the via 121 can include, but is not limited to, one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). The filling material can include conductive materials, such as metallic materials, alloy materials, or other conductive materials. Specifically, for example, including but not limited to tungsten, copper, silicon, germanium, etc.

[0070] In another embodiment, as shown in the appendix Figure 12 As shown, the isolation lead-out structure 122 can also contact the conductive channel 102 of the adjacent dummy transistor 108. That is, when the via 121 is formed by etching, the projection of the fourth mask opening in the direction perpendicular to the substrate 100 covers a portion of the conductive channel 102. At this time, the via 121 formed by etching the substrate 100 with the fourth mask opening exposes a portion of the conductive channel 102. It should be noted that the transistor here refers to the dummy transistor 108, that is, the transistor not used for storing data. The purpose of this arrangement is twofold: firstly, it increases the space for the isolation lead-out structure 122, reducing the difficulty of the etching process and subsequent processes; secondly, it increases the contact area between the isolation structure 110 and the isolation lead-out structure 122, allowing the charge to be better led out of the semiconductor structure, thereby improving the performance of the semiconductor structure.

[0071] It should be noted that after the isolation lead-out structure 122 is formed, the excess insulating and conductive materials on the back side 100a of the substrate can be removed by a surface planarization process, such as chemical mechanical polishing (CMP).

[0072] certainly, Figures 8 to 12 The embodiments shown are merely one possible specific implementation method and do not constitute a limitation of this disclosure. Other process solutions that can be used to prepare this semiconductor structure can also be adopted.

[0073] In summary, the semiconductor structure and its fabrication method provided in this disclosure can effectively reduce the probability of electrical interference and hammer effect in the semiconductor structure, and improve the reliability of the semiconductor structure.

[0074] Furthermore, the semiconductor structure and its fabrication method provided in this disclosure can improve product yield while enhancing semiconductor chip performance.

[0075] It should be noted that the semiconductor device fabrication method provided in this disclosure can be applied to DRAM structures or other semiconductor devices, and is not limited thereto. The embodiments of the semiconductor device fabrication method provided in this disclosure and the embodiments of the semiconductor devices belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.

[0076] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a plurality of vertical gate transistors arranged in an array; An isolation structure located inside the substrate, the isolation structure being situated between any two adjacent rows of transistors; The isolation structure includes a first sub-part, a second sub-part, and a third sub-part. The first sub-part and the third sub-part are located on both sides of the second sub-part. The lower surfaces of the first sub-part and the third sub-part are closer to the back surface of the substrate than the lower surface of the second sub-part. The lower surfaces of the first sub-part and / or the third sub-part are closer to the back surface of the substrate than the lower surface of the gate conductive layer of the transistor. An isolation lead-out structure located on the back side of the substrate, the isolation lead-out structure being electrically connected to the first sub-part or the third sub-part, the isolation lead-out structure being located at least in the substrate.

2. The semiconductor structure according to claim 1, characterized in that, The substrate includes a plurality of word lines, and the lower surfaces of the first sub-part and the third sub-part are lower than the lower surfaces of the word lines.

3. The semiconductor structure according to claim 2, characterized in that, Along the direction in which the word line extends, the length of the isolation structure is greater than the length of the word line, or the length of the isolation structure is less than the length of the word line.

4. The semiconductor structure according to any one of claims 1-3, characterized in that, The material of the isolation structure includes conductive materials.

5. The semiconductor structure according to claim 4, characterized in that, Also includes: A via is located on the back side of the substrate, through which either the first sub-portion or the third sub-portion is exposed; the isolation lead-out structure is at least partially located within the via.

6. The semiconductor structure according to claim 5, characterized in that, The substrate includes dummy transistors, and the isolation lead structure is also connected to the conductive channels of the dummy transistors on adjacent sides.

7. The semiconductor structure according to claim 5, characterized in that, The isolation lead-out structure is grounded or connected to an external power supply.

8. The semiconductor structure according to claim 5, characterized in that, The isolation structure and the isolation lead-out structure are made of the same conductive material.

9. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a plurality of vertical gate transistors arranged in an array; An isolation structure is formed inside the substrate, the isolation structure being located between any two adjacent rows of transistors; wherein the isolation structure includes a first sub-section, a second sub-section, and a third sub-section, the first sub-section and the third sub-section being located on both sides of the second sub-section, wherein the lower surfaces of the first sub-section and the third sub-section are closer to the back surface of the substrate than the lower surface of the second sub-section, and the lower surfaces of the first sub-section and / or the third sub-section are closer to the back surface of the substrate than the lower surface of the gate conductive layer of the transistor; A through-hole is formed by etching the back side of the substrate, and the first sub-part or the third sub-part is exposed from the through-hole; The via is filled to form an isolation lead-out structure, which is electrically connected to the first sub-part or the third sub-part, and the isolation lead-out structure is located at least in the substrate.

Images