Semiconductor structure and method of manufacturing the same
By designing the word line structure and the active region contact surface in the semiconductor structure to be raised or recessed, the channel length is increased, the short-channel effect problem is solved, and the performance of the transistor is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2023-04-25
- Publication Date
- 2026-07-31
AI Technical Summary
Existing technologies cannot effectively reduce short-channel effects in semiconductor structures, especially the decrease in threshold voltage of transistors as channel length decreases and the drain-induced barrier reduction phenomenon.
In semiconductor structures, word line structures are designed with raised or recessed surfaces at their contact surfaces with the active region to increase the length of the channel region. This is achieved by forming trenches of a specific configuration within the substrate and etching them to form the word line structure, ensuring that the channel region has a raised or recessed configuration.
Without altering the original semiconductor structure design, the length of the channel region was increased, thereby reducing the short-channel effect and improving transistor performance.
Smart Images
Figure CN116322042B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuits, and more particularly to a semiconductor structure and its fabrication method. Background Technology
[0002] As the critical dimensions of semiconductors shrink, transistors exhibit short-channel effects, including a decrease in the threshold voltage of the transistor as the channel length decreases and a reduction in the drain-induced barrier.
[0003] Currently, the industry uses buried gates in semiconductor structures to increase the length of the channel region in order to reduce the short-channel effect; however, this improvement still cannot meet the requirements. Summary of the Invention
[0004] The technical problem to be solved by the embodiments of this disclosure is to provide a semiconductor structure and a method for fabricating the same, which can reduce the short-channel effect of the semiconductor structure.
[0005] To address the aforementioned problems, this disclosure provides a semiconductor structure comprising: a substrate, wherein an isolation structure and an active region defined by the isolation structure are disposed within the substrate; and a word line structure, at least partially disposed within the substrate, and passing through the active region and the isolation structure in a direction parallel to the surface of the substrate, wherein, in a direction perpendicular to the surface of the substrate, the surface of the word line structure in contact with the active region has a first protrusion toward the substrate or a first recess away from the substrate.
[0006] In some embodiments, the first protrusion or the first recess is symmetrically arranged with the center line of the word line structure as the axis of symmetry.
[0007] In some embodiments, the region where the active region contacts the word line structure is a channel region, and the length of the channel region is 10 to 200 nm.
[0008] In some embodiments, the first protrusion or the first recess extends in the direction in which the word line structure extends.
[0009] This disclosure also provides a method for fabricating a semiconductor structure, comprising: providing a substrate, wherein an isolation structure and an active region defined by the isolation structure are disposed within the substrate, and a first mask layer is disposed on the surface of the substrate; forming a first trench, the first trench penetrating the first mask layer and extending into the substrate in a direction perpendicular to the surface of the substrate, and passing through the active region and the isolation structure in a direction parallel to the surface of the substrate; forming a second recess facing the substrate or a second protrusion away from the substrate at the bottom of the first trench in a direction perpendicular to the surface of the substrate; removing the first mask layer and forming a word line structure in the first trench, wherein the surface of the word line structure in contact with the active region forms a first protrusion at the second recess, or the surface of the word line structure in contact with the active region forms a first recess at the second protrusion.
[0010] In some embodiments, the step of forming a second recess facing the substrate or a second protrusion away from the substrate at the bottom of the first trench includes: forming a second mask layer in the first trench, the second mask layer exposing a portion of the surface of the bottom of the first trench; using the second mask layer as a mask, etching the bottom of the first trench to form the second recess or the second protrusion; and removing the second mask layer.
[0011] In some embodiments, a second recess facing the substrate is formed at the bottom of the first trench. The step of forming a second mask layer in the first trench includes: forming a first initial mask layer, the first initial mask layer covering the surface of the first mask layer and the inner wall of the first trench, the first initial mask layer not filling the first trench, and the area between adjacent sidewalls of the first initial mask layer in a direction parallel to the surface of the substrate serving as the second trench; removing at least the bottom of the first initial mask layer of the second trench, the remaining first initial mask layer serving as the second mask layer, the second mask layer at least covering the sidewalls of the first trench and exposing a portion of the surface at the bottom of the first trench.
[0012] In some embodiments, in a direction perpendicular to the substrate surface, the height of the second mask layer is 1 / 3 to 1 / 2 of the depth of the first trench.
[0013] In some embodiments, a second protrusion facing away from the substrate is formed at the bottom of the first trench. The step of forming a second mask layer in the first trench includes: forming a second initial mask layer, the second initial mask layer covering the surface of the first mask layer and the inner wall of the first trench, the second initial mask layer not filling the first trench, and the area between adjacent sidewalls of the second initial mask layer in a direction parallel to the surface of the substrate serving as the second trench; forming a third mask layer in the second trench; using the third mask layer as a mask, removing the second initial mask layer, the second initial mask layer covered by the third mask layer remaining as the second mask layer, the second mask layer being located at the bottom of the first trench, and exposing portions of the bottom surface of the first trench on both sides.
[0014] In some embodiments, the step of forming a third mask layer in the second trench includes: the height of the third mask layer in a direction perpendicular to the substrate surface is 1 / 3 to 1 / 2 of the depth of the second trench.
[0015] In some embodiments, the sum of the thicknesses of the adjacent sidewalls of the first initial mask layer in the direction parallel to the substrate surface is 1 / 2 to 2 / 3 of the width of the first trench, or the sum of the thicknesses of the adjacent sidewalls of the second initial mask layer in the direction parallel to the substrate surface is 1 / 2 to 2 / 3 of the width of the first trench.
[0016] In some embodiments, the first initial mask layer or the second initial mask layer is formed using an atomic layer deposition process.
[0017] The semiconductor structure provided in this disclosure has a channel region in the area where the active region contacts the word line structure. Since the surface of the word line structure in contact with the active region has a first protrusion facing the substrate or a first depression away from the substrate, the channel region has a protruding configuration. Compared with semiconductor structures where the channel region has a smooth planar configuration or an arc-shaped configuration, the semiconductor structure provided in this disclosure increases the length of the channel region without changing the original design of the semiconductor structure, thereby reducing the short-channel effect of the semiconductor structure. Attached Figure Description
[0018] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of this disclosure, wherein (a) is a top view and (b) is a cross-sectional schematic diagram along line A-A1 in (a);
[0019] Figure 2 A schematic diagram of a semiconductor structure provided in an embodiment of this disclosure, wherein (a) is a top view and (b) is a cross-sectional schematic diagram along line A-A1 in (a);
[0020] Figure 3This is a schematic diagram of the steps in a method for fabricating a semiconductor structure according to an embodiment of this disclosure;
[0021] Figures 4A-4E This is a process flow diagram of a method for fabricating a semiconductor structure according to an embodiment of this disclosure;
[0022] Figure 5 This is a schematic diagram of the steps of a method for fabricating a semiconductor structure according to another embodiment of this disclosure;
[0023] Figures 6A to 6D This is a process flow diagram of a method for fabricating a semiconductor structure according to another embodiment of this disclosure. Detailed Implementation
[0024] The specific embodiments of the semiconductor structure and its fabrication method provided by the present invention will be described in detail below with reference to the accompanying drawings. The semiconductor structure includes, but is not limited to, Dynamic Random Access Memory (DRAM).
[0025] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of this disclosure, wherein (a) is a top view and (b) is a cross-sectional view along line A-A1 in (a). Please refer to [link / reference]. Figure 1 The semiconductor structure includes: a substrate 100, in which an isolation structure 110 and an active region 101 defined by the isolation structure 110 are disposed; a word line structure 120, at least partially disposed in the substrate 100, and passing through the active region 101 and the isolation structure 110 in a direction parallel to the surface of the substrate 100 (Y direction in the figure), and in a direction perpendicular to the surface of the substrate 100 (Z direction in the figure), the surface of the word line structure 120 in contact with the active region 101 has a first protrusion 120A facing the substrate 100.
[0026] In the semiconductor structure provided in this embodiment, the region where the active region 101 contacts the word line structure 120 is a channel region. Since the surface of the word line structure 120 in contact with the active region 101 has a first protrusion 120A facing the substrate 100, the channel region has a protruding configuration. Compared with semiconductor structures where the channel region has a smooth planar configuration or an arc-shaped configuration, the semiconductor structure provided in this embodiment increases the length H1 of the channel region without changing the original design of the semiconductor structure, thereby reducing the short-channel effect of the semiconductor structure.
[0027] In some embodiments, the length H1 of the channel region is 10–200 nm to further reduce the short-channel effect. In some embodiments, the first protrusion 120A is symmetrically arranged about the center line of the word line structure 120 as an axis of symmetry. Specifically, as Figure 1As shown, the first protrusion 120A is located at the center of the word line structure 120, and it is symmetrically arranged about the center line O of the word line structure 120 as the axis of symmetry. In some embodiments, the first protrusion 120A extends along the direction of extension of the word line structure 120 (the Y direction in the figure).
[0028] The substrate 100 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, an SOI substrate, or a GOI (Germanium-on-Insulator) substrate, etc. The substrate 100 may also be a substrate containing other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, etc. The substrate 100 may also be a stacked structure, such as a silicon / germanium-silicon stack, etc. Furthermore, the substrate 100 may be an ion-doped substrate, which may be P-type doped or N-type doped. Multiple peripheral devices, such as field-effect transistors, capacitors, inductors, and / or diodes, may also be formed in the substrate 100. In this embodiment, the substrate 100 is a silicon substrate, and it may also include other device structures, such as transistor structures, metal wiring structures, etc., but these are not shown because they are irrelevant to the embodiments of this disclosure.
[0029] The isolation structure 110 may be a shallow trench isolation (STI) structure, which includes, but is not limited to, an oxide isolation structure or a composite isolation structure of an oxide layer and a nitride. In this embodiment, the isolation structure 110 is an oxide isolation structure. In some embodiments, the isolation structure 110 is flush with the surface of the substrate 100 in a direction perpendicular to the surface of the substrate 100 (as shown in the Z direction). In some embodiments, the active region 101 is a P-type active region 101 or an N-type active region 101, serving as the well region of a transistor.
[0030] In some embodiments, two word line structures 120 are provided in the same active region 101, and the two word line structures 120 are spaced apart along the X direction, and each word line structure 120 extends along the Y direction.
[0031] In some embodiments, the word line structure 120 includes a word line dielectric layer 121, a conductive layer 122 covering the word line dielectric layer 121 and filling the first trench 410, and an insulating capping layer 123 covering the conductive layer 122. The word line dielectric layer 121 covers the substrate and includes, but is not limited to, a silicon oxide layer or a high-k dielectric layer, the conductive layer 122 includes, but is not limited to, a polysilicon layer or a tungsten metal layer, and the insulating capping layer 123 includes, but is not limited to, a silicon nitride layer.
[0032] In some embodiments, a portion of the word line structure 120 is disposed within the substrate 100, and another portion is disposed on the surface of the substrate 100. In other embodiments, the word line structure 120 may be entirely disposed within the substrate 100. For example, in some embodiments, the word line dielectric layer 121 and the conductive layer 122 are entirely located within the substrate 100, and a portion of the insulating capping layer 123 is located within the substrate 100, while another portion is located on the surface of the substrate 100. In other embodiments, the word line dielectric layer 121 is entirely located within the substrate 100, a portion of the conductive layer 122 is located within the substrate 100, while another portion is located on the surface of the substrate 100, and the insulating capping layer 123 is entirely located on the surface of the substrate 100.
[0033] Another embodiment of this disclosure provides a semiconductor structure, which differs from the previous embodiment in that, in this embodiment, the surface of the word line structure 120 that contacts the active region 101 has a first recess 120B that faces away from the substrate 100, that is, the first recess 120B protrudes toward the word line structure. (See also...) Figure 2 In this diagram, (a) is a top view and (b) is a cross-sectional view along line A-A1 in (a).
[0034] In this semiconductor structure, the area where the active region 101 contacts the word line structure 120 is the channel region. Since the surface of the word line structure 120 in contact with the active region 101 has a first recess 120B facing the substrate 100, the channel region has a convex configuration. Compared with semiconductor structures where the channel region has a smooth planar configuration or an arc-shaped configuration, the semiconductor structure provided in this embodiment increases the length H1 of the channel region without changing the original design of the semiconductor structure, thereby reducing the short-channel effect of the semiconductor structure.
[0035] In some embodiments, the length H1 of the channel region is 10–200 nm to further reduce the short-channel effect. In some embodiments, the first recess 120B is symmetrically arranged about the center line of the word line structure 120 as the axis of symmetry. Specifically, as Figure 2 As shown, the first recess 120B is located at the center of the word line structure 120, and it is symmetrically arranged about the center line O of the word line structure 120 as the axis of symmetry. In some embodiments, the first recess 120B extends along the direction of extension of the word line structure 120 (the Y direction in the figure).
[0036] This disclosure also provides a method for fabricating the above-described semiconductor structure in one embodiment. Please refer to [link to relevant documentation]. Figure 3This is a schematic diagram of the steps of a semiconductor structure fabrication method provided in an embodiment of the present disclosure. The fabrication method includes the following steps: Step S30, providing a substrate 100, wherein an isolation structure 110 and an active region 101 defined by the isolation structure 110 are disposed in the substrate 100, and a first mask layer 400 is disposed on the surface of the substrate 100; Step S31, forming a first trench 410, wherein the first trench 410 penetrates the first mask layer 400 and extends into the substrate 100 in a direction perpendicular to the surface of the substrate 100, and in a direction parallel to the surface of the substrate 100, the first trench 410 passes through the active region 101 and the isolation structure 110; Step S32, forming a second recess 420 facing the substrate 100 at the bottom of the first trench 410 in a direction perpendicular to the surface of the substrate 100; Step S33, removing the first mask layer 400, and forming a word line structure 120 in the first trench 410, wherein a first protrusion 120A is formed at the second recess 420 on the surface of the word line structure 120 that contacts the active region 101.
[0037] The semiconductor structure fabrication method provided in this embodiment has a first protrusion 120A facing the substrate 100 on the surface of the word line structure 120 that contacts the active region 101. The region where the active region 101 contacts the word line structure 120 is a channel region. The channel region is not a smooth arc-shaped configuration, but a configuration with a protrusion on the basis of an arc-shaped configuration. Compared with a semiconductor structure with a smooth arc-shaped channel region, the semiconductor structure fabrication method provided in this embodiment can increase the length H1 of the channel region without changing the original design of the semiconductor structure, thereby reducing the short-channel effect of the semiconductor structure.
[0038] Figures 4A-4E This is a process flow diagram of a method for fabricating a semiconductor structure according to an embodiment of this disclosure.
[0039] Please see Figure 4A Wherein, (a) is a top view, and (b) is a cross-sectional view along line A-A1 in (a). In step S30, a substrate 100 is provided, wherein an isolation structure 110 and an active region 101 defined by the isolation structure 110 are disposed within the substrate 100, and a first mask layer 400 is disposed on the surface of the substrate 100. Figure 4A Only one active region 101 is schematically shown in the diagram. It can be understood that the semiconductor structure includes multiple active regions 101, which are independent of each other and isolated by the isolation structure 110. Figure 4A In Figure (a), the first mask layer is not shown.
[0040] In some embodiments, the method of forming an isolation structure 110 within a substrate 100 includes: forming shallow trenches within the substrate 100, the shallow trenches dividing the substrate 100 into a plurality of independent regions; filling the shallow trenches with an insulating material to form the isolation structure 110, wherein the regions of the substrate 100 between the isolation structures 110 are active regions 101. In some embodiments, after forming the isolation structure 110, the method further includes ion doping the active regions 101 to form a P-type active region 101 or an N-type active region 101, as well as serving as the well region of a subsequently formed transistor.
[0041] In some embodiments, the surface of the isolation structure 110 is flush with the surface of the substrate 100 in a direction perpendicular to the surface of the substrate 100 (as shown in the Z direction).
[0042] The first mask layer 400 covers the surface of the substrate 100, that is, the first mask layer 400 covers the surface of the active region 101 and the isolation structure 110. The first mask layer 400 may be a spin-coated carbon organic mask (SOC) or a spin-coated hard mask (SOH). In some embodiments, the first mask layer 400 may be formed by spin coating.
[0043] Please see Figure 4B In step S31, a first trench 410 is formed. The first trench 410 extends through the first mask layer 400 and into the substrate 100 in a direction perpendicular to the surface of the substrate 100 (as shown by the Z direction in the figure). In a direction parallel to the surface of the substrate 100 (as shown by the Y direction in the figure), the first trench 410 passes through the active region 101 and the isolation structure 110. In this step, the sidewalls of the first trench 410 expose the first mask layer 400 and the active region 101. (a) is a top view, and (b) is a cross-sectional view along line A-A1 in (a).
[0044] In some embodiments, the method of forming the first trench 410 includes: forming a hard mask layer and a photoresist layer on the surface of the first mask layer 400, the hard mask layer including an anti-reflective coating; patterning the photoresist layer and etching the hard mask layer with the photoresist layer as a shield to form a patterned hard mask layer; etching the first mask layer 400 with the hard mask layer as a shield to form a patterned first mask layer 400; etching the isolation structure 110 and the active region 101 with the hard mask layer and the first mask layer 400 as shields to form the first trench 410; and removing the remaining hard mask layer after forming the first trench 410.
[0045] In some embodiments, two first trenches 410 are formed in the same active region 101, and the two first trenches 410 are spaced apart along a direction parallel to the surface of the substrate 100 (X direction in the figure).
[0046] Please see Figure 4EIn the diagram, (a) is a top view and (b) is a cross-sectional view along line A-A1 in (a). In step S32, a second recess 420 is formed at the bottom of the first trench 410 facing the substrate 100 in a direction perpendicular to the surface of the substrate 100 (as shown in the Z direction). At the bottom of the first trench 410, the second recess 420 extends along the Y direction.
[0047] This disclosure also provides a method for forming a second recess 420. The method includes:
[0048] A second mask layer 430 is formed within the first trench 410, the second mask layer 430 exposing a portion of the surface at the bottom of the first trench 410. Specifically, the step of forming the second mask layer 430 within the first trench 410 includes:
[0049] Please see Figure 4C In the figure, (a) is a top view and (b) is a cross-sectional view along line A-A1 in (a), forming a first initial mask layer 440. The first initial mask layer 440 covers the surface of the first mask layer 400 and the inner wall of the first trench 410. The first initial mask layer 440 does not fill the first trench 410, and the area between the adjacent sidewalls of the first initial mask layer 440 in the direction parallel to the surface of the substrate 100 (X direction in the figure) is used as the second trench 441.
[0050] The first initial mask layer 440 may be an oxide layer, such as a silicon oxide layer, which has a large etching selectivity ratio with the first mask layer 400 to facilitate selective removal of the first initial mask layer 440 in subsequent process steps. In some embodiments, the first initial mask layer 440 may be formed using an atomic layer deposition process to provide a first initial mask layer 440 with good density.
[0051] In some embodiments, the sum of the thicknesses h1 and h2 of the adjacent sidewalls of the first initial mask layer 440 in the direction parallel to the surface of the substrate 100 (as shown in the X direction) is 1 / 2 to 2 / 3 of the width W1 of the first trench 410, that is, the width of the second trench 441 is 1 / 3 to 1 / 2 of the width W1 of the first trench 410, so as to further control the width of the subsequently formed second recess 420.
[0052] Please see Figure 4D In the figure, (a) is a top view and (b) is a cross-sectional view along line A-A1 in (a). At least the first initial mask layer 440 at the bottom of the second trench 441 is removed, and the remaining first initial mask layer 440 serves as the second mask layer 430. The second mask layer 430 at least covers the sidewall of the first trench 410 and exposes a portion of the bottom surface of the first trench 410.
[0053] In this step, the first initial mask layer 440 can be etched using a dry etching process. The first initial mask layer 440 at the bottom of the first trench 410 is removed to expose part of the surface at the bottom of the first trench 410, while the first initial mask layer 440 on the sidewall of the first trench 410 is retained.
[0054] In this step, the first initial mask layer 440 on the surface of the first mask layer 400 may be completely or partially removed. In some embodiments, the first initial mask layer 440 on the surface of the first mask layer 400 is completely removed, and the first initial mask layer 440 located on the sidewall of the first trench 410 is also over-etched, such that in the direction perpendicular to the surface of the substrate 100 (Z direction in the figure), the height H2 of the second mask layer 430 is 1 / 3 to 1 / 2 of the depth H3 of the first trench 410, so as to control the depth of the second recess 420 formed in subsequent process steps.
[0055] It is understood that in some embodiments, the first mask layer 400 is also partially etched during the over-etching of the first initial mask layer 440. Therefore, the depth H3 of the first trench 410 refers to the depth of the first trench 410 after the step of removing the first initial mask layer 440, and not the depth of the first trench 410 after the step of forming the first initial mask layer 440.
[0056] Please see Figure 4E After forming the second mask layer 430, the bottom of the first trench 410 is etched using the second mask layer 430 as a mask to form the second recess 420.
[0057] In some embodiments, since the second mask layer 430 is formed by atomic layer deposition and has good density, in this step, when the etching material etches the bottom of the first trench 410, it can reduce the etching rate of the etching material on the second mask layer 430, so that the second mask layer 430 can have a good shielding effect.
[0058] After this step, the second mask layer 430 is removed.
[0059] Please see Figure 1 In step S33, the first mask layer 400 is removed and a word line structure 120 is formed in the first trench 410. The surface of the word line structure 120 that contacts the active region 101 forms a first protrusion 120A at the second recess 420.
[0060] In some embodiments, the first mask layer 400 may be removed by processes such as ashing. After removing the first mask layer 400 and before forming the word line structure 120, a cleaning step is also included to remove particulate residues and prevent residual substances from affecting the performance of the word line structure 120.
[0061] The word line structure 120 includes a word line dielectric layer 121 covering the sidewalls of the first trench 410, a conductive layer 122 covering the word line dielectric layer 121 and filling the first trench 410, and an insulating capping layer 123 covering the conductive layer 122. The word line dielectric layer 121 includes, but is not limited to, a silicon oxide layer or a high-k dielectric layer, the conductive layer 122 includes, but is not limited to, a polysilicon layer or a tungsten metal layer, and the insulating capping layer 123 includes, but is not limited to, a silicon nitride layer.
[0062] In some embodiments, the method of forming the word line structure 120 includes: forming a word line dielectric material layer covering the surface of the isolation structure 110, the surface of the active region 101 and the sidewall of the first trench 410, a conductive material layer covering the sidewall of the word line dielectric material layer and filling the first trench 410, and an insulating material layer covering the conductive material layer; and patterning the insulating material layer, the conductive material layer and the word line dielectric material layer to form the word line structure 120.
[0063] In the semiconductor structure formed in this step, the surface of the word line structure 120 that contacts the active region 101 has a first protrusion 120A, which makes the channel region have a protruding configuration on the basis of the arc configuration, increasing the length of the channel region and reducing the short channel effect of the semiconductor structure.
[0064] Another embodiment of this disclosure also provides a method for fabricating the above-described semiconductor structure. Please refer to [link / reference]. Figure 5 The fabrication method includes the following steps: Step S50, providing a substrate 100, wherein an isolation structure 110 and an active region 101 defined by the isolation structure 110 are disposed in the substrate 100, and a first mask layer 400 is disposed on the surface of the substrate 100; Step S51, forming a first trench 410, wherein the first trench 410 penetrates the first mask layer 400 and extends into the substrate 100 in a direction perpendicular to the surface of the substrate 100, and in a direction parallel to the surface of the substrate 100, the first trench 410 passes through the active region 101 and the isolation structure 110; Step S52, forming a second protrusion 600 away from the substrate 100 at the bottom of the first trench 410 in a direction perpendicular to the surface of the substrate 100; Step S53, removing the first mask layer 400, and forming a word line structure 120 in the first trench 410, wherein a first recess 120B is formed at the second protrusion 600 on the surface of the word line structure 120 that contacts the active region 101.
[0065] The semiconductor structure fabrication method provided in this embodiment has a second protrusion 600 away from the substrate 100 on the surface of the word line structure 120 that contacts the active region 101. The area where the active region 101 contacts the word line structure 120 is a channel region, which is not a smooth arc-shaped configuration, but a protrusion on the basis of an arc-shaped configuration. Compared with a semiconductor structure with a smooth arc-shaped channel region, the semiconductor structure fabrication method provided in this embodiment can increase the length of the channel region without changing the original design of the semiconductor structure, thereby reducing the short-channel effect of the semiconductor structure.
[0066] Figures 6A to 6D This is a process flow diagram of a method for fabricating a semiconductor structure according to another embodiment of this disclosure.
[0067] Step S50 and Figure 3 Step S30 is the same as step S51. Figure 3 The steps in step S31 are the same and will not be repeated here.
[0068] Please see Figure 6D In the diagram, (a) is a top view and (b) is a cross-sectional view along line A-A1 in (a). In step S52, a second protrusion 600 is formed at the bottom of the first trench 410 in a direction perpendicular to the surface of the substrate 100 (as shown in the Z direction). The second protrusion 600 extends along the Y direction at the bottom of the first trench 410.
[0069] This disclosure also provides a method for forming a second protrusion 600. The method includes:
[0070] A second mask layer 610 is formed within the first trench 410, the second mask layer 610 exposing a portion of the surface at the bottom of the first trench 410. Specifically, the step of forming the second mask layer 610 within the first trench 410 includes:
[0071] Please see Figure 6A In the diagram, (a) is a top view and (b) is a cross-sectional view along line A-A1 in (a), forming a second initial mask layer 620. The second initial mask layer 620 covers the surface of the first mask layer 400 and the inner wall of the first trench 410. The second initial mask layer 620 does not fill the first trench 410, and the area between adjacent sidewalls of the second initial mask layer 620 in the direction parallel to the surface of the substrate 100 is used as the second trench 621.
[0072] In some embodiments, the method for forming the second initial mask layer 620 is the same as the method for forming the first initial mask layer 440, and the second initial mask layer 620 has the same structure as the first initial mask layer 440, which will not be described again.
[0073] Please see Figure 6B In this diagram, (a) is a top view and (b) is a cross-sectional view along line A-A1 in (a), where a third mask layer 630 is formed in the second trench 621.
[0074] The third mask layer 630 has a higher etching selectivity than the second initial mask layer 620. In some embodiments, the third mask layer 630 includes, but is not limited to, spin-coated organic carbon (SOC).
[0075] In this step, the method of forming the third mask layer 630 includes: forming a third mask material layer, the third mask material layer covering the surface of the second initial mask layer 620 and filling the second trench 621; removing the third mask material layer from the surface of the second initial mask layer 620, and retaining the third mask material layer in the second trench 621 for use as the third mask layer 630.
[0076] In some embodiments, when removing the third mask material layer, the third mask material layer is over-etched so that the third mask material layer in the second trench 621 is also partially removed, in order to further ensure that the surface of the second initial mask layer 620 is completely exposed and that the sidewalls of the second initial mask layer 620 located in the second trench 621 are partially exposed, that is, to increase the exposed area of the second initial mask layer 620, so as to further ensure that the second initial mask layer 620 covering the sidewalls of the first trench 410 can be completely removed in the subsequent step of removing the second initial mask layer 620.
[0077] For example, in some embodiments, after over-etching the third mask material layer, in the direction perpendicular to the surface of the substrate 100 (as shown in the Z direction), the height of the remaining third mask material layer is 1 / 3 to 1 / 2 of the depth of the second trench 621, that is, the height H4 of the third mask layer 630 is 1 / 3 to 1 / 2 of the depth H5 of the second trench 621, and a portion of the second initial mask layer 620 located on the sidewall of the second trench 621 is exposed.
[0078] Please see Figure 6C In Figure (a), (a) is a top view, and (b) is a cross-sectional view along line A-A1 in (a). Using the third mask layer 630 as a mask, the second initial mask layer 620 is removed. The second initial mask layer 620 covered by the third mask layer 630 is retained as the second mask layer 610. The second mask layer 610 is located at the bottom of the first trench 410, and its sides expose a portion of the bottom surface of the first trench 410. The third mask layer 630 is not shown in Figure (a).
[0079] In this step, a second mask layer 610 is formed in the middle region of the bottom of the first trench 410, exposing a portion of the bottom surface of the first trench 410 on both sides. The second mask layer 610 extends along the Y direction at the bottom of the first trench 410.
[0080] Please see Figure 6D After forming the second mask layer 610, the bottom of the first trench 410 is etched using the second mask layer 610 as a mask to form the second protrusion 600. In some embodiments, since the second mask layer 610 is formed by atomic layer deposition, it has good density. Therefore, in this step, when the etching material etches the bottom of the first trench 410, it can reduce the etching rate of the etching material on the second mask layer 610, so that the second mask layer 610 can have a good shielding effect.
[0081] After this step, the second mask layer 610 is removed. If there is still a residual third mask layer 630 on the second mask layer 610, the third mask layer 630 is removed simultaneously during the step of removing the second mask layer 610.
[0082] Please see Figure 2 In step S53, the first mask layer 400 is removed, and a word line structure 120 is formed in the first trench 410. The surface of the word line structure 120 that contacts the active region 101 forms a first recess 120B at the second protrusion 600. In some embodiments, the method for forming the word line structure 120 is the same as the method for forming the word line structure 120 in step S33, and will not be described again.
[0083] In the semiconductor structure formed in this step, the surface of the word line structure 120 that contacts the active region 101 has a first recess 120B, which makes the channel region have a convex configuration on the basis of the arc configuration, increasing the length of the channel region and reducing the short channel effect of the semiconductor structure.
[0084] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A semiconductor structure, characterized by, include: A substrate, wherein an isolation structure and an active region defined by the isolation structure are disposed therein; A word line structure is at least partially disposed within the substrate and passes through the active region and the isolation structure in a direction parallel to the surface of the substrate. In a direction perpendicular to the surface of the substrate, the surface of the word line structure that contacts the active region has a first protrusion toward the substrate or a first recess away from the substrate. The first protrusion or the first recess extends along the direction of the word line structure and is symmetrically arranged with the center line of the word line structure as the axis of symmetry.
2. The semiconductor structure according to claim 1, characterized in that, The region where the active region contacts the word line structure is the channel region, and the length of the channel region is 10~200nm.
3. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, wherein an isolation structure and an active region defined by the isolation structure are disposed therein, and a first mask layer is disposed on the surface of the substrate; A first trench is formed, the first trench penetrates the first mask layer and extends into the substrate in a direction perpendicular to the substrate surface, and the first trench passes through the active region and the isolation structure in a direction parallel to the substrate surface; In a direction perpendicular to the substrate surface, a second recess is formed at the bottom of the first trench, either facing the substrate or a second protrusion away from the substrate; Remove the first mask layer and form a word line structure in the first trench. The surface of the word line structure that contacts the active region forms a first protrusion at the second depression, or the surface of the word line structure that contacts the active region forms a first depression at the second protrusion. The step of forming a second recess facing the substrate or a second protrusion away from the substrate at the bottom of the first trench includes: A second mask layer is formed within the first trench, the second mask layer exposing a portion of the surface at the bottom of the first trench; Using the second mask layer as a mask, the bottom of the first trench is etched to form the second depression or the second protrusion; wherein the first protrusion or the first depression extends along the direction of the word line structure and is symmetrically arranged with the center line of the word line structure as the axis of symmetry; Remove the second mask layer.
4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The step of forming a second mask layer within the first trench, wherein a second recess is formed at the bottom of the first trench facing the substrate, includes: A first initial mask layer is formed, which covers the surface of the first mask layer and the inner wall of the first trench. The first initial mask layer does not fill the first trench, and the area between adjacent sidewalls of the first initial mask layer in the direction parallel to the substrate surface is used as a second trench. At least the first initial mask layer at the bottom of the second trench is removed, and the remaining first initial mask layer serves as the second mask layer. The second mask layer at least covers the sidewalls of the first trench and exposes a portion of the surface at the bottom of the first trench.
5. The method for preparing a semiconductor structure according to claim 4, characterized in that, In the direction perpendicular to the substrate surface, the height of the second mask layer is 1 / 3 to 1 / 2 of the depth of the first trench.
6. The method for preparing a semiconductor structure according to claim 3, characterized in that, The step of forming a second protrusion away from the substrate at the bottom of the first trench, and forming a second mask layer within the first trench, includes: A second initial mask layer is formed, which covers the surface of the first mask layer and the inner wall of the first trench. The second initial mask layer does not fill the first trench, and the area between adjacent sidewalls of the second initial mask layer in the direction parallel to the substrate surface is the second trench. A third mask layer is formed within the second trench; Using the third mask layer as a mask, the second initial mask layer is removed, and the second initial mask layer covered by the third mask layer is retained as the second mask layer. The second mask layer is located at the bottom of the first trench, and its sides expose a portion of the bottom surface of the first trench.
7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The step of forming a third mask layer in the second trench includes: in a direction perpendicular to the substrate surface, the height of the third mask layer is 1 / 3 to 1 / 2 of the depth of the second trench.
8. The method for preparing a semiconductor structure according to claim 5, characterized in that, The sum of the thicknesses of the adjacent sidewalls of the first initial mask layer in the direction parallel to the substrate surface is 1 / 2 to 2 / 3 of the width of the first trench.
9. The method for preparing a semiconductor structure according to claim 6 or 7, characterized in that, The sum of the thicknesses of the adjacent sidewalls of the second initial mask layer in the direction parallel to the substrate surface is 1 / 2 to 2 / 3 of the width of the first trench.