Semiconductor memory device and method of manufacturing the same

Abstract

This disclosure relates to a semiconductor memory device and a method for manufacturing the same. The semiconductor memory device includes: a gate stack comprising an interlayer insulating layer and a conductive pattern alternately stacked on a substrate in a vertical direction; a channel structure penetrating at least a portion of the gate stack and having a first end protruding upward above the gate stack; a memory layer surrounding the sidewalls of the channel structure; and a source layer formed on the gate stack. The channel structure includes: a core insulating layer formed in a central region of the channel structure and extending in a vertical direction; and a channel layer surrounding the sidewalls of the core insulating layer and formed to extend vertically above the core insulating layer and the memory layer.

Description

Technical Field

[0001] Various embodiments of this disclosure relate to electronic devices, and more specifically, to a semiconductor memory device having a vertical channel structure and a method of manufacturing the semiconductor memory device. Background Technology

[0002] Recently, the paradigm of the computing environment has shifted to ubiquitous computing, enabling computer systems to be used anytime, anywhere. Consequently, the use of portable electronic devices such as mobile phones, digital cameras, and laptops has increased rapidly. These portable electronic devices typically use memory systems employing semiconductor memory devices; in other words, they use data storage devices. Data storage devices serve as either the main memory or auxiliary memory devices in portable electronic devices.

[0003] The advantages of data storage devices using semiconductor memory devices are that they offer excellent stability and durability, high information access speed, and low power consumption due to the absence of mechanical driving components. Examples of memory systems with these advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces, solid-state drives (SSDs), and so on.

[0004] Semiconductor memory devices are broadly classified into volatile memory devices or non-volatile memory devices.

[0005] Non-volatile memory devices have relatively low write and read speeds, but retain the data stored within them even when power is interrupted. Therefore, non-volatile memory devices are used to store data that must be retained regardless of power supply. Representative examples of memory used in non-volatile memory devices include read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Flash memory is classified as either NOR or NAND. Summary of the Invention

[0006] Various embodiments of this disclosure relate to a semiconductor memory device and a method of manufacturing the semiconductor memory device, which, in certain embodiments, can more easily perform a process for interconnecting a channel layer having a vertical channel structure with a source layer.

[0007] An embodiment of the present disclosure provides a semiconductor memory device that may include: a gate stack comprising an interlayer insulating layer and a conductive pattern alternately stacked on a substrate in a vertical direction; a channel structure penetrating at least a portion of the gate stack and having a first end protruding upward above the gate stack; a memory layer surrounding sidewalls of the channel structure; and a source layer formed on the gate stack. The channel structure may include: a core insulating layer formed in a central region of the channel structure and extending in a vertical direction; and a channel layer surrounding sidewalls of the core insulating layer and formed to extend vertically above the core insulating layer and the memory layer.

[0008] An embodiment of the present disclosure provides a semiconductor memory device that may include: a gate stack comprising an interlayer insulating layer and a conductive pattern alternately stacked on a substrate in a vertical direction; a sacrificial substrate formed on the gate stack; a channel structure penetrating at least a portion of the gate stack and the sacrificial substrate, the channel structure having a first end protruding upward from the sacrificial substrate; a memory layer surrounding the sidewalls of the channel structure; and a source layer formed on the gate stack. The protruding first end of the channel structure may include an opening.

[0009] According to this disclosure, a method for manufacturing a semiconductor memory device is disclosed. The method may include the following steps: forming a memory cell array on a first substrate, such that the memory cell array includes a gate stack having interlayer insulating layers and conductive patterns alternately stacked in a vertical direction, a core insulating layer penetrating at least a portion of the gate stack and having a first end extending into the first substrate, a channel layer surrounding the sidewalls of the core insulating layer and the first end, and a memory layer extending from a region between the channel layer and the gate stack to a region between the end of the channel layer and the first substrate; performing a first etching process to etch the first substrate, the memory layer, and the channel layer to expose the first end of the core insulating layer; performing a second etching process to etch the exposed core insulating layer to a specific thickness, and then causing the channel layer to protrude such that the height of the upper portion of the channel layer is greater than the height of the upper portion of the core insulating layer; and forming a first source layer to surround the protruding channel layer. Attached Figure Description

[0010] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figure 2 It is used to describe Figure 1 The circuit diagram of the memory cell array.

[0012] Figure 3 This is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0013] Figure 4 It is used to describe Figure 1 A cross-sectional view of the memory cell array.

[0014] Figures 5A to 5F , Figure 6 , Figure 7 as well as Figures 8A to 8D This is a cross-sectional view used to describe a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0015] Figure 9 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0016] Figure 10 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0017] The specific structural or functional descriptions of embodiments of this disclosure incorporated herein are illustrative of implementations based on the concepts of this disclosure. Implementations based on the concepts of this disclosure may be practiced in various forms and should not be construed as limited to the implementations described herein.

[0018] Various embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings, which illustrate embodiments of the present disclosure so that those skilled in the art can readily practice the technical spirit of the present disclosure.

[0019] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0020] Reference Figure 1 The semiconductor memory device 10 includes peripheral circuitry PC and memory cell array 20.

[0021] The peripheral circuit PC can control programming operations that store data in the memory cell array 20, reading operations that output data stored in the memory cell array 20, and erasing operations that erase data stored in the memory cell array 20.

[0022] In an implementation, the peripheral circuit PC may include a voltage generator 31, a line decoder 33, a control circuit 35, and a page buffer group 37.

[0023] The memory cell array 20 may include multiple memory blocks. The memory cell array 20 can be connected to the row decoder 33 via word line WL and to the page buffer group 37 via bit line BL.

[0024] Control circuit 35 can control voltage generator 31, line decoder 33 and page buffer group 37 in response to command CMD and address ADD.

[0025] The voltage generator 31 can generate various operating voltages for programming, reading and erasing operations under the control of the control circuit 35, such as erasing voltage, grounding voltage, programming voltage, verification voltage, pass voltage and read voltage.

[0026] The line decoder 33 can select a memory block under the control of the control circuit 35. The line decoder 33 can apply an operating voltage to the word line WL connected to the selected memory block.

[0027] Page buffer group 37 can be connected to memory cell array 20 via bit line BL. During programming operations, page buffer group 37 can temporarily store data received from input / output circuitry (not shown) under the control of control circuitry 35. During read or verification operations, page buffer group 37 can sense the voltage or current of bit line BL under the control of control circuitry 35. Page buffer group 37 can select bit line BL under the control of control circuitry 35.

[0028] Structurally, the memory cell array 20 may overlap with a portion of the peripheral circuit PC.

[0029] Figure 2 It is used to describe Figure 1 The circuit diagram of the memory cell array.

[0030] Reference Figure 2 The memory cell array 20 may include multiple cell strings CS1 and CS2 connected between the source line SL and multiple bit lines BL. The multiple cell strings CS1 and CS2 may be connected together to multiple word lines WL1 to WLn.

[0031] Each of the multiple cell strings CS1 and CS2 may include at least one source selection transistor SST connected to the source layer SL, at least one drain selection transistor DST connected to the corresponding bit line BL, and multiple memory cells MC1 to MCn connected in series between the source selection transistor SST and the drain selection transistor DST.

[0032] The gates of multiple memory cells MC1 to MCn can be connected to multiple word lines WL1 to WLn, which are stacked and spaced apart from each other. The multiple word lines WL1 to WLn can be arranged between the source select line SSL and two or more drain select lines DSL1 and DSL2. The two or more drain select lines DSL1 and DSL2 can be spaced apart from each other at the same level.

[0033] The gate of the source-select transistor SST can be connected to the source-select line SSL. The gate of the drain-select transistor DST can be connected to the drain-select line corresponding to the gate of the drain-select transistor DST.

[0034] The source layer SL can be connected to the source of the source select transistor SST. The drain of the drain select transistor DST can be connected to the bit line corresponding to the drain of the drain select transistor DST.

[0035] Multiple unit strings CS1 and CS2 can be divided into string groups that are respectively connected to two or more drain select lines DSL1 and DSL2. Unit strings connected to the same word line and the same bit line can be independently controlled by different drain select lines. In addition, unit strings connected to the same drain select line can be independently controlled by different bit lines.

[0036] In this implementation, two or more drain select lines DSL1 and DSL2 may include a first drain select line DSL1 and a second drain select line DSL2. Multiple unit strings CS1 and CS2 may include a first unit string CS1 connected to a first string group of the first drain select line DSL1 and a second unit string CS2 connected to a second string group of the second drain select line DSL2.

[0037] Figure 3 This is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0038] Reference Figure 3 The semiconductor memory device 10 may include peripheral circuitry PC disposed on a substrate SUB and a gate stack GST overlapping the peripheral circuitry PC.

[0039] Each gate stack (GST) may include a source select line SSL, multiple word lines WL1 to WLn, and two or more drain select lines DSL1 and DSL2 that are separated from each other at the same height by a separation structure DSM.

[0040] The source select line SSL and multiple word lines WL1 to WLn can extend in a first direction X and a second direction Y, and can be formed in a planar shape parallel to each other on the upper surface of the substrate SUB. The first direction X can be the X-axis direction in the XYZ coordinate system, and the second direction Y can be the Y-axis direction in the XYZ coordinate system.

[0041] Multiple word lines WL1 to WLn can be stacked on a third direction Z to be spaced apart from each other. The third direction Z can be the Z-axis direction in the XYZ coordinate system. Multiple word lines WL1 to WLn can be arranged between two or more drain select lines DSL1 and DSL2 and source select line SSL.

[0042] The gate stack (GST) can be separated from each other through slit SI. The separated structure (DSM) can be formed to be shorter than slit SI in the third direction Z and can overlap with multiple word lines WL1 to WLn.

[0043] Each of the separation structure DSM and slit SI can extend in a linear, sawtooth, or wavy shape. The width of each of the separation structure DSM and slit SI can vary depending on the design specifications.

[0044] According to the implementation method, the source selection line SSL can be arranged closer to the peripheral circuit PC than two or more drain selection lines DSL1 and DSL2.

[0045] The semiconductor memory device 10 may include a source line SL disposed between a gate stack GST and a peripheral circuit PC, and multiple bit lines BL that are spaced further away from the peripheral circuit PC than the source line SL. The gate stack GST may be disposed between the multiple bit lines BL and the source line SL.

[0046] Figure 4 It is used to describe Figure 1 A cross-sectional view of the memory cell array 20.

[0047] Reference Figure 4 The memory cell array 20 can be configured such that the lower structure U and the upper structure T are adhered to each other and the source line structure SL is disposed on the upper structure T.

[0048] The upper structure T may include a gate stack GST separated from each other by a slit SI, a channel structure CH penetrating at least a portion of the gate stack GST, a memory layer ML extending along the sidewalls of each channel structure CH, and a bit line 41 and a first interconnection structure 1st_CS disposed below the gate stack GST.

[0049] Each gate stack (GST) may include interlayer insulating layers (ILDs) and conductive patterns CP1 to CPn alternately stacked in a vertical direction. Each of the conductive patterns CP1 to CPn may include various conductive materials such as doped silicon layers, metal layers, metal silicide layers, and barrier layers, and may include two or more types of conductive materials. For example, each of the conductive patterns CP1 to CPn may include tungsten and a titanium nitride (TiN) layer configured to surround the surface of the tungsten. Tungsten is a low-resistance material and can reduce the resistance of the conductive patterns CP1 to CPn. The titanium nitride (TiN) layer may serve as a barrier layer and prevent the tungsten and the interlayer insulating layers (ILDs) from directly contacting each other.

[0050] The first conductive pattern CP1, adjacent to bit line 41 among conductive patterns CP1 to CPn, can be used as a drain select line DSL. In other embodiments, two or more layers of conductive patterns adjacent to and continuously stacked with bit line 41 can be used as drain select lines. Among conductive patterns CP1 to CPn, the nth conductive pattern CPn adjacent to the first source layer SL1, the second source layer SL2, and the third source layer SL3 can be used as a source select line SSL. In various embodiments, two or more layers of conductive patterns adjacent to and continuously stacked with the first source layer SL1, the second source layer SL2, and the third source layer SL3 can be used as source select lines. Conductive patterns (e.g., CP2 to CPn-1) that are vertically adjacent to each other and disposed between the drain select line and the source select line can be used as referenced above. Figure 2 The word lines described are WL1 to WLn.

[0051] Each channel structure CH can vertically penetrate at least a portion of the gate stack GST, and the first end of the channel structure CH can be formed to protrude above the gate stack GST. Each channel structure CH can be formed hollow. The channel structure CH may include a core insulating layer 11 configured to fill the central region of the channel structure CH, a doped semiconductor layer 13 disposed below the core insulating layer 11, and a channel layer 15 configured to surround the surfaces of the core insulating layer 11 and the doped semiconductor layer 13. The channel layer 15 can be used as the channel region of its corresponding cell string. The channel layer 15 can be formed of a semiconductor material. In an embodiment, the channel layer 15 may include a silicon layer. Dopant can be implanted into the uppermost part of the channel layer 15 (i.e., the portion corresponding to the source selection transistor) by an ion implantation process. The channel structure CH can be formed to protrude above the interlayer insulating layer ILD disposed at the uppermost part of the gate stack GST. The protruding end of the channel structure CH may be formed only by the channel layer 15. For example, the channel layer 15 may be formed with a height greater than the height of the interlayer insulating layer ILD disposed at the top of the gate layer stack GST. For example, the channel layer 15 may be formed with a height greater than the height of the core insulating layer 11. That is, the channel layer 15 may be formed to protrude upward above the core insulating layer 11.

[0052] The memory layer ML can be formed as a surface surrounding the channel structure CH. The memory layer ML may include a tunnel insulating layer TI configured to surround the channel layer 15 of the channel structure CH, a data storage layer DS configured to surround the tunnel insulating layer TI, and a barrier insulating layer BI configured to surround the data storage layer DS. The memory layer ML may extend vertically from the channel structure CH and may extend shorter than the channel layer 15. That is, the memory layer ML may be formed with a height less than the height of the channel layer 15. Specifically, the channel layer 15 may be disposed between the memory layer ML and the core insulating layer 11, and its height may be greater than the height of both the memory layer ML and the core insulating layer 11. Therefore, due to the height of the channel layer 15, an opening may be formed in the upper part of the core insulating layer 11, and this opening may be filled using the first source layer SL1 and the second source layer SL2. The memory layer ML may be formed at a height equal to or greater than the height of the interlayer insulating layer IDL disposed at the uppermost part of the gate stack GST. The memory layer ML can be defined as a component included in the channel structure CH.

[0053] A sacrificial substrate SAS can be further disposed between the interlayer insulating layer ILD and the first source layer SL1 at the top of the gate stack GST.

[0054] Bit line 41 may be disposed below the gate stack GST. Bit line 41 may be connected to the channel structure CH via contact plugs 31 that penetrate at least a portion of the plurality of insulating layers 21, 25 and 27. Bit line 41 may be spaced apart from the substrate SUB via a first insulating structure 51 and a second insulating structure 81.

[0055] The first connection structure 1st_CS may include a first insulating structure 51 and a first connection structure C1 formed in the first insulating structure 51. The first connection structure C1 may include various conductive patterns 63, 65, and 67. The first insulating structure 51 may include two or more insulating layers 51A to 51D stacked between the bit line 41 and the second insulating structure 81.

[0056] The lower structure U may include: a complementary metal-oxide-semiconductor (CMOS) circuit structure CMOS, which includes a plurality of transistors TR formed on a substrate SUB; and a second interconnect structure 2nd_CS, which is formed on the CMOS circuit structure CMOS. An isolation layer ISO may be disposed in the substrate SUB and may isolate the junctions of the plurality of transistors TR from each other.

[0057] The second connection structure 2nd_CS may include a second insulating structure 81 formed on the substrate SUB and a second connection structure C2 formed in the second insulating structure 81. The second connection structure C2 may include various conductive patterns 83, 85, 87, 89 and 91 embedded in the second insulating structure 81. The second insulating structure 81 may include two or more insulating layers 81A to 81D stacked sequentially.

[0058] The upper structure T and the lower structure U can be adhered to each other via a bonding process. For example, the exposed conductive pattern 67 of the first connecting structure 1st_CS of the upper structure T and the exposed conductive pattern 91 of the second connecting structure 2nd_CS of the lower structure U can be arranged to face each other and adhere to each other. The conductive pattern 67 and the conductive pattern 91 can be defined as patterns for bonding metals.

[0059] A source line structure SL can be disposed on the upper structure T. The source line structure SL can be configured to include a first source layer SL1, a second source layer SL2, and a third source layer SL3. The first source layer SL1 can be implemented as a doped polysilicon layer. The first source layer SL1 can be formed along the upper surface of the sacrificial substrate SAS, the upper surface of the memory layer ML, the surface of the protrusion of the channel layer 15, and the upper surface of the core insulating layer 11. The first source layer SL1 can be formed to contact and be electrically and physically connected to the surface of the protrusion of the channel layer 15. The second source layer SL2 can be formed along the upper surface of the first source layer SL1 and may include a titanium (Ti) layer or a titanium nitride (TiN) layer. The second source layer SL2 can be formed such that an opening in the upper part of the core insulating layer 11 is embedded. The third source layer SL3 can be formed on the second source layer SL2. The third source layer SL3 can be formed of a metal material with low resistance. For example, the third source layer SL3 can be formed of tungsten W, thus reducing the resistance of the source line structure.

[0060] Source line structure SL can be used as Figure 2 The source line SL.

[0061] Figures 5A to 5F , Figure 6 , Figure 7 and Figures 8A to 8D This is a cross-sectional view used to describe a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0062] Figures 5A to 5F It is a cross-sectional view used to describe the steps of forming a memory cell array, a first linear array, and a first interconnection structure on a first substrate.

[0063] Reference Figure 5A The first material layer 111 and the second material layer 113 may be alternately stacked on the first substrate 101.

[0064] The first substrate 101 may be formed of a material with an etching rate different from that of the first material layer 111 and the second material layer 113. For example, the first substrate 101 may include silicon.

[0065] In an embodiment, the first material layer 111 may be a reference layer. Figure 4The described interlayer insulating layer (ILD) is made of an insulating material. The second material layer 113 may be formed of a material with an etch rate different from that of the first material layer 111. For example, the first material layer 111 may comprise silicon oxide, and the second material layer 113 may comprise silicon nitride. Although the following figures illustrate an embodiment where the first material layer 111 is implemented as an insulating layer and the second material layer 113 is implemented as a sacrificial layer, this disclosure is not limited thereto. The material properties of the first material layer 111 and the second material layer 113 may be varied. For example, the first material layer 111 may be made of a material used for the above reference. Figure 4 The interlayer insulation layer (ILD) described is made of insulating material, and the second material layer 113 may be made of material used for the above reference. Figure 4 The conductive patterns CP1 to CPn described are made of conductive material.

[0066] Reference Figure 5B A first mask pattern 121 having a first opening 125 can be formed on the stacked structure of the first material layer 111 and the second material layer 113. Subsequently, a channel hole 115 penetrating at least a portion of the first material layer 111 and the second material layer 113 can be formed through the first opening 125 in the first mask pattern 121. The channel hole 115 can extend into the first substrate 101 to a specific depth, partially penetrating the first substrate 101. Depending on the etchant used to form the channel hole 115, the channel hole 115 can be formed in various shapes.

[0067] In one embodiment, a first etchant can be used to form the channel hole 115. The etching rate of the first material layer 111 and the second material layer 113 corresponding to the first etchant can be higher than the etching rate of the first substrate 101 corresponding to the first etchant. As a result, the width of the end of the channel hole 115 extending into the first substrate 101 can be formed to be smaller than the width of the channel hole 115 passing through the first material layer 111 and the second material layer 113.

[0068] Reference Figure 5C A memory layer 137 and a channel structure 147 can be formed in each of the channel holes 115. The ends of the channel structure 147 extending into the first substrate 101 and the sidewalls of the channel structure 147 can be surrounded by the memory layer 137.

[0069] The steps of forming the memory layer 137 may include sequentially stacking a barrier insulating layer 135, a data storage layer 133, and a tunnel insulating layer 131 on the surface of the via 115. The barrier insulating layer 135, the data storage layer 133, and the tunnel insulating layer 131 may each include elements as described above. Figure 4 The barrier insulating layer BI, data storage layer DS, and tunnel insulating layer TI are made of the same material. The memory layer 137 may be formed in a pad shape, and the central region of the channel hole 115 may be defined by the memory layer 137.

[0070] Subsequently, a channel layer 141 may be formed on the surface of the memory layer 137, and then a channel structure 147 may be formed. The channel layer 141 may include a semiconductor layer serving as a channel region. For example, the channel layer 141 may include undoped polysilicon.

[0071] In one embodiment, the channel layer 141 may be formed in a pad shape, and the central region of the channel via 115 may include a portion not filled by the channel layer 141. When the channel layer 141 is formed in a pad shape, the steps of forming the channel structure 147 may include filling the central region of the channel via with a core insulating layer 143 on the channel layer 141, etching a portion of the core insulating layer 143 and defining a recessed region in a portion of the central region of each channel via 115, and filling the recessed region with a doped semiconductor layer 145. The core insulating layer 143 may include an oxide, and the doped semiconductor layer 145 may include a conductive dopant. The conductive dopant may include an n-type dopant for a junction. The conductive dopant may include an anti-doped p-type dopant.

[0072] In other embodiments, the channel layer 141 may be formed to fill the central region of the channel via 115, wherein the core insulating layer 143 and the doped semiconductor layer 145 may be excluded. When the core insulating layer 143 and the doped semiconductor layer 145 are omitted, the step of forming the channel structure 147 may further include the step of doping the channel layer 141 with a conductive dopant.

[0073] Reference Figure 5D ,exist Figure 5C After the first mask pattern 121 is removed, the first insulating layer 151 can be formed.

[0074] Then, a slit 153 can be formed. The slit 153 can penetrate the first insulating layer 151, and also can penetrate the laminated structure of the first material layer 111 and the second material layer 113. The slit 153 can correspond to... Figure 4 The slit SI is shown. Next, the second material layer 113 exposed through the slit 153 can be selectively removed, thus defining a horizontal space 155. The horizontal space 155 can be defined between the first material layers 111 that are adjacent to each other in the vertical direction.

[0075] Reference Figure 5E It can be filled by the third material layer 157 through the slit 153. Figure 5D The horizontal space 155 is shown. The third material layer 157 can be referenced above. Figure 4 The conductive patterns CP1 to CPn are described. A third material layer 157 may fill the horizontal space 155 to surround the channel structure 147 and the memory layer 137.

[0076] As described above, a gate stack 150 can be formed on the first substrate 101 by replacing the second material layer 113, which serves as a sacrificial layer, with a third material layer 157 serving as a conductive pattern. The gate stack 150 may include a structure in which a first material layer 111 serving as an interlayer insulating layer and a third material layer 157 serving as a conductive pattern are alternately stacked. The gate stack 150 may be at least partially penetrated by a channel structure 147, and the channel structure 147 may extend into the first substrate 101. A memory layer 137 may extend from the region between the channel structure 147 and the gate stack 150 to the region between the end of the channel structure 147 and the first substrate 101.

[0077] Based on the above reference Figures 5A to 5E The described process can be used to form the above reference on the first substrate 101. Figure 3 The description includes a storage block comprising multiple cell strings CS1 and CS2. (Refer to the above.) Figure 3 The described unit strings may include drain-select transistors (DST) and memory cells MC1 to MCn connected in series with each other. (Refer to the above...) Figure 3 The described drain-select transistor DST and memory cells MC1 to MCn can be defined in Figure 5E The channel structure 147 and the third material layer 157, which is a conductive pattern, are located in the intersection area and can be connected in series through the channel structure 147.

[0078] Next, a sidewall insulating layer 161 may be formed covering the sidewalls of the gate stack 150. Subsequently, a second insulating layer 163 may be formed extending to fill the slit 153 and cover the sidewall insulating layer 161 and the first insulating layer 151.

[0079] Reference Figure 5F A third insulating layer 171 may be formed on the second insulating layer 163. Thereafter, a contact plug 173 may be formed that penetrates the third insulating layer 171 or penetrates at least a portion of the third insulating layer 171 and the second insulating layer 163. The contact plug 173 may extend to contact the channel structure 147.

[0080] Next, a first linear array 175 may be formed. The first linear array 175 may be bit lines coupled to contact plugs 173. Subsequently, a first insulating structure 181 covering the first linear array 175 may be formed. The first insulating structure 181 may include two or more insulating layers (four layers 181A to 181D are shown). First connection structures 185, 189, 191 and 193 may be embedded in the first insulating structure 181 and may be electrically connected to each other via contact plugs (not shown).

[0081] The first connection structures 185, 189, 191 and 193 may include a first bonding metal material 193 having a surface exposed to the outside of the first insulating structure 181.

[0082] Figure 6 It is a cross-sectional view used to describe the steps of forming a CMOS circuit and a second connection structure on a second substrate.

[0083] Reference Figure 6 Multiple transistors 200 constituting a complementary metal-oxide-semiconductor (CMOS) circuit can be formed on the second substrate 201.

[0084] The second substrate 201 may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial layer substrate formed using a selective epitaxial growth method.

[0085] Transistors 200 may be formed in respective active regions of the second substrate 201 separated by an isolation layer 203. Each transistor 200 may include a gate insulating layer 207 and a gate electrode 209 stacked in its corresponding active region, and junctions 205a and 205b formed in the active regions disposed on both sides of the gate electrode 209. Each of junctions 205a and 205b may include a conductive dopant for realizing its corresponding transistor. Each of junctions 205a and 205b may include at least one of an n-type dopant and a p-type dopant.

[0086] After forming a plurality of transistors 200, a second connection structure 220 may be formed to the transistors 200 constituting a CMOS circuit, and a second insulating structure 211 configured to cover the second connection structure 220 and the transistors 200.

[0087] The second insulating structure 211 may include two or more insulating layers (four layers 211A to 211D are shown). A second connection structure 220 may be embedded within the second insulating structure 211. Each second connection structure 220 may include multiple conductive patterns 213, 215, 217, 219, 221, and 223. The second insulating structure 211 and the second connection structure 220 may be varied in various forms and are not limited to the examples shown in the figures.

[0088] The conductive patterns 213, 215, 217, 219, 221 and 223 included in the respective second connection structures 220 may include a second bonding metal material 223 having a surface exposed to the outside of the second insulating structure 211.

[0089] Figure 7 It is a cross-sectional view used to describe the steps of attaching the first connecting structure and the second connecting structure to each other.

[0090] Reference Figure 7 The first substrate 101 and the second substrate 201 are aligned such that the first bonding metal material 193 on the first substrate 101 and the second bonding metal material 223 on the second substrate 201 are in contact with each other. The first bonding metal material 193 and the second bonding metal material 223 may comprise various types of metal materials (e.g., copper).

[0091] Subsequently, the first bonding metal material 193 and the second bonding metal material 223 adhere to each other. For this purpose, the first bonding metal material 193 and the second bonding metal material 223 can be hardened after heat is applied to them. This disclosure is not limited thereto, and various processes for joining the first bonding metal material 193 and the second bonding metal material 223 to each other can be introduced.

[0092] Figures 8A to 8D It is a cross-sectional view used to describe the steps of forming a source line structure connected to multiple cell strings on the gate stack 150.

[0093] Reference Figure 8A Etching Figure 7 The first substrate 101, memory layer 137, and channel layer 141 are exposed, thus exposing the uppermost part of the core insulating layer 143. For example, a chemical mechanical polishing (CMP) process can be used to perform the etching process. For example, the first substrate 101, memory layer 137, and channel layer 141 can be etched to expose the uppermost part of the core insulating layer 143 using a CMP process.

[0094] Reference Figure 8B The exposed upper portion of the core insulating layer 143 is etched to a specific thickness, thereby causing the upper portion of the channel layer 141 to protrude. For example, the etching process can be performed using a wet etching process. For example, by using a wet etching process to etch the upper portion of the core insulating layer 143 to a specific thickness, the memory layer 137 and the first substrate 101 can also be etched to a predetermined extent.

[0095] The following description will refer to the enlarged attached diagram of region A.

[0096] Reference Figure 8C The channel layer 141 exposed by performing an etching process may have protrusions P. An opening defined by the protrusions P of the channel layer 141 may be formed on the upper part of the insulating layer 143.

[0097] Subsequently, a junction region can be formed by performing an ion implantation process and by implanting dopants into the channel layer 141, which serves as the channel for the source selection transistor.

[0098] Reference Figure 8DA first source layer 301 is formed along the entire upper surface of the structure, including the protrusion of the channel layer 141. The first source layer 301 may be implemented as a doped polysilicon layer. The first source layer 301 may be formed to make surface contact with the upper surface of the first substrate 101, the upper surface of the memory layer 137, and the protrusion of the channel layer 141.

[0099] Subsequently, a second source layer 303 may be formed along the upper surface of the first source layer 301, and the second source layer 303 may include a titanium (Ti) layer or a titanium nitride (TiN) layer. The second source layer 303 may be formed to fill an opening in the upper part of the core insulating layer 143.

[0100] Subsequently, a third source layer 305 can be formed on the second source layer 303. The third source layer 305 can be formed of a metallic material with low resistance. For example, the third source layer 305 can be formed of tungsten W, thus reducing the resistance of the source line structure.

[0101] According to embodiments of this disclosure, during the etching process of the first substrate, the core insulating layer can be etched to a specific thickness to make the channel layer of the channel structure protrude. Therefore, during the process of connecting the channel layer to the source layer, a process can be performed such that the protrusion of the channel layer and the source layer come into contact with each other, thus making the connection process easier to perform.

[0102] Figure 9 This is a block diagram illustrating the configuration of a memory system 1100 according to an embodiment of the present disclosure.

[0103] Reference Figure 9 The memory system 1100 may include a semiconductor memory device 1120 and a memory controller 1110.

[0104] The semiconductor memory device 1120 can be a multi-chip package composed of multiple flash memory chips. In an embodiment, the semiconductor memory device 1120 can be a reference... Figures 1 to 4 The semiconductor memory device 10 is described.

[0105] The memory controller 1110 controls the semiconductor memory device 1120 and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 serves as the working memory of the CPU 1112, which performs overall control operations for data exchange with the memory controller 1110. The host interface 1113 may be configured with a data exchange protocol connected to a host connected to the memory system 1100. Furthermore, the error correction block 1114 detects and corrects errors included in the data read from the semiconductor memory device 1120, and the memory interface 1115 interfaces with the semiconductor memory device 1120. Additionally, the memory controller 1110 may also include a read-only memory (ROM) for storing code data for interfacing with the host.

[0106] The aforementioned memory system 1100 may be a memory card or a solid-state drive (SSD), wherein the semiconductor memory device 1120 and the storage controller 1110 are combined with each other. For example, when the memory system 1100 is an SSD, the storage controller 1110 may communicate with an external device (e.g., a host) via one of various interface protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-E), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0107] Figure 10 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure.

[0108] Reference Figure 10 The computing system 1200 according to embodiments of the present disclosure may include a CPU 1220, random access memory (RAM) 1230, user interface 1240, modem 1250, and memory system 1210 electrically connected to a system bus 1260. Additionally, when the computing system 1200 is a mobile device, it may also include a battery for supplying operating voltage to the computing system 1200, and may also include an application chipset, camera image processor (CIS), mobile DRAM, etc.

[0109] According to this disclosure, during the process of connecting a channel layer with a vertical channel structure to a source layer, the core insulating layer of the channel structure is exposed and then etched to a specific depth to make the channel layer protrude. Therefore, a source layer with a protruding channel layer can be easily formed.

[0110] Although embodiments of the present disclosure have been disclosed for illustrative purposes, those skilled in the art will understand that various modifications, additions, and / or substitutions may be made. Therefore, the scope of this disclosure should be defined by the appended claims and their equivalents, and not by their preceding description.

[0111] Cross-references to related applications

[0112] This application claims priority to Korean Patent Application No. 10-2021-0182113, filed with the Korean Intellectual Property Office on December 17, 2021, the full disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A gate stack comprising alternating layers of interlayer insulating layers and conductive patterns, the gate stack overlapping a substrate in a vertical direction; A channel structure that penetrates at least a portion of the gate stack and has a first end that protrudes upward above the gate stack; A memory layer that surrounds the sidewalls of the channel structure; A source layer that overlaps with the gate stack; as well as First substrate, The channel structure includes: A core insulating layer is formed in the central region of the channel structure and extends in the vertical direction; and A trench layer that surrounds the sidewalls of the core insulation layer. The channel layer includes protrusions that extend upwards above the core insulating layer and the memory layer. The protrusions in the channel layer define the opening. The source layer includes a first source layer, which comprises a doped semiconductor material, and The first source layer is in contact with the upper surface of the memory layer, the upper surface of the first substrate, and the protrusion of the channel layer.

2. The semiconductor memory device according to claim 1, wherein, The source layer further includes a second source layer located on the first source layer and a third source layer located on the second source layer.

3. The semiconductor memory device according to claim 2, wherein, The first source layer includes a doped polysilicon layer. The second source layer includes a titanium layer or a titanium nitride layer, and The third source layer includes a tungsten layer.

4. The semiconductor memory device according to claim 1, wherein, The first source layer is directly connected to the protrusion of the channel layer.

5. A semiconductor memory device, the semiconductor memory device comprising: A gate stack comprising alternating layers of interlayer insulating layers and conductive patterns, the gate stack overlapping a substrate in a vertical direction; A first substrate, which overlaps with the gate stack; A channel structure that penetrates at least a portion of the gate stack and the first substrate, the channel structure having a first end protruding upward from the first substrate; A memory layer that surrounds the sidewalls of the channel structure; as well as The source layer overlaps with the gate layer stack. The protruding first end of the channel structure includes an opening. The upper surface of the first substrate is connected to the upper surface of the memory layer. The source layer includes a first source layer, which comprises a doped semiconductor material, and The first source layer is in contact with the upper surface of the memory layer, the upper surface of the first substrate, and the protruding first end of the channel structure.

6. The semiconductor memory device according to claim 5, wherein, The channel structure includes: A core insulating layer is formed in the central region of the channel structure and extends in the vertical direction; and A trench layer that surrounds the sidewalls of the core insulation layer.

7. The semiconductor memory device according to claim 6, wherein, The first source layer is directly connected to the protrusion of the channel layer.

8. The semiconductor memory device according to claim 7, wherein, The opening is defined by the protrusion of the channel layer and the upper part of the core insulation layer.

9. A method for manufacturing a semiconductor memory device, the method comprising the following steps: A memory cell array is formed on a first substrate, such that the memory cell array includes a gate stack, a core insulating layer, a channel layer, and a memory layer. The gate stack includes an interlayer insulating layer and a conductive pattern alternately stacked in a vertical direction. The core insulating layer penetrates at least a portion of the gate stack and has a first end extending into the first substrate. The channel layer surrounds the sidewalls of the core insulating layer and the first end. The memory layer extends from a region between the channel layer and the gate stack to a region between the end of the channel layer and the first substrate. A first etching process is performed to etch the first substrate, the memory layer, and the channel layer to expose the first end of the core insulating layer. The steps of performing the first etching process include exposing the upper surface of the first substrate and the upper surface of the memory layer. A second etching process is performed to etch the exposed core insulating layer to a specific thickness, and then to make the channel layer protrude such that the height of the upper part of the channel layer is greater than the height of the upper part of the core insulating layer. as well as A first source layer is formed to surround the protruding channel layer, and the first source layer is in contact with the upper surface of the first substrate and the upper surface of the memory layer. The upper surface of the first substrate is connected to the upper surface of the memory layer.

10. The method according to claim 9, wherein, The first etching process includes using a chemical mechanical polishing (CMP) process to etch the first substrate, the memory layer, and the channel layer, thereby exposing the upper portion of the core insulating layer.

11. The method according to claim 9, wherein, The second etching process includes etching the upper portion of the core insulating layer to a specific thickness using a wet etching process, wherein the upper portion of the core insulating layer is etched together with the memory layer and the first substrate.

12. The method according to claim 11, wherein, The channel layer is configured such that the upper portion of the core insulating layer and the upper portion of the memory layer are etched together using the second etching process to form a protrusion.

13. The method according to claim 12, wherein, The second etching process is used to etch the upper part of the core insulation layer, and then an opening defined by the protrusion is formed.

14. The method of claim 13, further comprising the step of: A second source layer is formed along the upper surface of the first source layer. The opening is filled by the first source layer and the second source layer.

15. The method of claim 14, further comprising forming a third source layer on the second source layer.

16. The method according to claim 15, wherein, The first source layer is implemented as a doped polysilicon layer. The second source layer is realized as a titanium layer or a titanium nitride layer, and The third source layer is implemented as a tungsten layer.

Images