Semiconductor memory device

Abstract

According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of conductive layers and a plurality of first insulating layers stacked one by one alternately and a stepped portion in which the plurality of conductive layers are processed into a stepped shape, and a plurality of second pillars extending in the stepped portion in the stacked body, wherein each of the plurality of second pillars includes a second insulating layer extending in a stacking direction in the stacked body, a semiconductor layer covering a sidewall of the second insulating layer, a third insulating layer disposed in contact with a sidewall of the semiconductor layer and covering the sidewall of the semiconductor layer, and a fourth insulating layer disposed in contact with a sidewall of the third insulating layer and covering the sidewall of the third insulating layer.

Description

[0001] Cross-reference of related applications

[0002] This application is based on and claims priority to Japanese Patent Application No. 2021-205073, filed on December 17, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments described herein generally relate to a semiconductor memory device. Background Technology

[0004] In semiconductor memory devices (such as three-dimensional non-volatile memory), memory cells are arranged in three dimensions as a stacked body in which multiple conductive layers and multiple insulating layers are alternately stacked. However, the stacked body is partially sunken along the stacking direction, which may result in the stacked body having an uneven upper surface. Summary of the Invention

[0005] Generally, according to one embodiment, a semiconductor memory device includes: a stacked body comprising a plurality of conductive layers and a plurality of first insulating layers stacked alternately and including a stepped portion, wherein the plurality of conductive layers are processed into a stepped shape in the stepped portion; a first pillar extending away from the stepped portion in the stacked body along a stacking direction of the stacked body in a first direction intersecting the stacking direction and forming a memory cell at each intersection point with at least a portion of the plurality of conductive layers; and a plurality of second pillars extending in the stacked body in the stepped portion along the stacking direction, wherein each of the plurality of second pillars includes: a second insulating layer extending in the stacked body along the stacking direction; a semiconductor layer covering a sidewall of the second insulating layer; a third insulating layer disposed to contact and cover the sidewall of the semiconductor layer; and a fourth insulating layer disposed to contact and cover the sidewall of the third insulating layer; and the third and fourth insulating layers contain the same material.

[0006] According to an embodiment, the sinking of the stacked body of the semiconductor memory device may be suppressed. Attached Figure Description

[0007] Figure 1A and 1B This is a view illustrating a schematic configuration example of a semiconductor memory device according to an embodiment;

[0008] Figures 2A to 2E This is a cross-sectional view illustrating an example configuration of a semiconductor memory device according to an embodiment;

[0009] Figure 3 It is a top view including the stepped region of the semiconductor memory device according to the embodiment;

[0010] Figures 4A to 4C This is a view illustrating, in sequence, portions of a procedure for manufacturing a semiconductor memory device according to an embodiment;

[0011] Figures 5A to 5C This is a view illustrating, in sequence, portions of a procedure for manufacturing a semiconductor memory device according to an embodiment;

[0012] Figures 6A to 6C This is a view illustrating, in sequence, portions of a procedure for manufacturing a semiconductor memory device according to an embodiment;

[0013] Figures 7Aa to 7Bc This is a view illustrating, in sequence, portions of a procedure for manufacturing a semiconductor memory device according to an embodiment;

[0014] Figures 8Aa to 8Bc This is a view illustrating, in sequence, portions of a procedure for manufacturing a semiconductor memory device according to an embodiment;

[0015] Figures 9A to 9C This is a view illustrating, in sequence, portions of a procedure for manufacturing a semiconductor memory device according to an embodiment;

[0016] Figures 10A to 10C This is a view illustrating, in sequence, portions of a procedure for manufacturing a semiconductor memory device according to an embodiment;

[0017] Figures 11Aa to 11Bb This is a view illustrating, in sequence, portions of a procedure for manufacturing a semiconductor memory device according to an embodiment;

[0018] Figures 12A to 12C This is a view illustrating, in sequence, portions of a procedure for manufacturing a semiconductor memory device according to an embodiment;

[0019] Figure 13 This is a view illustrating, in sequence, portions of a procedure for manufacturing a semiconductor memory device according to an embodiment;

[0020] Figures 14A to 14C This is a view illustrating, in sequence, portions of a procedure for manufacturing a semiconductor memory device according to an embodiment;

[0021] Figures 15A to 15C This is a cross-sectional view illustrating an example of the configuration of the stepped portion of a semiconductor memory device according to a first modified example of an embodiment;

[0022] Figure 16 It is a top view including the stepped region of a semiconductor memory device according to a first modified example of the embodiment;

[0023] Figure 17 This is a cross-sectional view along the X direction illustrating how a contact hole is formed in a stepped portion of a semiconductor memory device according to a first modified example of an embodiment.

[0024] Figure 18 This is a cross-sectional view along the Y direction illustrating an example of the configuration of the stepped portion of a semiconductor memory device according to a second modified example of an embodiment;

[0025] Figures 19A to 19C These are views illustrating, in sequence, portions of a procedure for manufacturing a semiconductor memory device according to a second modified example of an embodiment; and

[0026] Figures 20A to 20C This is a view illustrating, in sequence, portions of a procedure for manufacturing a semiconductor memory device according to a second modified example of an embodiment. Detailed Implementation

[0027] Exemplary embodiments of semiconductor memory devices will be explained in detail below with reference to the accompanying drawings. The invention is not limited to the following embodiments. Furthermore, the components in the following embodiments include those readily conceived by those skilled in the art, or those substantially the same.

[0028] (Configuration example of a semiconductor memory device)

[0029] Figure 1A and 1B This is a view illustrating a schematic configuration example of a semiconductor memory device 1 according to an embodiment. Figure 1A This is a cross-sectional view of the semiconductor memory device 1 along the X direction, and Figure 1B This is a schematic plan view illustrating the layout of semiconductor memory device 1. However, in Figure 1A In this diagram, shadows have been omitted to ensure visibility. Figure 1A Some gate selection lines and upper layer wirings have been omitted.

[0030] In this specification, both the X and Y directions are directions along the surface of the word line WL, which will be described later, and the X and Y directions are orthogonal to each other. Furthermore, the electrical lead-out direction of the word line WL, which will be described later, may be referred to as the first direction, and the first direction is along the X direction. The direction intersecting the first direction may be referred to as the second direction, and the second direction is along the Y direction. However, since the semiconductor memory device 1 may have manufacturing variations, the first and second directions need not be orthogonal to each other.

[0031] like Figure 1A and 1B As illustrated in the figure, the semiconductor memory device 1 includes peripheral circuitry CUA, memory region MR, through-connection region TP, and stepped region SR on substrate SB.

[0032] For example, the substrate SB is a semiconductor substrate, such as a silicon substrate. Peripheral circuitry CUA, including transistors TR, wiring, etc., is disposed on the substrate SB. The peripheral circuitry CUA facilitates the operation of the memory cells, as described later.

[0033] The peripheral circuitry CUA is covered by an insulating layer 50. The source line SL is disposed on the insulating layer 50. Multiple word lines WL are stacked on the source line SL. The multiple word lines WL are covered by an insulating layer 49. The insulating layer 49 also extends around the multiple word lines WL.

[0034] Multiple board contacts LI, extending along the stacking direction and penetrating the word lines WL, are arranged within the multiple word lines WL. Therefore, the multiple word lines WL are separated by multiple board contacts LI along the Y direction.

[0035] Multiple memory regions MR, stepped regions SR, and through-connect regions TP are arranged side-by-side along the X-direction between multiple board contacts LI. The multiple memory regions MR are spaced apart from each other along the X-direction, while the stepped regions SR and through-connect regions TP are interposed between the multiple memory regions.

[0036] In the memory region MR, a plurality of pillars PL are disposed, extending along the stacking direction through the word line WL. A plurality of memory cells are formed at the intersection points between the pillars PL and the word line WL. Therefore, the semiconductor memory device 1 is configured, for example, as a three-dimensional non-volatile memory, wherein the memory cells are arranged three-dimensionally in the memory region MR.

[0037] A stepped region SR contains multiple stepped sections SP, in which multiple letter lines WL are excavated downwards in a mortar-like shape along the stacking direction. For example, two stepped sections SP arranged along the Y direction with a plate joint LI inserted in the middle are placed in a stepped region SR.

[0038] The stepped portion SP forms one side of the mortar shape, which descends in a stepped manner from both sides in the X direction and one side in the Y direction toward the bottom surface. However, the stepped portion SP opens along the other side in the Y direction toward the side surface of the plate joint LI.

[0039] Each step of the stepped section SP is configured with word lines WL for each layer. Each layer's word lines WL maintain electrical conduction on both sides of the stepped section SP in the X direction through a step portion on one side of the stepped section SP in the Y direction. The connection point CC between each layer's word lines WL and the upper layer wiring MX is located in the platform portion of each step of the stepped section SP.

[0040] Therefore, word lines WL stacked in multiple layers can be individually led out. Write voltage, read voltage, etc., are applied to the memory cell from these contacts CC via word lines WL located at the same height as the memory cells on both sides of the memory region MR along the X direction.

[0041] In this specification, the direction in which the platform surface of each step of the stepped portion SP faces is defined as the top direction.

[0042] A through-connect region TP is positioned on one side of the stepped region SR along the X direction. A through-connect C4, penetrating multiple word lines WL, is positioned within the through-connect region TP. Through-connect C4 connects the peripheral circuitry CUA, positioned on the lower substrate SB, to the upper layer wiring MX, which connects to the contact CC of the stepped portion SP. Various voltages applied from contact CC to the memory cells are controlled by the peripheral circuitry CUA via through-connect C4, upper layer wiring MX, etc.

[0043] Next, we will refer to Figures 2A to 2E A detailed configuration example of semiconductor memory device 1 is described. Figures 2A to 2E This is a cross-sectional view illustrating an example configuration of a semiconductor memory device 1 according to an embodiment.

[0044] Figure 2A It is a cross-sectional view along the X direction, including the memory region MR and the stepped region SR. Figure 2B It is a cross-sectional view along the Y direction, including the stepped region SR and the through-joint region TP. However, in Figure 2A and 2B In this paper, the structures below the insulating layer 50, such as the substrate SB and the peripheral circuit CUA, are omitted.

[0045] Figure 2C and 2D This is a partially enlarged view illustrating the cross-section of the pillar PL located in the memory region MR. Figure 2EThis is a partially enlarged view illustrating the cross-section of the columnar portion HR placed in the stepped region SR and the through-connection region TP.

[0046] like Figure 2A and 2B The diagram illustrates that the source line SL has a multi-layer structure, for example, the lower source line DSLa, the middle source line BSL or the middle insulating layer SCO, and the upper source line DSLb are stacked on the insulating layer 50 in this order.

[0047] For example, the lower source line DSLa, the middle source line BSL, and the upper source line DSLb are polysilicon layers. At least the middle source line BSL can be a conductive polysilicon layer in which impurities are diffused, etc. The middle source line BSL is disposed below the memory region MR of the stacked main body LM.

[0048] For example, the intermediate insulating layer SCO is a silicon oxide layer, etc. The intermediate insulating layer SCO is placed under the stepped region SR, the through-contact region TP, etc. of the stacked main body LM.

[0049] The stacked host LM is positioned above the source line SL. Within the stacked host LM, multiple word lines WL and multiple insulating layers OL are stacked alternately. The select gate line SGD is positioned above the topmost word line WL, with insulating layers OL inserted between them. The select gate line SGS is positioned below the bottommost word line WL, with insulating layers OL inserted between them. The number of word lines WL, select gate lines SGD, and SGS stacked within the stacked host LM is arbitrary.

[0050] For example, the word line WL, which acts as multiple conductive layers, and the select gate lines SGD and SGS, are tungsten or molybdenum layers. For example, the insulating layer OL, which acts as multiple first insulating layers, is a silicon oxide layer.

[0051] The upper surface of the stacked body LM is covered by insulating layer 52. Insulating layer 52 is covered by insulating layer 53. Insulating layer 53 is covered by insulating layer 54. Insulating layers 52 to 54 together with insulating layer 51, which will be described later, constitute... Figure 1A The insulating layer 49 portion.

[0052] like Figure 2B The diagram illustrates that the stacked main body LM is divided along the Y direction by multiple board contacts LI.

[0053] The board contact LI, which acts as a board component, is arranged along the Y direction and extends along the stacking direction of the stacked body LM and along the X direction. That is, the board contact LI penetrates the insulating layer 52, the stacked body LM, and the upper source line DSLb, reaching the intermediate insulating layer SCO in the stepped region SR, the through contact region TP, etc., and reaching the intermediate source line BSL in the memory region MR. The board contact LI extends continuously from one end of the stacked body LM to the other end along the X direction in the stacked body LM.

[0054] Each of the board contacts LI includes an insulating layer 55 and a conductive layer 21. For example, the insulating layer 55 is a silicon oxide layer, etc. For example, the conductive layer 21 is a tungsten layer or a conductive polysilicon layer.

[0055] The insulating layer 55 covers the sidewalls of the contact LI along the Y direction facing each other. The conductive layer 21 fills the inner side of the insulating layer 55 and is in contact with... Figure 2B The conductive layer 21 is electrically connected to the source line SL, which contains the intermediate source line BSL, at different locations in the cross-section. Additionally, the conductive layer 21 is in contact with... Figure 2B In the cross-section illustrated in the diagram, at different locations, the upper layer wiring MX is connected to the insulating layer 54 via plugs V0 disposed in the insulating layer 53. Using this configuration, board contact LI serves as the source line contact.

[0056] However, instead of the board contact LI, a board component filled with an insulating layer can penetrate the stacked body LM and extend along the X direction, thereby dividing the stacked body LM along the Y direction. In this case, this board component is not used as a source line contact.

[0057] like Figure 2A As illustrated in the diagram, multiple pillars PL that penetrate the stacked main body LM, the upper source line DSLb, and the middle source line BSL and reach the lower source line DSLa are distributed in the memory region MR.

[0058] The columns PL, which act as multiple first columns, are arranged in, for example, an alternating pattern when viewed from the stacking direction of the stacked body LM. For example, the cross-sectional shape of each column PL in the direction along the layer direction of the stacked body LM (i.e., along the XY plane) is circular, elliptical, oval, etc.

[0059] Each of the multiple pillars PL includes a memory layer ME extending in the stacking direction within a stacked body LM, a channel layer CN penetrating the stacked body LM and connected to the intermediate source line BSL, a capping layer CP covering the upper surface of the channel layer CN, and a core layer CR serving as the core material of the pillar PL.

[0060] like Figure 2C and 2DThe diagram illustrates that the memory layer ME has a multi-layer structure, in which a barrier insulating layer BK, acting as the fourth insulating layer, a charge accumulation layer CT, acting as the fifth insulating layer, and a tunnel insulating layer TN, acting as the third insulating layer, are stacked in this order from the outer periphery of the pillar PL. More specifically, the memory layer ME is disposed on the side surface of the pillar PL, except at the depth of the intermediate source line BSL. The memory layer ME is also disposed on the bottom surface of the pillar PL, reaching the lower source line DSLa.

[0061] The channel layer CN penetrates the stacked body LM, the upper source line DSLb, and the intermediate source line BSL inside the memory layer ME, and reaches the lower source line DSLa. The side surface of the channel layer CN contacts the intermediate source line BSL and is therefore electrically connected to the source line SL containing the intermediate source line BSL. The core layer CR, which acts as a second insulating layer, fills the other inner side of the channel layer CN.

[0062] A top cover layer CP is disposed at the upper end portion of each of the plurality of posts PL. The top cover layer CP is disposed in insulating layer 52 to cover at least the upper end portion of channel layer CN and is connected to channel layer CN. The top cover layer CP is connected to bit line BL disposed in insulating layer 52 via plugs CH disposed in insulating layers 53 and 54.

[0063] For example, the barrier insulating layer BK, tunnel insulating layer TN, and core layer CR of the memory layer ME are silicon oxide layers, etc. For example, the charge accumulation layer CT of the memory layer ME is a silicon nitride layer, etc. The channel layer CN and capping layer CP are semiconductor layers, such as polycrystalline silicon layers or amorphous silicon layers.

[0064] like Figure 2D As illustrated in the diagram, using the above configuration, memory cells MC are formed in each portion of the side surface of the pillar PL facing each word line WL. When a predetermined voltage is applied from the word line WL, data is written to and read from the memory cells.

[0065] like Figure 2C As illustrated in the diagram, select gates STD and STS are formed in the portion of the select gate line SGD or SGS that faces above or below the word line WL on the side surface of the pillar PL. When a predetermined voltage is applied from each of the select gate lines SGD and SGS, select gates STD and STS are turned on or off, allowing the memory cell MC of the pillar PL to which select gates STD and STS belong to to enter a selected or unselected state.

[0066] like Figure 2B The diagram illustrates that the through-connector C4, the insulation portion NR, and the board portion BR are located in the through-connector area TP.

[0067] The insulating portion NR is the portion located inside the stacked body LM when viewed from the stacking direction, in which multiple insulating layers NL and multiple insulating layers OL are stacked alternately. For example, the multiple insulating layers NL are silicon nitride layers and are arranged at height positions corresponding to multiple word lines WL and select gate lines SGD and SGS, respectively.

[0068] The board portion BR is positioned on both sides of the insulating portion NR along the Y direction. The board portion BR extends along the X direction in the through contact area TP at the position between adjacent board contacts LI, penetrates the stacked body LM and the upper source line DSLb, and reaches the intermediate insulating layer SCO.

[0069] As will be described later, when a stacked body LM is formed from a stacked body in which a sacrificial layer and an insulating layer are stacked, the sacrificial layer is retained in the portion sandwiched between board portions BR without being replaced by word lines WL, etc., and remains as the insulating layer NL of the insulating portion NR.

[0070] In the insulating section NR, for example, multiple through-hole contacts C4 are arranged along the X direction (see...). Figure 1A However, instead of the X direction or other directions, multiple through-connectors C4 can also be arranged along the Y direction in the through-connector region TP.

[0071] The through contact C4 penetrates the insulating layer 52 and the insulating portion NR, passes through, for example, the opening OP provided in the source line SL, and reaches the insulating layer 50 covering the surrounding circuit CUA (see...). Figure 1A ).

[0072] The through-contact C4 includes an insulating layer 57 covering the outer periphery of the through-contact C4 and a conductive layer 23, such as a tungsten layer or a copper layer, filling the inner side of the insulating layer 57.

[0073] The conductive layer 23 is connected to the upper layer wiring MX disposed in the insulating layer 54 via the plug V0 disposed on the stacked body LM in the insulating layer 53. Additionally, the conductive layer 23 is connected to the peripheral circuit CUA via the lower layer wiring D2 disposed below the stacked body LM in the insulating layer 50. Therefore, the through contact C4 connects to components disposed on and below the stacked body LM.

[0074] Since the through contact C4 is placed in the insulating portion NR that does not include word lines WL, etc., and the conductive layer 23 of the through contact C4 is covered by the insulating layer 57, the withstand voltage between the through contact C4 and the word lines WL, etc. of the stacked body LM is maintained.

[0075] Notice, Figure 2BFor ease of explanation, components that do not necessarily lie on the same cross section are also illustrated, such as the columnar portion HR, which will be described later, and the through-joint C4, which are located in the through-joint area TP.

[0076] like Figure 2A and 2B The diagram illustrates that the stepped portions SP, SPf, and SPs are positioned within the stepped region SR. Each of the stepped portions SP, SPf, and SPs has a shape in which multiple word lines WL and multiple insulating layers OL are processed into a stepped shape.

[0077] Among these stepped portions SP, SPf, and SPs, the stepped portion SP has the function of electrically leading multiple word lines WL to the upper layer wiring MX. On the other hand, the entire stepped portion SPs formed by the word lines WL and the stepped portion SPf are virtual stepped portions that do not contribute to the function of the semiconductor memory device 1. These virtual stepped portions are also disposed at the two end portions of the stacked body LM along the X direction and the two end portions of the stacked body LM along the Y direction.

[0078] The stepped portion SP extends along the X direction away from the memory region MR near the through-junction TP, and decreases toward the memory region MR. The stepped portion SPf extends along the X direction so that it faces the stepped portion SP near the memory region MR, and decreases toward the stepped portion SP.

[0079] Stepped portions SPs are positioned near the plate contact LI, between stepped portions SP and SPf on one side along the Y direction. The stepped portions SPs extend along the Y direction so as to face the plate contact LI on the other side adjacent to the plate contact LI, and descend toward the plate contact LI on said other side.

[0080] Here, in the stepped sections SPf and SPs, the platform portion of each step is shorter than the platform portion of the stepped section SP. Therefore, the stepped sections SPf and SPs have a steeper shape than the stepped section SP, and the step length (i.e., the length from the uppermost step to the lowermost step) is less than the step length of the stepped section SP.

[0081] When the stepped portions SP, SPf, and SPs are arranged in this manner, the stacked main body LM has a mortar-shaped recess in the stepped region SR. In this mortar-shaped region, an insulating layer 51 (e.g., a silicon oxide layer) acting as a sixth insulating layer is arranged to cover the upper surface of the stepped portions SP, SPf, and SPs. The insulating layers 52 to 54 described above also cover the upper surface of the insulating layer 51.

[0082] In the stepped region SR, an insulating layer 51 is disposed on the stepped portions SP, SPf, and SPs, with insulating layers, such as silicon nitride layers (not illustrated), interspersed therebetween. The insulating layers (not illustrated) are disposed in a stepped shape along the word line WL and the select gate lines SGD and SGS.

[0083] The contact CC, which penetrates the insulating layers 52 and 51, is connected to the word line WL and the select gate lines SGD and SGS that constitute the corresponding steps of the stepped portion SP. In addition, the contact CC connected to the select gate line SGD is also disposed in the stepped portion of the stepped portion SPf formed by the select gate line SGD.

[0084] The contact CC includes an insulating layer 56 covering the outer periphery of the contact CC and a conductive layer 22, such as a tungsten layer or a copper layer, filling the inner side of the insulating layer 56. The conductive layer 22 is connected to the upper layer wiring MX disposed in the insulating layer 54 via a plug V0 disposed in the insulating layer 53. As described above, for example, the upper layer wiring MX is connected via a board contact LI to an adjacent through contact C4 in the Y direction through the contact region TP.

[0085] With this configuration, the word line WL of the corresponding layer, as well as the select gate lines SGD and SGS of the upper and lower layers of the word line WL, can be electrically led out. That is, with the above configuration, a predetermined voltage is applied from the peripheral circuit CUA through the through contact C4, contact CC, word line WL, etc., to the memory cell MC, and the memory cell MC can operate as a memory element.

[0086] Here, Figure 2B The diagram illustrates the cross-section of the third step, starting from the lowest step of the stepped portion SP. That is, Figure 2B The diagram illustrates that the second character line WL, starting from the bottommost character line WL, becomes part of the platform surface. Figure 2B In the diagram, stepped portions SP are positioned on both sides of the plate joint LI, illustrated in the central portion of the stepped region SR, along the Y direction. Stepped portions SPs are positioned on the sides of the plate joint LI opposite to each stepped portion SP along the Y direction.

[0087] In addition, multiple columnar portions HR that penetrate the insulating layer 51, the stacked main body LM, the upper source line DSLb and the intermediate insulating layer SCO and reach the lower source line DSLa are dispersedly arranged in the stepped region SR containing the stepped portions SP, SPf and SPs.

[0088] The columnar sections HR, which act as multiple second pillars, are arranged in an alternating or grid pattern to avoid interfering with the junction CC. For example, each of the columnar sections HR has a circular, elliptical, oval, or similar cross-sectional shape along the XY plane.

[0089] For example, each of the plurality of columnar portions HR does not have a portion corresponding to the charge accumulation layer CT between the layers of the column PL described above, and therefore does not contribute to the function of the semiconductor memory device 1. As will be described later, when a stacked body LM is formed from a stacked body having a sacrificial layer, the columnar portions HR serve to support the stacked body in which the sacrificial layer and the insulating layer are stacked.

[0090] More specifically, the columnar portion HR includes virtual layers TBd, CNd, and CRd extending along the stacking direction in the stacked body LM.

[0091] like Figure 2E The diagram illustrates that the virtual layer TBd has a multi-layer structure, in which virtual layer BKd, which acts as the fourth insulating layer, and virtual layer TNd, which acts as the third insulating layer, are stacked sequentially from the outer periphery of the columnar portion HR. The virtual layer TBd corresponds to the memory layer ME of the column PL described above, and the virtual layers BKd and TNd contained in the virtual layer TBd correspond to the blocking insulating layer BK and the tunnel insulating layer TN of the column PL, respectively.

[0092] However, unlike the memory layer ME of the columnar PL, the virtual layer TBd does not contain a layer corresponding to the charge accumulation layer CT. Furthermore, the virtual layer TBd is disposed on the side surface of the columnar portion HR without interruption from the upper source line DSLb to the lower source line DSLa. The virtual layer TBd is also disposed at the lower end of the columnar portion HR.

[0093] The virtual layer CNd penetrates the insulating layer 51, the stacked main body LM, the upper source line DSLb, and the intermediate insulating layer SCO on the inside of the virtual layer TBd and reaches the lower source line DSLa. The virtual layer CNd corresponds to the channel layer CN of the pillar PL described above.

[0094] However, the virtual layer TBd is disposed on the side surface of the virtual layer CNd extending from the upper source line DSLb to the lower source line DSLa, and the virtual layer CNd does not directly contact the intermediate insulating layer SCO. The virtual layer CRd, which acts as a second insulating layer, fills the other inner side of the virtual layer CNd. The virtual layer CRd corresponds to the core layer CR of the pillar PL described above and acts as the core material of the pillar portion HR.

[0095] Additionally, a virtual layer CPd is disposed at the upper end portion of each of the plurality of columnar portions HR. The virtual layer CPd is disposed in insulating layer 52 to cover at least the upper end portion of virtual layer CNd and is connected to virtual layer CNd. The virtual layer CPd corresponds to the top cover layer CP of column PL described above. Note that columnar portions HR do not necessarily contain virtual layer CPd.

[0096] Each layer contained in the columnar portion HR contains a material of the same type as the corresponding layer in column PL. That is, for example, the virtual layers BKd and TNd of the virtual layer TBd and the virtual layer CRd are silicon oxide layers, etc. The virtual layers CNd and CPd are semiconductor layers, such as polycrystalline silicon layers or amorphous silicon layers. Here, the semiconductor layers contained in the virtual layers CNd, etc., have a Young's modulus, for example, higher than that of the materials contained in the other virtual layers BKd, TNd, and CRd, and have the properties of being hard and almost non-deformable.

[0097] Note that multiple columnar sections HR are also distributed throughout the through-connection area TP to avoid interfering with the through-connection C4. Additionally, multiple columnar sections HR are also distributed at the two ends of the stacked main body LM along the X and Y directions within the virtual stepped section.

[0098] Next, Figure 3 The diagram illustrates the arrangement of the corresponding components in the stepped region SR. Figure 3 This is a top view including the stepped region SR of the semiconductor memory device 1 according to an embodiment. However, in Figure 3 Some components are omitted, such as insulating layers 51 to 54, plugs V0 and CH, bit line BL, and upper layer wiring MX. Note that the multiple dashed lines illustrated in the stepped portions SP and SPf represent the corresponding steps of the stepped portions SP and SPf.

[0099] like Figure 3 The diagram illustrates that multiple board contacts LI are aligned along the Y-axis and extend along the X-axis from the memory region MR to the stepped region SR within the stacked body LM. The region obtained by dividing the stacked body LM using multiple board contacts LI is also called the block region BLK.

[0100] Within the block region BLK, the select gate line SGD is further separated by multiple isolation layers SHE. The isolation layers SHE are insulating layers, such as silicon oxide layers, that penetrate the select gate line SGD and reach the insulating layer OL immediately below the select gate line SGD.

[0101] The isolation layer SHE extends along the X direction from the memory region MR in the stacked body LM to the uppermost step of the stepped portion SPf, i.e., the stepped portion formed by the select gate line SGD. Furthermore, on the stepped portion SP side facing the stepped portion SPf along the X direction, the isolation layer SHE extends along the X direction from the stepped portion formed by the select gate line SGD (which is the uppermost step of the stepped portion SP) to the memory region MR positioned further away along the X direction in the stacked body LM.

[0102] In other words, since the isolation layer SHE penetrates one or more conductive layers containing the uppermost conductive layer of the stacked body LM and extends in the X direction within the stacked body LM, these conductive layers are divided into segments of multiple selected gate lines SGD.

[0103] In the stepped portion SPf formed by the select gate line SGD, the contact CC connected to the select gate line SGD is disposed in each region isolated by the isolation layer SHE. Additionally, the contact CC connected to the select gate line SGS or the word line WL is disposed in each region BLK obtained by dividing the stepped portion SPf using the board contact LI in the stepped portion formed by the select gate line SGS and the word line WL.

[0104] Additionally, as described above, in the stepped portion of the SP formed by the selected gate line SGD, that is, in Figure 3 At the upper part of the memory region (not illustrated), the contact CC connected to the select gate line SGD is located in each region isolated by the isolation layer SHE. As described above, since the contact CC is located in both the stepped portions SP and SPf for the select gate line SGD which is further divided into multiple regions in the block region BLK, a predetermined voltage can be applied to the individual select gate STD on both sides along the X direction in the memory region MR.

[0105] The columnar portions HR are dispersedly arranged above the entire stepped region SR, which includes the stepped portions SP, SPf, and SPs. At the same height position of the stacked main body LM, the cross-sectional area of ​​the columnar portions HR in the direction along the XY plane is larger than, for example, the cross-sectional area of ​​the column PL in the direction along the XY plane. In addition, the spacing between the multiple columnar portions HR is larger than, for example, the spacing between the multiple columns PL, and the arrangement density of columnar portions HR per unit area of ​​word lines WL in the stacked main body LM is lower than the arrangement density of column PL per unit area of ​​word lines WL.

[0106] As described above, for example, because the column PL has a smaller cross-sectional area and smaller spacing compared to the columnar portion HR, a large number of memory cells MC can be formed in a high density within a stacked body LM of a predetermined size, and the storage capacity of the semiconductor memory device 1 can be increased. Furthermore, for example, unlike the column PL, the columnar portion HR is only used to support the stacked body LM and therefore does not have a precise configuration regarding the small cross-sectional area and small spacing, thus reducing the manufacturing burden.

[0107] (Method for manufacturing semiconductor memory devices)

[0108] Next, we will refer to Figures 4A to 14CA method for manufacturing a semiconductor memory device 1 according to an embodiment is described. Figures 4A to 14C This is a view illustrating, in sequence, portions of a procedure for manufacturing a semiconductor memory device 1 according to an embodiment. Note that it is assumed that... Figures 4A to 14C As illustrated in the diagram, the peripheral circuit CUA has been formed on the substrate SB and the insulating layer 50 covering the peripheral circuit CUA has been formed.

[0109] first, Figures 4A to 4C The diagram illustrates how the stepped SP section is formed. Figures 4A to 4C The diagram illustrates the cross-section along the Y direction of the region that will later become the stepped region SR.

[0110] like Figure 4A The diagram illustrates that these layers are formed on insulating layer 50 in the following order: lower source line DSLa, intermediate insulating layer SCO, and upper source line DSLb. For example, the intermediate insulating layer SCO is a silicon oxide layer, etc.

[0111] Additionally, a stacked body LMs is formed on the upper source line DSLb, in which multiple insulating layers NL and multiple insulating layers OL are stacked alternately. For example, the insulating layer NL is a silicon nitride layer, etc., and serves as a sacrificial layer that will later be replaced with a conductive material and become the word line WL and the select gate lines SGD and SGS.

[0112] like Figure 4B The illustration shows that in a certain region of the stacked host LMs, insulating layers NL and OL are cut down in a stepped shape to form a stepped portion SP. The stepped portion SP is formed by repeatedly thinning the mask pattern (e.g., a photoresist layer) and etching the insulating layers NL and OL of the stacked host LMs.

[0113] That is, a mask pattern with openings corresponding to the locations where the stepped portions SP will be formed is formed on the upper surface of the stacked main bodies LMs, and, for example, insulating layers NL and OL are etched away one by one. By using oxygen plasma or the like, the ends of the openings in the mask pattern are recessed to widen the openings, and the insulating layers NL and OL are further etched away one by one. By repeating this process multiple times, the insulating layers NL and OL in the openings of the mask pattern are excavated downwards in a stepped shape.

[0114] Furthermore, each time the above process is repeated a predetermined number of times, a new mask pattern is formed again, ensuring that the thickness of the mask pattern is equal to or greater than a predetermined value. At this time, by adjusting the position of the openings in the mask pattern, relatively gently sloping stepped portions SP and steep virtual stepped portions SPf and SPs are formed. Similarly, by adjusting the positions of the end portions of the mask patterns at the two end portions of the stacked bodies LMs along the X direction and the two end portions of the stacked bodies LMs along the Y direction, steep virtual stepped portions similar to stepped portions SPf and SPs are formed at the four end portions of the stacked bodies LMs, respectively.

[0115] Figure 4B This is a cross-sectional view of the third step from the bottom step of the stepped portion SP formed in this way. Figure 4B The cross-section illustrated herein will be divided into two stepped portions SP by the plate joint LI that will be formed later. The stepped portions SPs are formed on one side of the stacked main bodies LMs of each stepped portion SP along the Y direction.

[0116] like Figure 4C As illustrated in the diagram, an insulating layer 51, such as a silicon oxide layer, is formed covering the stepped portions SP and reaching the height of the upper surface of the stacked main bodies LMs. Specifically, the insulating layer 51 is formed in the mortar-shaped region surrounded by the stepped portions SP, SPs, and SPf. At this time, an insulating layer (not illustrated) is formed along the stepped shape of the insulating layer NL in the stepped portions SP, and an insulating layer 51 is formed in the stepped region SR via said insulating layer.

[0117] Additionally, an insulating layer 51 is formed in the peripheral region of the four end portions of the stacked main bodies LMs, each forming a virtual step-like portion. Furthermore, an insulating layer 52 is formed on the upper surface of these layers, covering the upper surface of the stacked main bodies LMs and the upper surface of the insulating layer 51.

[0118] Next, Figures 5A to 8Bc This diagram illustrates how to form the column PL and the columnar portion HR. Similar to... Figures 4A to 4C , Figures 5A to 5C The diagram illustrates the cross-section along the Y direction of the region containing the stepped portion SP.

[0119] like Figure 5A The diagram illustrates that multiple holes HL are formed in a mortar-shaped region surrounded by stepped portions SP, SPs and SPf, penetrating insulating layers 52 and 51, stacked main bodies LMs, upper source line DSLb and intermediate insulating layer SCO, and reaching the lower source line DSLa.

[0120] like Figure 5BThe diagram illustrates the formation of a dummy layer TBd within the via HL. Simultaneously, a dummy layer TBd is also formed on the upper surface of the insulating layer 52. As described above, the dummy layer TBd comprises dummy layers BKd and TNd, such as silicon oxide layers, and there is no layer between the dummy layers BKd and TNd corresponding to the charge accumulation layer CT of the pillar PL.

[0121] like Figure 5C The diagram illustrates that a virtual layer CNd is formed inside the virtual layer TBd within the hole HL. A virtual layer CNd is also formed on the upper surface of the insulating layer 52, with virtual layers TBd interposed therebetween. As described above, the virtual layer CNd is a semiconductor layer, such as a polycrystalline silicon layer or an amorphous silicon layer.

[0122] Additionally, a virtual layer CRd (e.g., a silicon oxide layer) fills the inside of the virtual layer CNd within the via HL. A virtual layer CRd is also formed on the upper surface of the insulating layer 52, with virtual layers TBd and CNd interposed therebetween.

[0123] Figures 6A to 6C The diagram illustrates the cross-section along the Y direction of the region that will later become the memory region MR. However, the pillar PL has circular, elliptical, oval, and other shapes, as described above, and therefore, the pillar PL has a similar cross-sectional shape regardless of the orientation of the cross-section.

[0124] like Figure 6A As illustrated in the diagram, in the region where the memory region MR will be formed, stacked bodies LMs are formed on the lower source line DSLa, the intermediate sacrificial layer SCN, and the upper source line DSLb, and an insulating layer 52 is formed on the stacked bodies LMs. The intermediate sacrificial layer SCN includes a silicon nitride layer, etc., and is later replaced with a conductive polysilicon layer, etc., to become an intermediate source line BSL. In this state, a plurality of memory vias MH are formed that penetrate the insulating layer 52 and the stacked bodies LMs and reach the lower source line DSLa.

[0125] like Figure 6B The diagram illustrates that a memory layer ME is formed within the memory aperture MH, wherein a barrier insulating layer BK, a charge accumulation layer CT, and a tunnel insulating layer TN are stacked in order from the outer periphery of the memory aperture MH. The memory layer ME is also formed on the upper surface of the insulating layer 52. As described above, for example, the barrier insulating layer BK and the tunnel insulating layer TN are silicon oxide layers, and for example, the charge accumulation layer CT is a silicon nitride layer, etc.

[0126] like Figure 6C As illustrated in the diagram, a channel layer CN, such as a polysilicon layer or an amorphous silicon layer, is formed on the inner side of the memory layer ME. A channel layer CN is also formed on the upper surface of the insulating layer 52, with the memory layer ME interposed therebetween.

[0127] In addition, the core layer CR (e.g., a silicon oxide layer) fills the other inner side of the channel layer CN. The core layer CR is also formed on the upper surface of the insulating layer 52, with the memory layer ME and the channel layer CN interposed therebetween.

[0128] Notice, Figures 5A to 6C The processing order described above can be changed. That is, Figures 6A to 6C The processing can be done Figures 5A to 5C Execute before processing.

[0129] In addition, Figures 5A to 6C The process illustrated in the diagram can be executed in parallel except for the process of forming a virtual layer TBd in the hole HL and the process of forming a memory layer ME in the memory hole MH.

[0130] That is, the processes of forming holes HL in the stepped portion SP and forming memory holes MH in the memory region MR can be performed in parallel. In addition, the processes of forming virtual layers CNd and CRd in holes HL and forming channel layer CN and core layer CR in memory holes MH can be performed in parallel.

[0131] When a virtual layer TBd is formed in a hole HL, a mask layer or similar material can be used to close the memory hole MH, and when a memory layer ME is formed in a memory hole MH, a mask layer or similar material can be used to close the hole HL.

[0132] Figures 7Aa to 8Bc The diagram illustrates the cross-section along the Y direction of both the region that will later become the memory region MR and the region containing the stepped portion SP. That is, Figures 7Aa to 8Bc Aa to Ac is a cross-sectional view along the Y direction of the region that will later become the memory region MR, and Figures 7Aa to 8Bc The Ba to Bc diagram illustrates the cross-section along the Y direction for the region containing the stepped portion SP. Figures 7Aa to 8Bc The processing of Aa to Ac in the code.

[0133] like Figure 7Aa The diagram illustrates the etching back process performed on the upper surface of the insulating layer 52 and the core layer CR within the memory hole MH. During this process, by selectively etching the core layer CR while using the underlying channel layer CN as a stop layer, a portion of the core layer CR within the memory hole MH is recessed relative to the channel layer CN, thus forming a recess DN at the upper end of the memory hole MH. Furthermore, the core layer CR on the upper surface of the insulating layer 52 is removed to expose the channel layer CN.

[0134] like Figure 7AbThe diagram illustrates the etching back process performed on the upper surface of the insulating layer 52 and the channel layer CN in the memory hole MH. During this process, selective etching of the channel layer CN is achieved by using the underlying memory layer ME as a stop layer relative to the memory layer ME. This causes a portion of the channel layer CN in the memory hole MH to recede downwards, and the recess DN at the upper end of the memory hole MH to be enlarged. The upper end of the core layer CR protrudes at the center of the recess DN. Furthermore, the channel layer CN on the upper surface of the insulating layer 52 is removed to expose the memory layer ME.

[0135] like Figure 7Ac The diagram illustrates the etching process, where the upper surface of the insulating layer 52 and the memory layer ME within the memory hole MH are etched back. The etching amount is adjusted so that the underlying insulating layer 52 is not removed. Therefore, a portion of the memory layer ME within the memory hole MH is recessed downwards, and the recess DN at the upper end of the memory hole MH is further enlarged. The upper portion of the core layer CR protruding from the center of the recess DN is also removed, making the bottom surface of the recess DN substantially flat. Additionally, the memory layer ME on the insulating layer 52 is removed to expose the insulating layer 52.

[0136] control Figure 7Aa to 7Ac The processing makes it possible to Figure 7Ac After the treatment, the bottom surface of the recess DN remains at the height position in the insulation layer 52 and does not reach the uppermost insulation layer NL.

[0137] like Figure 7Ba The diagram in the text illustrates that, through Figure 7Aa For the processing of the memory hole MH, the virtual layer CRd on the upper surface of the insulating layer 52 and in the hole HL is etched back, thus forming a recess DNr at the upper end of the hole HL. In addition, the virtual layer CRd on the upper surface of the insulating layer 52 is removed to expose the virtual layer CNd.

[0138] like Figure 7Bb The diagram in the text illustrates that, through Figure 7Ab For the processing of the memory hole MH, the dummy layer CNd on the upper surface of the insulating layer 52 and in the hole HL is etched back, thus enlarging the recess DNr at the upper end of the hole HL. The upper end of the dummy layer CRd protrudes at the center of the recess DNr. In addition, the dummy layer CNd on the upper surface of the insulating layer 52 is removed to expose the dummy layer TBd.

[0139] like Figure 7Bc The diagram in the text illustrates that, through Figure 7AcThe processing of the memory hole MH involves etching back the upper surface of the insulating layer 52 and the dummy layer TBd in the hole HL, thereby further enlarging the recess DNr at the upper end of the hole HL. The upper end portion of the dummy layer CRd protruding at the center of the recess DNr is also removed, making the bottom surface of the recess DNr substantially flat. Furthermore, the dummy layer TBd on the insulating layer 52 is removed to expose the insulating layer 52.

[0140] like Figure 8Aa and 8Ba The diagram illustrates that the interiors of the recesses DN and DNr are filled with polycrystalline silicon layers, amorphous silicon layers, etc., to form the top cap layer CP and the virtual layer CPd, respectively.

[0141] like Figure 8Ab and 8Bb The diagram illustrates that the upper surface of each of the insulating layer 52, the capping layer CP, and the dummy layer CPd is etched back. Therefore, the thickness of the insulating layer 52, the capping layer CP, and the dummy layer CPd is reduced.

[0142] like Figure 8Ac and 8Bc The diagram illustrates that the thickness of the insulating layer 52, which is reduced by etch-back, is increased by additionally stacking the insulating layer 52. Therefore, the upper surfaces of the capping layer CP and the virtual layer CPd are covered by the insulating layer 52.

[0143] As described above, multiple pillars PL and multiple pillar sections HR are formed. However, at this stage, the channel layer CN of the pillar PL is entirely covered by the memory layer ME and is not connected to the intermediate sacrificial layer SCN, which will later become the intermediate source line BSL.

[0144] Note that the columnar portion HR is a virtual component that does not contribute to the functionality of the semiconductor memory device 1. Therefore, the columnar portion HR need not contain the virtual layer CPd, and no virtualization is required on the columnar portion HR. Figure 8Ba to 8Bc The treatment. In this case, the recess DNr of the columnar portion HR can be backfilled with, for example, an insulating layer 52, etc.

[0145] Next, Figures 9A to 11Bb The diagram illustrates how the intermediate source line BSL and word line WL are formed.

[0146] Similar to Figure 8Aa to 8Ac etc, Figures 9A to 10C The diagram illustrates a cross-section along the Y direction of the region that will later become the memory region MR.

[0147] like Figure 9AThe diagram illustrates the formation of a slit ST that penetrates the insulating layer 52, the stacked main bodies LMs, and the upper source line DSLb, reaching the intermediate sacrificial layer SCN. The slit ST also extends along the X direction within the stacked main bodies LMs.

[0148] like Figure 9B The diagram illustrates that an insulating layer 55p is formed on the sidewalls of the slit ST facing each other along the Y direction.

[0149] and Figure 9A and 9B In parallel processing, a contact hole that will later become a through contact C4 and a slit that will later become a board portion BR can be formed in the through contact area TP.

[0150] That is, when in Figure 9A When the slit ST is formed, a contact hole is formed that penetrates the insulating layer 52, the stacked main bodies LMs, and the source line SL and reaches the insulating layer 50. In addition, a slit is formed that penetrates the insulating layer 52, the stacked main bodies LMs, and the upper source line DSLb and reaches the middle insulating layer SCO so as to clamp the contact hole from both sides along the Y direction.

[0151] In addition, when in Figure 9B When an insulating layer 55p is formed on the sidewall of the slit ST, an insulating layer is also formed on the sidewall and bottom surfaces of the contact hole and the slit. Subsequently, a sacrificial layer (e.g., an amorphous silicon layer) fills the other inner side of the insulating layer in the contact hole, and the contact hole is protected from the processing.

[0152] like Figure 9C The diagram illustrates how a removal liquid (e.g., hot phosphoric acid) for the intermediate sacrificial layer SCN flows through a slit ST protected by an insulating layer 55p on the sidewall, removing the intermediate sacrificial layer SCN sandwiched between the lower source line DSLa and the upper source line DSLb.

[0153] Therefore, gap layers GPs are formed between the lower source line DSLa and the upper source line DSLb. Furthermore, a portion of the memory layer ME in the outer periphery of the pillar PL is exposed within the gap layers GPs. At this time, since the sidewalls of the slit ST are protected by the insulating layer 55p, the removal of the insulating layer NL in the stacked main bodies LMs is also suppressed.

[0154] like Figure 10A The diagram illustrates how appropriate flow of chemical liquid through the slit ST into the gap layers GPs sequentially removes the barrier insulation layer BK, charge accumulation layer CT, and tunnel insulation layer TN exposed within the gap layers GPs. Consequently, the memory layer ME is partially removed from the sidewall of the pillar PL, and the inner portion of the channel layer CN is exposed within the gap layers GPs.

[0155] like Figure 10BThe diagram illustrates, for example, that source gas (e.g., amorphous silicon) is injected from a slit ST protected by an insulating layer 55p on the sidewall to fill the interstitial layers GPs with amorphous silicon, etc. Additionally, the substrate SB is heat-treated to polycrystallineize the amorphous silicon filling the interstitial layers GPs, thereby forming an intermediate source line BSL containing polycrystalline silicon, etc.

[0156] Therefore, a portion of the channel layer CN of the pillar PL is connected to the source line SL via the intermediate source line BSL at the sidewall.

[0157] like Figure 10C The diagram illustrates the removal of the insulating layer 55p on the sidewall of the slit ST in one step.

[0158] It is preferable that the columnar portion HR of the virtual component does not conduct electricity with the source line SL. As described above, in the region where the columnar portion HR is located (e.g., the stepped region SR and the through-contact region TP, excluding the memory region MR), the intermediate sacrificial layer SCN is not placed between the lower source line DSLa and the upper source line DSLb, and the intermediate insulating layer SCO is placed between the lower source line DSLa and the upper source line DSLb. Therefore, in Figures 9A to 10C In the processing, in the stepped region SR, through-connection region TP, etc., the removal of intermediate sacrificial layer SCN, the removal of virtual layer TBd, the formation of intermediate source line BSL, etc. are not performed.

[0159] Figures 11Aa to 11Bb The diagram illustrates the cross-section along the Y direction of the region that will later become the memory region MR and the cross-section along the Y direction of the region that will later become the through-junction region TP. That is, similar to the description above. Figures 9A to 10C etc, Figure 11Aa and 11Ab This is a cross-sectional view along the Y direction of the region that will later become the memory region MR. Figure 11Ba and 11Bb The diagram illustrates the cross-sections along the Y direction of the area that will later become the through-joint region TP, corresponding to... Figure 11Aa and 11Ab The processing.

[0160] like Figure 11Aa The illustration shows, for example, that a removal liquid (e.g., hot phosphoric acid) for the insulating layer NL flows from the slit ST into the stacked bodies LMs to remove the insulating layer NL of the stacked bodies LMs, having already removed the insulating layer 55p from the sidewall of the slit. Thus, a stacked body LMg is formed comprising a plurality of gap layers GP obtained by removing the insulating layer NL between the insulating layers OL.

[0161] like Figure 11BaAs illustrated in the diagram, in the region that will later become the through contact area TP, an insulating layer 57 is formed on the sidewall and bottom surfaces, and contact holes C4s are formed therein, in which the inner side of the insulating layer 57 is filled with a sacrificial layer 23s. In addition, slits BRs are formed, each having a sidewall and a bottom surface on which an insulating layer 58 is formed, so as to clamp the contact holes C4s from both sides in the Y direction.

[0162] Furthermore, in this state, the insulating layer NL is removed through the above-described process in the memory region MR within the through-contact region TP, thus forming a stacked body LMG containing multiple gap layers GP. However, since the region forming the contact holes C4s is shielded by slits BRs that clamp the region from both sides along the Y direction, the removal liquid for the insulating layer NL does not flow into the region. Therefore, the insulating layer NL between the insulating layers OL is maintained in this region.

[0163] Note that the stacked body LMG, containing multiple gap layers GP, has a fragile structure. In the memory region MR, multiple pillars PL support this fragile stacked body LMG. In the through-junction region TP, multiple pillar-like portions HR support the stacked body LMG. The multiple pillar-like portions HR also support the stacked body LMG at both ends of the stacked body LMG along the X direction and at both ends of the stacked body LMG along the Y direction in the stepped region SR and the stepped portions.

[0164] The support structure of the column PL and columnar portion HR inhibits bending of the remaining insulation layer OL and twisting and collapse of the stacked main body LMg.

[0165] like Figure 11Ab and 11Bb The diagram illustrates that a source gas of a conductive material (e.g., tungsten or molybdenum) is injected into a stacked body LMG through a slit ST, and the gap layer GP of the stacked body LMG is filled with conductive material to form multiple word lines WL. Thus, a stacked body LM is formed in which multiple word lines WL and multiple insulating layers OL are alternately stacked. Furthermore, a select gate line SGS is formed below the bottommost word line WL, with insulating layers OL interposed between them.

[0166] However, in the area where the insulating layer NL is retained, word lines WL, etc., are not formed, and an insulating portion NR is formed in which multiple insulating layers NL and multiple insulating layers OL are stacked alternately.

[0167] As described above, the process of forming the intermediate source line BSL from the intermediate sacrificial layer SCN and the process of forming the word line WL from the insulating layer NL are also called replacement processes.

[0168] In the replacement process for word lines WL, etc., after removing the insulating layer NL of the stacked main bodies LMs through the slit ST, a layer containing a metal oxide (e.g., aluminum oxide) can be formed on the inner wall of the interstitial layer GP before filling the interstitial layer GP with a conductive material. In this case, the layer containing the metal oxide is formed on the upper and lower surfaces of the insulating layer OL along the stacking direction of the stacked main bodies LMs. Furthermore, a layer containing a barrier metal (e.g., titanium, titanium nitride, tantalum, or tantalum nitride) can be further inserted between this layer containing the metal oxide and the conductive material (e.g., tungsten or molybdenum) to suppress the diffusion of tungsten, molybdenum, etc., into other layers.

[0169] Here, in Figure 11Ab and 11Bb In this configuration, a conductive layer 24 is formed above the topmost word line WL, with an insulating layer OL interposed therebetween. The conductive layer 24 is patterned into a select gate line SGD by forming an isolation layer SHE, as described below.

[0170] Figures 12A to 12C A diagram illustrating how the isolation layer SHE is formed. Figures 12A to 12C The diagram illustrates a cross-section of the memory region MR along the Y direction, which differs from... Figure 11Aa , 11Ab The cross-section shown in the document.

[0171] like Figure 12A The diagram illustrates that, in the current process, multiple pillars PL are formed in the memory region MR at predetermined cycles.

[0172] like Figure 12B The diagram illustrates a recess TR that penetrates the insulating layer 52 and the conductive layer 24, which becomes the select gate line SGD, and extends substantially along the X direction within the stacked body LM. Here, since the semiconductor memory device 1 of the embodiment includes only one select gate line SGD, the recess TR penetrates the conductive layer 24 corresponding to the uppermost layer and reaches the insulating layer OL immediately below the conductive layer 24.

[0173] In addition, Figure 12B In the example illustrated, a groove TR is formed immediately on one of a plurality of columns PL arranged at a predetermined period. This is because the columns PL can also be arranged at the location where the isolation layer SHE is formed, thus maintaining the predetermined period of column arrangement when forming multiple columns PL.

[0174] In this scenario, the upper structure of the pillar PL disappears due to the groove TR, and no effective memory cell MC is formed in this pillar PL. Therefore, the pillar PL that forms the groove TR becomes a virtual pillar PLd that does not contribute to the function of the semiconductor memory device 1.

[0175] like Figure 12CAs illustrated in the diagram, the groove TR is filled with an insulating layer 59 (e.g., a silicon oxide layer). This forms an isolation layer SHE, allowing the conductive layer 24 above the word line WL to be patterned into the select gate line SGD.

[0176] Next, Figures 13 to 14C A diagram illustrating how to form a contact CC. Figure 13 It is a cross-sectional view along the X direction containing the memory region MR and the stepped region SR, and corresponds to Figure 2A . Figures 14A to 14C This is an enlarged cross-sectional view of the stepped portion SP along the X direction.

[0177] like Figure 13 The diagram illustrates the formation of word lines WL that penetrate insulating layers 52 and 51 and reach the corresponding steps constituting the stepped portion SP, as well as multiple contact holes HLc for select gate lines SGD and SGS. Additionally, a contact hole HLc is formed that penetrates insulating layer 52 and reaches the select gate line SGD of the uppermost step constituting the stepped portion SPf.

[0178] For example, multiple contact holes HLc are formed together. However, the contact holes HLc have different depths. Therefore, as described above, an insulating layer, such as a silicon nitride layer, is formed in advance to cover the stepped portions SP and SPf. In the following text, as... Figures 14A to 14C The diagram illustrates how multiple contact holes HLc are formed when an insulating layer is used as a stop layer.

[0179] like Figure 14A As illustrated in the diagram, for example, the upper and side surfaces of the word lines WL of each step in the stepped portion SP are covered by a stop layer STP that acts as a seventh insulating layer, with an insulating layer 51a, such as a silicon oxide layer, interspersed therebetween. The insulating layer 51 described above is formed on the stepped portion SP, with the insulating layer 51a and the stop layer STP interspersed therebetween.

[0180] However, the stop layer STP is positioned to avoid the location where the slit ST described above is formed and does not contact the slit ST. Therefore, when replacing it with, for example, a word line WL, it is important to prevent the stop layer STP from being replaced with a conductive layer or even a silicon nitride layer, etc.

[0181] When multiple contact holes HLc are formed in the stepped portion SP, selective etching conditions relative to the stop layer STP (such as a silicon nitride layer) can be used to selectively remove insulating layers 52 and 51 (such as a silicon oxide layer). Therefore, the etching of the contact holes HLc can be temporarily stopped when the bottom surfaces of the multiple contact holes HLc reach the stop layer STP at different depths.

[0182] like Figure 14BAs illustrated in the diagram, etching of the stop layer STP is then performed. Therefore, the lower portions of the multiple contact holes HLc penetrate the stop layer STP at different depths and reach the insulating layer 51a beneath the stop layer STP.

[0183] like Figure 14C As illustrated in the diagram, thereafter, by using selective etching conditions relative to the word line WL (e.g., tungsten layer, etc.), the bottom surface of each contact hole HLc reaches the corresponding word line WL, thereby enabling the selective removal of the insulating layer 51a.

[0184] Therefore, for example, it is possible to form multiple contact holes HLc with different arrival depths while suppressing penetration of the word line WL to be connected. However, Figure 14B Processing for removing the stop layer STP in the middle and Figure 14C The process of removing insulating layer 51a can be performed together. In this case, for example, selective etching conditions relative to word line WL can be used to make it possible to remove both stop layer STP and insulating layer 51a.

[0185] Subsequently, an insulating layer 56 is formed covering the sidewalls of the contact hole HLc (see...). Figure 2A ), and conductive layer 22 (see Figure 2A The insulating layer 56 is filled on the other inner side. This forms multiple contacts CC that connect to the multiple word lines WL and the select gate lines SGD and SGS.

[0186] After forming contact CC in the stepped portions SP and SPf, or before forming contact CC, a through contact C4 is formed in the through contact region TP. That is, the sacrificial layer 23s in the contact hole C4s and the insulating layer 57 on the bottom surface of the contact hole C4s are removed, and the conductive layer 23 (see Figure 2B The insulating layer 57 on the sidewall of the fill contact hole C4s is filled. Thus, a through contact C4 is formed, which is connected to the peripheral circuit CUA via the lower layer wiring D2 in the insulating layer 50.

[0187] Additionally, an insulating layer 55 is formed on the sidewall of the slit ST before or during the formation of the through-connector C4, and the inner side of the insulating layer 55 is filled with a conductive layer 21 to form a board contact LI that will become a source line contact. However, the insulating layer 55, etc., can be filled with the slit ST without forming the conductive layer 21, and a board component that does not function as a source line contact can be formed.

[0188] Additionally, an insulating layer 53 is formed on the insulating layer 52, and a plug V0 is formed that penetrates the insulating layer 53 and connects to each of board contact LI, through contact C4, and contact CC. Furthermore, a plug CH is formed that penetrates the insulating layers 53 and 52 and connects to the post PL. Moreover, an insulating layer 54 is formed on the insulating layer 53, and upper layer wiring MX, bit line BL, etc., are formed that are respectively connected to the plugs V0 and CH.

[0189] For example, plugs V0 and CH, upper layer routing MX, bit lines BL, etc., can be formed together by using dual damascene methods, etc.

[0190] Semiconductor memory device 1, as described above in the manufacturing embodiments.

[0191] In the manufacturing of semiconductor memory devices (e.g., three-dimensional non-volatile memory), a stacked body containing conductive and insulating layers can be formed by replacing a sacrificial layer in the stacked body with a conductive layer. In this case, to support the fragile stacked body containing multiple gap layers during replacement, columnar portions can be arranged, for example, in stepped regions, etc. For example, the columnar portions have a structure in which an insulating layer (e.g., a silicon oxide layer) fills holes penetrating the stacked body.

[0192] However, in cases where the columnar portions are formed of insulating layers, the insulating layers contained within the columnar portions can shrink due to heat treatment during subsequent manufacturing processes. Furthermore, due to the shrinkage of multiple columnar portions, the entire stepped region, etc., in which these columnar portions are arranged, can sink along the stacking direction of the stacked body compared to other regions (e.g., memory regions). That is, the upper surface of the mid-segment semiconductor memory device exhibits unevenness during manufacturing. The sinking caused by the shrinkage of the columnar portions is more pronounced in stepped regions, etc., covered by a single insulating layer than in through-hole regions, etc., with a stacked structure.

[0193] When this sinking occurs, for example, in some cases during processes using photolithography, the sunken area is not focused and is not properly exposed. Additionally, for example, in removal processes where metal material filling holes, grooves, etc., is polished from the upper surface of a stacked body, polishing residue of the metal material can be generated in the area where sinking has occurred.

[0194] According to the embodiment of the semiconductor memory device 1, the columnar portion HR includes a virtual layer CRd extending along the stacking direction of the stacked body LM, a virtual layer CNd covering the sidewall of the virtual layer CRd, a virtual layer TNd covering the sidewall of the virtual layer CNd, and a virtual layer BKd covering the sidewall of the virtual layer TNd, without inserting a layer corresponding to the charge accumulation layer CT.

[0195] As described above, the dummy layer CNd, which is a semiconductor layer, has a higher Young's modulus than, for example, an insulating layer (e.g., a silicon oxide layer), and is rigid and has almost no thermal shrinkage properties. Since the columnar portion HR contains the dummy layer CNd, thermal shrinkage of the columnar portion HR can be suppressed, and sinking of the stepped region SR, etc., in which the columnar portion HR is disposed can be suppressed relative to other regions.

[0196] Furthermore, for example, even in semiconductor layers with high Young's modulus, polymerization can occur due to heat treatment as the volume of the semiconductor layer increases. Since the virtual layer CRd is placed as the core material of the columnar portion HR and covered by a thin virtual layer CNd, it is possible to suppress the polymerization of the virtual layer CNd and further suppress the sinking of the stepped region SR.

[0197] Furthermore, when the slit ST is formed, the slit ST and its adjacent columnar portion HR may come into contact with each other due to positional displacement, widening of the slit ST, etc. In cases where the columnar portion HR contains a silicon nitride layer corresponding to the charge accumulation layer CT, the silicon nitride layer of the columnar portion HR in contact with the slit ST may be exposed within the slit ST. Therefore, when the insulating layer NL is replaced with a word line WL, there is a possibility that part or all of the silicon nitride layer inside the columnar portion HR may be replaced by a conductive layer via the exposed portion. Consequently, a conductive layer may be formed inside the columnar portion HR at locations spanning multiple word lines WL, and therefore, there is a possibility that the withstand voltage between the multiple word lines WL may be insufficient.

[0198] By utilizing the configuration in which the columnar portion HR does not contain a layer corresponding to the charge accumulation layer CT, and even in the case where the columnar portion HR becomes in contact with the slit ST, it is possible to suppress the insufficient withstand voltage of the word line WL and suppress the influence on the electrical characteristics of the semiconductor memory device 1.

[0199] Furthermore, in the case where the slit ST and the columnar portion HR become contacted with each other and the dummy layer CNd of the columnar portion HR is exposed in the slit ST, the exposed surface of the dummy layer CNd may be oxidized by subsequent processing, and an insulating layer 55 is formed on the sidewall of the slit ST after the replacement process with the word line WL. Therefore, for example, electrical conduction between the dummy layer CNd exposed in the slit ST and the conductive layer 21 that subsequently fills the slit ST is suppressed.

[0200] As described above, in the semiconductor memory device 1 of the embodiment, the structure of the columnar portion HR supporting the stacked main body LM can be optimized.

[0201] (First modified example)

[0202] Next, we will refer to Figures 15A to 17A semiconductor memory device 2 according to a first modified example of an embodiment is described. The first modified example of the semiconductor memory device 2 differs from the embodiment described above in that, in addition to the columnar portion HR described above, it also has a columnar portion HRm having the same layer structure as the column PL. Hereinafter, the same reference numerals are assigned to the same components as those in the embodiment described above, and their description may be omitted.

[0203] Figures 15A to 15C This is a cross-sectional view illustrating an example of the configuration of the stepped portion SP2 of a semiconductor memory device 2 according to a first modified example of an embodiment. Figure 15A It is a cross-sectional view along the Y direction containing the stepped region SR2. Figure 15B This is a partially enlarged view illustrating the cross-section of the columnar portion HR placed in the stepped region SR2. Figure 15C This is a partially enlarged view illustrating the cross-section of the columnar portion HRm placed in the stepped region SR2.

[0204] like Figure 15A As illustrated in the diagram, two types of columnar portions HR and HRm with different layer structures are dispersedly arranged in the stepped region SR2 of the semiconductor memory device 2.

[0205] The columnar portions HR are arranged side-by-side along the plate joint LI in the X direction at least adjacent to the plate joint LI in the Y direction. The columnar portions HR may be distributed throughout the stepped region SR, except for the positions adjacent to the joint CC.

[0206] like Figure 15B As illustrated in the diagram, the columnar portion HR has the same configuration as the columnar portion HR included in the semiconductor memory device 1 of the embodiment described above. That is, Figure 15B The embodiments described above Figure 2E same.

[0207] The columnar portion HRm, which acts as the third pillar, extends along the stacking direction of the stacked body LM and is arranged at least near the contact CC so as to surround the contact CC when viewed from the stacking direction of the stacked body LM. The columnar portion HRm may be distributed throughout the stepped area SR, except for the position near the board contact LI.

[0208] like Figure 15C As illustrated in the diagram, for example, the columnar portion HRm has the same layer structure as the column PL. That is, the columnar portion HRm contains virtual layers CRd, CNd, MEd, and CPd.

[0209] The virtual layer CRd, which acts as the second insulating layer, is a component corresponding to the core layer CR of the pillar PL, and is a silicon oxide layer (first oxide layer) that penetrates the insulating layer 51, the stacked main body LM, the upper source line DSL and the middle insulating layer SCO and reaches the lower source line DSLa, etc.

[0210] The virtual layer CNd is a component corresponding to the channel layer CN of the pillar PL, and is a semiconductor layer, such as a polycrystalline silicon layer or an amorphous silicon layer, covering the sidewalls and bottom surface of the virtual layer CRd.

[0211] The virtual layer MEd is a component corresponding to the memory layer ME of the cylinder PL, and covers the sidewalls and bottom surface of the virtual layer CNd. The virtual layer MEd also covers the sidewalls of the virtual layer CNd at a height corresponding to the intermediate insulating layer SCO.

[0212] The virtual layer MEd has a stacked structure in which a virtual layer BKd, which acts as a fourth insulating layer, a virtual layer CTd, which acts as a fifth insulating layer, and a virtual layer TNd, which acts as a third insulating layer (corresponding to the barrier insulating layer BK, the charge accumulation layer CT, and the tunnel insulating layer TN of the pillar PL, respectively), are stacked sequentially from the outer periphery of the pillar portion HRm. For example, the virtual layers TNd and BKd are silicon oxide layers (second and third oxide layers), etc., and for example, the virtual layer CTd is a silicon nitride layer (first nitride layer), etc.

[0213] The virtual layer CPd is a component corresponding to the top cover layer CP of the pillar PL, and is a semiconductor layer, such as a polycrystalline silicon layer or an amorphous silicon layer, disposed at the upper end of the pillar portion HRm in the insulating layer 52. However, the pillar portion HRm does not necessarily contain the virtual layer CPd.

[0214] As described above, the difference between columnar portion HRm and columnar portion HR is that columnar portion HRm includes a virtual layer CTd corresponding to the charge accumulation layer CT.

[0215] Next, Figure 16 The diagram illustrates the arrangement of the corresponding components in the stepped region SR2. Figure 16 This is a top view of the stepped region SR2 of the semiconductor memory device 2 according to a first modified example of the embodiment. However, in Figure 16 Some components are omitted, such as insulating layers 51 to 54, plugs V0 and CH, bit line BL, and upper layer wiring MX.

[0216] like Figure 16As illustrated in the diagram, for example, the cross-sectional area of ​​the columnar portion HRm along the XY plane is approximately the same as that of the columnar portion HR along the XY plane. Multiple columnar portions HR and HRm are arranged as a whole in a predetermined period within the stepped region SR2 while avoiding interference with the contact CC.

[0217] exist Figure 16 In this example, the columnar portion HRm is arranged to surround the contact CC, which is connected to the word line WL and the select gate lines SGD and SGS. Additionally, the columnar portion HR is arranged to surround the contact CC at a position further outward than the columnar portion HRm. That is, the columnar portions HR are distributed throughout the entire stepped region SR2, except for the position adjacent to the contact CC.

[0218] However, as described above, the columnar portion HR can be exclusively arranged along the plate joint LI at a position adjacent to the plate joint LI, and the columnar portion HRm can be distributed in the entire stepped region SR2 at positions other than those adjacent to the plate joint LI.

[0219] Furthermore, note that in the through-joint area TP and the virtual stepped section, at both ends of the stacked main body LM along the X and Y directions, columnar portions HR and HRm can be arranged in these areas, provided that the columnar portion HR is arranged at least near the board joint LI. However, it is more convenient to arrange only the columnar portions HR dispersedly at the ends of the stacked main body LM in the through-joint area TP and the virtual stepped section, without arranging the columnar portions HRm.

[0220] The configuration of the semiconductor memory device 2 as described above, for example, can be obtained by forming a columnar portion HRm together with the column PL.

[0221] When a contact hole HLc is formed in the stepped portion SP2, the contact hole HLc may come into contact with the columnar portion HRm near the contact hole HLc. Several possible reasons exist that could lead to contact between the contact hole HLc and the columnar portion HRm, as described below.

[0222] One of the reasons is the contact hole HLc (when forming the contact CC) or the hole HL (see Figure 5A At least one of the following (when forming the columnar portion HRm) is tilted relative to the substrate SB, for example, due to the oblique incidence of ions in the plasma. Another reason, for example, is the distortion that occurs in the stacked body LMG when replacing with word lines WL, so that the formed columnar portion HRm is tilted.

[0223] Another reason is that when the contact point CC is formed, the contact hole HLc is formed in a state that causes a positional displacement relative to the columnar portion HRm.

[0224] Figure 17 The diagram illustrates an example where the contact hole HLc and the columnar portion HRm are in contact with each other.

[0225] Figure 17 This is a cross-sectional view along the X direction illustrating how a contact hole HLc is formed in the stepped portion SP2 of a semiconductor memory device 2 according to a first modified example of an embodiment. Figure 17 In the example illustrated in the diagram, since the contact hole HLc is inclined, the lower end of the contact hole HLc contacts the columnar portion HRm.

[0226] exist Figure 17 In the example, the columnar portion HRm has a cavity NST in the dummy layer CRd. This cavity NST can be formed by creating an unfilled portion when the dummy layer CRd, for example, fills the hole HL with the core material that serves as the columnar portions HR and HRm.

[0227] As described above, in the case where the columnar portion HRm has a cavity NST in the virtual layer CRd, if the etching continues to the inside of the columnar portion HRm and reaches the cavity NST when the contact hole HLc is formed, there is a possibility that the cavity NST will also be filled by the conductive layer 22 when the contact hole HLc is filled with the conductive layer 22.

[0228] However, when forming the contact hole HLc, as described above, the insulating layer 51, which serves as the fourth oxide layer, is etched selectively relative to the stop layer STP, which serves as the second nitride layer, formed on the stepped portion SP2, so that the lower end portion of the contact hole HLc remains on the stop layer STP.

[0229] Therefore, although the portion of the virtual layer BKd in the outermost peripheral part of the columnar portion HRm that contacts the contact hole HLc may be etched away, the virtual layer CTd inside the virtual layer BKd serves as an etch stop layer and inhibits further etching into the columnar portion HRm.

[0230] Subsequently, when the stop layer STP on the word line WL is removed, the dummy layer CTd in the columnar portion HRm can also be removed. However, at that time, the dummy layer TNd inside the dummy layer CTd is used as a stop layer. Additionally, when the insulating layer 51a on the upper surface of the word line WL is removed, for example, even if the dummy layer TNd in the columnar portion HRm is removed, the dummy layer CNd located further inside the columnar portion HRm is used as a stop layer.

[0231] According to the first modified example of the semiconductor memory device 2, the columnar portion HRm having the same layer structure as the column PL is disposed closer to the contact CC than the columnar portion HRm, and the stop layer STP containing the same material type as the virtual layer CTd of the columnar portion HRm is disposed on a plurality of word lines WL and select gate lines SGD and SGS processed into a stepped shape.

[0232] Therefore, even in cases where the contact hole HLc and the columnar portion HRm come into contact with each other, etching is stopped by the dummy layer CTd, and the conductive layer 22 of the contact CC may be suppressed from filling the cavity NST in the dummy layer CRd. Thus, for example, conduction between the contact CC and the columnar portion HRm, or conduction between the contact CC and another word line WL via the columnar portion HRm, is suppressed.

[0233] Even in cases where a stop layer STP is set on multiple word lines WL that are not processed into a stepped shape in the stepped portion SP2, as well as on the select gate lines SGD and SGS, a virtual layer CTd containing a material different from the insulating layer 51 is placed in the columnar portion HRm, so that the virtual layer CTd can be used as a stop layer to resist etching toward the inside of the columnar portion HRm when forming the contact hole HLc.

[0234] According to the first modified example of the semiconductor memory device 2, other effects similar to those of the embodiments described above are obtained.

[0235] (Second modified example)

[0236] The columnar portion HRm of the first modified example described above can be used in combination with columnar portions that replace the columnar portion HRm described above as a single insulating layer. In this case, the ratio between the columnar portion that serves as a single insulating layer and the columnar portion HRm described above can be appropriately adjusted according to the degree of sinking in the stepped region SR2, etc. That is, when the proportion of the columnar portion HRm in the stepped region SR2 increases, the sinking of the stepped region SR2, etc., can be further suppressed.

[0237] Furthermore, in cases where the columnar portion as a single insulating layer is used in combination with the columnar portion HRm described above, as described below, the manufacturing process of the semiconductor memory device can be simplified by using the columnar portion HRm, whose diameter is increased relative to the columnar portion as a single insulating layer.

[0238] The following text will refer to Figures 18 to 20CThe second modified example of the semiconductor memory device 3 is described. The second modified example of the semiconductor memory device 3 differs from the first modified example of the semiconductor memory device described above in that the semiconductor memory device 3 includes a pillar-shaped portion HRk as a single insulating layer. Hereinafter, the same reference numerals are assigned to the same components as those of the first modified example described above, and their description may be omitted.

[0239] Figure 18 This is a cross-sectional view along the Y direction illustrating an example of the configuration of the stepped portion SP3 of a semiconductor memory device 3 according to a second modified example of an embodiment.

[0240] like Figure 18 The diagram illustrates that the semiconductor memory device 3 includes two types of columnar portions HRg and HRk with different sizes and layer structures in the stepped region SR3. Multiple columnar portions HRg and HRk are arranged as a whole in the stepped region SR3 at a predetermined period while avoiding interference with board contacts LI and CC.

[0241] The columnar portion HRg, which acts as the third pillar, has the same configuration as the columnar portion HRm included in the semiconductor memory device 2 of the first modified example described above. However, the cross-sectional area of ​​the columnar portion HRg in the direction along the XY plane is larger than (for example) the cross-sectional area of ​​the columnar portion HRm in the direction along the XY plane.

[0242] More specifically, the columnar portion HRg includes a virtual layer CRd that serves as a first oxide layer, extending along the stacking direction within the insulating layer 51 and the stacked body LM. Additionally, the columnar portion HRg includes a virtual layer CNd, which is a semiconductor layer, etc., covering the sidewalls of the virtual layer CRd. Furthermore, the columnar portion HRg includes a virtual layer MEd that covers the sidewalls of the virtual layer CNd.

[0243] The virtual layer MEd includes a virtual layer TNd that acts as a second oxide layer, a virtual layer CTd that acts as a first nitride layer covering the sidewalls of the virtual layer TNd, and a virtual layer BKd that acts as a third oxide layer covering the sidewalls of the virtual layer CTd.

[0244] In addition, the columnar portion HRg may contain a virtual layer CPd, such as a semiconductor layer.

[0245] The columnar portion HRg is arranged at least near the contact point CC so as to surround the contact point CC when viewed from the stacking direction of the stacked body LM. At this time, in order to suppress the sinking of the stepped region SR3, it is preferable to distribute the columnar portion HRg throughout the stepped region SR3 except for the position near the plate contact LI.

[0246] For example, the columnar portion HRk, which acts as the second pillar, contains a single dummy layer BKd. The dummy layer BKd is a layer corresponding to the barrier insulating layer BK of the pillar PL, and is, for example, a silicon oxide layer, etc.

[0247] The cross-sectional area of ​​the columnar portion HRk in the direction along the XY plane (for example) is smaller than the cross-sectional area of ​​the columnar portion HRg in the direction along the XY plane, and is equal to or smaller than the cross-sectional area of ​​the columnar portion HR included in the semiconductor memory device 2 of the first modified example described above.

[0248] The columnar portions HRk are arranged side-by-side along the plate joint LI in the X direction, at least at a position adjacent to the plate joint LI in the Y direction. In this case, as described above, in order to suppress the subsidence of the stepped region SR3, it is preferable to restrict the position of the easily thermally shrinkable columnar portions HRk to the smallest possible area near the plate joint LI.

[0249] Note that in the second modified example of the semiconductor memory device 3, the columnar portions HRg and HRk may also be arranged at a predetermined ratio at the end portion of the stacked body LM in the through-contact region TP and the virtual step-like portion.

[0250] Figures 19A to 20C This is a view illustrating, in sequence, a portion of the procedure for manufacturing a semiconductor memory device 3 according to a second modified example of an embodiment. Figures 19A to 20C The diagram illustrates a cross-section along the Y direction containing the stepped region SR3, corresponding to the description above. Figure 18 The cross-section of the columnar portions HRg and HRk will be described in detail below.

[0251] like Figure 19A The diagram illustrates the formation of multiple holes HLg and HLk that penetrate insulating layers 52 and 51, stacked main bodies LMs, upper source line DSLb, and intermediate insulating layer SCO, reaching the lower source line DSLa. Hole HLg is formed to have a diameter larger than that of hole HLk.

[0252] like Figure 19B The diagram illustrates the formation of a virtual layer BKd within multiple holes HLg and HLk. For example, after forming a virtual layer BKd with a thickness approximately the same as the barrier insulating layer BK in the pillar PL, further formation of the virtual layer BKd continues. In this way, due to the size difference between holes HLg and HLk, the virtual layer BKd covers the sidewalls and bottom surface of hole HLg and substantially completely fills hole HLk. This forms the pillar-shaped portion HRk. A virtual layer BKd is also formed on the upper surface of the insulating layer 52.

[0253] like Figure 19C As illustrated in the diagram, virtual layers CTd and TNd are stacked sequentially on the inside of virtual layer BKd in via HLg to form virtual layer MEd, further forming virtual layer CNd, and the inside of virtual layer CNd is filled with virtual layer CRd. Virtual layer MEd, containing the previously formed virtual layer BKd, is also formed on the upper surface of insulating layer 52. Additionally, virtual layer CNd is formed on the upper surface of insulating layer 52, with virtual layers MEd interposed therebetween, and virtual layer CRd further covers virtual layer CNd.

[0254] At this point, since the columnar portion HRk is already filled with the virtual layer BKd, the virtual layers CTd, TNd, CNd and CRd are not formed in the holes HLk of the columnar portion HRk.

[0255] like Figure 20A The diagram illustrates that the dummy layer CRd is etched back onto the upper surface of the insulating layer 52 and within the hole HLg to form a recess at the upper end portion of the hole HLg. The dummy layer CNd is exposed on the upper surface of the insulating layer 52. The dummy layer CRd is also removed from the upper surface of the columnar portion HRk.

[0256] like Figure 20B The diagram illustrates that the virtual layer CNd is etched back onto the upper surface of the insulating layer 52 and into the hole HLg to enlarge the recess at the upper end of the hole HLg. The virtual layer MEd is exposed on the upper surface of the insulating layer 52. The virtual layer CNd is also removed from the upper surface of the columnar portion HRk.

[0257] Additionally, the virtual layer MEd on the upper surface of the insulating layer 52 and in the hole HLg is etched back to further enlarge the recess at the upper end of the hole HLg. Therefore, the virtual layer MEd is also removed from the upper surface of the insulating layer 52 to expose the upper surface of the columnar portion HRk.

[0258] like Figure 20C As illustrated in the diagram, the recessed portion of the upper end of the via HLg is filled with a virtual layer CPd, and the upper end of the virtual layer CPd is etched back together with the insulating layer 52. This forms the columnar portion HRg. Furthermore, in the above process, the virtual layer CPd is not formed at the upper end of the columnar portion HRk. Subsequently, an etched-back insulating layer 52 is stacked to cover the upper surfaces of the columnar portions HRg and HRk.

[0259] In this way, the columnar portions HRg and HRk of the second modified example are formed.

[0260] As described above, the columnar portion HRg has a larger diameter than the columnar portion HRk, allowing them to be formed together. Therefore, columnar portions HRg and HRk with different layer structures can be densely formed as a whole in the stepped region SR3, etc., at a predetermined period.

[0261] In addition, Figures 19A to 19C In the process illustrated in the diagram, when forming the barrier insulating layer BK of the pillar PL, the process of forming the virtual layer BKd in the holes HLg and HLk can be performed in parallel. After forming the barrier insulating layer BK of the desired thickness in the memory hole MH, the memory hole MH is protected with a mask layer, etc., and as described above, the process of forming the virtual layer BKd in the holes HLg and HLk continues until the hole HLk is substantially completely filled.

[0262] Furthermore, even after the formation of the virtual layer BKd, the processes of forming the charge accumulation layer CT, tunnel insulation layer TN, channel layer CN, core layer CR, and capping layer CP in the column PL, and the processes of forming the virtual layers CTd, TNd, CNd, CRd, and CPd in ​​the columnar portion HRg can be performed in parallel. However, as in the embodiment described above, the columnar portion HRg need not include the virtual layer CPd, and can be skipped. Figures 20A to 20C Treatment of HRg and HRk in columnar sections.

[0263] For example, other methods for manufacturing semiconductor memory device 3 are similar to the methods for manufacturing semiconductor memory device 1 of the embodiments described above.

[0264] In the above examples, the columnar portions HRg and HRk are made to be of different sizes, and together they form columnar portions HRg and HRk. However, these columnar portions can be formed individually by making the size of the columnar portion that serves as a single insulating layer substantially the same as the size of the columnar portion having the same layer structure as column PL.

[0265] As described above, in the first and second modified examples, each includes an oxide layer extending along the stacking direction of the stacked body LM and columnar portions HRm and HRg of a nitride layer extending along the stacking direction of the stacked body LM at predetermined positions in the oxide layer, which are arranged at least near the contact CC, such that it is possible to suppress the sinking of the stacked body LM while allowing the columnar portions HRm and HRg to contact the contact CC.

[0266] Additionally, in the first and second modified examples, columnar portions HR and HRk, each comprising one or more oxide layers, are disposed at least near the plate contact LI, and do not contain a nitride layer corresponding to the charge accumulation layer CT of the column PL, thereby making it possible for the columnar portions HR and HRk to contact the plate contact LI.

[0267] (Other modified examples)

[0268] In the embodiments described above and the first and second modified examples, the stepped portions SP and SP2, etc., are disposed in the central portion of the stacked body LM and are held by the memory region MR. However, for example, the contact CC may be disposed in the stepped portions on one or both sides of the stacked body LM along the X direction to have the function of leading out word lines WL, etc. Furthermore, in this case, the configuration of the columnar portions HR, HRm, HRg, and HRk, etc., in the embodiments described above and the first and second modified examples can be applied.

[0269] In the embodiments described above and the first and second modified examples, the pillar PL is connected to the source line SL on the side surface of the channel layer CN, but is not limited thereto. For example, the pillar can be connected to the source line at the lower end portion of the channel layer by removing the memory layer on the bottom surface of the pillar.

[0270] Furthermore, in the embodiments described above and the first and second modified examples, insulating layers NL and OL are stacked alternately to form stacked bodies LMs. However, stacked bodies LMs can be formed in multiple layers, and in this case, pillars PL, pillar portions HR, HRm, HRg and HRk, step portions SP and SP2, etc., can be formed in stages each time a layer of stacked bodies LMs is formed. Therefore, the number of stacked word lines WL can be further increased.

[0271] In the embodiments described above, as well as the first and second modified examples, the peripheral circuitry CUA is disposed below the stacked body LM. However, the peripheral circuitry CUA may be disposed above the stacked body LM or in the same layer as the stacked body LM.

[0272] In the case where the peripheral circuit CUA is disposed on the stacked body LM, for example, the peripheral circuit CUA may be formed on a semiconductor substrate different from the substrate on which the stacked body LM is formed, and the semiconductor substrate on which the peripheral circuit CUA is formed may be bonded to the upper surface of the stacked body LM.

[0273] In cases where the peripheral circuitry CUA is positioned on the same layer as the stacked body LM, the stacked body LM can be formed on the semiconductor substrate on which the peripheral circuitry CUA is formed. Using this configuration, a polysilicon layer or similar layer can be formed as a source line on the semiconductor substrate, or impurities can be diffused into the surface layer of the semiconductor substrate, allowing a portion of the semiconductor substrate to be used as a source line. In this case, the semiconductor memory device does not need to include a through-connection region TP.

[0274] While specific embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. In fact, the novel embodiments described herein can be embodied in various other forms; furthermore, various omissions, substitutions, and changes can be made to the forms of the embodiments described herein without departing from the spirit of the invention. It is intended that the appended claims and their equivalents cover such forms or modifications that fall within the scope and spirit of the invention.

Claims

1. A semiconductor memory device, comprising: A stacked body comprising a plurality of conductive layers and a plurality of first insulating layers stacked alternately and including a stepped portion in which the plurality of conductive layers are processed into a stepped shape. The first pillar extends away from the stepped portion in the stacked body along the stacking direction of the stacked body in a first direction intersecting the stacking direction and forms a memory cell at each intersection point with at least a portion of the plurality of conductive layers. and Multiple second pillars, which extend along the stacking direction in the stepped portion of the stacked body, wherein The first column includes A second insulating layer extends in the stacked body along the stacking direction. A semiconductor layer that covers the sidewalls of the second insulating layer. A third insulating layer covers the sidewalls of the semiconductor layer. A fourth insulating layer, which covers the sidewalls of the third insulating layer, and A charge accumulation layer, containing an insulating material of a different type than that of the third and fourth insulating layers, is inserted between the third and fourth insulating layers. Each of the plurality of second pillars includes The second insulating layer extends in the stacked body along the stacking direction. The semiconductor layer covers the sidewalls of the second insulating layer. The third insulating layer covers the sidewalls of the semiconductor layer, and The fourth insulating layer covers the sidewall of the third insulating layer, and no charge accumulation layer is inserted between the third insulating layer and the fourth insulating layer.

2. The semiconductor memory device according to claim 1, wherein The third and fourth insulating layers are oxide layers, and the charge accumulation layer is a nitride layer.

3. The semiconductor memory device according to claim 1, further comprising: The first plate component and the second plate component extend along the stacking direction and the first direction at positions away from each other along a second direction intersecting the stacking direction and the first direction, wherein... The plurality of second columns are distributed between the first plate component and the second plate component.

4. The semiconductor memory device according to claim 1, further comprising: A contact, which is disposed in the stepped portion and connected to one of the plurality of conductive layers; and A plurality of third posts, which extend along the stacking direction in the stepped portion of the stacked body at a location closer to the joint than the plurality of second posts, wherein Each of the plurality of third pillars has the same layer structure as the first pillar.

5. The semiconductor memory device according to claim 4, wherein When viewed from the stacking direction, the plurality of third pillars surround the junction.

6. The semiconductor memory device of claim 5, further comprising: The first plate component and the second plate component extend along the stacking direction and the first direction at positions away from each other along a second direction intersecting the stacking direction and the first direction, wherein... At least a portion of the plurality of second pillars are arranged along the first plate component and the second plate component.

7. A semiconductor memory device, comprising: A stacked body comprising a plurality of conductive layers and a plurality of insulating layers stacked alternately and including a stepped portion in which the plurality of conductive layers are processed into a stepped shape. The first pillar extends away from the stepped portion in the stacked body along the stacking direction of the stacked body in a first direction intersecting the stacking direction and forms a memory cell at each intersection point with at least a portion of the plurality of conductive layers. and Multiple second pillars and multiple third pillars extend along the stacking direction in the stepped portion of the stacked body, wherein Each of the plurality of third pillars includes An oxide layer extending along the stacking direction, and A nitride layer extends along the stacking direction at a predetermined position inside the oxide layer, and Each of the plurality of second pillars includes One or more oxide layers extending along the stacking direction, without including the nitride layer.

8. The semiconductor memory device according to claim 7, wherein Each of the plurality of third pillars includes A first oxide layer extends in the stacked body along the stacking direction. A semiconductor layer that covers the sidewalls of the first oxide layer. A second oxide layer covers the sidewalls of the semiconductor layer. A first nitride layer covers the sidewalls of the second oxide layer, and A third oxide layer covers the sidewalls of the first nitride layer.

9. The semiconductor memory device according to claim 8, wherein Each of the plurality of second pillars includes The first oxide layer extends along the stacking direction in the stacked body. The semiconductor layer covers the sidewalls of the first oxide layer. The second oxide layer covers the sidewalls of the semiconductor layer, and The third oxide layer covers the sidewall of the second oxide layer.

10. The semiconductor memory device of claim 8, further comprising: The first plate component and the second plate component extend along the stacking direction and the first direction at positions away from each other along a second direction intersecting the stacking direction and the first direction, wherein... At least a portion of the plurality of second pillars are arranged along the first plate component and the second plate component.

11. The semiconductor memory device of claim 8, further comprising: A contact, which is disposed in the stepped portion and connected to one of the plurality of conductive layers, wherein The plurality of third posts are positioned closer to the junction than the plurality of second posts and surround the junction when viewed from the stacking direction.

12. The semiconductor memory device of claim 11, wherein... When viewed from the stacking direction, at least a portion of the plurality of second pillars surrounds the junction at a position farther than the position of the plurality of third pillars.

13. The semiconductor memory device of claim 11, further comprising: A fourth oxide layer covers the upper side of the plurality of conductive layers processed into the stepped shape in the stepped portion and has a flush upper surface. and A second nitride layer is disposed between the plurality of conductive layers and the fourth oxide layer along the stepped shape of the plurality of conductive layers in the stepped portion and is penetrated by the junction together with the fourth oxide layer.

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