Semiconductor device and method of manufacturing the same
By forming a second insulating layer with a composite structure between the conductive pillar and the contact pad, the short circuit problem caused by excessive lateral etching in three-dimensional memory devices is solved, thereby improving the reliability and performance of the devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2022-12-09
- Publication Date
- 2026-06-16
AI Technical Summary
In the fabrication of 3D memory devices, short circuits caused by excessive lateral etching affect the reliability and performance of the devices.
A second insulating layer is formed between the conductive pillar and the contact pad, comprising a stacked first dielectric layer, a second dielectric layer and a third dielectric layer, which prevents short circuits caused by excessive lateral etching.
This improves the component reliability and performance of semiconductor devices, avoids short circuit problems caused by excessive lateral etching at the bottom of conductive pillars, and enhances the reliability and performance of the device.
Smart Images
Figure CN116322060B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor device, and more particularly to a three-dimensional memory device and a method for fabricating the same. Background Technology
[0002] In modern electronic products, memory plays an indispensable and crucial role. Besides storing user data, memory is also responsible for storing program code executed by the central processing unit (CPU) and information that needs to be temporarily saved during computation. Memory can be divided into volatile memory and non-volatile memory. Common volatile memory includes dynamic random access memory (DRAM) and static random access memory (SRAM), whose data is lost after power is turned off and must be re-entered when power is restored. Non-volatile memory includes read-only memory (ROM) and flash memory, whose stored data persists even when power is cut off, allowing direct retrieval of previously stored valid data upon power restoration.
[0003] NAND flash memory boasts advantages such as small size, low power consumption, fast write speed, and low manufacturing cost, making it the most widely used non-volatile memory. With advancements in semiconductor manufacturing processes, NAND flash memory has evolved from planar structures to three-dimensional (3D) stacking to achieve higher cell density per unit wafer area, meeting the demand for higher storage capacity. However, as the number of layers in the memory stacking structure gradually increases, related manufacturing processes and device structures require further improvement to maintain good device performance while simplifying the manufacturing process. Summary of the Invention
[0004] The purpose of this invention is to provide a semiconductor device with an additional second isolation layer of a composite layer structure to effectively avoid short circuit problems caused by excessive lateral etching, thereby improving the component reliability and performance of the semiconductor device.
[0005] The present invention aims to provide a method for fabricating a semiconductor device by additionally forming a second insulating layer between the stacked layers and the contact pads. This second insulating layer effectively prevents short circuits caused by excessive lateral etching during via formation. Consequently, the resulting semiconductor device exhibits optimized component reliability and performance.
[0006] The present invention aims to provide a semiconductor device, including a substrate, a plurality of contact pads, and a plurality of conductive pillars. The contact pads are disposed separately within a first insulating layer and located on the substrate. The plurality of conductive pillars are disposed separately within a second insulating layer and respectively contact each of the contact pads. The second insulating layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked on the sidewalls of the conductive pillars, wherein the first dielectric layer simultaneously physically contacts both the second dielectric layer and the third dielectric layer.
[0007] The present invention aims to provide a method for fabricating a semiconductor device, comprising the following steps: First, a substrate is provided, and a plurality of contact pads are formed on the substrate, which are spaced apart within a first insulating layer. Then, a plurality of conductive pillars are formed on the substrate, which are spaced apart within a second insulating layer. Each conductive pillar contacts one of the contact pads and includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked on the sidewalls of the conductive pillar, wherein the first dielectric layer simultaneously physically contacts both the second dielectric layer and the third dielectric layer. Attached Figure Description
[0008] The accompanying drawings are provided to give a more in-depth understanding of this embodiment and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams for illustrative and drafting purposes, and relative dimensions and scales have been adjusted. The same symbols represent corresponding or similar features in different embodiments.
[0009] Figures 1 to 10 The illustration is a schematic diagram of a method for fabricating a semiconductor device according to a first embodiment of the present invention, wherein:
[0010] Figure 1 This is a schematic cross-sectional view of a semiconductor device after the formation of a metal oxide material layer.
[0011] Figure 2 This is a cross-sectional schematic diagram of a semiconductor device after patterning fabrication.
[0012] Figure 3 This is a cross-sectional schematic diagram of a semiconductor device after the first processing step.
[0013] Figure 4 This is a cross-sectional schematic diagram of a semiconductor device after undergoing the second processing fabrication process.
[0014] Figure 5 This is a schematic cross-sectional view of a semiconductor device after the formation of stacked layers.
[0015] Figure 6This is a cross-sectional schematic diagram of a semiconductor device after the first etching process.
[0016] Figure 7 This is a cross-sectional schematic diagram of a semiconductor device after the second etching process.
[0017] Figure 8 This is a schematic cross-sectional view of a semiconductor device after the mask layer has been formed.
[0018] Figure 9 This is a schematic cross-sectional view of a semiconductor device after a via has been formed; and
[0019] Figure 10 This is a schematic cross-sectional view of a semiconductor device after the conductive pillars have been formed.
[0020] Figures 11 to 12 The illustration is a schematic diagram of a method for fabricating a semiconductor device according to a second embodiment of the present invention, wherein:
[0021] Figure 11 This is a schematic cross-sectional view of a semiconductor device after a via has been formed; and
[0022] Figure 12 This is a schematic cross-sectional view of a semiconductor device after the conductive pillars have been formed.
[0023] Figures 13 to 14 The illustration is a schematic diagram of a method for fabricating a semiconductor device according to a third embodiment of the present invention, wherein:
[0024] Figure 13 This is a schematic cross-sectional view of a semiconductor device after a via has been formed; and
[0025] Figure 14 This is a schematic cross-sectional view of a semiconductor device after the conductive pillars have been formed.
[0026] Figure 15 The diagram shown is a cross-sectional schematic of a semiconductor device according to a preferred embodiment of the present invention.
[0027] The reference numerals in the attached figures are explained as follows:
[0028] 100 substrate
[0029] 110 Insulation Layer
[0030] 112 Plug
[0031] 114 First Insulation Layer
[0032] 116 Contact Pad
[0033] 118 Insulation layer
[0034] 120 Metal oxide material layer
[0035] 122, 124, 126 metal oxide patterns
[0036] 128, 228, 328 dielectric layers
[0037] 130 Stack Layer Structure
[0038] 130a Conductive-Dielectric Layer Pair
[0039] 132 Dielectric Layer
[0040] 134 Conductive Layer
[0041] 140, 142, 144 through holes
[0042] 152, 252, 352 dielectric layers
[0043] 154 Barrier Layer
[0044] 156 mask layers
[0045] 160, 260, 360 Second Insulation Layer
[0046] 170, 270, 370 conductive pillars
[0047] Barrier layers 172, 272, and 372
[0048] 174, 274, 374 conductive layers
[0049] 200, 300, 400 semiconductor devices
[0050] 340 through hole
[0051] 410-digit contact plug
[0052] 470-channel structure
[0053] 472 Channel Layer
[0054] 474 Fill layer
[0055] 500 3D NAND storage devices
[0056] P1 and P2 processing techniques
[0057] E1, E2, E3, E4 Etching Processes Detailed Implementation
[0058] To enable those skilled in the art to further understand this invention, several preferred embodiments are listed below, and the composition and desired effects of the invention are explained in detail with reference to the accompanying drawings. Those skilled in the art can, without departing from the spirit of the invention, substitute, recombine, or mix features from the following embodiments to complete other embodiments.
[0059] Figures 1 to 10 The illustration is a schematic diagram of a method for fabricating a semiconductor device 200 according to a first embodiment of the present invention. First, please refer to... Figure 1 As shown, a substrate 100 is provided, which may be, for example, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, or a substrate made of other suitable materials. A plurality of plugs 112 are further formed on the substrate 100 within an insulating layer 110 above the substrate 100. The insulating layer 110 includes, for example, an insulating material such as silicon dioxide or silicon oxynitride, while the plugs 112 include a conductive material such as aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), or copper (Cu), preferably tungsten, but not limited thereto. In one embodiment, other films (not shown) may be additionally disposed between the substrate 100 and the insulating layer 110, but this is not a limitation. Furthermore, the specific number of plugs 112 can be adjusted according to actual needs, and is not limited thereto. Figure 1 The examples shown are limited to those shown.
[0060] Then, a plurality of contact pads 116 are formed on the substrate 100, disposed within the first insulating layer 114 and respectively contacting the plugs 112 below. The first insulating layer 114 includes, for example, an insulating material such as silicon oxide or silicon oxynitride, preferably the same material as the insulating layer 110, while the contact pads 116 also include a conductive material such as aluminum, titanium, tantalum, tungsten, or copper, preferably tungsten, but not limited thereto. In one embodiment, the fabrication of the contact pads 116 includes, but is not limited to, the following steps. First, an insulating material layer (not shown) is formed on the insulating layer 110. A mask layer (not shown) is used to etch a plurality of trenches (not shown) within the insulating material layer to expose the plugs 112 below. A conductive material is filled into the trenches, and the mask layer is completely removed after a planarization process. Thus, the first insulating layer 114 and the contact pads 116 located within the first insulating layer 114 are formed on the substrate 100.
[0061] Again Figure 1 As shown, a metal oxide material layer 120 is formed on the substrate 100, which integrally covers the first insulating layer 114 and the contact pad 116. It should be noted that the metal oxide material layer 120 includes, for example, a material with a significant etch selectivity to the first insulating layer 114, such as aluminum oxide (Al2O3), titanium oxide, tantalum oxide, tungsten oxide, or copper oxide, preferably aluminum oxide, but not limited thereto.
[0062] like Figure 2 As shown, a patterning process is performed using another mask layer (not shown) to pattern the metal oxide material layer 120 into multiple metal oxide patterns 122, and then the other mask layer is completely removed. In detail, the metal oxide patterns 122 are formed on each contact pad 116 in a spaced manner, corresponding to each contact pad 116 and exposing the underlying first insulating layer 114.
[0063] like Figure 3 As shown, a processing technique P1 is performed, such as a wet etching process, to thin and finely adjust the size (including length and / or thickness) of each metal oxide pattern 122, forming multiple relatively small metal oxide patterns 124 to partially expose the underlying contact pads 116. This allows for more efficient control over the size (e.g., length) of each contact pad 116 exposed from each metal oxide pattern 124, but is not a limitation thereof.
[0064] like Figure 4 As shown, an insulating layer 118 is formed on the substrate 100, covering the sidewalls of each metal oxide pattern 124. The insulating layer 118 includes, for example, insulating materials such as silicon oxide and silicon oxynitride, and preferably includes the same material as the first insulating layer 114, but is not limited thereto. In one embodiment, the fabrication of the insulating layer 118 includes, but is not limited to, the following steps: First, a dielectric material (not shown) is formed to cover the metal oxide pattern 124, the underlying contact pad 116, and the first insulating layer 114. After a planarization process, an insulating layer 118 with its top surface flush with the top surface of the metal oxide pattern 124 is formed. Then, a processing process P2 is performed, such as a thermal oxidation process, in which heat and oxygen are introduced to modify the texture of each metal oxide pattern 124 into a more rigid and dense structure without changing its material composition. Thus, in subsequent etching processes (including wet etching or dry etching), each metal oxide pattern 124 can have a relatively large etching selectivity relative to the insulating layers 118 on both sides.
[0065] like Figure 5As shown, a stacked layer structure 130 with at least one stacked layer is formed on the metal oxide pattern 124 and the insulating layer 118. In this embodiment, the stacked layer structure 130 includes, for example, a plurality of alternately stacked dielectric layers 132 and a plurality of conductive layers 134, and each conductive layer 134 and the dielectric layer 132 above it together form a set of conductive-dielectric layer pairs 130a. The specific number of conductive-dielectric layer pairs 130a can be adjusted according to actual needs, and is not limited to... Figure 5 The examples shown are for illustrative purposes only. In detail, the conductive layer 134 may include, for example, a conductive material such as aluminum, titanium, tantalum, tungsten, copper, titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), titanium-tungsten (Ti / W), titanium and titanium nitride (Ti / TiN), polysilicon, doped silicon, metal silicide, or any combination thereof, preferably including tungsten. The dielectric layer 132 may include, for example, a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof, preferably including the same material as the first insulating layer 114 and / or the insulating layer 118, but is not limited thereto.
[0066] like Figure 6 As shown, an etching process E1 is performed using another mask layer (not shown), for example, a dry etching process, to etch the dielectric layers 132, the conductive layers 134, and the metal oxide pattern 124 to form a plurality of vias 140 within the stacked layer structure 130. Specifically, the dry etching process vertically etches the dielectric layers 132, the conductive layers 134, and a portion of the metal oxide pattern 124 downwards, such that the vias 140 can penetrate the stacked layer structure 130, and the metal oxide pattern 124 is partially etched, exposing a surface of the metal oxide pattern 124 below the top surface of the insulating layer 118.
[0067] like Figure 7 As shown, the etching process E2, using the aforementioned additional mask layer, is a wet etching process, further etching the metal oxide pattern 124 to form a plurality of vias 142 and a plurality of metal oxide patterns 126. Specifically, the wet etching process E2 is performed by, as... Figure 6 Each via 140 is vertically and simultaneously laterally etched with a metal oxide pattern 124 to integrally thin the metal oxide pattern 124, so that each metal oxide pattern 126 can have a U-shaped cross-sectional structure and is located at the bottom of each via 142. Then, the additional mask layer is completely removed.
[0068] like Figure 8As shown, a dielectric layer 152, a barrier layer 154, and a mask layer 156 are sequentially formed on the two opposite sidewalls of each via 142. The dielectric layer 152 may include, for example, a high dielectric constant dielectric material, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), zinc oxide (ZrO2), titanium oxide (TiO2), or a group thereof. The barrier layer 154 may include, for example, titanium, tantalum, titanium nitride, or tantalum nitride. The mask layer 156 may include a semiconductor material, such as amorphous silicon, but is not limited thereto. Specifically, the fabrication of the dielectric layer 152, barrier layer 154, and mask layer 156 includes, but is not limited to, the following steps. First, multiple deposition processes are performed on substrate 100 to sequentially form a dielectric material layer (not shown), a barrier material layer, and a mask material layer, which conformally cover the top surface of the stacked layer structure 130 and the inner surface of each via 142. Then, through a single etching process, the mask material layer, the barrier material layer, and the dielectric material layer covering the top surface of the stacked layer structure 130 and the bottom surface of each via 142 are removed, exposing each metal oxide pattern 126. This allows the dielectric layer 152 and the barrier layer 154 to have an L-shaped cross-sectional structure and to be sequentially stacked on the sidewalls of each via 142. The mask layer 156 is located on the barrier layer 154 and has an I-shaped cross-sectional structure.
[0069] like Figure 9 As shown, the mask layer 156 and barrier layer 154 are completely removed, exposing the dielectric layer 152. Then, the underlying metal oxide pattern 126 is patterned through the dielectric layer 152 to form multiple dielectric layers 128, partially exposing the top surfaces of the underlying contact pads 116. Simultaneously, multiple vias 144 are formed, each via 144 penetrating the stacked layer structure 130 and... Figure 8 The metal oxide patterns 124 are shown. Thus, each dielectric layer 128 can correspondingly have an L-shaped cross-sectional structure and is located at the bottom of each through-hole 144. Specifically, each dielectric layer 128 should be horizontally sandwiched between dielectric layers 152 and insulating layers 118 of different materials, and the horizontal portion of dielectric layer 128 and the horizontal portion of dielectric layer 152 have mutually flush inner sidewalls, while the vertical portion of dielectric layer 128 has inner sidewalls flush with the sidewall of dielectric layer 132 in the vertical direction. In this configuration, the stacked dielectric layers 152, 128, 132, and 118 can collectively form a second insulating layer 160 surrounding the bottom of each through-hole 144, wherein dielectric layer 152 simultaneously physically contacts both dielectric layer 132 and dielectric layer 128, such as... Figure 9As shown. It should be noted that the dielectric layer 152 (including a high dielectric constant dielectric material), the dielectric layer 128 (including a metal oxide material), and the dielectric layer 132 (including a dielectric material, such as the same as the first insulating layer 114) each include different materials, which can achieve a more optimized insulating effect.
[0070] Subsequently, such as Figure 10 As shown, a plurality of conductive pillars 170 are formed on the substrate 100, each located within a via 144 to electrically connect to a contact pad 116. Each conductive pillar 170 is disposed separately within the stacked layer structure 130 and the second insulating layer 160, and includes a barrier layer 172 and a conductive layer 174 stacked sequentially. In one embodiment, the barrier layer 172 may be made of materials such as titanium, tantalum, titanium nitride, or tantalum nitride, while the conductive layer 174 may be made of a metal material such as aluminum, titanium, tantalum, tungsten, or copper, but is not limited thereto. The fabrication of the conductive pillars 170 includes, but is not limited to, the following steps: First, a barrier material layer (not shown) is conventionally formed using a deposition process, covering the dielectric layer 152, the dielectric layer 128, and the contact pad 116, and a conductive material layer (not shown) is formed, at least filling the... Figure 9 The remaining space of the through-hole 144 shown is then used to form conductive pillars 170 through a planarization process. In this way, the bottom surface of each conductive pillar 170 can be coplanar with the bottom surface of the dielectric layer 128 and directly physically contact each contact pad 116.
[0071] Thus, the fabrication of the semiconductor device 200 in the first embodiment of the present invention is completed. According to this embodiment, the semiconductor device 200 has conductive pillars 170 disposed separately within a second insulating layer 160 to electrically connect to the contact pad 116. The second insulating layer 160 is formed by stacking dielectric layers 152, 128, and 132 of different materials with an insulating layer 118, thus having a composite layer structure. This effectively avoids the problem of short circuits at the bottom of the conductive pillars 170 caused by excessive lateral etching at the bottom of the vias 144, thereby improving the device reliability and performance of the semiconductor device 200.
[0072] On the other hand, according to the fabrication method of this embodiment, a metal oxide material layer 120 with significant etch selectivity is additionally formed between the stacked structure 130 and the contact pads 116, and a dielectric layer 128 with an L-shaped cross-section structure is formed by a two-stage etching process (including a wet etching process or a dry etching process). This dielectric layer 128 has a metal oxide material, such as alumina, with significant etch selectivity relative to the first insulating layer 114. Thus, the provision of the dielectric layer 128 effectively avoids the problem of short circuits at the bottom of the subsequently formed conductive pillars 170 due to excessive lateral etching during the formation of the via 144. Furthermore, it should be noted that due to the aforementioned wet etching process, the extension range of the dielectric layer 128 in the horizontal direction is significantly smaller than its extension range in the vertical direction, and also smaller than the extension range of each contact pad 116 in the horizontal direction. This further prevents short circuits caused by contact between the bottom sidewalls of the conductive pillars 170. Therefore, the semiconductor device 200 fabricated by the method of this embodiment has optimized device reliability and performance.
[0073] Those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor device and its formation method of the present invention may have other forms, and are not limited to those described above. The following will further describe other embodiments or variations of the semiconductor device and its formation method of the present invention. For the sake of simplicity, the following description focuses on the differences between the embodiments, without repeating the similarities. Furthermore, the same components in the various embodiments of the present invention are designated with the same reference numerals to facilitate comparison between the embodiments.
[0074] Please refer to Figures 11 to 12 The illustration is a schematic diagram of the fabrication method of the semiconductor device 300 in the second embodiment of the present invention. The front-end steps of the fabrication method in this embodiment are generally the same as those in the first embodiment described above, such as... Figures 1 to 6 As shown, it will not be described again here. The main difference between the formation method of this embodiment and the formation method of the first embodiment is that after the etching process E1, an etching process E3 is performed, such as a wet etching process, to further etch the metal oxide pattern 124 to form a plurality of through holes 244 and a plurality of dielectric layers 228.
[0075] In detail, such as Figure 11 As shown, the wet etching process E3 involves vertical and simultaneous lateral etching, as... Figure 6The metal oxide patterns 124 shown are thinned integrally until the underlying contact pads 116 are exposed to form a dielectric layer 228. Thus, the extension range of each dielectric layer 228 in the horizontal direction is significantly smaller than its extension range in the vertical direction, and it has a cross-sectional structure that is narrower at the top and wider at the bottom, and is located at the bottom of each via 244.
[0076] Then, as Figure 12 As shown, a dielectric layer 252, a barrier layer 272, and a conductive layer 274, comprising a high dielectric constant dielectric material, are sequentially formed within each via 244. The dielectric layer 252 covers only the two opposite sidewalls of each via 244, while the barrier layer 272 and the conductive layer 274 together form a conductive pillar 270. The barrier layer 272 conformally covers the dielectric layer 252, the dielectric layer 228, and the contact pad 116, while the conductive layer 274 fills the... Figure 11 The remaining space of the through hole 244 shown.
[0077] Thus, the fabrication of the semiconductor device 300 in the second embodiment of the present invention is completed. According to the fabrication method of the semiconductor device 300 in this embodiment, the dielectric layer 228 is directly formed by etching process E3. Thus, the fabrication method of this embodiment can omit the formation of the barrier layer 154 and the mask layer 156 in the previous embodiment. Under the premise of simplifying the fabrication process, a semiconductor device 300 with optimized device reliability and performance is obtained.
[0078] On the other hand, in the semiconductor device 300 according to this embodiment, a dielectric layer 228 (including a metal oxide material) is additionally provided between the dielectric layer 252 (including a high dielectric constant dielectric material) and the insulating layer 118 (including a dielectric material, for example, the same as the first insulating layer 114) of different materials. The horizontal portion of the dielectric layer 228 and the horizontal portion of the dielectric layer 252 both have mutually flush inner sidewalls, and the bottom surface of the dielectric layer 228 is coplanar with the bottom surface of each conductive pillar 270. With this configuration, the stacked dielectric layers 252, 228, 132, and 118 together form a second insulating layer 260, surrounding the bottom of each conductive pillar 270, so that the dielectric layer 252 simultaneously physically contacts both the dielectric layer 132 and the dielectric layer 228, achieving a more optimized isolation effect. Therefore, the second isolation layer 260 in this embodiment also has a composite layer structure, which can effectively avoid the problem of short circuit at the bottom of the conductive pillar 270 caused by excessive lateral etching, thereby improving the device reliability and performance of the semiconductor device 300.
[0079] Please refer to Figures 13 to 14The illustration is a schematic diagram of a method for fabricating a semiconductor device 400 according to a third embodiment of the present invention. The front-end steps of the fabrication method in this embodiment are largely the same as those in the first embodiment described above, such as... Figures 1 to 5 As shown, it will not be described again here. The main difference between the formation method of this embodiment and the formation method of the first embodiment is that, after the etching process E4, a plurality of vias (not shown) with significant lateral expansion are formed in the dielectric layer 328 by a lateral etching process.
[0080] In detail, the first step is to perform an etching process, such as a dry etching process, etching vertically downwards. Figure 5 The dielectric layers 132, conductive layers 134, and partial metal oxide patterns 124 shown enable each via 140 to penetrate the stacked layer structure 130, and the partial etching of the metal oxide patterns 124 forms multiple vias 340, such as... Figure 13 As shown. Then, the wet etching process (not shown) is performed simultaneously, etching vertically and laterally as shown. Figure 13 The metal oxide patterns 124 shown are used to enhance the lateral etching of each metal oxide pattern 124 by controlling the etching conditions of the wet etching process to form a dielectric layer 328. The vias formed under this operation exhibit a partially expanded appearance to both sides within the dielectric layer 328 but do not laterally erode through the dielectric layer 328, instead having a gyroscope-like or flying saucer-like depression, such as... Figure 14 As shown.
[0081] Then, as Figure 14 As shown, a dielectric layer 352, a barrier layer 372, and a conductive layer 374, comprising a high dielectric constant dielectric material, are sequentially formed within each of the vias. The dielectric layer 352 conformally covers only the two opposite sidewalls of each via, while the barrier layer 372 and the conductive layer 374 together form a conductive pillar 370. The barrier layer 372 conformally covers the dielectric layer 352, the dielectric layer 328, and the contact pad 116, while the conductive layer 374 fills the remaining space of each via. With this configuration, each conductive pillar 370 can correspondingly have a structure similar to a gyroscope or a flying saucer, such as... Figure 14 As shown.
[0082] Thus, the fabrication of the semiconductor device 400 in the third embodiment of the present invention is completed. According to the fabrication method of the semiconductor device 400 in this embodiment, by strengthening the lateral etching conditions in the wet etching process, the vias that partially expand to both sides are formed within the dielectric layer 328, while a gyroscope-like or flying saucer-like recess is formed on the dielectric layer 328. Thus, the fabrication method of this embodiment can also produce a semiconductor device 400 with optimized device reliability and performance while simplifying the fabrication process.
[0083] On the other hand, in the semiconductor device 400 according to this embodiment, a dielectric layer 328 (including a metal oxide material) is additionally disposed between the dielectric layer 352 (including a high dielectric constant dielectric material) and the insulating layer 118 (including a dielectric material, for example, the same as the first insulating layer 114) of different materials. The dielectric layer 328 has a gyroscope-like or flying saucer-like recess, and its bottom surface is coplanar with the bottom surface of each conductive post 370. The dielectric layer 352 conformally covers the recess of the dielectric layer 328. With this configuration, the stacked dielectric layers 352, 328, 132, and 118 together form a second insulating layer 360, surrounding the bottom of each conductive post 370. This allows the dielectric layer 352 to physically contact both the dielectric layer 132 and the dielectric layer 328 simultaneously, achieving a more optimized isolation effect. Therefore, the second isolation layer 360 in this embodiment also has a composite layer structure, which can effectively avoid the problem of short circuit at the bottom of the conductive pillar 370 caused by excessive lateral etching, thereby improving the device reliability and performance of the semiconductor device 400.
[0084] In general, the manufacturing method of the present invention involves additionally forming a dielectric layer (e.g., a metal oxide material) with a relatively large etching selection at the bottom of the via during the formation of the via. This prevents excessive lateral etching of the bottom of the via in subsequent etching processes (especially wet etching processes), ensuring that the conductive pillars subsequently formed within the via have reliable structure and performance, thus avoiding short circuits. In the semiconductor device of the present invention, an additional dielectric layer (e.g., a metal oxide material) is formed at the bottom of the conductive pillars. Due to the influence of the aforementioned wet etching process, the dielectric layer has, for example, an L-shaped cross-section structure or a gyroscope-shaped or UFO-shaped recessed structure, located on both sidewalls of each conductive pillar to further isolate the bottom of the pillar and prevent short circuits.
[0085] Therefore, the fabrication method and / or semiconductor device of the present invention can be applied to the formation of vertical columnar semiconductor structures, such as conductive pillars and plugs, to improve the structural reliability and performance of said semiconductor structures. Please refer to... Figure 15The illustration shows a cross-sectional view of a semiconductor device in a preferred embodiment of the present invention. In this embodiment, the semiconductor device is, for example, a three-dimensional NAND memory device 500, including a substrate 110, a stacked layer structure 130 disposed on the substrate 110, and a plurality of channel structures 470 penetrating the stacked layer structure 130. The stacked layer structure 130 serves as a memory stack structure, and each word line (i.e., each conductive layer 134) is fanned out by the staircase structure on both sides to be electrically connected to the word line contact plug 410.
[0086] In detail, the channel structure 370 has, for example, a cylindrical shape to electrically connect to the contact pads 116 disposed within the first insulating layer. Each channel structure 130 further includes a dielectric layer 152, a channel layer 472, and a filling layer 474 that fills the remaining space of the channel hole, disposed along the sidewall of the via (not shown). The channel layer 472 includes, for example, a semiconductor material, such as polysilicon, while the filling layer 474 includes an insulating material, such as silicon oxide. Thus, the channel structure 470, the conductive layer 134, and the contact pads 116 (as source / drain electrodes) can together form a transistor, and the intersection of each channel structure 470 and each conductive layer 134 can serve as a memory cell, with each conductive layer 134 acting as a word line to control the writing and reading of data in each memory cell.
[0087] It should be noted that an additional dielectric layer 128 is provided at the bottom of each channel structure 470, sandwiched between the dielectric layer 152 and the insulating layer 118, and presents an L-shaped cross-section. The dielectric layer 128 also includes a metal oxide material with relatively large etching to improve the short circuit problem that is prone to occur during the formation of the vias. Furthermore, in this embodiment, the stacked dielectric layers 152, 128, 132, and 118 together form a second insulating layer 160, surrounding the bottom of each channel structure 370, so that the dielectric layer 152 can simultaneously physically contact the dielectric layers 132 and 128 to achieve a more optimized isolation effect. Thus, the three-dimensional NAND memory device 500 of this embodiment can also have a more reliable structure and performance, avoiding the problem of short circuits. In addition, other components or details of the three-dimensional NAND memory device 500 in this embodiment are generally the same as those in the first embodiment described above, and will not be repeated here.
[0088] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A semiconductor device, characterized in that, include: Substrate; A stacked layer structure comprising alternating stacked dielectric layers and multiple conductive layers; Multiple contact pads are disposed separately within the first insulating layer and located on the substrate; as well as Multiple conductive pillars are disposed separately within a second insulating layer, each conductive pillar contacting a contact pad. The second insulating layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked on the sidewalls of the conductive pillars. The first dielectric layer physically contacts both the second dielectric layer and the third dielectric layer, and the first dielectric layer is located between the stacked layer structure and the conductive pillars. The inner sidewall of the second dielectric layer is flush with the sidewall of the third dielectric layer.
2. The semiconductor device according to claim 1, characterized in that, The bottom surface of the second dielectric layer is coplanar with the bottom surface of the conductive pillar.
3. The semiconductor device according to claim 1, characterized in that, The second dielectric layer extends less in the horizontal direction than each of the contact pads extends in the horizontal direction.
4. The semiconductor device according to claim 1, characterized in that, The third dielectric layer, the second dielectric layer, and the first dielectric layer each comprise different materials. The first dielectric layer comprises a high dielectric constant dielectric material, and the third dielectric layer comprises the same material as the first insulating layer.
5. The semiconductor device according to claim 4, characterized in that, The second dielectric layer comprises a metal oxide material.
6. The semiconductor device according to claim 1, characterized in that, Both the second dielectric layer and the first dielectric layer have an L-shaped cross-section, wherein the inner sidewall of the horizontal portion of the L-shaped cross-section of the first dielectric layer is flush with the inner sidewall of the horizontal portion of the L-shaped cross-section of the second dielectric layer.
7. The semiconductor device according to claim 6, characterized in that, The vertical portion of the L-shaped cross-section of the second dielectric layer is flush with the sidewall of the third dielectric layer.
8. The semiconductor device according to claim 1, characterized in that, The second dielectric layer has a gyroscope-shaped or UFO-shaped recess, and the first dielectric layer conformally covers the recess of the dielectric layer.
9. The semiconductor device according to claim 1, characterized in that, Each of the conductive pillars includes a barrier layer and a conductive layer stacked in sequence.
10. A semiconductor device, characterized in that, include: Substrate; Multiple contact pads are disposed separately within the first insulating layer and located on the substrate; as well as Multiple conductive pillars are disposed separately within a second insulating layer, each conductive pillar contacting a contact pad. The second insulating layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked on the sidewalls of the conductive pillars. The first dielectric layer physically contacts both the second dielectric layer and the third dielectric layer. Both the second dielectric layer and the first dielectric layer have an L-shaped cross-section. The inner sidewall of the horizontal portion of the L-shaped cross-section of the first dielectric layer is flush with the inner sidewall of the horizontal portion of the L-shaped cross-section of the second dielectric layer.
11. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A plurality of contact pads are formed on the substrate and disposed within a first insulating layer, which are spaced apart from each other; A stacked layer structure is formed on the substrate, the stacked layer structure comprising a plurality of dielectric layers and a plurality of conductive layers stacked alternately; as well as A plurality of conductive pillars are formed on the substrate and disposed within a second insulating layer, which are spaced apart from each other. The conductive pillars contact each of the contact pads. The second insulating layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked on the sidewalls of the conductive pillars. The first dielectric layer is in physical contact with both the second dielectric layer and the third dielectric layer. The first dielectric layer is located between the stacked layer structure and the conductive pillars. The inner sidewall of the second dielectric layer is flush with the sidewall of the third dielectric layer.
12. The method for fabricating a semiconductor device according to claim 11, characterized in that, Also includes: Multiple metal oxide patterns are formed on the substrate, each corresponding to one of the contact pads; An insulating layer is formed on the substrate to cover the metal oxide pattern; At least one stacked layer is formed on the metal oxide pattern and the insulating layer; Multiple first through-holes are formed, each penetrating through the at least one stacked layer and each of the metal oxide patterns; as well as The conductive pillar is formed within each of the first through holes.
13. The method for fabricating a semiconductor device according to claim 12, characterized in that, At least one stacked layer includes multiple conductive layers and multiple dielectric layers stacked alternately.
14. The method for fabricating a semiconductor device according to claim 12, characterized in that, Forming the metal oxide pattern further includes: A metal oxide material layer is formed on the substrate; and The metal oxide material layer is patterned to form the metal oxide pattern.
15. The method for fabricating a semiconductor device according to claim 12, characterized in that, The process also includes the following steps before the formation of the conductive pillar: Multiple second vias are formed, each penetrating through the at least one stacked layer, and each of the metal oxide patterns is partially etched. A dielectric material layer, a barrier material layer, and a mask material layer are formed sequentially stacked within each of the second vias; and A wet etching process is performed to partially remove the mask material layer, the barrier material layer, the dielectric material layer, and the metal oxide pattern, forming the first via, the mask layer, and the barrier layer; and Completely remove the mask layer and the barrier layer.
16. The method for fabricating a semiconductor device according to claim 12, characterized in that, The formation of the first through hole also includes: Perform a dry etching process to vertically etch the at least one stacked layer; and The metal oxide pattern is etched laterally using a wet etching process.
17. The method for fabricating a semiconductor device according to claim 15, characterized in that, Before forming the insulating layer, the barrier material layer, and the mask material layer, the method further includes: The metal oxide pattern is thinned through a processing technique.
18. The method for fabricating a semiconductor device according to claim 11, characterized in that, The bottom surface of the second dielectric layer is coplanar with the bottom surface of the conductive pillar.
19. The method for fabricating a semiconductor device according to claim 18, characterized in that, The second dielectric layer and the first dielectric layer each have an L-shaped cross-section, wherein the inner sidewall of the horizontal portion of the first dielectric layer is flush with the inner sidewall of the horizontal portion of the second dielectric layer.
20. The method for fabricating a semiconductor device according to claim 12, characterized in that, The formation of the conductive pillar further includes: A barrier layer and a conductive layer are sequentially formed within the first through-hole.