Current sensor leakage compensation technique

Abstract

A current sensor circuit comprising: a plurality of resistive circuit elements having different resistance values disposed between at least one input terminal and an output terminal of the current sensor circuit; a first plurality of switch circuits coupled between the input terminal and the resistive circuit elements, wherein each switch circuit of the first plurality of switch circuits comprises a pair of transistors connected in series; at least one drive amplifier comprising an output connected to the output terminal and an input; and a second plurality of switch circuits each comprising a first switch terminal coupled to the at least one drive amplifier output and a second switch terminal coupled to a common connection of the pair of transistors of the first plurality of switch circuits.

Description

[0001] Claiming priority

[0002] This application is a PCT application claiming priority to U.S. Patent Application Serial No. 17 / 079845, filed October 26, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This document relates to electronic circuits used for monitoring current in electronic systems. Background Technology

[0004] Current monitoring circuits are used to monitor and report load current information in electronic systems. In some systems, it is necessary to report load current information with high accuracy over a wide current range spanning tens of orders of magnitude. Current sensor circuits typically include a sensing resistor and a current-sensing amplifier to generate an output signal. The current through the sensing resistor is measured by observing the voltage generated across the sensing resistor through the input of the current-sensing amplifier. Due to Ohm's law, the voltage across the resistor terminals is proportional to the current flowing through the resistor. Error sources in current sensor circuits include offset errors caused by finite open-loop gain and component mismatch in the current monitoring circuitry. Summary of the Invention

[0005] This document generally relates to electronic circuits for monitoring current. In some aspects, a current sensor circuit includes a plurality of resistive circuit elements with different resistance values ​​arranged between at least one input terminal and an output terminal of the current sensor circuit; a first plurality of switching circuits coupled between the input terminal and the resistive circuit elements, wherein each of the first plurality of switching circuits includes a pair of transistors connected in series; at least one drive amplifier including an output and an input connected to the output terminal; and a second plurality of switching circuits, each of the switching circuits including a first switching terminal coupled to the output of the at least one drive amplifier and a second switching terminal coupled to a common connection of the pair of transistors of the first plurality of switching circuits.

[0006] In some aspects, a method for operating current monitoring includes: connecting a first resistive circuit element selected for monitoring current between a first input terminal and an output terminal of a current monitoring circuit by activating a first pair of transistors connected to a first resistive circuit element, wherein the pair of transistors is connected in series; driving a common connection of a pair of transistors connected to an unselected resistive circuit element with the output voltage of the output terminal; and sensing the voltage across the selected first resistive circuit element.

[0007] In some aspects, an electronic system includes: a first circuit power rail; a circuit load; and a current monitoring circuit coupled to the first circuit power rail and the circuit load, and includes: a plurality of resistive circuit elements disposed between at least one input terminal and an output terminal of the current sensor circuit, wherein the resistive circuit elements have different resistance values; a first plurality of switching circuits coupled between the at least one input terminal and the resistive circuit elements, wherein each of the first plurality of switching circuits includes a pair of transistors connected in series with the drain regions of transistors connected together; at least one drive amplifier including an output and an input connected to the output terminal; a second plurality of switching circuits, each of the switching circuits including a first switching terminal coupled to the output of the at least one drive amplifier and a second switching terminal coupled to the common drain of the pair of transistors of the first plurality of switching circuits; and a sensing amplifier configured to provide an output signal representing at least a portion of the load current to the output terminal.

[0008] This section is intended to provide an overview of the subject matter of this patent application. It is not intended to provide an exclusive or exhaustive explanation of the invention. Detailed descriptions are included to provide further information regarding this patent application. Attached Figure Description

[0009] In accompanying drawings that are not necessarily drawn to scale, the same numbers may describe similar parts in different views. Similar numbers with different letter suffixes may represent different instances of similar components. The accompanying drawings are illustrated in general terms by way of example and not limitation, of the various embodiments discussed in this document.

[0010] Figure 1 This is a schematic diagram of an example of a multi-range current monitoring circuit.

[0011] Figure 2 This is a schematic diagram of a circuit used to simulate leakage current.

[0012] Figure 3 yes Figure 2 The simulation results of leakage current versus temperature in the circuit are shown in the graph.

[0013] Figure 4 This is under the condition that the temperature remains constant. Figure 2 The simulation results of the leakage current versus the drain-source voltage in the circuit are shown in the graph.

[0014] Figure 5 This is a circuit diagram of an example of a multi-range current sensor circuit.

[0015] Figure 6 A cross-section of a typical isolated n-type metal-oxide-semiconductor (NMOS) device is shown.

[0016] Figure 7 An example of a multi-range current sensor circuit is shown.

[0017] Figure 8 This is a block diagram of an example current monitoring system.

[0018] Figure 9 This is a block diagram of another example of a current monitoring system.

[0019] Figure 10 This is a flowchart of a method for operating a multi-range current monitoring circuit in an electronic system. Detailed Implementation

[0020] Current sensor circuits are used to monitor the current supplied to electronic systems. The error sources in current sensor circuits are offset errors caused by finite open-loop gain and component mismatch. When the input signal is small, the offset error of the current sensing amplifier contributes the most to the output accuracy. When the input signal is large relative to the offset error, the output accuracy improves due to the larger signal-to-noise ratio.

[0021] Multi-range current monitoring circuits can sense current over a wide input range with good accuracy. They utilize multiple shunt resistors of varying values ​​to measure current at different current levels. An appropriate shunt resistor is selected to conduct the current based on the current level. Using multiple shunt resistors allows the current sensing monitoring circuit to maintain a good signal-to-noise ratio over a wide current range. This also minimizes the impact of offset errors on the current monitor output when the input signal becomes too small.

[0022] Figure 1 This is a schematic diagram of an example of a multi-range current monitoring circuit 100. The circuit consists of resistive circuit elements (e.g., shunt resistors) Rs1 to Rs7, used to conduct current (iload) from the input terminal (IN) to the output terminal (OUT) through switches (S1-S7). The resistive circuit elements can be resistors, integrated resistors, or active devices (e.g., transistors). A sensing amplifier (A1) senses the voltage across the shunt resistors to provide an output indicating the magnitude and polarity of the current. This is achieved by connecting the inverting input of the sense amplifier A1 to the bottom of the shunt resistors and the OUT terminal, and by connecting the non-inverting input to the top of one of the shunt resistors through switches (S1b to S7b). Series switches (S1-S7) are connected to the common input circuit node (IN terminal) and the resistive circuit elements.

[0023] The IN terminal of the current sensor circuit 100 can be driven by a low-impedance source, such as a voltage regulator. It can also be connected to a high-output-impedance node, such as a current source. The output terminal of the current sensor circuit can be connected to a circuit load, for example, for load current monitoring purposes. Some examples of circuit loads include a motor or a battery (e.g., for charging). When the load is connected to the output terminal, the load current (iload) flows into the load through one of the shunt resistors, and information related to the load current (e.g., amplitude and polarity) is reported through the current monitoring terminal (IMON). The output of the current monitoring circuit (IMON) can be in the form of current, voltage, digital value, etc.

[0024] exist Figure 1 In the example current sensor circuit, seven resistors are used to measure the load current between +2.5 amps (2.5A) and -2.5A. Table 1 shows examples of shunt resistor values ​​(in ohms) and shunt resistor current ranges (in amps).

[0025] Table 1

[0026]

[0027] Each shunt resistor is designed to handle a specific current range of 100 millivolts (100 mV) full-scale voltage. Considering conduction losses and accuracy, this current monitoring circuit uses a 100 mV full-scale range. A higher full-scale voltage would result in better accuracy due to a higher signal-to-noise ratio, but would also lead to higher conduction losses due to a larger voltage drop across the shunt resistors.

[0028] During normal operation, current enters the current monitoring circuit through the IN terminal. It then flows through a shunt resistor and leaves the circuit through the OUT terminal. The current leaving the OUT terminal is called "iload / ". Switches (S1-S7 and S1b-S7b) are... Figure 1 A separate control circuit, not shown, controls the operation. During operation, one of the switches (S1-S7) will close, connecting the corresponding shunt resistor to the IN terminal. Switches (S1b-S7b) connect the positive input of the sense amplifier A1 to the selected shunt resistor. The states of switches (S1-S7 and S1b-S7b) can be manually changed by user input or automatically changed by the control circuit based on current information (iload). The sense amplifier A1 senses the voltage across the selected shunt resistor and outputs a signal at terminal IMON indicating the magnitude and polarity of the current iload.

[0029] In some applications, high current measurement accuracy is required across the entire current range, while accuracy in the lower current range may be limited by the leakage current of the series switches (S1-S7). This is because the aging switches need to be large enough to conduct the full-scale current for each range, and when they are turned off, the leakage current of these off switches can cause iload current and affect the current monitor output.

[0030] As an example illustrating the problem of leakage current in switches, assume a current of 5 microamps (5uA) flows through switch S1 and resistor Rsl (20 kΩ). Assuming the on-resistance of S1 is negligible, the voltage difference between the IN and OUT terminals is 100mV. When the series switches (S2-S7) are closed, the voltage across the shunt resistors (Rs2-Rs7) is 0V. This means the voltage between the drain and source terminals of the series switches (S2-S7) is 100mV. Although all series switches (S2-S7) can have leakage current, most of it originates from S7, which has the highest current range and is therefore the largest device in terms of area. The leakage current increases exponentially with temperature due to the generation of charge carriers in the space charge region. The leakage current is also a function of the reverse bias voltage.

[0031] Figure 2 This is a schematic diagram of a circuit used to simulate the temperature dependence of leakage current. The device used in the simulation is an n-type metal-oxide-semiconductor (NMOS) device with its source, body, and gate all grounded. The drain of the NMOS is connected to a voltage source VI. By connecting the source, body, and gate together, the NMOS device operates in the off region. The NMOS device is sized to handle a maximum current of 2.5A and has the characteristics of… Figure 1 The switch (S7) in the circuit example has the same current handling capability.

[0032] Figure 3 yes Figure 2 The simulation results of leakage current versus temperature for the NMOS device are shown in the figure. The voltage source V1 is set to 100 millivolts (100 mV), and the temperature is scanned during the simulation.

[0033] Figure 4 This is a simulation result of leakage current versus drain-source voltage (Vds) at a constant temperature of 125℃. Note that at a drain-source voltage of 100mV, the leakage current is approximately 1.93 microamps (1.93pA), and the leakage current decreases as the drain-supply voltage approaches 0V.

[0034] Figure 5This is a circuit diagram of an example of a multi-range current sensor circuit 500. The circuit includes an input terminal (IN), an output terminal (OUT), and a current monitoring terminal (IMON). The circuit also includes multiple resistive circuit elements or resistors (e.g., shunt resistors Rs1 to Rs7). The resistive circuit elements can be any integrated device with a predetermined resistance value. To simplify the circuit, Figure 5 The circuitry that provides the IMON output (e.g., a sense amplifier and a switch that connects the sense amplifier to a resistor) is not shown.

[0035] The circuit includes a switching circuit that connects shunt resistors Rs1-Rs7 to the IN terminal. The switching circuit consists of back-to-back NMOS devices Mla-M7a and Mlb-M7b. The NMOS transistors in each back-to-back pair share the same drain connection and the same gate connection (labeled g1-g7). The gate voltage of the NMOS device is driven high relative to the source voltage, causing the NMOS device to turn on and form a low-impedance path between the IN terminal and the shunt resistors. When the gate-source voltage is driven "low" (below the threshold voltage), the NMOS device turns off, disconnecting the shunt resistors from the IN terminal.

[0036] The shunt resistors are numbered according to their current handling capabilities; Rs7 senses the highest current in the iload current range, and Rsl senses the lowest current. The back-to-back NMOS devices are controlled such that the iload current can only pass through one of the shunt resistors. Driver amplifier A2 is configured in unity-gain configuration, with its positive input connected to the OUT terminal. Switches Slc-S7c each have a switch terminal connected to the output of driver amplifier A2 and another switch terminal connected to the common drain of the back-to-back NMOS devices. The control signals for switches Slc-S7c are complementary to the gate connections gl-g7 of the NMOS devices. This allows switches S1c-S7c to operate in the opposite states of the back-to-back NMOS devices (e.g., switch S7c is off when NMOS devices M7a and M7b are on).

[0037] exist Figure 5 In the example, the back-to-back NMOS devices have a common drain connection. In a variant, the back-to-back NMOS devices have a common source connection. In other variants, devices Mla-M7a and Mlb-M7b are p-type metal-oxide-semiconductor (PMOS) devices with either a common drain connection or a common source connection. Although transistor pairs are shown as having a common gate connection to activate the transistor pair, individual gate connections can be used to activate the transistors in a back-to-back pair. Furthermore, although Figure 5 The example circuit in the diagram shows a single drive amplifier A2, but multiple drive amplifiers can be coupled to the OUT terminal and used for the common connection of the drive transistor pairs.

[0038] When the iload current is at its highest current range, gate connection g7 is driven high. NMOS devices M7a and M7b are turned on and conduct the iload current. NMOS devices M1a-M6a and M1b-M6b are turned off to block any current from the other shunt resistors Rsl-Rs6. Switches Slc-S6c are closed or activated, connecting the output of driver amplifier A2 to the common connection of back-to-back NMOS devices M1a-M6a and M1b-M6b. Driver amplifier A2 buffers the voltage at the OUT terminal node and drives the drain of the turned-off NMOS devices M1b-M6b through switches Slc-S6c. Because the drain current of NMOS devices M1a-M6b is equal to the current in Rsl-Rs6, the source voltage of NMOS devices (M1b-M6c) is the same as the voltage at the OUT terminal, and the drain voltage of the NMOS devices is also the same. This makes the drain-source voltage (Vds) of NMOS devices M1a-M6b equal to 0V. Figure 4 As shown, when the Vds voltage is close to 0V, the drain-source (body) leakage current becomes 0A. By driving the drain voltage to the source voltage through the driver amplifier A2, the leakage current is canceled out, and the current in Rs1-Rs6 is 0A. This means that the current in Rs7 must be equal to the current iload. Although iload is in the highest current range, where the sensed current is the largest, the leakage current from the NMOS (Mlb-M6b) will not have a significant impact on the current monitor output IMON.

[0039] When the iload current is in its minimum current range, Rsl conducts iload with NMOS devices M1a and M1b conducting. NMOS devices M2a-M7a and M2b-M7b are turned off to prevent current from flowing into other shunt resistors Rs2-Rs7. Switches S2c-S7c are closed, and the drains of M2b-M7b are driven by driver amplifier A2 to a voltage equal to the voltage at the OUT terminal. This allows the drain voltage of NMOS devices M2b-M7b to be equal to the source voltage, therefore the drain-source voltage (Vds) is 0V. By making the drain-source voltage zero, the leakage current in NMOS devices M2b-M7b must also be zero, such as... Figure 4 The drain-source correlation is shown in the figure.

[0040] When the iload current is positive, it means that iload flows into the IN terminal and out of the OUT terminal, and the source of NMOS devices M1a-M7a is at a higher potential than the drain (Vs > Vd). The voltage drop between the IN and OUT terminals depends on the on-resistance of the conducting back-to-back NMOS devices and the shunt resistor. The back-to-back NMOS devices in the circuit are designed such that when they are turned on at full scale in the corresponding current range, the voltage across the drain and source is less than the forward bias voltage of the device's body diode. For a positive iload current, the voltage at the IN terminal will be higher than the node voltage at the OUT terminal. When the drive amplifier A2 turns off the drain of NMOS devices M1a-M7b through switches S1c-S7c, the voltage across the source and drain of NMOS-M7a will be equal to the voltage difference between the IN and OUT terminals. In the design, it is important to ensure that the voltage drop from the IN terminal to the OUT terminal does not exceed the forward bias voltage of the body diodes of M1a-M7a. Otherwise, the body diodes of the NMOS devices M1a-M7a will be turned on when the device is turned off, and the drive will be opposite to that provided by the drive amplifier A2.

[0041] When the iload current is negative, it means that current flows into the OUT terminal and out of the IN terminal, and the voltage at the IN terminal is lower than the voltage at the OUT terminal. The voltage difference between the IN and OUT terminals depends on the conducting shunt resistor and the voltage drop across the back-to-back NMOS devices. With the drive amplifier A2 operating to keep the Vds of the turn-off NMOS devices M1b-M7b at 0V, the Vds voltage of the turn-off NMOS devices M1a-M7a is equal to the voltage drop from the OUT terminal to the IN terminal. Because the drain voltage of the turn-off NMOS devices M1a-M7a is higher than the source voltage, the body diodes of these NMOS devices are reverse biased.

[0042] Figure 5 The leakage current compensation technique uses back-to-back NMOS devices to control the current through the shunt resistor. When the back-to-back NMOS devices are turned off to cut off the current through the shunt resistor, the drive amplifier A2 drives Vds to 0V through switches Slc-S7c to the turned-off NMOS devices (M1b-M7b). Although discussed in the discussion... Figure 1 Switches S1-S7 use NMOS devices ( Figure 5 This can be achieved using M1a-M7a and M1b-M7b, but PMOS devices can also be used. Other arrangements of switches S1-S7 can also be used, such as back-to-back NMOS devices with a common source connection. Figure 5The current sensor circuit shown uses a single drive amplifier A2 to disable leakage current by driving the drain-source voltage of the NMOS devices M1b-M7b to 0V. Multiple drive amplifiers can be used instead of a single drive amplifier A2 to achieve the same purpose. Figure 5 In the current sensor circuit example, the shunt resistor can be an integrated on-chip resistor circuit element or an external discrete circuit element.

[0043] For manufacturing techniques using p-type substrates, n-type materials are used to isolate the NMOS devices (M1a-M7a and M1b-M7b) to separate the NMOS body from the substrate. This n-type material that isolates the substrate from the NMOS body is commonly referred to as "isolation". Figure 6 The image shows a cross-section of a typical isolated NMOS device. The NMOS device is surrounded by an n-type material (deep n-well), which isolates the NMOS device from the p-substrate. Under normal bias conditions, the p-substrate (sub) is always biased with a voltage lower than that of the deep n-well (iso), causing the junction diode (D) between the deep n-well and the p-substrate to... sub Reverse bias. The body of an NMOS device is an isolated p-well. The body of the NMOS device should be at a voltage equal to or lower than that of the deep n-well (iso) to prevent the junction diode (D) between the isolated p-well (body) and the deep n-well (iso) from breaking during normal operation. iso Positive bias.

[0044] When in such Figure 5 The current sensor circuit shown uses, for example, Figure 6 When isolating NMOS devices as shown, it is helpful to pay special attention to the isolation (iso) bias of the NMOS device because the junction diode (D) iso Leakage in the junction diode (D) can cause errors in the current monitor output. This is because leakage in the junction diode (D) can lead to errors in the current monitor output. iso Any leakage current will flow into the body of NMOS devices M1b-M7b. The current iload is equal to all current in shunt resistors Rs1-Rs7 and all current in the isolation body junction diodes (D) of NMOS devices M1b-M7b. iso The sum of leakage currents. (D) iso The leakage current depends on the reverse bias voltage: the larger the reverse bias voltage, the larger the leakage current. For Figure 5 In the current sensor circuit, the isolation to the NMOS devices (M1b-M7b and M1a-M7a) should be biased at the same voltage as their body and source to minimize junction diode (D) isolation. isoReverse bias. One way to achieve this is to connect the isolation (iso) of the NMOS (M1b-M7b and M1a-M7a) to its drain; when the NMOS (M1b~M7b) is off, amplifier A2 drives the drain, isolating the off NMOS (M1b-M7b) to its source via switches (S1c-S7c). A junction diode (D) between the isolation (iso) and the substrate (sub) sub The leakage current will be provided by the drive amplifier A2, and since this leakage current will not increase the iload, it will not affect the accuracy of the current monitor output.

[0045] Figure 7 An example of a multi-range current sensor circuit 700 is shown, which is similar to Figure 5 The example shows a current sensor circuit. A clamping resistor R7 (or other clamping resistor circuit element) is added to the circuit, its terminals connected to the drain and source of back-to-back NMOS devices M7a and M7b for the highest iload current range. The gate control signal for gate connection g7 comes from... Figure 7 The circuit is not shown in the diagram. When Rs7 conducts iload current, g7 is pulled high relative to the source to turn on NMOS devices M7a and M7b. When NMOS devices M7a and M7b need to be turned off to block the current through Rs7, the circuit driving g7 becomes high impedance. This allows the gate connected to g7 to be pulled down to the drain by resistor R7. This configuration allows NMOS devices M7a and M7b to be clamped to a differential voltage between the IN and OUT terminals.

[0046] As an explanation Figure 7 An example of clamping circuit operation is given, assuming NMOS devices M1a-M7a and M1b-M7b are initially off, and a positive iload current is pushed into the IN terminal. Because all back-to-back NMOS devices are off, the IN terminal node is pulled high by a positive current. The potential at the IN terminal continues to increase until the differential voltage between the IN and OUT terminals equals the forward diode voltage of the body diode of device M7a plus the threshold voltage of device M7b. As the IN terminal voltage increases, the body diode of M7a becomes forward biased and pulls the gate of M7b upward through the clamping resistor R7. When the gate-source voltage (Vgs) of M7b is greater than the threshold voltage, current begins to flow from the IN terminal to the OUT terminal through the body diode of M7a, the channel of M7b, and resistor Rs7. Using the clamping circuit, the differential voltage between the IN and OUT terminals is limited to Vd. M7a +VgS M7b +IR, where Vd M7a It is the forward diode voltage of the body diode of device M7a, VgS M7bIR is the gate-source voltage of device M7b, and IR is the voltage drop across shunt resistor Rs7.

[0047] When the back-to-back NMOS devices are initially disconnected and the negative iload current on the IN terminal decreases, the voltage at the IN terminal begins to drop. As the IN terminal voltage continues to decrease, the body diode of device M7b eventually becomes forward biased, pulling up the gate of device M7a through clamping resistor R7 until Vgs of M7a exceeds the threshold voltage. When this occurs, current begins to flow from the OUT terminal to the IN terminal through resistor Rs7, the body diode of M7b, and the channel of M7a. This limits the differential voltage between the OUT and IN terminals to Vd. M7b +VgS M7a +IR, where Vd M7b This is the forward diode voltage of the body diode of M7b, VgS. M7a IR is the gate-source voltage of M7a, and IR is the voltage drop across the shunt resistor Rs7.

[0048] Clamping circuits can protect shunt resistors and back-to-back NMOS transistors (M1a-M7b and M1b-M7b) from damage by limiting the maximum differential voltage between the IN and OUT terminals in both directions. Because devices M7a, M7b, and Rs7 are used for the highest current sensing range, their current handling capabilities make them advantageous for use as clamping devices to limit the differential IN-OUT voltage.

[0049] Figure 8 This is a block diagram of an example current monitoring system 800, in which a multi-range current monitoring circuit 802 is used to monitor load current. The circuit load can be any electrical load, such as a rechargeable battery or a motor. The current monitoring circuit 802 uses multiple shunt resistors to transfer current from the IN terminal to the OUT terminal. Depending on the magnitude of the load current, one of the shunt resistors conducts the load current. The IMON terminal outputs a signal indicating the magnitude and polarity of the iload current. The IMON terminal can be connected to the output of a sensing amplifier, and the signal IMON can be in the form of a voltage output or a current output, etc. System 800 may include an analog-to-digital converter (ADC) circuit 804 to provide a digital output indicating the magnitude of the load current.

[0050] Regulator U1 draws power from the circuit power supply terminals and drives the IN terminal of current monitoring circuit 802. When regulator U11 supplies current to the load, the load current flows from the power supply terminals through regulator U1 and current monitoring circuit 802 to the load. In some applications, regulator U1 can release the load. When the load discharges, current flows from the load to ground through the current monitoring circuit and regulator U1. Regulator U1 can be a linear regulator, a switching converter regulator, or other type of regulator. The current range of current monitoring circuit 802 can be manually changed by user input to set a switch to select the shunt resistor for the current range. In some aspects, control circuit 806 includes logic circuitry to automatically select the shunt resistor based on the magnitude of the sensed load current. One or more comparator circuits can be used to detect the magnitude of the sensed load current, and the logic circuitry allows combinations of switches to select the appropriate shunt resistor. If multi-range current monitoring circuit 802 includes ADC circuitry 804, the control circuitry can periodically (e.g., periodically) activate the ADC circuitry to convert the voltage across the resistive circuit element sensed by sense amplifier A1. If the magnitude of the sensed current moves to a new current range determined by the comparator, the control circuit 806 can change the shunt resistor.

[0051] Figure 9 This is a block diagram of another example of a current monitoring system 900, in which a multi-range current monitoring circuit 902 is used to monitor the load current. In this system, two regulators, U1 and U2, are powered by circuit power supply terminals Supply1 and Supply2. Either circuit power supply can provide load current (iload) to the circuit Load through the multi-range current monitoring circuit 902. The current monitoring circuit has two input terminals, INI and IN2. The shunt resistors in the multi-range current monitoring circuit 902 are divided into two groups, shunt resistors Rs6 and Rs7 (… Figure 5 The first set of resistors (Rs7 or Rs6) is connected to the output of regulator U1 via terminal IN1, while the other shunt resistors Rs5-Rs1 are connected to the output of regulator U2 via IN2. When regulator U1 drives the load current, one of the shunt resistors in the first set (Rs7 or Rs6) conducts the current to the load. When regulator U2 drives the load current, one of the shunt resistors in the second set (Rs1-Rs5) conducts the current to the load. In some respects, a DC-DC converter can be used for regulator U1 to provide load current over a higher current range, while a linear regulator can be used for regulator U2 to provide load current over a lower current range. DC-DC converters are advantageous for providing higher output power and higher efficiency, while linear regulators are ideal for low power output and better noise performance.

[0052] For completeness. Figure 10This is a flowchart of a method for operating a multi-range current monitoring circuit of an electronic system. At 1005, a first resistive circuit element is selected for monitoring current and is connected between the input and output terminals of the current monitoring circuit by activating a first pair of transistors connected to the resistive circuit element. The pair of transistors is connected in series, and the resistive circuit element can be a shunt resistor connected in series with the transistor pair.

[0053] At 1010, the output voltage at the output terminal drives the common connection of the transistor pair connected to the unselected resistor circuit element. The transistor can be an NMOS or PMOS device, and the common connection can be a common drain connection or a common source connection. At 1015, the voltage across the selected resistor circuit element is sensed, and a signal representing the monitored current is generated. The generated output signal can be quantized using an ADC circuit.

[0054] The apparatus, system, and method described herein provide a leaf-age current compensation technique that addresses accuracy issues in multi-range current monitoring circuits caused by leakage current from electronic switches. This technique uses back-to-back NMOS devices as series switches to block current passing through a shunt resistor. The leakage current of the back-to-back NMOS devices is invalidated by driving the drain-source voltage of one of the back-to-back NMOS devices to 0V. A clamping circuit can be used to protect the series devices and the shunt resistor. This leakage compensation technique can be used in systems where the load current is provided by one or more regulators.

[0055] Additional notes and aspects

[0056] The first aspect (Aspect 1) includes a subject (e.g., a current sensor circuit) comprising: a plurality of resistive circuit elements disposed between at least one input terminal and an output terminal of the current sensor circuit, wherein the resistive circuit elements have different resistance values; a first plurality of switching circuits coupled between the input terminal and the resistive circuit elements, wherein each of the first plurality of switching circuits includes a pair of transistors connected in series; at least one drive amplifier including an output and an input connected to the output terminal; and a second plurality of switching circuits, each of the switching circuits including a first switching terminal coupled to the output of the at least one drive amplifier and a second switching terminal coupled to a common connection of the pair of transistors of the first plurality of switching circuits.

[0057] In aspect 2, the subject matter of aspect 1 may optionally include: a clamping resistor circuit element coupled between a common drain connection of at least one transistor pair and a common gate connection of the at least one transistor pair in the first plurality of switching circuits.

[0058] In aspect 3, the subject matter of one or both of aspects 1 and 2 may optionally include: at least one sensing amplifier configured to sense the voltage across the resistive circuit elements of the plurality of resistive circuit elements and output an electrical signal representing the load current.

[0059] In aspect 4, the subject matter of one or any combination of aspects 1-3 may optionally include: a sensing amplifier including a first input coupled to the output terminal; and a third plurality of switching circuits coupled to the plurality of resistive circuit elements, each switching circuit including a first switching terminal coupled to the resistive circuit element and a second switching terminal coupled to a second input of the sensing amplifier.

[0060] In aspect 5, the subject matter of aspect 4 may optionally include an analog-to-digital converter (ADC) circuit coupled to the output of the sense amplifier.

[0061] In aspect 6, the subject matter of aspect 5 may optionally include: a plurality of input terminals, wherein a portion of the plurality of resistive circuit elements is arranged between each input terminal of the plurality of input terminals and the output terminal; and control circuitry configured to periodically connect the resistive circuit elements to the input terminals of the plurality of input terminals and initiate the conversion of the voltage sensed by the sense amplifier across the resistive circuit elements by the ADC circuitry.

[0062] In aspect 7, the subject matter of one or any combination of aspects 1-6 may optionally include: a plurality of drive amplifiers, each drive amplifier being connected to a portion of the switching circuit of the second plurality of switching circuits.

[0063] In aspect 8, the subject matter of one or any combination of aspects 1-7 may optionally include: at least one comparator circuit configured to determine a current range received at the input terminal, and to select a resistive circuit element of a plurality of resistive circuit elements by enabling a first switching circuit of the first plurality of switching circuits and a second switching circuit of the second plurality of switching circuits according to the determined current range.

[0064] Aspect 9 includes a subject matter (e.g., a method of operating a current monitoring circuit of an electronic system) or may optionally be combined with one or any combination of aspects 1-8 to include a subject matter comprising: connecting a first resistor circuit unit selected for monitoring current between a first input terminal and an output terminal of the current monitoring circuit by activating a first pair of transistors connected to a first resistor circuit element, wherein the pair of transistors is connected in series; driving a common connection of a pair of transistors connected to an unselected resistor circuit element with the output voltage of the output terminal; and sensing the voltage across the selected first resistor circuit element.

[0065] In aspect 10, the subject matter of aspect 9 may optionally include: limiting the voltage between the input terminal and the output terminal to a maximum voltage.

[0066] In aspect 11, the subject matter of aspect 10 may optionally include: limiting the voltage by using a resistor connected between the common connection of the transistor pair and the common gate connection of the transistor pair to clamp the voltage between the input terminal and the output terminal.

[0067] In aspect 12, the subject matter of one or any combination of aspects 9-11 may optionally include: using the current monitoring circuit to determine the current range of the current to be monitored; and selecting the resistive circuit element according to the determined current range.

[0068] In aspect 13, one or any combination of aspects 9-12 may optionally include: generating an electrical signal representing the load current of the electronic system.

[0069] In aspect 14, the subject matter of one or any combination of aspects 9-13 may optionally include quantizing the sensed voltage using an ADC circuit.

[0070] In aspect 15, the subject matter of one or any combination of aspects 9-14 may optionally include: disconnecting the first resistive circuit element from the first input terminal; connecting a second resistive element between the second input terminal and the output terminal of the current monitoring circuit by activating a second pair of transistors connected to the second resistive circuit element, wherein the second pair of transistors has a common connection; and sensing the voltage across the second resistive circuit element.

[0071] Aspect 16 includes a subject matter (e.g., an electronic system), or may optionally be combined with one or any combination of aspects 1-15 to include a subject matter such as: a first circuit power supply rail; a circuit load; and a current monitoring circuit coupled to the first circuit power supply rail and the circuit load. The current monitoring circuit includes: a plurality of resistive circuit elements disposed between at least one input terminal and an output terminal of the current sensor circuit, wherein the resistive circuit elements have different resistance values; a first plurality of switching circuits coupled between the at least one input terminal and the resistive circuit elements, wherein each of the first plurality of switching circuits includes a pair of transistors connected in series with the drain regions of transistors connected together; at least one drive amplifier including an output and an input connected to the output terminal; a second plurality of switching circuits, each switch circuit including a first switch terminal coupled to the output of the at least one drive amplifier and a second switch terminal coupled to the common drain of the pair of transistors of the first plurality of switching circuits; and a sensing amplifier configured to provide an output signal representing at least a portion of the load current to the output terminal.

[0072] In aspect 17, the subject matter of aspect 16 may optionally include: a second circuit power supply rail; and at least a first input terminal and a second input terminal. The first input terminal is coupled to the first circuit power supply rail and a first portion of the first plurality of switching circuits, and the second input terminal is coupled to the second circuit power supply rail and a second portion of the first plurality of switching circuits.

[0073] In aspect 18, the subject matter of aspect 17 may optionally include: an analog-to-digital converter (ADC) circuit coupled to the sense amplifier; and control circuitry configured to periodically initiate measurements of sense current from the first circuit power rail and sense current from the second circuit power rail using the ADC circuitry.

[0074] In aspect 19, the subject matter of one or any combination of aspects 16-18 may optionally include: a third plurality of switching circuits coupled to the plurality of resistive circuit elements, each switching circuit including a first switching terminal coupled to the resistive circuit element and a second switching terminal coupled to the non-inverting input of the sense amplifier. The inverting input of the sense amplifier is coupled to an output terminal.

[0075] In aspect 20, the subject matter of one or any combination of aspects 16-19 may optionally include: a clamping resistor circuit element coupled between a common drain connection of at least one transistor pair and a common gate connection of the at least one transistor pair in the first plurality of switching circuits.

[0076] These non-limiting aspects can be combined in any arrangement or combination. The above detailed description includes references to the accompanying drawings, which form part of the detailed description. Illustrations: Figure 2 Specific embodiments in which the invention can be practiced are illustrated. These embodiments are also referred to herein as “examples” or “aspects.” All publications, patents, and patent documents mentioned in this document are incorporated herein by reference in their entirety, as if individually incorporated by reference. In the event of any inconsistency between the usage in this document and the documents merged by reference, the usage in the merged references shall be considered supplementary to this document; in the case of irreconcilable inconsistencies, the usage in this document shall prevail.

[0077] In this document, the terms “a” or “some” are common in patent documents and include one or more, independent of any other instances or uses of “at least one” or “one or more.” In this document, the term “or” is used to mean non-exclusive or, unless otherwise stated, “A or B” includes “A but not B,” “B but not A,” and “A and B.” In the appended claims, the terms “comprising” and “wherein” are used as synonyms for the corresponding terms “including” and “wherein.” Furthermore, in the following claims, the terms “comprising” and “including” are open-ended, meaning that a system, apparatus, article, or process that includes elements other than those listed after the term in a claim is still considered to fall within the scope of that claim. Additionally, in the following claims, the terms “first,” “second,” and “third,” etc., are used merely as labels and are not intended to impose numerical requirements on their objects. Examples of methods described herein may be implemented at least in part by a machine or computer.

[0078] The foregoing description is intended to be illustrative and not restrictive. For example, the foregoing examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, for example, by those skilled in the art upon review of the foregoing description. The abstract is provided to conform to 37C.FR §1.72(b) to allow the reader to quickly determine the nature of the technical disclosure. It should be understood that this document is not intended to interpret or limit the scope or meaning of the claims. Furthermore, in the foregoing detailed description, various features may be grouped together to simplify this disclosure. This should not be construed as meaning that unclaimed features of the disclosure are essential to any claim. Rather, the subject matter of the invention may not include all features of a particular disclosed embodiment. Therefore, the following claims are hereby incorporated into the detailed specification, each claim existing independently as a separate embodiment. The scope of the invention should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. A current sensor circuit, comprising: Multiple resistive circuit elements are arranged between at least one input terminal and one output terminal of the current sensor circuit, wherein the multiple resistive circuit elements have different resistance values. A plurality of switching circuits are coupled between the input terminal and the plurality of resistive circuit elements, wherein each of the plurality of switching circuits comprises a pair of transistors connected in series. At least one driver amplifier, including an output and an input, wherein the input is connected to the output terminal; and The second plurality of switching circuits, each of the switching circuits including a first switching terminal coupled to the output of the at least one drive amplifier and a second switching terminal coupled to a common connection of a pair of transistors of the first plurality of switching circuits.

2. The current sensor circuit according to claim 1, comprising a clamping resistor circuit element coupled between a common drain connection of at least one transistor pair in the first plurality of switching circuits and a common gate connection of the at least one transistor pair.

3. The current sensor circuit according to claim 1, comprising at least one sensing amplifier, the at least one sensing amplifier being configured to sense the voltage across the resistive circuit elements among the plurality of resistive circuit elements and output an electrical signal representing the load current.

4. The current sensor circuit according to claim 2, comprising at least one sensing amplifier, the at least one sensing amplifier being configured to sense the voltage across the resistive circuit elements among the plurality of resistive circuit elements and output an electrical signal representing the load current.

5. The current sensor circuit according to any one of claims 1-4, comprising: A sensing amplifier, including a first input coupled to the output terminal; and A third plurality of switching circuits are coupled to the plurality of resistive circuit elements, each switching circuit including a first switching terminal coupled to the resistive circuit element and a second switching terminal coupled to the second input of the sensing amplifier.

6. The current sensor circuit of claim 5, comprising an analog-to-digital converter (ADC) circuit coupled to the output of the sensing amplifier.

7. The current sensor circuit according to claim 6, comprising: Multiple input terminals, wherein a portion of the multiple resistive circuit elements is arranged between each of the multiple input terminals and the output terminal; and The control circuit is configured to periodically connect the resistive circuit element to one of the plurality of input terminals and initiate the conversion of the voltage sensed by the sense amplifier across the resistive circuit element by the ADC circuit.

8. The current sensor circuit according to any one of claims 1-4, comprising a plurality of drive amplifiers, each drive amplifier being connected to a portion of a switch circuit in the plurality of switch circuits.

9. The current sensor circuit according to any one of claims 1-4, comprising at least one comparator circuit configured to determine a range of current received at the input terminal and to select a resistive circuit element among the plurality of resistive circuit elements by activating a first switching circuit among the first plurality of switching circuits and a second switching circuit among the second plurality of switching circuits according to the determined range of current.

10. A method for operating a current monitoring circuit of an electronic system. The current monitoring circuit includes: Multiple resistive circuit elements are respectively arranged between at least one input terminal and an output terminal of the current monitoring circuit, wherein the at least one input terminal includes a first input terminal; as well as A plurality of first switching circuits are respectively coupled between the at least one input terminal and the plurality of resistive circuit elements, wherein each of the first plurality of switching circuits includes a pair of transistors connected in series. The method includes: By activating the first pair of transistors of the first pair of transistors in the first plurality of switching circuits connected to the first resistor element selected for current monitoring in the plurality of resistor circuit elements, the first resistor element is connected between the first input terminal and the output terminal of the current monitoring circuit, wherein the first pair of transistors is connected in series. The common connection of the transistor pairs in the first plurality of switching circuits connected to the unselected resistor circuit elements in the plurality of resistor circuit elements is driven by the output voltage of the output terminal; and The voltage across the selected first resistive circuit element is sensed.

11. The method of claim 10, further comprising limiting the voltage between the input terminal and the output terminal to a maximum voltage.

12. The method of claim 11, wherein limiting the voltage comprises clamping the voltage between the input terminal and the output terminal using a resistor connected between the common connection of the transistor pair and the common gate connection of the transistor pair.

13. The method according to any one of claims 10-12, comprising: The current monitoring circuit is used to determine the current range of the current to be monitored. and The resistor circuit element is selected based on the determined current range.

14. The method according to any one of claims 10-12, comprising generating an electrical signal representing the load current of the electronic system.

15. The method according to any one of claims 10-12, comprising quantizing the sensed voltage using an analog-to-digital converter (ADC) circuit.

16. The method according to any one of claims 10-12, wherein the at least one input terminal further comprises a second input terminal. The method further includes: Disconnect the first resistor circuit element from the first input terminal; By activating a second pair of transistors connected to a second resistor element in one of the plurality of resistor elements in the first plurality of switching circuits, the second resistor element is connected between the second input terminal and the output terminal of the current monitoring circuit, wherein the second pair of transistors has a common connection; and The voltage across the second resistive circuit element is sensed.

17. An electronic system comprising: First circuit power supply rail; Circuit load; and A current monitoring circuit, coupled to the first circuit power supply rail and the circuit load, and comprising: Multiple resistive circuit elements are arranged between at least one input terminal and one output terminal of the current monitoring circuit, wherein the multiple resistive circuit elements have different resistance values; A plurality of switching circuits are coupled between the at least one input terminal and the plurality of resistive circuit elements, wherein each of the plurality of switching circuits includes a pair of transistors connected in series, the drain regions of the transistors being connected together. At least one driver amplifier, including an output and an input connected to the output terminal; The second plurality of switching circuits, each switching circuit including a first switching terminal coupled to the output of the at least one drive amplifier and a second switching terminal connected to the common drain of a pair of transistors coupled to the first plurality of switching circuits; and A sensing amplifier is configured to provide an output signal representing at least a portion of the load current to the output terminal.

18. The electronic system of claim 17, comprising: Second circuit power supply rail; and At least the first input terminal and the second input terminal; The first input terminal is coupled to the first circuit power supply rail and a first part of the first plurality of switch circuits, and the second input terminal is coupled to the second circuit power supply rail and a second part of the first plurality of switch circuits.

19. The electronic system of claim 18, comprising: An analog-to-digital converter (ADC) circuit coupled to the sensing amplifier; and The control circuit is configured to periodically initiate measurements of the sensed current from the first circuit power rail and the sensed current from the second circuit power rail using an ADC circuit.

20. The electronic system according to any one of claims 17-19, comprising: A third plurality of switching circuits are coupled to the plurality of resistive circuit elements, each switching circuit including a first switching terminal coupled to the resistive circuit element and a second switching terminal coupled to the non-inverting input of the sensing amplifier; and The inverting input of the sense amplifier is coupled to the output terminal.

21. The electronic system according to any one of claims 17-19, comprising a clamping resistor circuit element coupled between a common drain connection of at least one transistor pair and a common gate connection of the at least one transistor pair in the plurality of switching circuits.

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