Data transfer management within a memory device having multiple memory regions with different memory densities

Abstract

Data is received at a memory device from a host system, where the memory device includes a primary region to initially store the data received from the host system and one or more secondary regions to store data transferred from the primary region. A write operation is performed on one or more write units of the primary region with the data received from the host system, where a write unit of the primary region has a lower density than a write unit of the secondary region. It is determined whether to write at least a portion of the data received from the host system to a subset of write units of the primary region that corresponds to a predetermined number of write units. In response to determining that the subset of write units of the primary region is written to, another write operation is performed on at least one write unit of the secondary region with respective data of the subset of write units of the primary region.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory subsystems, and more specifically, to data transfer management within a memory device having multiple memory regions with different memory densities. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Attached Figure Description

[0003] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0004] Figure 1 This describes an instance computing environment including a memory subsystem according to some embodiments of the present disclosure.

[0005] Figure 2 This is a block diagram of an example method for migrating data from one memory area to another according to some embodiments of the present disclosure.

[0006] Figure 3A This is a block diagram of another example method for migrating data from one memory region of a memory device to another memory region according to some embodiments of the present disclosure.

[0007] Figure 3B This is a block diagram of another example method for migrating data from one memory region of a memory device to another memory region according to some embodiments of the present disclosure.

[0008] Figure 4 This is a flowchart of an example method for migrating data stored in a single-level cell (SLC) memory area to a four-level cell (QLC) memory area according to some embodiments of this disclosure.

[0009] Figure 5A This is a block diagram of another example method for migrating data from one memory region of a memory device to another memory region according to some embodiments of the present disclosure.

[0010] Figure 5B This is a block diagram of another example method for migrating data from one memory region of a memory device to another memory region according to some embodiments of the present disclosure.

[0011] Figure 6This is a flowchart of an example method for transferring data from one area of ​​a memory device to another area of ​​a memory device according to some embodiments of the present disclosure.

[0012] Figure 7 A block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0013] This disclosure pertains to data transfer management within a memory device having multiple memory regions with different memory densities. The memory subsystem may be a storage device, a memory module, or a combination of both. The following description, in conjunction with... Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that contains one or more components (such as memory devices) for storing data. The host system can provide data to be stored at the memory subsystem and can request retrieval of data from the memory subsystem.

[0014] Memory devices can include volatile and non-volatile memory devices capable of storing data from a host system. An example of a non-volatile memory device is a NAND flash memory device. (The following text is in conjunction with...) Figure 1 Other examples of non-volatile memory devices are described. Each of these non-volatile memory devices may contain one or more arrays of memory cells. A memory cell (“cell”) is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits stored. Logic states may be represented by binary values, such as “0” and “1” or combinations of such values. For example, a single-level cell (SLC) may store one bit of information and have two logic states. As another example, a four-level cell (QLC) may store four bits of information and have sixteen logic states.

[0015] Various memory access operations can be performed on memory cells. Data can be written to, read from, and erased from memory cells. Memory cells can be grouped into write units (e.g., pages). For some types of memory devices, a page is the smallest unit of writing. For some types of memory devices (e.g., NAND), memory cells can be grouped into erase units (e.g., physical blocks as a set of pages). A physical block is a 2D memory array of pages (cell rows) and strings (cell columns). Data can be written to a block page by page. Data can be erased at the block level. However, portions of a block cannot be erased.

[0016] A region (e.g., a memory cell, such as a block, within the same erase unit) of a physical memory device (e.g., NAND) may be configured as a lower-density cell type, such as SLC, and may operate in a corresponding lower-density mode (e.g., SLC mode). Another region may be configured as a higher-density cell type, such as QLC, and may operate in a corresponding higher-density mode (e.g., QLC mode). For simplicity, SLC is used throughout this specification as an example of a lower-density cell type, and QLC is used throughout this specification as an example of a higher-density cell type.

[0017] Although more bits can be stored in a higher density block (e.g., a QLC block) compared to a lower density block (e.g., an SLC block), writing data to a QLC block is generally slower than writing data to an SLC block. For simplicity, the SLC block is used throughout this specification as an example of a lower density block, and the QLC block is used throughout this specification as an example of a higher density block.

[0018] To improve performance, the memory subsystem can utilize regions of memory devices with lower-density blocks as caches. For example, the cache could be an SLC cache. The memory subsystem controller can configure regions of a physical memory device (e.g., memory cells within the same erase unit, such as blocks) as a lower-density cell type, such as SLC, and operate in the corresponding lower-density mode (e.g., SLC mode). Another region can be configured as a higher-density cell type, such as QLC, and operate in the corresponding higher-density mode (e.g., QLC mode).

[0019] The memory subsystem can prioritize host write requests and write data for host write requests to a cache (e.g., an SLC cache). When the SLC cache is filled, data can be relocated to a higher-density area (e.g., a QLC block).

[0020] When the host system is idle, a conventional memory device can transfer data written to an area with lower density blocks (e.g., SLC) to an area with higher density blocks (e.g., QLC). When the host system becomes active again, the conventional memory device switches back to storing data in the lower density blocks. However, while the conventional memory device has switched back to programming data in the lower density blocks, blocks in the higher density blocks (e.g., QLC blocks) may remain open. That is, the QLC blocks may not be fully written, and therefore only some pages are programmed. The next time the host system becomes idle and the conventional memory device writes data to the remaining pages at the QLC blocks, high reliability errors (HREs) may be introduced in the next programming operation. Because some time has passed since the last programming operation at the QLC blocks, charge loss is likely to occur at the memory cells of previously written pages, and therefore, erroneous bit information may be read while reading previously written information for the next programming pass. Thus, the conventional memory device inevitably propagates internal read errors to subsequent programming passes. However, conventional memory devices do not provide an error correction solution for errors propagating from internal reads of information from previously written pages in a QLC block. Furthermore, low-density parity checking (LDPC) or any other error correction code (ECC) may not correct such errors because the error correction operation of LDPC or other ECCs is performed based on the assumption that the written data is at least close to reliable.

[0021] The present disclosure addresses the above and other shortcomings by incorporating a memory subsystem that transfers data stored in a memory region with lower-density blocks to another memory region with higher-density blocks in a locked-step manner, regardless of the host system's state (e.g., idle or active). Once the memory subsystem determines that the write cell in the region with lower-density blocks stores enough data to fully program a single write cell in the region with higher-density blocks, the memory subsystem migrates the data from the region with lower-density blocks to the region with higher-density blocks. When migrating data, the memory subsystem writes multiple bits of information to all pages in the block or all cells in a page of the region with higher-density blocks at once, thereby eliminating any need for internal reads.

[0022] The advantages of this disclosure include, but are not limited to, increased memory capacity, because the size of regions with lower-density blocks can be kept to a minimum, and therefore, more memory cells can be allocated to regions with higher-density blocks. Furthermore, another advantage of this disclosure may include maintaining data integrity by eliminating internal errors introduced in multiple stages of the programming cycle operation. Therefore, memory cells have a reduced error rate, and thus longer program / erase (P / E) cycles are possible, resulting in a longer expected lifetime.

[0023] Figure 1 This description describes an example computing environment 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0024] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0025] The computing environment 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. The host system 120 uses the memory subsystem 110, for example, to write data to and read data from the memory subsystem 110. As used herein, “coupled to” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without intervening components), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0026] Host system 120 may be a computing device, such as a desktop computer, laptop computer, network server, mobile device, vehicle (e.g., aircraft, drone, train, automobile, or other means of transportation), Internet of Things (IoT) device, or such computing device containing memory and processing power. Host system 120 may be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 may further utilize an NVM High Speed ​​(NVMe) interface to access memory components, such as memory device 130. The physical host interface provides an interface for transmitting control, address, data, and other signals between memory subsystem 110 and host system 120.

[0027] The memory device may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. The volatile memory device (e.g., memory device 140) may be, but is not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0028] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory. The crosspoint array of the non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash memory-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them.

[0029] Although non-volatile memory devices such as 3D cross-point type and NAND type memory are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), magnetic random access memory (MRAM), NOR flash memory, electrically erasable programmable read-only memory (EEPROM), and cross-point arrays of non-volatile memory cells.

[0030] One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such arrays. In some embodiments, a particular memory device may include SLC regions and MLC regions, TLC regions, or QLC regions of memory cells. Such regions in the memory device may contain groups of SLC, MLC, TLC, or QLC memory cells configured as regions of the memory device. The memory cells of the memory device 130 may be grouped into pages or codewords, which may refer to write units or logical units of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks as write units or logical units to store data. Some types of memory (e.g., 3D cross-point) can group pages across the die and channels to form management units (MUs).

[0031] The memory subsystem controller 115 can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0032] The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0033] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although in Figure 1The instance memory subsystem 110 has been described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 may not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0034] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to enable the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical MU addresses, physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry translates commands received from the host system into command instructions to access the memory device 130 and translates responses associated with the memory device 130 into information for the host system 120.

[0035] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0036] In some embodiments, memory device 130 includes a local media controller 135, which operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0037] Memory subsystem 110 includes a data transfer management component 113 that manages the transfer of data from one area of ​​memory device 130 to another area of ​​memory device 130, wherein the latter area has a higher block density than the former. In some embodiments, memory subsystem controller 115 includes at least a portion of data transfer management component 113. For example, memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, data transfer management component 113 is part of host system 110, an application program, or an operating system.

[0038] Data transfer management component 113 can receive data from host system 120 for storage in memory device 130. Memory device 130 may have a primary area and one or more auxiliary areas, the primary area initially storing data received from the host system, and the auxiliary areas storing data transferred from the primary area. Data transfer management component 113 can perform write operations on one or more write units in the primary area using the data received from host system 120. During a write operation, data transfer management component 113 can monitor the progress of the write operation to determine whether a subset of write units in the primary area corresponding to a predetermined number of write units has been written to at least a portion of the data received from host system 120. In response to determining that the subset of write units in the primary area is being written based on the progress of the write operation, data transfer management component 113 can perform another write operation on at least one write unit in an auxiliary area using the corresponding data from the subset of write units in the primary area, thereby migrating data from the primary area to the auxiliary area, such that an integer number of auxiliary write units are written.

[0039] In some other embodiments, the data transfer management component 113 may receive data from the host system 120. The data transfer management component 113 may write data to one or more write cells in a region of the memory device 130 having lower density blocks (e.g., SLC blocks). In response to determining that four write cells in the SLC memory region have been written with at least a portion of the data received from the host system 120, the data transfer management component 113 may migrate corresponding data stored in the four write cells in the region having lower density blocks to a single write cell in a region of the memory device 130 having higher density blocks (e.g., QLC blocks). Further details regarding the operation of the data transfer management component 113 are described below.

[0040] Figure 2This is a block diagram 200 illustrating an example method for migrating data from one memory region 220 to another memory region 240 according to some embodiments of the present disclosure. The method may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, specialized logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on a processing device), or a combination thereof. In some embodiments, the method is performed by… Figure 1 The data transmission management component 113 executes. Although the method can be described in a specific order or sequence, the order of processes can be modified unless otherwise specified. Therefore, the embodiments should be understood as examples only, and the illustrated processes can be executed in different orders, and some processes can be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0041] The processing device may receive data from a host system (e.g., host system 120) for storage. In one embodiment, the data may be part of a stream. Based on specific criteria (e.g., the expected lifetime of the data), the stream corresponds to packets of data stored at multiple write units in the memory device 210. Once the processing device receives the data, it may store the data in the memory device 210. In one embodiment, the memory device 210 may include at least two dissimilar memory regions configured to have different memory densities (or bit densities): a first memory region 220 and a second memory region 240. The first memory region 220 may be configured to have a smaller memory density than the second memory region 240. In one embodiment, the first memory region 220 may be configured as the lowest density memory and the second memory region 240 may be configured as the highest density memory. For example, the first memory region 220 may be configured as a single-level-cell (SLC) memory, and the second memory region 240 may be configured as a four-level-cell (QLC) memory. In another embodiment, the first memory region 220 may span an area in the memory device 210 smaller than the second memory region 240, such as... Figure 2 As explained in the document. In other words, the first memory region 220 may contain a smaller number of memory cells than the second memory region 240. The first memory region 220 may serve as a cache memory in the memory device 210.

[0042] When storing data, the processing device may initially store or write data received from the host system to a first memory area 220, and then migrate the data from the first memory area 220 to a second memory area 240 when a trigger condition is met. For example, the processing device may write data to write units (e.g., write units 230A to 230N) in the first memory area 220. In one embodiment, a write unit may correspond to a page, which is the smallest write unit and contains a group of memory units (e.g., SLC). In another embodiment, a write unit may correspond to a block containing such a group of pages. The processing device may perform write operations on the write units (e.g., write units 230A to 230N) serially (e.g., one write unit after another) or in parallel (e.g., multiple write units at a time). Furthermore, the processing device performs write operations on the write units sequentially. Additionally, the processing device may store data of the same stream in the first memory area 220. In other words, the processing device may store data of different streams in different memory devices, rather than mixing data from different streams in one memory device.

[0043] When performing a write operation on a write unit (e.g., write units 230A to 230N), the processing device monitors the progress of the programming or write operation in the first memory region 220 to identify the timing for migrating data from the first memory region 220 to the second memory region 240. For example, the processing device can determine how much has been written to the write units of the first memory region 220 on a periodic basis. Figure 2 As explained, shaded write units 230A to 230E represent write units that have been programmed or written. When a write unit corresponds to a block, the write unit is considered written when all pages of that write unit have been written. Other write units 230E to 230N represent write units that have not yet been written.

[0044] In one embodiment, the processing device may determine whether the first four write units (e.g., write units 230A to 230D) of the first memory region 220 are programmed as trigger conditions for migration. For example, if the write units correspond to pages, the processing device may determine whether the four pages (e.g., write units 230A to 230D) are storing data. As another example, if the write units correspond to blocks, the processing device may determine whether all four blocks (e.g., write units 230A to 230D) have been completely written. That is, the processing device may determine whether all pages of each block (e.g., write units 230A to 230D) have been programmed. If not all four write units (e.g., write units 230A to 230D) have been programmed, the processing device may wait until they are all written or virtual data is stored in any of the write units in order to perform the migration process at regular intervals.

[0045] Once the processing device determines that the first four write units (e.g., write units 230A to 230D) have been written, at operation 260, the processing device can migrate the data stored in the four write units (e.g., write units 230A to 230D) to write units (e.g., write unit 250A) in the second memory region 240. The write units in the second memory region 240 (e.g., write units 250A to 250N) may correspond to pages (i.e., pages with QLC groups) or blocks (i.e., blocks containing page groups with QLCs). For example, the processing device can write data from four SLC blocks in the first memory region 220 to one QLC block in the second memory region 240. The processing device can write data from the four SLC blocks to the lower, upper, additional, and top pages of the QLC block in the second memory region 240 (e.g., via multiple programming operations). In some embodiments, the processing device can program data to the write units all at once. This type of programming technique is sometimes referred to as a single-pass programming scheme. According to a single-programming scheme, the processing device can program multiple pages in a word line at once. For example, the processing device can write data to all pages of a QLC block in a QLC memory at once. Although in Figure 2 In the text, the first memory region 220 and the second memory region 240 are described as being in the same memory device 210, but the first memory region 220 and the second memory region 240 may be located in different memory devices.

[0046] Subsequently, the processing device can determine whether another set of four write units (e.g., write units 230E to 230H (not shown)) following the write units in the first memory region 220 (e.g., write units 230A to 230D) have been written. In response to determining that the next four write units in the first memory region 220 have been written, the processing device can migrate the data written in the next four write units to write units in the second memory region 240 (e.g., write unit 250B), which will be programmed next in sequence (e.g., write unit 250B adjacent to write unit 250A). Thus, the processing device can continue to migrate data from the first memory region 220 to the second memory region 240 in this locked stepping manner. That is, once the four adjacent write units in the first memory region 220 have been written, the processing device can perform a write operation to write the data stored in the four write units in the first memory region 220 to a single write unit in the second memory region 240. In some embodiments, the processing device can perform the migration operation without notifying the host system. Furthermore, migration can occur while the processing device is storing data from the host system. In different embodiments, the first memory region 220 may be programmed to have different memory densities, such as SLC or MLC, as long as the memory density of the first memory region 220 is lower than the memory density of the second memory region 240. Similarly, the second memory region 240 may be configured as an MLC, TLC, or QLC memory, depending on whether the memory density of the second memory region 240 is higher than the memory density of the first memory region 220.

[0047] Figure 3A This is a block diagram 300 illustrating another example of a method for migrating data from one memory region 320 of a memory device 310 to another memory region 340 according to some embodiments of the present disclosure. The method may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, the method is performed by… Figure 1 The data transmission management component 113 executes. Although the method can be described in a specific order or sequence, the order of processes can be modified unless otherwise specified. Therefore, the embodiments should be understood as examples only, and the illustrated processes can be executed in different orders, and some processes can be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0048] Similar to about Figure 2In the described method, the processing device can receive data from a host system (e.g., host system 120) for storage. In one embodiment, the processing device may first store the data in a memory region (e.g., first memory region 320) of a memory device (e.g., memory device 310), but the data will later be moved to another memory region (e.g., second memory region 340) of the memory device (e.g., memory device 310) with a higher memory density. As described above, the first memory region 320 may correspond to... Figure 2 The first memory region 220, and the second memory region 340 may correspond to Figure 2 The second memory region 240. Therefore, the first memory region 320 can be configured as a single-level-cell (SLC) memory as a cache memory, and the second memory region 340 is a four-level-cell (QLC) memory. In other words, the first memory region 320 contains groups of write cells (e.g., write cells 330A to 330N), such as blocks or pages each having several SLCs. And the second memory region 340 has groups of write cells (e.g., write cells 345A to 345N), such as blocks or pages each having several QLCs.

[0049] Although the processing device stores data from the host system to the first memory region 320, specifically, to one or more write cells (e.g., write cells 330A to 330N) in the first memory region 320, the processing device can determine whether four adjacent write cells have been written as a trigger condition for migration. As an example, the processing device can determine that the first four write cells (e.g., write cells 330A to 330D) are storing data from the host system. Therefore, the processing device can initiate the migration of data from the first memory region 320 to the second memory region 340. Simultaneously, the processing device can receive instructions from the host system to delete data or sub-data stored at write cell 330B (e.g., in...). Figure 3A This is part of the data (marked with an "x"). In other instances, the host system can command the processing unit to delete all data.

[0050] Once the processing device determines that the first four write units (e.g., write units 330A to 330D) have been written, regardless of whether any of them stores invalid data, the processing device can retrieve the data stored in all four write units (e.g., write units 330A to 330D) for migration. Therefore, at operation 348, the processing device can, as per the relevant... Figure 2 Operation 260 describes a similar manner in which retrieved data containing invalid data (such as data marked with an “X”) is written from write unit 330B to write unit (e.g., write unit 345A) of the second memory area 340.

[0051] Once the data written to the first four write units (e.g., write units 330A to 330D) has been migrated, the processing device can determine whether the next four write units in the first memory area 320 (e.g., write units 330E to 330H (not shown)) have been written, and if so, perform a migration operation, regardless of whether the host system has instructed the deletion of data stored in any of these write units (e.g., write units 330E to 330H (not shown)). The processing device can perform the migration operation in this iterative manner while storing data received from the host system 120.

[0052] Figure 3B This is a block diagram 350 illustrating another example of a method for migrating data from one memory region 370 of a memory device 360 ​​to another memory region 390 according to some embodiments of the present disclosure. The method may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, the method is performed by… Figure 1 The data transmission management component 113 executes. Although the method can be described in a specific order or sequence, the order of processes can be modified unless otherwise specified. Therefore, the embodiments should be understood as examples only, and the illustrated processes can be executed in different orders, and some processes can be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0053] Similar to about Figure 2 In the described method, the processing device can receive data from a host system (e.g., host system 120) for storage. In one embodiment, the processing device may first store the data in a memory region (e.g., a first memory region 370) of a memory device (e.g., memory device 360), but the data will later be moved to another memory region (e.g., a second memory region 390) of the memory device (e.g., memory device 360) with a higher memory density. The first memory region 370 and the second memory region 390 may respectively correspond to Figure 2 The first memory regions 220 and 240. Therefore, the first memory region 370 can be configured as a single-level-cell (SLC) memory, and the second memory region 390 is a four-level-cell (QLC) memory. In other words, the first memory region 370 contains groups of write cells (e.g., write cells 380A to 380N), such as blocks or pages each having several SLCs. Similarly, the second memory region 390 has groups of write cells (e.g., write cells 395A to 395N), such as blocks or pages each having several QLCs.

[0054] Although the processing device stores data from the host system 120 to one or more write units 380A to 380N in the first memory area 370, the processing device can monitor the progress of the write operation. In one embodiment, the processing device can monitor whether the write operation of the first four write units (e.g., write units 380A to 380D) has been completed. However, at any time before the data stored in the four write units (e.g., write units 380A to 380D) is completely migrated to write unit 395A in the second memory area 390, the processing device can receive a command from the host system to delete data stored in any of the four write units (e.g., write units 380A to 380D) (e.g., write unit 380B). In response to receiving the delete command, the processing device can determine that the write unit (e.g., write unit 380B) is storing invalid data, as indicated by "X". Once the processing device identifies that write unit 380B stores invalid data, it can determine whether the write unit immediately following the four write units (e.g., write units 380A to 380D) (e.g., write unit 380E) has been written and stores valid data (e.g., the host system has not yet instructed to delete the data stored at write unit 380E). Therefore, the processing device can determine whether the write operation at the updated set of the four write units (e.g., write units 380A to 380C and 380E) has been completed.

[0055] In response to determining that an updated set of four write units (e.g., write units 380A to 380C and 380E) has been written, the processing device may perform a migration operation. In one embodiment, the processing device may retrieve data stored in the updated set of four write units (e.g., write units 380A to 380C and 380E). The processing device may write the retrieved data to a write unit (e.g., write unit 395A) of the second memory region 390. In one embodiment, the processing device may perform the migration operation while storing data received from the host system. In some embodiments, the processing device may perform the migration operation without notifying the host system. Subsequently, once the processing device determines that the next four write units of the first memory region 370 have been written and valid data has been stored, the processing device may perform another migration operation.

[0056] Figure 4This is a flowchart 400 of an example method for migrating data stored in a single-level-cell (SLC) memory area to a four-level-cell (QLC) memory area according to some embodiments of the present disclosure. Method 400 may be performed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1 The data transmission management component 113 executes. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0057] At operation 410, the processing device receives data from a host system (e.g., host system 120) of the memory device. In some embodiments, the memory device may include different memory regions configured to have different memory densities. For example, the memory device may include a single-level-cell (SLC) memory region and a four-level-cell (QLC) memory region. An SLC memory region may be associated with an SLC. A QLC memory region may be associated with a QLC. In one embodiment, the size of the SLC memory region may be smaller than the size of the QLC memory region having a smaller number of memory cells allocated to it.

[0058] At operation 420, the processing device writes data to one or more write cells in the SLC memory area of ​​the memory device. The SLC memory area may contain multiple write cells. A write cell may correspond to a page or a block having multiple pages.

[0059] At operation 430, in response to determining that at least a portion of the data received from the host system has been written to the four write cells of the SLC memory region, the processing device migrates the corresponding data stored in the four write cells of the SLC memory region to a single write cell of the QLC memory region of the memory device. For example, the processing device may determine that the memory density of the four write cells of the SLC memory region corresponds to the memory density of a single write cell of the QLC memory region. To perform a write operation on a single write cell of the QLC memory region, the processing device may determine that the four write cells of the SLC memory region should store data. In one embodiment, the four write cells may be adjacent write cells in the SLC memory region. After determining that the four write cells of the SLC memory region have been written, the processing device may immediately migrate the corresponding data stored in the four write cells of the SLC memory region to a single write cell of the QLC memory region. In some embodiments, the processing device may retrieve data from the four write cells of the SLC memory region and program the retrieved data into the write cell of the QLC memory region at once. For example, in the case where the write cell of the QLC memory region corresponds to a page, the processing device may program all memory cells of the page at once. In one instance of a block, where the write unit of the QLC area corresponds to another block, the processing device can program all pages of the block at once.

[0060] In other embodiments, the processing device may receive a command to delete a portion of data received from the host system. In one embodiment, the processing device may receive a deletion command when the corresponding data is stored in the SLC memory area. The processing device may then treat the requested portion of the data as invalid data. For example, the processing device may record an indication that invalid data is stored at the corresponding write unit in a mapping table that maps the logical addresses of the host system to the physical addresses of the memory devices. Furthermore, the processing device may determine whether any of the four write units in the SLC memory area stores invalid data.

[0061] In response to determining that at least one of the four write cells in the SLC memory region stores invalid data, the processing device can determine the number of write cells storing invalid data among the four write cells. Based on the determined number, the processing device can determine the number of write cells located among the four write cells that have been written with valid data. Subsequently, the processing device can migrate the valid data stored in the four write cells to a write cell in the QLC memory region. Therefore, the processing device can avoid transferring invalid data to the QLC memory region. Thus, when the processing device determines that any of the initial four write cells in the SLC memory region contains invalid data, the processing device finds another write cell whose data can be copied to the write cells in the QLC memory region.

[0062] In other embodiments, the processing device may migrate data from the initially determined four write cells of the SLC memory region to write cells of the QLC memory region, regardless of whether invalid data will be stored in the write cells of the QLC memory region. For example, in response to determining that a write cell among the four write cells of the SLC memory region stores invalid data, the processing device may still migrate the corresponding data stored in the four write cells of the SLC memory region to a single write cell of the QLC memory region of the memory device.

[0063] In other embodiments, after data has been migrated from four write cells in the SLC memory region, the processing device may determine whether the next four write cells in the SLC memory region have been written. The next four write cells may correspond to a set of four write cells that have been programmed after the initial four write cells in the SLC memory region and are located adjacent to the initial set of four write cells. In response to determining that the next four write cells in the SLC memory region have been written, the processing device may migrate the corresponding data stored in the next four write cells in the SLC memory region to another write cell in the QLC memory region, which immediately follows the write cell in the QLC memory region previously written with data from the initial four write cells in the SLC memory region.

[0064] Figure 5A This is a block diagram 500 illustrating another example of a method for migrating data from one memory region 520 of a memory device 510 to another memory region 540 according to some embodiments of the present disclosure. The method may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, the method is performed by… Figure 1 The data transmission management component 113 executes. Although the method can be described in a specific order or sequence, the order of processes can be modified unless otherwise specified. Therefore, the embodiments should be understood as examples only, and the illustrated processes can be executed in different orders, and some processes can be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0065] Similar to about Figure 2The described method allows the processing device to receive data from a host system (e.g., host system 120) for storage. In one embodiment, the processing device may first store the data in a memory region (e.g., first memory region 520) of a memory device (e.g., memory device 510), but later transfer the data to another memory region (e.g., second memory region 540) of the memory device (e.g., memory device 510). Thus, the first memory region 520 may correspond to a cache memory for memory device 510. In one embodiment, the first memory region 520 may be configured to be located in a memory location with a lower density than the second memory region 540. For example, the first memory region 520 may be configured as a multi-level cell (MLC) memory, and the second memory region 540 as a quad-level cell (QLC) memory. Therefore, the first memory region 520 may contain a group of write units (e.g., write units 530A to 530N), each having a set of pages or blocks of MLCs. In addition, the second memory region 540 has a group of write cells (e.g., write cells 545A to 545N), each containing a block or page of QLC.

[0066] As mentioned above Figure 2 As described, the shaded areas in write cells 530A to 530N and 545A to 545N represent data written to the respective write cells. A fully shaded write cell indicates a write cell fully programmed with data (e.g., where the write cell corresponds to a block, all pages of the block are storing data). Additionally, partially shaded write cells depict write cells that are being written with data (e.g., where the write cell corresponds to a block, some pages within the block are storing data).

[0067] Although data from the host system is written to write cells in the first memory region 520, the processing device can determine the number of write cells in the first memory region 520 that should be monitored regarding the progress of the write operation. The processing device can determine the number of write cells based on the memory density of the first memory region 520 and the second memory region 540. For example, the first memory region 520 is configured with an MLC memory density; while the second memory region 540 is configured with a QLC memory density. In order to program one write cell (e.g., write cells 545A to 545N) of the second memory region 540 each time, the processing device can determine that data from two write cells (e.g., write cells 530A and 530B) of the first memory region 520 is required. Therefore, the number of write cells in the first memory region 520 that need to be written for migration depends on the ratio of the memory densities of the first memory region 520 to the second memory region 540.

[0068] Therefore, once the processing device determines that two write units (e.g., write units 530A and 530B) in the first memory region 520 have been written, at operation 548, the processing device can migrate the data stored in the two write units (e.g., write units 530A and 530B) in the first memory region 520 to a write unit (e.g., write unit 545A) in the second memory region 540. Subsequently, the processing device can determine whether the next two write units (e.g., write units 530C and 530D) have been programmed. As explained, the two write units (e.g., write units 530C and 530D) may not yet be fully programmed. In this case, the processing device can wait until the write units (e.g., write units 530C and 530D) are fully written before migrating the corresponding data to the next write unit (e.g., write unit 545B) in the second memory region 540 (e.g., a one-to-two ratio, thus requiring data from the two write units in the first memory region 520 to program one write unit in the second memory region 540).

[0069] Although the data from the host system remains stored in the first memory area 520, the processing device may receive a request from the host system to delete, for example, some data stored in write unit 530B of the first memory area 520. In one embodiment, the processing device may continue to move data from, for example, write units 530A and 530B of the first memory area 520 to the second memory area 540. In other embodiments, the processing device may determine not to migrate the corresponding data from write unit 530B. Alternatively, the processing device may determine whether the next write unit 530C is ready for migration (e.g., write unit 530C has been fully written and stores valid data (e.g., data not requested to be deleted). While write unit 530C is being written, the processing device may continue to migrate data from write units 530A and 530C to write unit 545A of the second memory area 540.

[0070] Figure 5B This is a block diagram 550 illustrating another example of a method for migrating data from one memory region 570 of a memory device 560 to another memory region 590 according to some embodiments of the present disclosure. The method may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, the method is performed by… Figure 1The data transmission management component 113 executes. Although the method can be described in a specific order or sequence, the order of processes can be modified unless otherwise specified. Therefore, the embodiments should be understood as examples only, and the illustrated processes can be executed in different orders, and some processes can be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0071] Similar to about Figure 2 In the described method, the processing device receives data from a host system (e.g., host system 120) for storage. The processing device may initially store the data in a memory region (e.g., a first memory region 570) of a memory device (e.g., memory device 560), but later transfer the data to another memory region (e.g., a second memory region 590) of the memory device (e.g., memory device 560). The first memory region 570 may be configured as a three-level-cell (TLC) memory, and the second memory region 590 is a four-level-cell (QLC) memory. Thus, the first memory region 570 may be configured to be located in a memory location with a lower density than the second memory region 590. To fully program the write cells of the second memory region 590, the processing device may determine to program three write cells at a time based on the memory densities of the first and second memory regions 570 and 590, to avoid any write cells of the second memory region 590 remaining partially programmed. Therefore, in this example, the processing device can monitor the progress of the write operation to determine whether the four write units (e.g., write units 580A-D) of the first memory region 570 have been fully written. Once the four write units (e.g., write units 580A-580D) have been written, the processing device can migrate data from the four write units (e.g., write units 580A-580D) to the three write units (e.g., write units 595A-595C) of the second memory region 590. In one embodiment, the processing device can read data stored in the four write units (e.g., write units 580A-580D) of the first memory region 570 and program the data into the three write units (e.g., write units 595A-595C) of the second memory region 590 at one time (e.g., in parallel).

[0072] Figure 6 This is a flowchart of an example method 600 for transferring data from one area of ​​a memory device to another area of ​​a memory device according to some embodiments of the present disclosure. Method 600 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, specialized logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 600 is performed by… Figure 1The data transmission management component 113 executes. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0073] At operation 610, the processing device receives data from a host system (e.g., 120) of a memory device (e.g., memory device 130 or memory device 140). In some embodiments, the memory device has a primary area and other auxiliary areas. The primary area may initially store data received from the host system; while the auxiliary areas may store data transferred (moved or migrated) from the primary area. In one embodiment, the primary area may be configured to have a lower memory density than the auxiliary areas. Therefore, the processing device utilizes the primary area as a cache memory to quickly store data received from the host system, and later migrates the data in the cache memory to different areas of the memory device for long-term storage.

[0074] For example, a primary region may be associated with a single-level cell (SLC). A primary region may contain groups of write cells, and each write cell may contain groups of memory cells. A write cell may correspond to a page or a block of pages. Therefore, a write cell in a primary region may contain multiple SLCs. Each SLC may store one bit per memory cell. Therefore, a write cell in a primary region can be programmed faster compared to other memory cells in a secondary region that store more data bits per memory cell. As an example, a secondary region may be associated with a multi-level cell (MLC), a three-level cell (TLC), or a four-level cell (QLC). In another embodiment, a primary region may be associated with an MLC, and a secondary region may be associated with a TLC or a QLC. However, in another embodiment, a primary region may be associated with a TLC, and a secondary region may be associated with a QLC.

[0075] At operation 620, the processing device performs a write operation on one or more write units of the primary area using data received from the host system. In one embodiment, the processing device may write data to the write units sequentially.

[0076] As another example, the primary region can be configured with a TLC memory density, and the secondary region can be configured with a QLC memory density. In this case, the four write units of the primary region can correspond to the three write units of the secondary region. Therefore, the processing device can determine the number of write units in the primary region as four write units, which has a total memory density corresponding to the three write units of the secondary region.

[0077] At operation 630, the processing device monitors the progress of the write operation to determine whether a subset of write units in the main region, corresponding to a predetermined number of write units in the main region, has been written with at least a portion of the data received from the host system. In some embodiments, the processing device may monitor the number of write units in the main region that have been programmed based on data received from the host system. The processing device may determine the predetermined number of write units to be monitored as the number of write units in the main region with a total memory density corresponding to at least one write unit in the auxiliary region. As an example, the main region may be configured to have an SLC memory density, and the auxiliary region may have an MLC memory density. Therefore, the total memory density of two write units in the main region is equal to the memory density of one write unit in the auxiliary region. That is, data stored in two write units in the main region may be migrated to one write unit in the auxiliary region. When the main region has an MLC memory density and the auxiliary region has a QLC memory density, the same ratio of write units may be applied. Therefore, the processing device may determine two write units as the number of write units in the main region with a total memory density corresponding to one write unit in the auxiliary region.

[0078] In an instance where the primary region is configured with an MLC memory density and the secondary region has a QLC memory density, the processing device can determine whether two write units in the primary region are storing data from the host system. In one embodiment, the two write units may be positioned adjacent to each other in the primary region. The two write units may be sequentially programmed to store data. In another instance where the primary region is configured with a TLC memory density and the secondary region has a QLC memory density, the processing device can determine whether four write units in the primary region are storing data from the host system. The four write units may be positioned adjacent to each other in the primary region.

[0079] At operation 640, in response to the process determining that a subset of write cells in the primary region has been written based on the write operation, the processing device performs another write operation on at least one write cell in the secondary region using the corresponding data from the subset of write cells in the primary region. For example, the processing device may read data stored in the subset of write cells in the primary region and write said data to a write cell in the secondary region. The processing device may later erase the data stored in the subset of write cells in the primary region.

[0080] When the primary region is configured with an MLC memory density and the secondary region with a QLC memory density, the processing device can read data stored in two write units in the primary region and program the data into one write unit in the secondary region. Therefore, the write unit in the secondary region can be programmed only once. As another example, when the primary region is configured with a TLC memory density and the secondary region with a QLC memory density, the processing device can read data stored in four write units in the primary region and program the data into three write units in the secondary region. The processing device can perform the write operation serially or in parallel.

[0081] In some implementations, write units within a subset of write units in the primary area may store invalid data. Invalid data may correspond to a portion of data received from the host system that is subsequently requested to be deleted by the host system. For example, after receiving data from the host system, the processing device may later receive a command from the host system to delete the data or a portion of the data, while the corresponding data remains stored in the primary area. In response, the processing device may still copy the invalid data from the primary area to write units in the secondary area. In one implementation, the processing device may record the address of the invalid data in the secondary area in a mapping table that maps logical block addresses of the host system to physical block addresses of the memory device. In another embodiment, the processing device may ignore write units in the primary area storing invalid data and find another write unit whose data will be transferred to the write units in the secondary area in place of the write unit containing invalid data.

[0082] In other implementations, in response to determining that a subset of write units in the primary area has not been fully written, the processing device may continue writing data from the host system to the remaining write units in the primary area until all write units in the subset of write units in the primary area have been written. For example, if the primary area is configured as MLC memory and the secondary area is configured as QLC memory, the processing device may monitor the progress of the write operation to determine whether two write units have been programmed. If not, the processing device may wait until data is written to the two write units, and once the two write units are written, the processing device may initiate the migration of the corresponding data from the two write units to the write units in the secondary area. Furthermore, after moving data from the two write units, the processing device may continue to monitor the progress of the programming operation at the next two write units until the processing device completes the migration of the data stored in the primary area to the secondary area.

[0083] Figure 7 This describes an instance machine of computer system 700, within which an instruction set executable for causing the machine to perform any or more of the methods discussed herein is provided. In some embodiments, computer system 700 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110, or may be used to perform controller operations (e.g., execute an operating system to perform operations corresponding to...). Figure 1 (Operation of data transmission management component 113). In alternative embodiments, the machine may connect (e.g., network) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0084] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0085] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0086] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 for communication via network 720.

[0087] Data storage system 718 may include machine-readable storage medium 724 (also referred to as computer-readable medium) on which one or more instruction sets 726 or software embodying any one or more of the methods or functions described herein are stored. The instructions 726 may also reside wholly or at least partially within main memory 704 and / or processing device 702 during execution by computer system 700, which also constitute machine-readable storage medium. Machine-readable storage medium 724, data storage system 718, and / or main memory 704 may correspond to... Figure 1 The memory subsystem 110.

[0088] In one embodiment, instruction 726 includes implementation of read and write voltage management components (e.g., Figure 1 The data transfer management component 113) corresponds to the functional instructions. Although the machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0089] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0090] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0091] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions and each coupled to a computer system bus.

[0092] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0093] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon for programming a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any means for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0094] In the foregoing description, embodiments of this disclosure have been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory system comprising: A memory device comprising a primary area for initially storing data received from a host system and one or more auxiliary areas for storing data transferred from the primary area; as well as A processing device operatively coupled to the memory device, the processing device being configured to perform operations including: Receive the first portion of the data stream from the host system; A write operation is performed on one or more write units of the main region using the first portion of the data stream received from the host system, wherein the write units of the main region have a lower block density than the write units of the auxiliary region; Monitor the progress of the write operation to determine whether at least a portion of the first part of the data stream received from the host system is written to a subset of write units corresponding to a predetermined number of write units in the main area; It is determined that at least one write unit in the subset of write units in the main region stores invalid data; In response to the process determining, based on the write operation, that a subset of write units in the primary region has been written, another write operation is performed on at least one write unit in the secondary region using corresponding data from the subset of write units in the primary region, the corresponding data including the invalid data; and Receive the second part of the data stream from the host system.

2. The memory system of claim 1, wherein the operation further comprises: The predetermined number of write cells is determined as the number of write cells in the main region that have a total memory density corresponding to one or more write cells in the auxiliary region.

3. The memory system of claim 1, wherein the operation further comprises: In response to the process determining, based on the write operation, that the subset of write units in the main region has not been fully written, another portion of the data stream continues to be written from the host system to one or more other write units in the main region until all write units in the subset of write units in the main region have been written.

4. The memory system according to claim 1, wherein: Each write cell in the primary region is associated with a single-level cell (SLC); and Each write cell in the auxiliary region is associated with a multi-level cell (MLC), a three-level cell (TLC), or a four-level cell (QLC).

5. The memory system according to claim 1, wherein: Each write unit in the main region is associated with an MLC; and Each write cell in the auxiliary region is associated with a TLC or QLC.

6. The memory system according to claim 1, wherein: Each write unit in the primary region is associated with a TLC; and Each write cell in the auxiliary region is associated with a QLC.

7. A method of operating a memory device, comprising: The first portion of a data stream is received from the host system at the memory device, the memory device including a main area for initially storing data received from the host system and one or more auxiliary areas for storing data transferred from the main area; A write operation is performed on one or more write units of the main region using the first portion of the data stream received from the host system, wherein the write units of the main region have a lower block density than the write units of the auxiliary region; Monitor the progress of the write operation to determine whether at least a portion of the first part of the data stream received from the host system is written to a subset of write units corresponding to a predetermined number of write units in the main area; It is determined that at least one write unit in the subset of write units in the main region stores invalid data; In response to the process determining, based on the write operation, that a subset of write units in the primary region has been written, another write operation is performed on at least one write unit in the secondary region using corresponding data from the subset of write units in the primary region, the corresponding data including the invalid data; and The second portion of the data stream is received from the host system at the memory device.

8. The method of claim 7, further comprising: The predetermined number of write cells is determined as the number of write cells in the main region that have a total memory density corresponding to one or more write cells in the auxiliary region.

9. The method of claim 7, further comprising: In response to the process determining, based on the write operation, that the subset of write units in the main region has not been fully written, another portion of the data stream continues to be written from the host system to one or more other write units in the main region until all write units in the subset of write units in the main region have been written.

10. The method according to claim 7, wherein: Each write cell in the primary region is associated with a single-level cell (SLC); and Each write cell in the auxiliary region is associated with a multi-level cell (MLC), a three-level cell (TLC), or a four-level cell (QLC).

11. The method according to claim 7, wherein: Each write unit in the main region is associated with an MLC; and Each write cell in the auxiliary region is associated with a TLC or QLC.

12. The method according to claim 7, wherein: Each write unit in the primary region is associated with a TLC; and Each write cell in the auxiliary region is associated with a QLC.

13. A method of operating a memory device, comprising: The first portion of the data stream is received from the host system at the memory device; The first portion of the data stream is written to one or more write cells of a region of the memory device having a single-level cell (SLC) block; and Four write units of a region of the memory device having an SLC block are determined to be written into the first portion of the data stream received from the host system; It is determined that at least one of the four write units in the area having SLC blocks of the memory device stores invalid data; In response to determining that four write units of the area of ​​the memory device having an SLC block have been written with at least a portion of the first part of the data stream received from the host system, corresponding data stored in the four write units of the area of ​​the memory device having an SLC block is migrated to a single write unit of the area of ​​the memory device having a four-level cell (QLC) block, the corresponding data including the invalid data; as well as The second portion of the data stream is received from the host system at the memory device.

14. The method of claim 13, further comprising: A command is received to delete another portion of the data stream received from the host system, the invalid data corresponding to the other portion of the data stream associated with the deletion command.

15. The method of claim 14, further comprising: In response to determining that at least one of the four write units of the area having an SLC block in the memory device stores the invalid data, the number of write units storing the invalid data among the four write units is determined; Identify one or more write units corresponding to the number of write units that have not been written with the invalid data, wherein the one or more write units are positioned immediately following the four write units; as well as The corresponding data stored in one or more write units located immediately following the four write units and in any one or more write units among the four write units that do not store the invalid data are migrated to the single write unit of the area of ​​the memory device having a QLC block.

16. The method of claim 13, further comprising: Determine whether four additional write cells immediately following the four write cells in the region of the memory device having an SLC block have been written; as well as In response to determining that the additional four write units of the area of ​​the memory device having an SLC block have been written, the corresponding data stored in the additional four write units of the SLC memory area is migrated to another write unit of the area of ​​the memory device having a QLC block, the other write unit being immediately following the single write unit of the area of ​​the memory device having a QLC block.

17. The method of claim 13, wherein: The region of the memory device having SLC blocks is smaller than the region of the memory device having QLC blocks; The write unit of the region of the memory device having an SLC block corresponds to a page comprising multiple SLCs or a block comprising multiple pages; and The write unit of the region of the memory device having QLC blocks corresponds to a page comprising multiple QLCs or a block comprising multiple pages.

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