Josephson double balanced coupler

Abstract

A technique is provided to assist quantum gates between qubits using tunable couplers. In one example, a quantum coupling device may include a Josephson ring modulator (JRM) operatively coupled to a first qubit and a second qubit in a balanced bridge topology via respective first and second capacitive devices. The JRM provides tunable coupling between the first qubit and the second qubit.

Description

Background Technology

[0001] This disclosure relates to a quantum coupling device, and more specifically to a quantum coupling device that assists in the establishment of quantum gates between qubits. Summary of the Invention

[0002] The following overview is presented to provide a basic understanding of one or more embodiments of the invention. This overview is not intended to limit key or essential elements or to define any scope of a particular embodiment or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the specific implementations presented later. In one or more embodiments described herein, systems, devices, computer-implemented methods, and / or computer program products are described that use tunable couplers to assist quantum gates between multiple qubits.

[0003] According to an embodiment, the quantum coupling device may include a Josephson ring modulator (JRM) operatively coupled to a first qubit and a second qubit in a balanced bridge topology via respective first and second capacitor elements. The JRM provides tunable coupling between the first qubit and the second qubit.

[0004] In one embodiment, the quantum coupling device may further include a biasing component that applies a bias to the JRM to facilitate control over the coupling between the first qubit and the second qubit. In another embodiment, the first qubit and the second qubit remain decoupled until the bias is applied to the JRM. In yet another embodiment, the biasing component applies a radio frequency (RF) charge bias signal to the JRM to drive parameter conversion between the first qubit and the second qubit. In yet another embodiment, the biasing component applies an RF flux bias signal to the JRM to drive parameter conversion between the first qubit and the second qubit. In yet another embodiment, the RF charge bias signal and / or the RF flux bias signal includes a difference frequency defined by the respective frequencies of the first qubit and the second qubit.

[0005] In one embodiment, the first and second qubits are degenerate qubits. In this embodiment, a DC flux bias signal is applied to the JRM to drive excitation exchange between the first and second qubits. In another embodiment, the first and second qubits are non-degenerate qubits. In this embodiment, a DC flux bias signal is applied to the JRM to drive ZZ interaction between the first and second qubits. In another embodiment, the quantum coupling device may further include: a flux bias line established on an interposer layer, the interposer layer forming a loop below the JRM. In another embodiment, the flux bias line includes: an entry flux bias line and a return path running alongside the entry flux bias line. In another embodiment, the first capacitive device is formed inside the blade of the first qubit.

[0006] According to another embodiment, a computer-implemented method may include: operatively coupling a JRM to a first qubit and a second qubit in a balanced bridge topology via respective first capacitive and second capacitive devices. The computer-implemented method may further include: tunably coupling the first qubit and the second qubit using the JRM.

[0007] In one embodiment, the computer-implemented method may further include: applying a bias to the JRM to facilitate control over the coupling between the first qubit and the second qubit. In another embodiment, the first qubit and the second qubit remain decoupled until the bias is applied to the JRM. In yet another embodiment, the computer-implemented method may further include: controlling the polarity of the coupling between the first qubit and the second qubit by adjusting the polarity of the bias applied to the JRM.

[0008] In one embodiment, the computer-implemented method may further include: applying an RF charge bias signal to the JRM to drive parameter switching between the first qubit and the second qubit. In another embodiment, the computer-implemented method may further include: applying an RF flux bias signal to the JRM to drive parameter switching between the first qubit and the second qubit. In another embodiment, the first qubit and the second qubit are degenerate qubits. In yet another embodiment, the computer-implemented method may further include: applying a DC flux bias signal to the JRM to drive excitation exchange between the first qubit and the second qubit. In yet another embodiment, the first qubit and the second qubit are non-degenerate qubits. In yet another embodiment, the computer-implemented method may further include: applying a DC flux bias signal to the JRM to drive ZZ interaction between the first qubit and the second qubit.

[0009] According to another embodiment, the quantum coupling system may include a Josephson ring modulator (JRM), a first qubit, and a second qubit. The first qubit is coupled to the JRM via a first inductor. The second qubit is coupled to the JRM via a second inductor. The first and second qubits are coupled to the JRM in a balanced bridge topology via corresponding first and second inductors. The JRM may provide tunable coupling between the first and second qubits. In one embodiment, the system further includes a biasing component that applies a bias to the JRM to control the coupling between the first and second qubits. In another embodiment, the first and second qubits remain decoupled until the bias is applied to the JRM. Attached Figure Description

[0010] Figure 1-4 A circuit diagram of an exemplary, non-limiting device that can use a Josephson ring modulator (JRM) to assist quantum gates between qubits according to one or more embodiments described herein is shown.

[0011] Figures 5A-5D Exemplary, non-limiting response patterns of the relationship between JRM and qubits according to one or more embodiments described herein are shown.

[0012] Figure 6 A circuit diagram of an exemplary, non-limiting reduced coupling circuit used in a simulation according to one or more embodiments described herein is shown.

[0013] Figure 7 The illustration depicts Figure 6 The graph shows the WRSpice simulation results of the circuit.

[0014] Figure 8 An exemplary, non-limiting graph depicting the relationship between device energy levels and magnetic flux bias (in magnetic flux quanta) according to one or more embodiments described herein is shown.

[0015] Figure 9 An exemplary, non-limiting pseudo-color map depicting the relationship between ZZ coupling and flux bias and second qubit frequency according to one or more embodiments described herein is shown.

[0016] Figure 10 An exemplary non-limiting graph depicting the relationship between ZZ coupling and magnetic flux bias (in units of magnetic flux quanta) according to one or more embodiments described herein is shown.

[0017] Figure 11An exemplary non-limiting graph depicting the relationship between ZZ coupling and magnetic flux bias (in magnetic flux quanta) according to one or more embodiments described herein is shown.

[0018] Figure 12 An exemplary non-limiting graph showing the relationship between the applied flux bias and the time used to formulate a two-qubit phase gate, according to one or more embodiments described herein.

[0019] Figure 13 The diagram illustrates the relative phase difference between the |01> quantum state and the |11> quantum state according to one or more embodiments described herein, and the method for... Figure 12 An exemplary non-restrictive graph showing the relationship between the applied flux distribution and time.

[0020] Figure 14 An exemplary, non-limiting example diagram is shown depicting the relationship between eigenstate occupancy |Cn|^2 and eigenstate number n according to one or more embodiments described herein.

[0021] Figure 15 An exemplary non-limiting graph depicting the relationship between the excitation expectation of a first qubit and a second qubit and time, according to one or more embodiments described herein, is shown, wherein the first qubit and the second qubit are coupled via a ring modulator.

[0022] Figure 16 An exemplary non-limiting graph depicting the relationship between the excitation expectation of a first qubit and a second qubit and time, according to one or more embodiments described herein, is shown, wherein the first qubit and the second qubit are coupled via a JRM during a swapping operation.

[0023] Figure 17 A top view of an exemplary, non-limiting device, according to one or more embodiments described herein, is shown that can reduce the routing complexity associated with cross features in a multidimensional qubit array.

[0024] Figure 18 A top view of an exemplary, non-limiting device including a multidimensional qubit array according to one or more embodiments described herein is shown.

[0025] Figure 19 A top view of an exemplary, non-limiting device that can facilitate enhanced coupling according to one or more embodiments described herein is shown.

[0026] Figure 20An exemplary non-limiting graph depicting the relationship between the relative phase difference and time between the |01> quantum state and the |11> quantum state according to one or more embodiments described herein is shown.

[0027] Figure 21 An exemplary non-limiting graph depicting the relationship between a population and its eigenstates according to one or more embodiments described herein is shown.

[0028] Figure 22 An exemplary non-limiting graph depicting the relationship between the expected value of the excitation and time, according to one or more embodiments described herein, is shown.

[0029] Figure 23 An example non-limiting graph depicting the relationship between the applied flux bias and the time used to formulate a two-qubit gate via a JRM is shown according to one or more embodiments described herein.

[0030] Figure 24-25 A top view of an exemplary, non-limiting device that can facilitate flux coupling according to one or more embodiments described herein is shown.

[0031] Figure 26-27 A flowchart illustrating an exemplary, non-limiting computer implementation of a method that can use JRM to assist quantum gates between qubits according to one or more embodiments of the present description is shown.

[0032] Figure 28 A block diagram illustrating an exemplary, non-limiting operating environment that may facilitate one or more embodiments described herein. Detailed Implementation

[0033] The following detailed description is illustrative only and is not intended to limit the application or use of the embodiments and / or implementations. Furthermore, it is not intended to be limited by any explicit or implicit information presented in the prior background or summary of the invention, or in the detailed description.

[0034] One or more embodiments will now be described with reference to the accompanying drawings, wherein the same reference numerals are used throughout to refer to the same elements. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that one or more embodiments may be practiced without these specific details in various circumstances.

[0035] Classical computers operate on binary digits (or bits) that store or represent information as binary states to perform computation and information processing functions. In contrast, quantum computing devices operate on qubits (or quantum bits), which store or represent information as binary states and superpositions of binary states. To do this, quantum computing devices utilize quantum mechanical phenomena such as entanglement and interference.

[0036] Quantum computing uses qubits instead of classical computation bits as its basic unit. A qubit (e.g., a quantum binary digit) is a quantum mechanical simulation of that classical bit. While a classical bit can only take on one of two fundamental states (e.g., 0 or 1), a qubit can take on a superposition of these fundamental states (e.g., α|0>+β|1), where α and β are complex scalars such that |α| 2 +|β| 2 =1), thus allowing multiple qubits to theoretically hold more information exponentially than the same number of classical bits. Therefore, quantum computers (e.g., computers that use qubits instead of just classical bits) can theoretically solve problems that might be extremely difficult for classical computers very quickly. A bit in a classical computer is simply a binary digit with a value of 0 or 1. Almost any device with two distinct states can be used to represent a classical bit: switches, valves, magnets, coins, etc. Qubits participate in the quantum mystery, occupying a superposition of 0 and 1 states. A qubit may not have an intermediate value, such as 0.63; when the state of the qubit is measured, the result is either 0 or 1. However, during computation, a qubit can act as a mixture of states, for example: 63% 0 and 37% 1. General quantum programming requires coordination between the quantum and classical parts of computation. One way to consider general quantum programming is to identify the processes and abstractions involved in specifying a quantum algorithm, translating that algorithm into an executable form, running experiments or simulations, and analyzing those results. The concept throughout these processes is the use of intermediate representations. The intermediate representation (IR) of a computation is neither its source language description nor the target machine instructions, but something in between. During the translation and optimization process, the compiler can use several IRs. The input is source code describing the quantum algorithm and one or more compile-time parameters. The output is a quantum / classical program expressed using high-level IRs. The difference between a quantum and a classical computer is that the quantum computer is probabilistic, so a measurement of the algorithm's output provides an appropriate solution within an algorithm-specific confidence interval. This computation is then repeated until a potentially deterministic solution that satisfactorily satisfies the problem can be achieved.

[0037] By using the laws of quantum mechanics to process information, quantum computers offer new ways to perform computational tasks such as molecular computing, financial risk calculation, optimization, and more.

[0038] A key component of important quantum computing devices is the two-qubit gate, which facilitates the exchange of information between adjacent qubits. Current techniques for coupling two qubits employ various approaches, each with its own advantages and disadvantages in terms of gate speed, fidelity, and ease of operation.

[0039] For example, feasible cross-resonant gates typically involve adjacent qubits with relatively close frequencies (e.g., within anharmonicity) but not actually overlapping. This necessitates strict requirements on the frequencies of the coupled qubit pairs. As another example, techniques employing static coupling (e.g., using capacitors) between adjacent qubits must generally handle qubit-qubit interactions that are always on even when the associated controller is not actively executing a two-qubit gate. Cross-resonant gate architectures can use an intermediate qubit to reduce residual crosstalk between adjacent qubits. While the intermediate qubit can reduce residual crosstalk to a relatively low level, this reduction is not zero. In some instances, residual crosstalk can lead to unintentional coherent rotations or coherent qubit errors, which negatively impact gate fidelity.

[0040] Figure 1 A circuit diagram of an exemplary, non-limiting device that can use a Josephson ring modulator (JRM) to assist quantum gates between qubits according to one or more embodiments described herein is shown.

[0041] like Figure 1 As illustrated in the exemplary embodiment, device 100 includes a JRM 110, a first qubit 120, a second qubit 130, a first capacitive device 140, and a second capacitive device 150. JRM 110 includes four Josephson junctions (JJs) 112, 114, 116, and 118 arranged in a ring configuration. In this embodiment, the ring configuration is a Wheatstone bridge configuration.

[0042] Those skilled in the art will recognize that the JRM110 includes three orthogonal electrical modes. Reference Figures 5A-5C The three orthogonal electrical modes of the JRM110 include: Figure 5A Φ X The X mode is represented; in Figure 5B Φ Y The Y-mode represented; and in Figure 5C Φ Z The Z-mode is represented. In an embodiment, the Hamiltonian operator of JRM110 can be approximated using the Hamiltonian operator defined by Equation 1:

[0043]

[0044] According to Equation 1 above, E CThis represents the electrostatic charging energy of each Josephson junction. The charge operator representing mode X, The charge operator representing mode Y, E represents the charge operator of mode Z. J Φ represents the Josephson energy of each Josephson junction. X The flux operator Φ represents pattern X. Y The flux operator Φ represents mode Y. Z The flux operator Φ represents mode Z. Bias The applied flux bias is represented by n, which is an integer, and φ0 represents the superconducting magnetic flux quantum. As described in more detail below, the JRM 110 can provide tunable coupling between the first quantum bit 120 and the second quantum bit 130.

[0045] The first qubit 120 includes a JJ 122 coupled in parallel with a capacitive device 124. The first qubit 120 further includes a capacitive device 128 coupled to ground for the JJ 122. The second qubit 130 includes a JJ 132 coupled in parallel with a capacitive device 134. The second qubit 130 further includes a capacitive device 138 coupled to ground for the JJ 132. Capacitive devices 126 and 136 couple the first qubit 120 and the second qubit 130 to external circuitry, respectively. Examples of qubits suitable for implementing the first qubit 120 and / or the second qubit 130 include, but are not limited to: fixed-frequency qubits, tunable qubits, transmission qubits, fixed-frequency transmission qubits, tunable transmission qubits, etc. Reference Figure 5D The first qubit 120 and the second qubit 130 each include electrical modes represented by Φ1 and Φ2, respectively.

[0046] The first capacitive device 140 includes a capacitive device 142 that couples node 121 of the first qubit 120 to node 111 of the JRM 110, and a capacitive device 148 that couples node 123 of the first qubit 120 to node 115 of the JRM 110. The first capacitive device 140 further includes capacitive devices 144 and 146 that are coupled in parallel with the JRM 110 via nodes 111 and 115. The second capacitive device 150 includes a capacitive device 152 that couples node 131 of the second qubit 130 to node 113 of the JRM 110, and a capacitive device 158 that couples node 133 of the second qubit 130 to node 117 of the JRM 110. The second capacitive device 150 further includes capacitive devices 154 and 156 that are coupled in parallel with the JRM 110 via nodes 113 and 117.

[0047] Figure 2A circuit diagram of an exemplary, non-limiting device 200, which can use a Josephson ring modulator (JRM) to assist quantum gates between qubits according to one or more embodiments described herein, is shown. Similar to... Figure 1 Device 100 and device 200 also include JRM 110, first qubit 120, and second qubit 130. For example... Figure 2 As shown, the device 200 further includes a first reactor device 240 and a second reactor device 250.

[0048] The first reactive device 240 includes an inductor 242 coupled in parallel with JRM 110 via nodes 111 and 115. The first reactive device 240 further includes a capacitive device 244 inserted between node 121 of the first qubit 120 and the inductor 242. The second reactive device 250 includes an inductor 252 coupled in parallel with JRM 110 via nodes 113 and 117. The second reactive device 250 further includes a capacitive device 254 inserted between node 131 of the second qubit 130 and the inductor 252. In an embodiment, the inductor 242 and / or the inductor 252 may be implemented using three winding transformations with a 1:1:1 turns ratio.

[0049] The various embodiments described herein relate to quantum coupling devices that assist a two-qubit gate having zero static coupling in an off state and high coupling (e.g., >1 GHz) in an on state. For this purpose, in a balanced bridge topology, adjacent qubits (e.g., first qubit 120 and second qubit 130) are connected across a JRM (e.g., JRM 110). The balanced bridge topology can connect the modes of the JRM (e.g., in capacitors or mutual inductors, respectively) via capacitors or mutual inductors. Figures 5A-5C The X, Y, and / or Z modes of JRM 110 depicted in the diagram are weakly coupled to modes of adjacent qubits (e.g., in...). Figure 5D The pattern of the first qubit 120 and the second qubit 130 depicted in the image.

[0050] For example, Figure 1 Device 100 illustrates an embodiment in which adjacent qubits are capacitively coupled to a JRM to form a balanced bridge topology. In this example, JRM 110 is operatively coupled to a first qubit 120 and a second qubit 130 in the balanced bridge topology via a first capacitive device 140 and a second capacitive device 150, respectively. As another example, Figure 2Device 200 illustrates an embodiment in which adjacent qubits are coupled to each other to a JRM to form a balanced bridge topology. In this example, JRM 110 is operatively coupled to a first qubit 120 and a second qubit 130 in the balanced bridge topology via a first reactive device 240 and a second reactive device 250, respectively.

[0051] By connecting the first qubit 120 and the second qubit 130 across JRM 110 in a balanced bridge topology, the first qubit 120 and the second qubit 130 remain decoupled until a bias is applied to JRM 110. In other words, when no bias (e.g., charge, flux, and / or current) is applied to JRM 110, devices 100 and / or 200 facilitate a two-qubit gate with zero static coupling. It is worth noting that the zero static coupling provided by various embodiments of this disclosure is agnostic to detuning between the coupled qubits.

[0052] One aspect of this disclosure that facilitates this zero static coupling is that the corresponding critical currents of the four JJ 112, 114, 116, and 118 forming the JRM 110 are nominally equal. Furthermore, by virtue of having nominally equivalent critical currents, the corresponding Josephson inductances of these four JJ 112, 114, 116, and 118 are also nominally equivalent. As an example, Figure 1 The oscillation of the first qubit 120 in JRM 110 can induce equal voltages with opposite polarities at nodes 111 and 115. Due to the symmetry of the four JJs 112, 114, 116, and 118 forming JRM 110, no voltage is induced at nodes 113 and 117 of JRM 110. In this case, nodes 113 and 117 of JRM 110 become virtual ground. As a result of nodes 113 and 117 becoming virtual ground, no signal is coupled from the first qubit 120 to the second qubit 130.

[0053] While the first qubit 120 and the second qubit 130 remain decoupled until a bias is applied to the JRM 110, the unbalanced bridge topology facilitates tunable coupling of the first qubit 120 and the second qubit 130. To this end, embodiments of this disclosure utilize a biasing component that applies a bias to the JRM to facilitate control over the coupling between the first qubit 120 and the second qubit 130. Figure 3-4 An exemplary biasing component for facilitating tunably coupled adjacent qubits, implemented according to embodiments of the present disclosure, is shown.

[0054] Figure 3 A circuit diagram of another exemplary, non-limiting device 300 that can use JRM to assist quantum gates between qubits according to one or more embodiments described herein is shown. Figure 3As shown, device 300 includes a biasing component 310 for applying a bias signal to device 100. Figure 3 In this embodiment, biasing component 310 includes a current source 320 and a flux bias line 330 forming a loop within JRM 110 of device 100. The current source 320 generates a flux bias signal to be applied to JRM 110 via the flux bias line 330. In an embodiment, the current source 320 may generate a flux bias signal with a tunable amplitude. The drive current for applying the flux bias signal to JRM 110 via the flux bias line 330 similarly passes through the four JJ112, 114, 116, and 118 forming JRM 110.

[0055] In one embodiment, biasing component 310 applies a direct current (DC) flux bias signal to JRM 110. In this embodiment, applying the DC flux bias signal to JRM 110 modulates the corresponding critical currents in the four JJs 112, 114, 116, and 118 forming JRM 110. By modulating the corresponding critical currents, the corresponding inductances of the four JJs 112, 114, 116, and 118 forming JRM 110 are also modulated. Such modulation disrupts the symmetry of JRM 110 by breaking the inductance matching between the nodes of JRM 110 (e.g., nodes 111, 113, 115, and 117). Breaking the symmetry of JRM 110 causes the balanced bridge topology to become unbalanced, which helps to provide tunable coupling between the first qubit 120 and the second qubit 130.

[0056] In embodiments where the first qubit 120 and the second qubit 130 are degenerate qubits, applying a DC flux bias signal to the JRM 110 drives excitation exchange between the first qubit 120 and the second qubit 130. For example, applying a DC flux bias signal to the JRM 110 can drive an XX-like exchange interaction between the first qubit 120 and the second qubit 130. In embodiments where the first qubit 120 and the second qubit 130 are non-degenerate qubits, applying a DC flux bias signal to the JRM 110 drives a ZZ interaction between the first qubit 120 and the second qubit 130.

[0057] In one embodiment, biasing component 310 applies a radio frequency (RF) flux bias signal to JRM 110. In another embodiment, the RF flux bias signal includes a difference frequency defined by the respective frequencies of the first qubit 120 and the second qubit 130. For example, the difference frequency is defined by the respective resonant frequencies of the first qubit 120 and the second qubit 130. In embodiments where the first qubit 120 and the second qubit 130 are non-degenerate qubits, applying the RF flux bias signal to JRM 110 drives parameter switching between the first qubit 120 and the second qubit 130. In embodiments where the first qubit 120 and the second qubit 130 are non-degenerate qubits, applying the RF flux bias signal to JRM 110 drives three-wave mixing in JRM 110 and performs excitation exchange between the first qubit 120 and the second qubit 130.

[0058] In an embodiment, device 300 further includes a polarity component 340 that controls the polarity of the coupling between the first qubit 120 and the second qubit 130. The polarity component 340 controls the polarity of the coupling by adjusting the polarity of a flux bias signal applied to the JRM 110. As an example, applying a flux bias signal to the JRM 110 achieves coupling between the first qubit 120 and the second qubit 130. Because the JJs (e.g., the four JJs 112, 114, 116, and 118 forming the JRM 110) are nonlinear inductors, the current induced in each qubit (i.e., the first qubit 120 and the second qubit 130) flowing in the same direction as the flux bias signal within the JRM 110 experiences a higher inductance than the induced current flowing in the opposite direction to the flux bias signal.

[0059] Therefore, the polarity component 340 can control the polarity of the coupling between the first qubit 120 and the second qubit 130 by controlling the polarity of the flux bias signal generated by the bias component 330. Specifically, when a flux bias signal in the first direction (or polarity) is applied to the JRM 110, the excitation of each qubit can be coupled to each other with a positive polarity. Alternatively, when a flux bias signal in a second direction (or polarity) opposite to the first direction is applied to the JRM 110, the excitation of each qubit can be coupled to each other with a negative polarity. (Refer to below...) Figure 6-7 This aspect of the disclosure will be discussed in more detail.

[0060] Figure 4 A circuit diagram of an exemplary, non-limiting device 400, which can use a Josephson ring modulator (JRM) to assist in the quantum gate between qubits according to one or more embodiments described herein, is shown. Figure 4 As shown, device 400 includes a biasing component 410 for applying a bias signal to device 100. Figure 4 In this embodiment, biasing component 410 includes a voltage source 420 and a pair of charge bias lines (i.e., charge bias lines 432 and 434). Voltage source 410 generates a charge bias signal for application to JRM 110 via charge bias lines 432 and 434. In an embodiment, voltage source 410 can generate a charge bias signal with an adjustable resonant amplitude and a tunable frequency. In an embodiment, applying the charge bias signal to JRM 110 via charge bias lines 432 and 434 drives the Z-mode of JRM 110 (e.g., ...). Figure 5C Z-mode).

[0061] In one embodiment, biasing component 410 applies an RF charge bias signal to JRM 110. In another embodiment, this RF charge bias signal includes a difference frequency defined by the respective frequencies of the first qubit 120 and the second qubit 130. For example, the difference frequency is defined by the respective resonant frequencies of the first qubit 120 and the second qubit 130. In embodiments where the first qubit 120 and the second qubit 130 are non-degenerate qubits, applying the RF charge bias signal to JRM 110 drives parameter switching between the first qubit 120 and the second qubit 130. In embodiments where the first qubit 120 and the second qubit 130 are non-degenerate qubits, applying the RF charge bias signal to JRM 110 drives a three-wave mixing operation in JRM 110 and enables excitation exchange between the first qubit 120 and the second qubit 130.

[0062] Devices 100, 200, 300, and / or 400 may include semiconductor and / or superconducting devices that can be implemented in quantum devices. Examples of suitable quantum devices that can implement devices 100, 200, 300, and / or 400 include, but are not limited to, quantum hardware, quantum processors, quantum computers, etc.

[0063] Fabrication of the various embodiments of this disclosure described herein and / or illustrated in the accompanying drawings (e.g., devices 100, 200, 300, and / or 400) may include a multi-step sequence of steps, such as photolithography and / or chemical processing steps, which facilitate the incremental creation of electronic-based systems, devices, components, and / or circuits in semiconductor and / or superconducting devices (e.g., integrated circuits). For example, the various embodiments of this disclosure described herein and / or illustrated in the figures (e.g., devices 100, 200, 300, and / or 400) may be fabricated on a substrate (e.g., devices 100, 200, 300, and / or 400). Silicon (Si) substrates employing technologies including, but not limited to, the following: photolithography, microlithography, nanolithography, nanoimprinting, photomask technology, patterning technology, photoresist technology (e.g., positive photoresist, negative photoresist, mixed-tone photoresist, etc.), etching technology (e.g., reactive ion etching (RIE), dry etching, wet etching, ion beam etching, plasma etching, laser ablation, etc.), evaporation technology, sputtering technology, plasma ashing technology, heat treatment (e.g., rapid thermal annealing, furnace annealing, thermal oxidation, etc.), chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), chemical mechanical planarization (CMP), back polishing technology and / or another technology used for manufacturing integrated circuits.

[0064] Various materials can be used to manufacture the various embodiments of this disclosure described herein and / or illustrated in the accompanying drawings (e.g., devices 100, 200, 300, and / or 400). For example, the different embodiments of this disclosure described herein and / or illustrated in the accompanying drawings (e.g., devices 100, 200, 300, and / or 400) can be manufactured using one or more different material classes, including but not limited to: conductive materials, semiconductor materials, superconducting materials, dielectric materials, polymer materials, organic materials, inorganic materials, nonconducting materials, and / or another material that can be used in conjunction with one or more of the techniques described above for manufacturing integrated circuits.

[0065] Figure 6 A schematic diagram of circuit 600, illustrating an exemplary, non-limiting reduced-coupling circuit used in a simulation according to one or more embodiments described herein, is shown. Figure 6 As shown, the reduced coupling circuit 600 provides an example in which adjacent qubits are coupled to each other on the JRM to form a balanced bridge topology. In this example, the JRM 610 is operatively coupled to the first qubit 620 and the second qubit 630 in the balanced bridge topology via the first inductor 640 and the second inductor 650, respectively.

[0066] Figure 7Description is shown Figure 6 The WRSpice simulation results of the circuit are shown in graph 700. Figure 7 In the diagram, graph 700 is a pseudo-color graph depicting the result produced by the analog reduced coupling circuit 600, which can be plotted as: a second qubit bias current represented as bias current 2 and expressed in microamps (μA) on the Y-axis (e.g., the vertical axis of graph 700); a first qubit bias current represented as bias current 1 and expressed in microamps (μA) on the X-axis (e.g., the horizontal axis of graph 700); and the resulting two-qubit coupling between the first qubit 620 and the second qubit 630, represented by varying colors on the Z-axis (e.g., the axis extending into and out of the page in graph 700), corresponding to a coupling from approximately –2*e 7 radians per second to 2*e 7 In radians per second, such as Figure 7 The J-figure is shown in the diagram.

[0067] In an example embodiment, to generate graph 700, the coupler is simulated using qubits replaced by an RF audio source with a simulated scattering matrix. In this example, the transmission-scattering matrix element S21 is calculated in the simulation, and then the transmission-scattering matrix element S21 is converted into an impedance matrix, thereby calculating the coupling strength J. In this example, the simulation uses the following parameters: the corresponding mutual inductance (M) between each qubit and JRM = 160 picohms (pH); the first qubit frequency (e.g., resonant frequency) ω in the first qubit 620. qb,1 = 2π x 5 GHz; and the frequency (e.g., resonant frequency) of the first quantum bit in the second quantum bit 630 is ω. qb,2 = 2π x 5GHz.

[0068] As shown in graph 700, the resulting two-qubit coupling J is relatively low (e.g., approximately 0 Hz) for a relatively large bias current. This result indicates that the reduced coupling circuit 600 can realize a coupling device that is highly insensitive to flux noise. Graph 700 further demonstrates that the polarity of the resulting two-qubit coupling J can be tuned from positive to negative by adjusting the polarity of the corresponding bias current. This result shows that a maximum two-qubit coupling J greater than 2 MHz can be achieved by adjusting the polarity of the corresponding bias current.

[0069] Figure 8 An exemplary non-limiting graph 800 depicting the relationship between device energy levels and magnetic flux bias according to one or more embodiments described herein is shown. Figure 8 In the diagram, the occupied labeled energy state is illustrated under a zero flux bias.

[0070] Figure 9 An exemplary non-limiting pseudo-color map 900 depicting the relationship between ZZ coupling and flux bias and the frequency of the second qubit 120 according to one or more embodiments described herein. As shown in Figure 900, the ZZ coupling is relatively low (e.g., about 10 kHz) for the region 910 corresponding to the zero flux bias. Figure 900 further shows that the ZZ coupling can be relatively high (e.g., >1 GHz) outside region 910.

[0071] Figure 10 An exemplary, non-limiting graph 1000 depicting the relationship between ZZ coupling and flux bias according to one or more embodiments described herein is shown. As shown in Figure 1000, ZZ coupling can be substantially zero in a stable off-state region 1010 corresponding to a flux bias of 0. In embodiments, the stable off-state region 1010 corresponds to an off-state that can be set by changing the flux bias. Figure 1000 also shows that in the on-state outside region 1010, ZZ coupling can be relatively large (e.g., approximately several MHz or more).

[0072] Figure 11 Example non-limiting graph 1100 depicting the relationship between ZZ coupling and magnetic flux bias in units of magnetic flux quanta according to one or more embodiments described herein.

[0073] Figure 12 An exemplary non-limiting graph 1200 is shown illustrating the relationship between the applied flux bias and the timing of the phase gate used to formulate two-qubit control, according to one or more embodiments described herein.

[0074] Figure 13 The diagram illustrates the relative phase difference between the |01> quantum state and the |11> quantum state according to one or more embodiments described herein, and the method for... Figure 12 An exemplary non-restrictive curve 1300 shows the relationship between the applied flux distribution and the time.

[0075] Figure 14 Figure 1400 illustrates an exemplary, non-limiting example depicting the relationship between eigenstate occupancy |Cn|^2 and eigenstate number n according to one or more embodiments described herein.

[0076] Figure 15 An exemplary non-limiting graph 1500 is shown depicting the relationship between the excitation expectation of a first qubit and a second qubit and time, according to one or more embodiments described herein, wherein the first qubit and the second qubit are coupled via a ring modulator.

[0077] Figure 16An exemplary non-limiting graph 1600 is shown, depicting the relationship between the excitation expectation value of a first qubit and a second qubit versus time, according to one or more embodiments described herein, wherein the first qubit and the second qubit are coupled via a JRM during a swapping operation. In an embodiment, by using... Figure 4 Example device 400 is used to drive parameter conversion (or exchange) between first qubit 120 and second qubit 130 to obtain Figure 1600. In this embodiment, first qubit 120 and second qubit 130 are detuned to approximately 600 MHz.

[0078] Figure 17 A top view of an exemplary, non-limiting device 1700, according to one or more embodiments described herein, is shown, which can reduce the routing complexity associated with cross-features in multidimensional (e.g., 2D) qubit arrays. Such as Figure 1 The cross-feature 170 can cause undesirable effects (e.g., crosstalk, noise, etc.) that adversely affect device operation. These undesirable effects can be mitigated by properly routing traces or locating components during the design phase. However, with the scaling advancements in quantum computing technologies, complex multi-qubit architectures (e.g., Figure 18 The multidimensional qubit array has generated increasingly complex wiring and layout problems.

[0079] To alleviate such wiring and / or layout complexity, example device 1700 implements a Manhattan knot, which creates a tunnel knot geometry that also serves as a crossover feature. Specifically, device 1700 includes a JRM 1710, which includes four JJs 1712, 1714, 1716, and 1718 arranged in a ring configuration. JRM 1710 also includes a first connection 1720 coupled to JJ 1714 and a second connection 1730 coupled to JJ 1718. Connections 1720, 1730, 1740, and 1750 connect JRM 1710 to these capacitive or inductive qubit couplers.

[0080] Figure 18A top view of an exemplary, non-limiting device 1800 including a multidimensional qubit array according to one or more embodiments described herein is shown. Device 1800 includes four qubits (i.e., first qubit 1810, second qubit 1820, third qubit 1830, and fourth qubit 1840) arranged in a 2D array. In an embodiment, the four qubits of device 1800 are quadrupole qubits that can provide full 2D connectivity. In device 1800, first qubit 1810 is coupled to second qubit 1820 via JRM 1850; second qubit 1820 is coupled to third qubit 1830 via JRM 1860; third qubit 1830 is coupled to fourth qubit 1840 via JRM 1870; and fourth qubit 1840 is coupled to first qubit 1810 via JRM 1880. Figure 18 As shown, each JRM of device 1800 includes four Manhattan knots.

[0081] Figure 19 A top view of an exemplary, non-limiting device 1900 that can facilitate enhanced coupling according to one or more embodiments described herein is shown. Device 1900 includes a qubit 1910 comprising four or more voltage blades (i.e., blades 1912, 1914, 1916, and 1918). Figure 19 As shown, two capacitive devices are formed inside or within the coverage area of ​​each blade, including qubit 1910. For example, capacitive devices 1920 and 1930 are formed inside or within the coverage area of ​​blade 1912.

[0082] Figures 20 to 23 It shows the relationship with Figure 19 An exemplary non-limiting graph corresponding to the simulation results obtained by the exemplary device 1900. Figure 20 An exemplary non-limiting graph 2000 is shown, depicting the relationship between the relative phase difference and time between the |01> quantum state and the |11> quantum state according to one or more embodiments described herein. Figure 21 An exemplary non-limiting graph 2100 depicting the relationship between a population and its eigenstates according to one or more embodiments described herein is shown. Figure 22 An exemplary non-limiting graph 2200 depicting the relationship between the expected value of the excitation and time according to one or more embodiments described herein is shown. Figure 23 An example non-limiting graph depicting the relationship between the applied flux bias and the time used to formulate a two-qubit gate via a JRM is shown according to one or more embodiments described herein.

[0083] Figure 24A top view of an exemplary, non-limiting device 2400 that can facilitate flux coupling according to one or more embodiments described herein is shown. Device 2400 includes a JRM 2410 located above an intermediary layer 2420. The insertion between the JRM 2410 and the intermediary layer 2420 is a flux bias line 2430 established on the intermediary layer 2420, which forms a loop under the JRM 2410.

[0084] Figure 25 A top view of an exemplary, non-limiting device 2500 that can facilitate flux coupling according to one or more embodiments described herein is shown. Device 2500 includes a JRM 2510 and a flux bias line 2520, the flux bias line 2520 including an incoming flux bias line 2522 forming a loop adjacent to the JRM 2510. Instead of coupling the flux bias line 2520 to ground for a return path, the flux bias line 2520 further includes a return path 2524 that runs alongside the incoming flux bias line 2522. In embodiments, providing a flux bias line 2520 with a return path 2524 that routes along the incoming flux bias line 2522 facilitates limiting unintended stray flux coupling within device 2500.

[0085] Figure 26 A flowchart illustrating an exemplary, non-limiting computer-implemented method 2600 that can use a JRM to assist quantum gates between qubits according to one or more embodiments of the present description is shown. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. At 2602, the computer-implemented method 2600 may include operatively coupling a JRM (e.g., JRM 110) to a first qubit and a second qubit (e.g., first qubit 120 and second qubit 130) in a balanced bridge topology via respective first and second capacitive devices (e.g., first capacitive device 140 and second capacitive device 150). At 2604, the computer-implemented method 2600 may include tunably coupling the first qubit and the second qubit using the JRM. In embodiments, the first qubit and the second qubit remain decoupled until a bias is applied to the JRM.

[0086] Figure 27A flowchart illustrating an exemplary, non-limiting computer-implemented method 2700 according to one or more embodiments of the present description, which may use a JRM to assist in the quantum gate between qubits, is shown. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. At 2702, the computer-implemented method 2700 may include operatively coupling a JRM (e.g., JRM 110) to a first qubit and a second qubit (e.g., first qubit 120 and second qubit 130) in a balanced bridge topology via respective first and second capacitive devices (e.g., first capacitive device 140 and second capacitive device 150). At 2704, the computer-implemented method 2700 may include tunably coupling the first qubit and the second qubit using the JRM. At 2706, the computer-implemented method 2700 may include applying a bias to the JRM to assist in controlling the coupling between the first qubit and the second qubit.

[0087] In one embodiment, the first and second qubits remain decoupled until a bias is applied to the JRM. In another embodiment, the computer-implemented method 2700 may further include applying an RF charge bias signal to the JRM to drive parameter conversion between the first and second qubits. For example, Figure 4 The biasing component 410 can be used to apply an RF charge bias signal to the JRM. In an embodiment, the computer-implemented method 2700 may further include applying an RF flux bias signal to the JRM to drive parameter conversion between the first qubit and the second qubit. For example, Figure 3 The biasing component 310 can be used to apply an RF flux bias signal to the JRM.

[0088] In this embodiment, the first and second qubits are degenerate qubits. In this embodiment, the computer-implemented method 2700 may further include: applying a DC flux bias signal to the JRM to drive excitation exchange between the first and second qubits. For example, Figure 3 The biasing component 310 can be used to apply a DC flux bias signal to the JRM. In an embodiment, the first and second qubits are non-degenerate qubits. In this embodiment, the computer-implemented method 2700 may further include applying the DC flux bias signal to the JRM to drive ZZ interaction between the first and second qubits. For example, Figure 3 The biasing component 310 can be used to apply a DC flux bias signal to the JRM. In an embodiment, the computer-implemented method 2700 may further include controlling the polarity of the coupling between the first qubit and the second qubit by adjusting the polarity of the bias applied to the JRM. For example, Figure 3-4The polarity components 340 and / or 440 can be used to adjust the polarity of the bias voltage applied to the JRM.

[0089] In order to provide context for the various aspects of the disclosed subject, Figure 28 The following discussion is intended to provide a general description of the suitable environment in which the various aspects of the disclosed subject matter can be realized. Figure 28 A block diagram of an exemplary, non-limiting operating environment 2800 that can facilitate one or more embodiments described herein is shown. For example, the operating environment 2800 can be used to implement the above-described embodiments, as described below. Figure 1-4 The described exemplary, non-limiting multi-step manufacturing sequence can be implemented for manufacturing devices (e.g., devices 100, 200, 300, and / or 400) according to one or more embodiments of the present disclosure as described herein. In another example, operating environment 2800 can be used to implement the above-described embodiments, as described below. Figure 26-27 One or more exemplary, non-limiting computer-implemented methods 2600 and / or 2700 are described herein. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0090] It can be done through a computing system (e.g., Figure 28 The operating environment shown and described below (2800) and / or computing device (e.g., Figure 28 The computer 2812 shown and described below implements the above (see reference 2812). Figure 1-4 The described exemplary, non-limiting multi-step manufacturing sequence can be implemented as manufacturing equipment 100, 200, 300, and / or 400. In a non-limiting exemplary embodiment, such a computing system (e.g., operating environment 2800) and / or such a computing device (e.g., computer 2812) may include one or more processors and one or more memory devices thereon on which executable instructions, when executed by the one or more processors, facilitate the above references. Figure 1-4 The performance of the exemplary, non-limiting multi-step manufacturing sequence described herein. As a non-limiting example, one or more processors may facilitate the above-described process by guiding and / or controlling one or more systems and / or devices for performing semiconductor and / or superconductor device manufacturing. Figure 1-4 The exemplary, non-limiting multi-step manufacturing sequence described herein.

[0091] In another example, the above reference Figures 26 to 27One or more of the exemplary, non-limiting computer-implemented methods 2600 and / or 2700 described may also be implemented (e.g., executed) by the operating environment 2800. As a non-limiting example, one or more processors of such a computing device (e.g., computer 2812) may facilitate the above-described methods by booting and / or controlling one or more systems and / or devices (e.g., biasing component 310, biasing component 410, polarizing component 340, and / or polarizing component 440) operable for performing operations and / or routines. Figures 26 to 27 The performance of one or more exemplary, non-limiting computer-implemented methods 2600 and / or 2700 described herein.

[0092] For simplicity of explanation, the computer-implemented method is depicted and described as a series of actions. It should be understood and recognized that the subject matter innovation is not limited to the actions shown and / or the order of the actions; for example, actions may occur in different orders and / or simultaneously, and may occur with other actions not presented and described herein. Furthermore, not all actions shown are necessary to implement the computer-implemented method according to the disclosed subject matter. Moreover, those skilled in the art will understand and appreciate that the computer-implemented method may alternatively be represented as a series of interrelated states via state diagrams or events. Furthermore, it should be understood that the computer-implemented method disclosed below and throughout this specification can be stored on an article of art to facilitate the transfer and assignment of such computer-implemented method to a computer. As used herein, the term article of art is intended to encompass a computer program accessible from any computer-readable device or storage medium.

[0093] Reference Figure 28 The suitable operating environment 2800 for implementing various aspects of this disclosure may also include a computer 2812. The computer 2812 may also include a processing unit 2814, system memory 2816, and a system bus 2818. The system bus 2818 couples system components, including but not limited to the system memory 2816, to the processing unit 2814. The processing unit 2814 may be any of the various available processors. Dual microprocessors and other multiprocessor architectures may also be used as the processing unit 2814. The system bus 2818 may be any of several types of bus architectures, including memory buses or memory controllers, peripheral buses or external buses, and / or local buses using any of the various available bus architectures, including but not limited to Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), FireWire (IEEE 1394), and Small Computer System Interface (SCSI).

[0094] System memory 2816 may also include volatile memory 2820 and non-volatile memory 2822. The Basic Input / Output System (BIOS) is stored in the non-volatile memory 2822, and this BIOS includes basic routines for transferring information between components within the computer 2812 (such as during startup). The computer 2812 may also include removable / non-removable, volatile / non-volatile computer storage media. For example, Figure 28 Disk storage 2824 is shown. Disk storage 2824 may also include, but is not limited to, devices such as disk drives, floppy disk drives, magnetic tape drives, Jaz drives, Zip drives, LS-100 drives, flash memory cards, or memory sticks. Disk storage 2824 may also include storage media, either alone or in combination with other storage media. To facilitate connection of disk storage 2824 to system bus 2818, a removable or non-removable interface, such as interface 2826, is typically used. Figure 28 Software that acts as an intermediary between the user and the basic computer resources described in the suitable operating environment 2800 is also described. Such software may also include, for example, an operating system 2828. The operating system 2828, which may be stored on disk storage 2824, is used to control and allocate the resources of computer 2812.

[0095] System application 2830 utilizes operating system 2828 to manage resources through program module 2832 and program data 2834, such as stored in system memory 2816 or disk storage 2824. It should be understood that this disclosure can be implemented using different operating systems or combinations of operating systems. Users input commands or information into computer 2812 through one or more input devices 2836. Input devices 2836 include, but are not limited to, pointing devices such as mice, trackballs, pens, touchpads, keyboards, microphones, joysticks, gamepads, disc satellite dishes, scanners, TV tuner cards, digital cameras, digital camcorders, and webcams. These and other input devices are connected to processing unit 2814 via system bus 2818 through interface port(s) 2838. Interface ports(s) 2838 include, for example, serial ports, parallel ports, game ports, and Universal Serial Bus (USB). Output devices(s) 2840 use some of the same type of ports as input devices(s) 2836. Therefore, for example, a USB port can be used to provide input to computer 2812 and output information from computer 2812 to one or more output devices 2840. Output adapter 2842 is provided to illustrate that, in addition to other output devices 2840 that require dedicated adapters, there are other output devices 2840 such as monitors, speakers, and printers. By way of illustration and not limitation, output adapter 2842 includes video and sound cards that provide a means of connection between output devices 2840 and system bus 2818. It should be noted that other devices and / or systems of devices provide both input and output capabilities, such as one or more remote computers 2844.

[0096] Computer 2812 can operate in a networked environment using a logical connection to one or more remote computers (such as one or more remote computers 2844). The one or more remote computers 2844 can be computers, servers, routers, network PCs, workstations, microprocessor-based appliances, peer-to-peer devices, or other common network nodes, and typically may also include many or all of the elements described relative to computer 2812. For simplicity, only the memory storage device 2846 is shown as one or more remote computers 2844. The one or more remote computers 2844 are logically connected to computer 2812 via network interface 2848 and then physically connected via communication connection 2850. Network interface 2848 includes wired and / or wireless communication networks, such as local area networks (LANs), wide area networks (WANs), cellular networks, etc. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Wire Distributed Data Interface (CDDI), Ethernet, Token Ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks (such as Integrated Services Digital Network (ISDN)) and their variants, packet-switched networks, and Digital Subscriber Line (DSL). One or more communication connections 2850 refer to the hardware / software used to connect network interface 2848 to system bus 2818. Although communication connection 2850 is shown inside computer 2812 for clarity, it may also be outside computer 2812. For illustrative purposes only, the hardware / software used to connect to network interface 2848 may also include internal and external technologies such as modems, including conventional telephone-grade modems, cable modems and DSL modems, ISDN adapters, and Ethernet cards.

[0097] This invention can be a system, method, apparatus, and / or computer program product at any possible level of technical detail integration. The computer program product may include a computer-readable storage medium (or medium) having computer-readable program instructions thereon for causing a processor to execute aspects of the invention. The computer-readable storage medium may be a tangible device capable of retaining and storing instructions for use by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or suitable combinations of any of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media may also include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital universal disc (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards or protrusions in slots having instructions recorded thereon, and any combinations of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through fiber optic cables), or electrical signals transmitted through wires.

[0098] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the corresponding computing / processing device. The computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as the "C" programming language or similar programming languages). Computer-readable program instructions may execute entirely on a user's computer, partially on a user's computer, as a standalone software package, partially on a user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, a field-programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuitry in order to perform aspects of this embodiment.

[0099] This document describes aspects of the invention with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, executable via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner, such that the computer-readable storage medium in which the instructions are stored includes an article of manufacture containing instructions that implement aspects of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to produce computer-implemented processing, such that the instructions that execute on the computer, other programmable apparatus, or other device perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0100] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. Each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing one or more specified logical functions. In some alternative embodiments, the functions marked in the blocks may occur in a non-consecutive order. For example, depending on the functions involved, two consecutively shown blocks may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action or performs a combination of dedicated hardware and computer instructions.

[0101] While the subject matter has been described above in the general context of computer-executable instructions for a computer program product running on a computer and / or multiple computers, those skilled in the art will recognize that this disclosure may also be implemented in combination with other program modules. Typically, program modules include routines, programs, components, data structures, etc., that perform specific tasks and / or implement specific abstract data types. Furthermore, those skilled in the art will recognize that the computer implementation methods of the present invention can be practiced with other computer system configurations, including single-processor or multi-processor computer systems, small computing devices, mainframe computers, and computers, handheld computing devices (e.g., PDAs, telephones), microprocessor-based or programmable consumables or industrial electronics, etc. The aspects shown can also be practiced in a distributed computing environment where tasks are performed by remote processing devices linked via a communication network. However, some (if not all) aspects of the invention can be practiced on a standalone computer. In a distributed computing environment, program modules may reside in both local and remote memory storage devices. For example, in one or more embodiments, the computer-executable component may be executed from memory that may include or consist of one or more distributed memory cells. As used herein, the terms “memory” and “memory cell” are interchangeable. Furthermore, one or more embodiments described herein are capable of executing code from computer executable components in a distributed manner, for example, multiple processors working together or cooperating to execute code from one or more distributed memory units. As used herein, the term "memory" may include a single memory or memory unit at one location or multiple memories or memory units at one or more locations.

[0102] As used herein, the terms “component,” “system,” “platform,” “interface,” etc., may refer to and / or include computer-related entities or entities associated with an operating machine having one or more specific functions. Entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process, processor, object, executable file, execution thread, program, and / or computer running on a processor. As an illustration, both an application running on a server and the server itself can be components. One or more components may reside within a process and / or an execution thread, and components may reside on one computer and / or be distributed across two or more computers. In another example, a corresponding component may be executed from a different computer-readable medium having different data structures stored thereon. Components may communicate via local and / or remote processes, such as according to signals having one or more data packets (e.g., data from a component interacting with another component in a local system, a distributed system, and / or data from a component interacting with other systems across a network such as the Internet via signals). As another example, a component may be a device having specific functions provided by a mechanical part operated by electrical or electronic circuitry, which is operated by a software or firmware application executed by a processor. In such a case, the processor can be internal or external to the device and can execute at least a portion of the software or firmware application. As another example, a component can be a device that provides a specific function through electronic components without mechanical parts, wherein the electronic components can include a processor or other means for performing software or firmware that at least partially imparts the functionality to the electronic components. In one aspect, the component can be emulated via a virtual machine, for example, within a cloud computing system.

[0103] Furthermore, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise specified or clearly apparent from the context, "X adopts A or B" is intended to mean any natural inclusive permutation. That is, if X adopts A; X adopts B; or X adopts both A and B, then "X adopts A or B" is satisfied in any of the foregoing cases. Additionally, the articles "a" and "an" as used in this specification and the accompanying drawings should generally be interpreted as meaning "one or more," unless otherwise specified or clearly apparent from the context to refer to the singular form. As used herein, the terms "example" and / or "exemplary" are used to indicate that something is used as an example, illustration, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited to such examples. Furthermore, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as superior to or advantageous over other aspects or designs, nor does it imply the exclusion of equivalent exemplary structures and techniques known to those skilled in the art.

[0104] As used herein, the term "processor" can refer to substantially any computing processing unit or device, including but not limited to a single-core processor; a single processor with software multithreading capabilities; a multi-core processor; a multi-core processor with software multithreading capabilities; a multi-core processor with hardware multithreading technology; a parallel platform; and a parallel platform with distributed shared memory. Additionally, "processor" can refer to an integrated circuit, application-specific integrated circuit (ASIC), digital signal processor (DSP), field-programmable gate array (FPGA), programmable logic controller (PLC), complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. Furthermore, processors can utilize nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates, to optimize space utilization or enhance the performance of user devices. Processors can also be implemented as a combination of computing processing units. In this disclosure, terms such as "memory," "storage device," "data storage device," "data storage," "database," and substantially any other information storage component, as used in relation to the operation and function of a component, are used to refer to a "memory component," an entity implemented in "memory," or a component that includes memory. It should be understood that the memory and / or memory components described herein can be volatile or non-volatile memory, or may include both volatile and non-volatile memory. By way of example and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include, for example, RAM that can serve as an external cache memory. By way of illustration and not limitation, RAM can be obtained in many forms, such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Furthermore, the memory components of the systems or computer-implemented methods disclosed herein are intended to include (but are not limited to) these and any other suitable types of memory.

[0105] The above description includes only examples of systems and computer-implemented methods. Of course, for the purposes of describing this disclosure, it is impossible to describe every conceivable combination of components or computer-implemented method; however, those skilled in the art will recognize that many further combinations and substitutions of this disclosure are possible. Furthermore, the use of terms such as “comprising,” “having,” “possessing,” etc., in the detailed description, claims, appendices, and drawings is intended to be inclusive, similar to the way “comprising” is interpreted as the term “comprising” when used as a transitional word in a claim.

[0106] Various embodiments have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A quantum coupling device, comprising: A Josephson ring modulator (JRM) is operatively coupled to a first qubit and a second qubit via corresponding first and second capacitive devices to form a balanced bridge topology. When the JRM is not biased, the first qubit and the second qubit remain decoupled. When the JRM is biased, the JRM provides tunable coupling between the first qubit and the second qubit to realize two-qubit gate operation between the first qubit and the second qubit.

2. The quantum coupling device according to claim 1, further comprising: A biasing component applies a bias to the JRM to facilitate control over the coupling between the first qubit and the second qubit.

3. The quantum coupling device according to claim 2, further comprising: A polarity component that controls the polarity of the coupling between the first qubit and the second qubit by adjusting the polarity of the bias applied to the JRM.

4. The quantum coupling device according to claim 2, wherein, The biasing component applies an RF charge bias signal to the JRM to drive parameter conversion between the first qubit and the second qubit.

5. The quantum coupling device according to claim 4, wherein, The RF charge bias signal includes a difference frequency defined by the corresponding frequencies of the first qubit and the second qubit.

6. The quantum coupling device according to claim 2, wherein, The biasing component applies an RF flux bias signal to the JRM to drive parameter conversion between the first qubit and the second qubit.

7. The quantum coupling device according to claim 6, wherein, The RF flux bias signal includes a difference frequency defined by the corresponding frequencies of the first qubit and the second qubit.

8. The quantum coupling device according to claim 2, wherein, The first qubit and the second qubit are degenerate qubits, and wherein a DC flux bias signal is applied to the JRM to drive the excitation exchange between the first qubit and the second qubit.

9. The quantum coupling device according to claim 2, wherein, The first qubit and the second qubit are non-degenerate qubits, and wherein a DC flux bias signal is applied to the JRM to drive the ZZ interaction between the first qubit and the second qubit.

10. The quantum coupling device according to claim 2, further comprising: A flux bias line is established on the intermediary layer, which forms a loop below the JRM.

11. The quantum coupling device according to claim 10, wherein, The flux bias line includes: an entry flux bias line and a return path that runs alongside the entry flux bias line.

12. The quantum coupling device according to claim 2, wherein, The first capacitive device is formed inside the blade of the first qubit.

13. A computer-implemented method, comprising: The Josephson ring modulator (JRM) is operatively coupled to the first and second qubits via corresponding first and second capacitive devices to form a balanced bridge topology. In response to the JRM not being biased, the first qubit and the second qubit remain decoupled; and In response to the JRM being biased, the JRM is used to provide tunable coupling between the first qubit and the second qubit to enable two-qubit gate operation between the first qubit and the second qubit.

14. The computer-implemented method according to claim 13, further comprising: A bias is applied to the JRM to facilitate control over the coupling between the first qubit and the second qubit.

15. The computer-implemented method according to claim 14, further comprising: The polarity of the coupling between the first qubit and the second qubit is controlled by adjusting the polarity of the bias applied to the JRM.

16. The computer-implemented method according to claim 14, further comprising: An RF charge bias signal is applied to the JRM to drive parameter conversion between the first qubit and the second qubit.

17. The computer-implemented method of claim 14, further comprising applying a radio frequency (RF) flux bias signal to the JRM to drive parameter conversion between the first qubit and the second qubit.

18. The computer-implemented method according to claim 14, wherein, The first qubit and the second qubit are degenerate qubits, and the method further includes: applying a DC flux bias signal to the JRM to drive excitation exchange between the first qubit and the second qubit.

19. The computer-implemented method according to claim 14, wherein, The first qubit and the second qubit are non-degenerate qubits, and the method further includes: applying a DC flux bias signal to the JRM to drive ZZ interaction between the first qubit and the second qubit.

20. A quantum coupling system, comprising: Josephson ring modulator (JRM); The first qubit is coupled to the JRM via a first inductive component; as well as A second qubit is coupled to the JRM via a second inductor, wherein the first qubit and the second qubit are coupled to the JRM via corresponding first and second reactance coupling devices to form a balanced bridge topology, and wherein when the JRM is not biased, the first qubit and the second qubit remain decoupled, and when the JRM is biased, the JRM provides tunable coupling between the first qubit and the second qubit to enable two-qubit gate operation between the first qubit and the second qubit.

21. The system of claim 20, further comprising: A biasing component applies a bias to the JRM to control the coupling between the first qubit and the second qubit.

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