Static random access memory (SRAM) bitcell circuit and SRAM bitcell array circuit with minimum distance between storage circuit active region and read port circuit active region to reduce area

Abstract

The SRAM cell circuit has a minimum distance between the storage circuit active area and the read port circuit active area to reduce area. The SRAM cell circuit is formed in FinFETs in the storage circuit active area and the read port active area, each including one or more diffusion regions of a substrate. Design rule constraints limit a minimum center-to-center distance between adjacent parallel fins. The SRAM bitcell has a reduced total area because the distance between the storage circuit active area and the read port active area is reduced to a minimum separation distance that is between 1.0 and 2.15 times the minimum center-to-center distance between adjacent fins. Minimizing the separation distance can include repositioning a gate contact of a write access transistor from a location between the storage circuit active area and the read port active area to a location that overlaps the storage circuit active area.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Patent Application Serial No. 17 / 038,037, filed September 30, 2020, entitled “STATIC RANDOM ACCESS MEMORY(SRAM) BIT CELL CIRCUITS WITH A MINIMUM DISTANCE BETWEEN A STORAGE CIRCUIT ACTIVEREGION AND A READ PORT CIRCUIT ACTIVE REGION TO REDUCE AREA AND SRAM BIT CELLARRAY CIRCUITS”, which is incorporated herein by reference in its entirety. Technical Field

[0003] The field of this disclosure generally relates to memory circuits in integrated circuits, and more specifically to reducing the area of ​​memory circuits. Background Technology

[0004] Integrated circuit (IC) chips with processing circuitry are indispensable to the functionality of electronic devices. The processing circuitry (“processor”) reads instructions and data from memory circuitry for processing and stores the processed data back to the memory circuitry. Static random access memory (SRAM) is a type of memory circuitry that can be used in a processor. SRAM comprises multiple bit cells organized in rows and columns of an SRAM bit cell array, where each bit cell can store a single data value (bit) of digital data. Each bit cell includes storage circuitry and at least one access port for accessing the storage circuitry. Accessing the storage circuitry includes writing a data value to the storage circuitry in response to a write operation and reading the stored data value in response to a read operation. The processor issues write and read operations that control the access port to access the storage circuitry. Some bit cell circuitry includes one port for writing data to the storage circuitry and another port for reading the stored data value from the storage circuitry. In some examples, the processing circuitry may issue more than one read operation to the SRAM array, which may lead to conflicts between overlapping read operations. In such an example, the SRAM bit cell circuitry in the SRAM array can employ multiple read ports and one write port to avoid conflicting read operations. Each read port included in the SRAM bit cell circuitry increases the size of the SRAM bit cell circuitry, and this increase is doubled for each bit cell in the bit cell array. Summary of the Invention

[0005] The aspects disclosed herein include static random access memory (SRAM) cell circuits with minimal distance between the active region of the memory circuit and the active region of the read port circuit to reduce area. SRAM bit cell array circuits and related fabrication methods are also disclosed. The SRAM bit cells are implemented as complementary metal-oxide-semiconductor (CMOS) circuits. Transistors of the CMOS circuits are provided as fin field-effect transistors (FETs) formed in fins on a substrate, and an array of fins can be used to create the SRAM bit cell array circuit. Each SRAM bit cell circuit (“SRAM bit cell”) in the SRAM bit cell array circuit includes a memory circuit and at least one read port circuit. The FinFET of the memory circuit is disposed within the active region of the memory circuit. The active region of the memory circuit includes one or more diffusion regions of the substrate in which impurities have diffused to form N-type and / or P-type materials. The FinFET of the read port circuit is disposed within the read port active region, which also includes one or more diffusion regions. Fins formed in the respective active regions extend parallel to each other in a first direction. The design rules constrain the center-to-center distance between adjacent parallel fins in a second direction orthogonal to the first direction.

[0006] The exemplary SRAM bit cells disclosed herein have a reduced total area because the spacing between the active regions of the memory circuitry and the active regions of the read port is reduced. The spacing is based on a minimum fin pitch, which is the minimum center-to-center distance between a fin and its nearest adjacent fin in a direction orthogonal to a first direction in which the fins extend. In one example, minimizing the active region spacing includes repositioning the gate contact of the write access transistor from a location between the active regions of the memory circuitry and the active regions of the read port to a location overlapping the active regions of the memory circuitry. In this example, the gate contact is disposed in a first metal (M1) layer.

[0007] In this regard, in one aspect, a memory bit cell circuit is disclosed. The memory bit cell circuit includes a substrate. The memory bit cell circuit also includes a first plurality of fins extending on the substrate in a first direction. In a second direction orthogonal to the first direction, the minimum center-to-center distance from the first fin among the first plurality of fins to the nearest adjacent fin is the minimum fin spacing. The memory bit cell circuit also includes a storage circuit configured to store data values. The storage circuit includes an active region of the storage circuit on the substrate. The active region of the storage circuit includes a first subset of the first plurality of fins. The memory bit cell circuit also includes a read port circuit configured to read data values ​​from the storage circuit. The read port circuit includes a read port active region on the substrate. The read port active region includes a second subset of the first plurality of fins. The memory bit cell circuit also includes a passive region between the active region of the storage circuit and the active region of the read port. The width of the passive region from the active region of the storage circuit to the active region of the read port in the second direction is between 1.0 and 2.15 times the minimum fin spacing.

[0008] In another aspect, a memory bit cell array circuit is disclosed. The memory bit cell array circuit includes a substrate. The memory bit cell array circuit also includes a first plurality of fins extending on the substrate in a first direction. In a second direction orthogonal to the first direction, the minimum center-to-center distance from the first fin among the first plurality of fins to the nearest adjacent fin is the minimum fin spacing. The first memory bit cell circuit also includes a first storage circuit configured to store a first data value. The first storage circuit includes a first storage circuit active region on the substrate. The first storage circuit active region includes a first subset of the first plurality of fins. The first memory bit cell circuit also includes a first read port circuit configured to read the first data value. The first read port circuit includes a first read port active region on the substrate. The first read port active region includes a second subset of the first plurality of fins. The first read port circuit is located on a first side of the first storage circuit in the second direction. The memory bit cell array circuit also includes a second memory bit cell circuit. The second memory bit cell circuit includes a second plurality of fins extending on the substrate in the first direction. The second memory bit cell circuit also includes a second storage circuit configured to store a second data value. The second storage circuit includes a second storage circuit active region on the substrate. The active region of the second memory circuit includes a first subset of the second plurality of fins. The second memory bit cell circuit also includes a second read port circuit configured to read a second data value. The second read port circuit includes a second read port active region of the substrate. The second read port active region includes a second subset of the second plurality of fins. The second read port circuit is located on a second side of the second memory circuit in a second direction. The memory bit cell array circuit also includes a passive array region between the first read port circuit and the second read port circuit. The width of the passive array region from the first read port active region to the second read port active region is between 1.0 times and 2.15 times the minimum fin spacing.

[0009] In another aspect, a method for manufacturing a memory bit cell array circuit is disclosed. The method includes forming a substrate. The method further includes forming a first memory bit cell circuit. The first memory bit cell circuit includes a first plurality of fins extending on the substrate in a first direction. In a second direction orthogonal to the first direction, the minimum center-to-center distance from the first fin among the first plurality of fins to the nearest adjacent fin is the minimum fin spacing. The first memory bit cell circuit also includes a first storage circuit configured to store a first data value. The first storage circuit includes a first storage circuit active region on the substrate. The first storage circuit active region includes a first subset of the first plurality of fins. The first memory bit cell circuit also includes a first read port circuit configured to read the first data value. The first read port circuit includes a first read port active region on the substrate. The first read port active region includes a second subset of the first plurality of fins. The first read port circuit is located on a first side of the first storage circuit in the second direction. The method further includes forming a second memory bit cell circuit. The second memory bit cell circuit includes a second plurality of fins extending on the substrate in the first direction. The second memory bit cell circuit also includes a second storage circuit configured to store a second data value. The second storage circuit includes a second storage circuit active region on the substrate. The second memory circuit active region includes a first subset of the second plurality of fins. The second memory bit cell circuit also includes a second read port circuit configured to read a second data value. The second read port circuit includes a second read port active region of a substrate. The second read port active region includes a second subset of the second plurality of fins. The second read port circuit is located on a second side of the second memory circuit in a second direction. The method further includes forming a passive array region between the first read port circuit and the second read port circuit. The width of the passive array region from the first read port active region to the second read port active region is between 1.0 times and 2.15 times the minimum fin spacing. Attached Figure Description

[0010] Figure 1 This is a circuit diagram of a static random access memory (SRAM) bit cell circuit, which includes a six-transistor (6T) storage circuit and a two-transistor (2T) read port circuit.

[0011] Figure 2 It involves combining existing memory bit cell circuits with exemplary memory bit cell circuits (such as...) Figure 1 A top plan view comparing the exemplary memory bit cell circuit with an SRAM bit cell circuit, the exemplary memory bit cell circuit including a minimized passive bit cell region and gate contacts overlapping with the active region of the memory circuit to reduce the bit cell circuit length.

[0012] Figure 3This is a cross-sectional side view of the layers that form vertical interconnects to couple fin field-effect transistors (FETs) to the metal interconnect layers;

[0013] Figure 4 yes Figure 2 A top plan view of the bit cell array of the memory bit cell circuit, including the minimized passive bit cell region and also including the minimized passive array region to reduce the array length;

[0014] Figure 5 yes Figure 2 and Figure 4 A top plan view of the track in the first metal (M1) layer of an exemplary memory bit cell circuit;

[0015] Figure 6 It is a circuit diagram of an SRAM bit cell circuit that includes a 6T storage circuit and two 2T read port circuits;

[0016] Figure 7 It involves combining existing memory bit cell circuits with exemplary memory bit cell circuits (such as...) Figure 6 A top plan view comparing the exemplary memory bit cell circuit with an SRAM bit cell circuit, which includes two minimized passive bit cell regions and gate contacts that overlap with the active region of the memory circuit to reduce the length of the bit cell circuit.

[0017] Figure 8 yes Figure 7 A top plan view of the bit cell array of the memory bit cell circuit;

[0018] Figure 9 yes Figure 7 and Figure 8 A top plan view of the tracks of the first metal (M1) layer in an exemplary memory bit cell circuit;

[0019] Figure 10 This is a block diagram of an exemplary wireless communication device, which includes a radio frequency (RF) module, such as... Figure 4 and Figure 8 The bit cell array in; and

[0020] Figure 11 This is a block diagram of an exemplary processor-based system, including an SRAM bit cell array. The SRAM bit cell array includes minimized passive bit cell regions, minimized passive array regions, and gate contacts overlapping with active regions of the memory circuitry to reduce the array length. Figure 4 and Figure 8 As shown in any of the figures. Detailed Implementation

[0021] Several exemplary aspects of this disclosure are now described with reference to the accompanying drawings. As used herein, the term “exemplary” means “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or superior to the others.

[0022] The aspects disclosed herein include static random access memory (SRAM) cell circuits with minimal distance between the active region of the memory circuit and the active region of the read port circuit to reduce area. SRAM bit cell array circuits and related fabrication methods are also disclosed. The SRAM bit cells are implemented as complementary metal-oxide-semiconductor (CMOS) circuits. Transistors of the CMOS circuits are provided as fin field-effect transistors (FETs) (FinFETs) formed in fins on a substrate, and an array of fins can be used to create the SRAM bit cell array circuit. Each SRAM bit cell circuit (“SRAM bit cell”) in the SRAM bit cell array circuit includes a memory circuit and at least one read port circuit. The FinFET of the memory circuit is disposed within the active region of the memory circuit. The active region of the memory circuit includes one or more diffusion regions of the substrate in which impurities have diffused to form N-type and / or P-type materials. The FinFET of the read port circuit is disposed within the read port active region, which also includes one or more diffusion regions. The fins formed in the respective active regions extend parallel to each other in a first direction. The design rules constrain the minimum center-to-center distance between adjacent parallel fins in a second direction orthogonal to the first direction.

[0023] The exemplary SRAM bit cells disclosed herein have a reduced total area because the spacing between the active regions of the memory circuitry and the active regions of the read port is reduced. The spacing distance is based on a minimum fin pitch, which is the minimum center-to-center distance between a fin and its nearest adjacent fin in a direction orthogonal to a first direction in which the fin extends. In one example, minimizing the active region spacing distance includes repositioning the gate contact of the write access transistor from a location between the active regions of the memory circuitry and the active regions of the read port to a location overlapping the active regions of the memory circuitry. In this example, the gate contact is disposed in a first metal (M1) layer.

[0024] The circuit diagram of SRAM bit cell circuit 100 is as follows: Figure 1 As shown. Before discussing the creative aspects of the physical implementation of the SRAM bit cell circuit 100, as Figure 2As shown, details of the SRAM bit cell circuit 100 and its operation are first given. The SRAM bit cell circuit (“bit cell”) 100 includes a six-transistor (6T) SRAM storage circuit 102 and a two-transistor (2T) read port circuit 104. Bit cell 100 is an example of a memory bit cell circuit 106. The 6T SRAM storage circuit (“storage circuit”) 102 stores the real data value 108T at the real data node 110T and the two's complement data value 108C at the two's complement data node 110C. The storage circuit 102 includes circuits powered by a power supply voltage V. DD Powered cross-coupled inverters 112(0), 112(1). Cross-coupled inverters 112(0), 112(1) reinforce each other to maintain the real data value 108T and the two's complement data value 108C in voltage form at the real data node 110T and the two's complement data node 110C, respectively. Each cross-coupled inverter 112(0), 112(1) includes a corresponding pull-up P-type FET (PFET) 114(0), 114(1) series-coupled to the corresponding pull-down N-type FET (NFET) 116(0), 116(1). NFET write access transistors 118(0), 118(1) are coupled to the corresponding cross-coupled inverters 112(0), 112(1) to provide corresponding combined write ports 120(0), 120(1) of bit cell 100.

[0025] The NFET write access transistors 118(0) and 118(1) control the writing of data to bit cell 100 during a write operation. This is in response to the power supply voltage V. DD The voltage supplied from the write word line (“WWL”) to the gate G(0) of the NFET write access transistor 118(0) represents the voltage coupled to the real data value 108T provided on the write bit line (“WBL”) to the real data node 110T. This is in response to the supply voltage V. DD The gate G(1) of the NFET write access transistor 118(1) provided from WWL represents the two's complement voltage of the two's complement data value 108C provided on the two's complement write bit line (“WBLB”) coupled to the two's complement data node 110C.

[0026] The read port circuit 104 includes NFETs 122(0) and 122(1), the source and drain of which are coupled in series to the read bit line (“RBL”) and ground (V). SS Between ), the complement data node 110C is coupled to the gate G(2) of NFET 122(0), and the read word line (“RWL”) is coupled to the gate B(3) of NFET 122(1). During the read operation, RBL is precharged to the supply voltage V. DD(For example, binary "1"). In response to RWL, it is determined to be the supply voltage V. DD NFET 122(1) is turned on. RBL will remain charged or discharged through NFET 122(0), depending on the voltage V of the complement data node 110C. COMP Whether NFET 122(0) is turned on. At this point, the voltage on RBL will correspond to the actual data value of 108T.

[0027] Figure 2 This is a top plan view of the bit cells 202L and 202U of example bit cells 202L and 202U relative to 200. Figure 1 The physical implementation of bit unit 100 in the document. An understanding of the exemplary aspects disclosed herein will be facilitated by the following explanation of the structure of bit unit 200. The characteristics of each bit unit in bit units 202L and 202U can be determined according to... Figure 1 Refer to the label of bit cell 100. In bit cells 202L and 202U, NFETs 116(0), 116(1), 122(0) and 122(1), NFET write access transistors 118(0), 118(1) and PFETs 114(0), 114(1) are collectively referred to as FinFET 204, and in Figure 2 Not separately labeled. FinFET 204 is formed in multiple fins 206 on substrate 208. At this point, the FinFET 204 in memory circuit 102 is disposed in the active region 210 of memory circuit on substrate 208. The FinFET 204 in read port circuit 104 is disposed in the active region 212 of read port on substrate 208.

[0028] To optimize the layout area efficiency of the bit cells within 200, bit cell 202U is arranged to mirror bit cell 202L across mirror line 214. In this respect, the active storage circuitry 210 and the active read port 212 of bit cell 202U are arranged to mirror the active storage circuitry 210 and the active read port 212 of bit cell 202L across mirror line 214. Each storage circuit in storage circuitry 102 is coupled to the corresponding read port circuitry 104 on the mirror line 214 to form bit cells 202L and 202U.

[0029] Figure 2The document also includes a top plan view of bit cell pair 216, which includes bit cells 218L and 218U. Bit cells 218L and 218U are also implementations of bit cells 100 in additional fins 220 of substrate 208. Within bit cell pair 216, bit cells 218U and 218L each include a storage circuit active region 210 and a read port active region 212. The storage circuit active region 210 and read port active region 212 of bit cell 218U mirror the storage circuit active region 210 and read port active region 210 of bit cell 218L across mirror line 222.

[0030] Figure 2 The difference between bit pair 200 and bit pair 216 is that the length L of bit pair 200 is... 200 The length L of a bit cell is less than 216. 216 As described below, the area of ​​the substrate 208 occupied by bit cell pair 200 is reduced compared to bit cell pair 216. The reduction in area is attributable to other aspects of the respective bit cell pair, since a storage circuit active region 210 and a read port active region 212 are employed in each bit cell of bit cells 202L, 202U, 218L, and 218U. The description of the storage circuit active region 210 and the read port active region 212 in bit cell 202L also applies to bit cells 202U, 218L, and 218U.

[0031] The PFETs 114(0), 114(1), NFETs 116(0), 116(1), and NFET write access transistors 118(0), 118(1) of the storage circuit 102 are implemented in multiple fins 206 in the active region 210 of the storage circuit and the active region 212 of the read port in the substrate 208.

[0032] In this context, the active region is a region of the substrate in which impurities or dopants have diffused into the substrate 208 to form P-type and / or N-type semiconductor materials. For example, the substrate 208, formed of silicon, may be doped with pentavalent impurities (e.g., phosphorus or arsenic) to form an N-type semiconductor material, or with trivalent impurities (e.g., boron or aluminum) to form a P-type semiconductor material. Therefore, in this example, the fin 206 is formed of N-type and / or P-type semiconductor materials. The passive region includes the non-diffused region of the substrate 208 in which impurities have not diffused to form P-type or N-type materials.

[0033] Fin 206 Figure 2 The fins extend parallel to each other along a first direction A1 corresponding to the Y-axis. Design rules for fabricating fins 206 on substrate 208 require that the center-to-center distance D1 be at least equal to the minimum fin spacing P. MIN(Not shown), this is the minimum distance D1 allowed by the design rules. Minimum fin spacing P MIN exist Figure 2 The distance D1 is measured in the second direction A2, which corresponds to the X-axis (i.e., is orthogonal to the Y-axis). The distance D1 is measured in the second direction A2 from the center C1 of the first fin 206A to the center C2 of the nearest adjacent fin 206B.

[0034] Figure 2 It also includes a passive region 232 between the active region 210 of the storage circuit and the active region 212 of the read port. The passive region 232 is a region in which the substrate 208 is not doped with impurities to form an N-type or P-type semiconductor material. The passive region 232 may include at least one passive fin. According to design rules, the passive region 232 should not be less than a minimum width W in the second direction A2. 232 The minimum width W from one active region to another. 232 (Such as the distance from the active region 210 of the storage circuit to the read port circuit region 212) is set to the minimum allowable fin spacing P. MIN A multiple of. Minimum width W 232 It can be the minimum fin spacing P MIN 1.0 to 2.15 times.

[0035] In contrast to bit cell 202L, the passive region 234 between the active region 210 of the storage circuit and the active region 212 of the read port in bit cells 218L and 218U has a width W. 234 The width W of the passive region 234 in bit cell 218L 234 Greater than width W 232 And greater than the minimum allowable fin spacing P MIN 2.15 times. The width W of bit cell 202L 232 Width W of bit cell 218L 234 The difference between them produces bit units of length L of 200. 200 Compared to the length L of 216 bits per unit 216 The difference lies in the area occupied by bit cell 202L compared to bit cell 218L.

[0036] On the other hand, Figure 2 The top plan view shows the gate (e.g., polysilicon gate) 236 above the channel region 238 of the FinFET 204 used to control bit cell pairs 200 and 216. Figure 2Gate contacts 240A-240C are also shown for coupling the gate 236 of bit cell 202L to a metal layer (not shown) to provide connectivity outside the bit cell pair 200. Bit cell 218L in bit cell pair 216 includes gate contacts 242A-242C corresponding to the gate contacts 240A-240C in bit cell 202L. In bit cell 218L, gate contact 242B is located above passive region 234. However, the electrical connection between gate contact 242B and conductive gate 236 can be located anywhere along conductive gate 236. This allows for a width W of passive region 232 in bit cell pair 200. 232 The width W of the passive region 234 in bit cell pair 216 is less than 234 The gate contact 240B in bit cell 202L is not completely located above the passive region 232. Instead, the gate contact 240B of bit cell 202L is positioned such that the region of the gate contact 240B at least partially overlaps with the active region 210 of the memory circuit. In one example, the region of the gate contact 240B may completely overlap with the active region 210 of the memory circuit (e.g., in the case where all regions of the gate contact 240B are directly above the active region 210 of the memory circuit). Positioning the bit cell 202L in this way results in the bit cell pair 200 having a dimension L in the second direction A2. 200 Able to be smaller than the size L of 216 bit cells 216 .

[0037] Figure 3 yes Figure 2 A cross-sectional side view of the vertical interconnects 300 and 302 used in the bit cell 202L. Vertical interconnect 300 couples the source / drain terminals 304 of the FinFET 204 to a second metal (M2) layer. Vertical interconnect 300 includes a contact 306 in a first layer 308 corresponding to the gate 236. The contact 306 is disposed on the source / drain terminals 304. In the first vertical interconnect layer V0, a ​​via 310 couples the contact 306 to the first metal (M1) layer. In the second vertical interconnect layer V1, a via 312 couples the M1 layer to the M2 layer.

[0038] In the vertical interconnect 302, via 314 couples the gate 236 to the M1 layer. Figure 2In bit cell 218L, gate contact 242B is located on gate 236 in passive region 234. However, in bit cell 202L, gate contact 240B is located in a region above gate 236 that at least partially overlaps with active region 210 of memory circuitry. Via 314 can be positioned above channel region 238 within active region 210 of memory circuitry or above other portions of gate 236. Positioning vertical interconnect 302 on gate 236 to overlap with active region 210 of memory circuitry allows passive region 232 of bit cell 202L to be smaller than passive region 234 of bit cell 218L. (See again...) Figure 3 The via 316 in the second vertical interconnect layer V1 couples layer M1 to layer M2. Vertical interconnect 302 can be used to transmit the power supply voltage V. DD Coupled to Figure 1 The NFET in bit cell 100 writes the gates G(0) and G(1) of access transistors 118(0) and 118(1) and couples RWL to the gate G(3) of NFET 122(1).

[0039] Figure 4 This is a top plan view of an exemplary 2×2 SRAM bit cell array circuit (“2×2 array”) 400 including bit cells 402L and 402U in bit cell pair 404. Bit cell pair 404 corresponds to... Figure 2 The 2×2 array 400 also includes bit cells 406L and 406U in bit cell pair 408. Bit cell pair 408 mirrors bit cell pair 404 across mirror line 410 to optimize the area efficiency of 2×2 array 400. In other words, the storage circuit 102 and read port circuit 104 of bit cells 406L and 406U are located relative to the mirror line 410 at positions opposite to the storage lines 102 and read port circuit 104 of bit cells 402L and 402U. For example, the read port circuit 104 of bit cell 402L is located on a first side of storage circuit 102 in the second direction A2, and the read port circuit 104 of bit cell 406L is located on a second side of storage circuit 102 in the second direction, wherein the mirror line 410 is located between the respective read port circuits 104. In the 2×2 array 400, the bottom row 412 includes bit cells 402L and 406L, and the top row 414 includes bit cells 402U and 406U. The first column 416 of the 2×2 array 400 includes bit cells 402L and 402U, and the second column 418 includes bit cells 406L and 406U.

[0040] The active area 420 of the read ports of bit units 402L, 402U, 406L, and 406U corresponds to... Figure 2The active region 212 is the read port in the array. Design rules require a passive array region 424 between the active region 420 of the read port in bit pair 404 and the active region 420 of the read port in bit pair 408. Furthermore, the minimum width W from one active region to another... 424 (Such as the distance between the active areas 420 of the read ports) is set to the minimum allowable fin spacing P. MIN Multiples of. Design rules require a minimum width W of 424 for the passive array region. 424 Minimum fin spacing P MIN 1.0 to 2.15 times. In the example of a 2×2 array 400, the width W of the passive array region 424 is... 424 Set to minimum fin spacing P MIN Twice (2×). Furthermore, since bit units 402L and 402U correspond to... Figure 2 Bit cells 202L and 202U are included, so each bit cell in bit cells 402L, 402U, 406L, and 406U includes a passive region 232 between the active region 210 of the storage circuit and the active region 212 of the read port. The passive region 232 has a width W. 232 The minimum width W of the passive array region 232 232 It is the minimum fin spacing P MIN 1.0 to 2.15 times.

[0041] Figure 4 It also includes a top plan view of a 2×2 SRAM bit cell array circuit 426. The 2×2 array 426 includes bit cell pairs 428 and 430, which are mirror images of each other across mirror line 410. Bit cell pair 428 includes bit cell 432L, and bit cell pair 430 includes bit cell 434L. Each bit cell in bit cells 432L and 434L includes a read port active region 420. A passive array region 436 between the read port active region 420 in bit cell 432L and the read port active region 420 in bit cell 434L has a value greater than the minimum fin pitch P. MIN 2.15 times the width W 436 Therefore, the passive array region 436 in the 2×2 array 426 is wider than the passive array region 424 in the 2×2 array 400. Furthermore, the passive bit cell region 234 in the 2×2 array 426 is wider than the passive bit cell region 232 in the 2×2 array 400. Therefore, the length L of the 2×2 array 400 is... 400 Less than Figure 4 The length L of the 2×2 array 426 in the array 426 Therefore, a large SRAM array (not shown) including bit cell pairs 404 and 408 will have a shorter length than a large SRAM array including bit cell pairs 428 and 430.

[0042] Figure 5 yes Figure 2 The diagram shows a top plan view of the M1 layer 500 used in bit cells 202L and 202U, and a top plan view of the M1 layer 502 used in bit cells 218L and 218U. The M1 layers 500 and 502 include a metal track 504 extending in a first direction A1. In another exemplary aspect of bit cell 202L, Figure 5 It shows Figure 2 The number of tracks 504 in the M1 layer 500 of bit cell 202L is less than the number of tracks 504 used in the M1 layer 502 of bit cell 218L. Specifically, in M1 layer 500, each bit cell in bit cell 202L uses eight (8) tracks 504, while in M1 layer 502, each bit cell in bit cell 218L uses nine (9) tracks 504. (See reference...) Figure 4 For each bit of bit cells 402L, 402U, 406L, and 406U, the M1 layer 500 includes no more than eight tracks 504 in the 2×2 array 400. Therefore, in addition to having a reduced length L... 400 In addition, the M1 layer 500 of the 2×2 array 400 has less congestion than the M1 layer 502 of the 2×2 array 426.

[0043] Further reference Figure 5 The M1 layer 500 in the active region 210 of the storage circuit of bit cells 202L and 202U has the same number of tracks 504 as the M1 layer 502 in the active region 210 of the storage circuit of bit cells 218L and 218U. However, compared with the M1 layer 502 in the corresponding region of bit cells 218L and 218U, the tracks 504 of the M1 layer 500 in the passive region 232 of bit cell 202L and the active region 212 of the read port have been reconfigured. The M1 layer 502 of bit cell 218L includes a passive region 234 for V SS (For example, grounded) rail 504 and the active area 212 of the read port for V SS In the case of another track 504, the M1 layer 500 of bit cell 202L only uses V SS A single track 504. Due to the width W of the passive region 234 of bit cell 218L. 234 In comparison, the width W of the passive region 232 in bit cell 202L is... 232 Decrease, so it is coupled to V SS The metal trace extends a shorter distance in the second direction A2. Therefore, the bit cell 218L is coupled to V in the M1 layer 502. SS One of the tracks in track 504 can be removed without causing a grounding problem in bit cell 202L.

[0044] In another example, including the exemplary aspects disclosed herein, Figure 6 This is a circuit diagram of the SRAM bit cell circuit 600. The SRAM bit cell circuit (“bit cell”) 600 includes a 6T SRAM storage circuit (“storage circuit”) 602 and two (2) 2T read port circuits 604A and 604B. Therefore, the bit cell 600 is a ten-transistor (10T) bit cell. Figure 6 The storage circuit 602 in the middle and Figure 1 The storage circuit 102 is the same as that in the memory, and the read port circuit 604A is the same as that in the memory. Figure 1 The read port circuit 104 is the same as that in the previous one. Figure 6 The read port circuit 604B is the same as the read port circuit 604A and operates in the same manner as the read port circuit 604A. However, the read port circuit 604A is configured to read the two's complement data value 606C from the two's complement data node 608C of the bit unit 600, and the read port circuit 604B is configured to read the real data value 606T from the real data node 608T.

[0045] Refer to the above Figure 1 The description states that the read operation of the SRAM bit cell circuit 100 includes a first step of pre-charging the RBL and a second step of discharging or holding the charge on the RBL, depending on whether the NFET 122(0) is powered by the voltage V on the complement data node 110C. COMP Therefore, read operations in the SRAM bit cell circuit 100 cannot be performed more frequently than once every other cycle of the processor clock. Instead, in the bit cell 600, which has a first read port circuit 604A coupled to the two's complement data node 608C and a second read port circuit 604B coupled to the real data node 608T, one of the real data value 606T and the two's complement data value 606C can be read alternately in each cycle.

[0046] Figure 7 This is a top plan view of bit cells 702L and 702U relative to 700. Bit cells 702L and 702U are... Figure 6 Each implementation of bit cell 600 includes the inventive aspects disclosed herein. Bit cell 702L includes memory circuitry 704 corresponding to memory circuitry 602. Bit cell 702L also includes... Figure 6 The storage circuit 704A and 604B have corresponding read port circuits 706A and 706B. Read port circuit 706A includes an active read port region 708A disposed on the first side of the storage circuit 704 in the second direction A2, and read port circuit 706B includes an active read port region 708B disposed on the second side of the storage circuit 704 in the second direction A2.

[0047] The bit cell pair 700 is implemented in a FinFET 710 within a plurality of fins 712, which extend on a substrate 714 in a first direction A1 corresponding to the Y-axis. According to design rules, the minimum fin spacing P... MIN (Not shown) is a predetermined distance in the second direction A2. Minimum fin spacing P MIN This is, for example, the minimum center-to-center distance of fin 712 measured from the center of the first fin (in the second direction) to the center of the nearest adjacent fin. The fins 712 in the bit unit pair 700 are at least at the minimum fin spacing P. MIN Or, more, may be separated. Storage circuit 704 includes a subset of multiple fins 712 disposed in the active region 722 of the storage circuit. Read port circuits 706A and 706B each include a corresponding subset of multiple fins 712 disposed in the active regions 708A and 708B of the read port, respectively. Figure 7 A gate 726 extending in the second direction A2 is also shown. The gate 726 extends over the channel region 728 to control the FinFET 710.

[0048] Bit cell 702L includes a first passive bit cell region 730A between the active region 708A of the read port circuit 706A and the active region 722 of the storage circuit. Bit cell 702L also includes a second passive bit cell region 730B between the active region 708B of the read port and the active region 722 of the storage circuit. Each passive bit cell region in the first passive bit cell region 730A and the second passive bit cell region 730B has a width W. 730 The minimum width from one active region to another (such as the width W from the active region 722 of the storage circuit to the passive bit cell region 730A of the read port circuit region 708A). 730 The minimum allowable fin spacing P is set. MIN A multiple of. Minimum width W 730 It can be the minimum fin spacing P MIN 1.0 to 2.15 times.

[0049] Figure 7 It also includes a top plan view of bit cell pair 732, which includes bit cells 734L and 734U, and does not implement the inventive aspects disclosed herein. Bit cells 734L and 734U in bit cell pair 732 each include bits having a width W. 736The first passive bit cell region 736A and the second passive bit cell region 736B. Bit cells 734L and 734U each include a memory circuit 738 in the same active memory circuit region 740 as the active memory circuit region 722 in bit cell 702L. However, the width W of the first passive bit cell region 736A and the second passive bit cell region 736B is... 736 Greater than minimum width W 730 And greater than the minimum fin spacing P MIN 2.15 times. Therefore, Figure 7 The bit unit in the middle is 700 with a length L 700 The length L of the bit cell is less than 732. 732 .

[0050] On the other hand, a gate contact 742 that vertically couples the gate 726 to the metal layer in the bit cell pair 700 (e.g., in a BEOL process) is at least partially disposed above the active region 722 of the memory circuit. At least a portion of the region of the gate contact 742 overlaps with the active region 722 of the memory circuit. The gate contact 742 may completely overlap with the active region 722 of the memory circuit (e.g., directly above it). Positioning the gate contact 742 at least partially above the active region 722 of the memory circuit allows the first passive bit cell region 730A and the second passive bit cell region 730B to be smaller in width than the first passive bit cell region 736A and the second passive bit cell region 736B of the bit cell pair 732.

[0051] Figure 8 This is a top plan view of an exemplary 2×2 SRAM bit cell array circuit (“2×2 array”) 800, which includes bit cells 802L and 802U in a bit cell pair 804, the bit cell pair 804 corresponding to Figure 7The 2×2 array 800 also includes bit cells 806L and 806U in bit cell pair 808. Bit cell pair 808 mirrors bit cell pair 804 across mirror line 810 to optimize the area efficiency of 2×2 array 800. Each bit cell in bit cells 802L, 802U, 806L, and 806U includes memory circuitry 704 in memory circuitry active region 722, and read port circuits 706A and 706B in read port active regions 708A and 708B, respectively. In bit cell 802L, read port circuit 706A is located on a first side (i.e., closer to mirror line 810) on the second direction A2 of memory circuitry 704, and read port circuit 706B is located on a second side on the second direction A2 of memory circuitry 704. In bit cell 806L, read port circuit 706A is located on the second side of storage circuit 704 (i.e., closer to mirror line 810), and read port circuit 706B is located on the first side of storage circuit 704 in the second direction A2. Mirror line 810 bisects the passive array region 812 of 2×2 array 800 between the active read port region 708A of bit cell 802L and the active read port region 708B of bit cell 806L. The minimum width from one active region to another (such as the width W from the active read port region 708A of bit cell 802L to the passive array region 812 of the active read port region 708A of bit cell 806L) 812 The minimum allowable fin spacing P is set. MIN A multiple of. Minimum width W 812 It can be the minimum fin spacing P allowed by the design rules. MIN 1.0 to 2.15 times.

[0052] Figure 8 It also includes a top plan view of a 2×2 array circuit 814. The 2×2 array 814 includes a pair of bit cells 816 having bit cells 818L and 818U, and a pair of bit cells 822L and 822U. Each bit cell among the bit cells 818L, 818U, 822L, and 822U includes a read port active region 708A and a read port active region 708B on opposite sides of the active region 722 of the storage circuit. Furthermore, each bit cell among the bit cells 818L, 818U, 822L, and 822U includes a first passive bit cell region 824A and a second passive bit cell region 824B corresponding to a first passive bit cell region 730A and a second passive bit cell region 730B. However, the first passive bit cell region 730A and the second passive bit cell region 730B have a width W. 730 (in P) MIN(between 1.0 and 2.15 times), while the first passive bit cell region 824A and the second passive bit cell region 824B of the 2×2 array 814 each have a value greater than the minimum fin spacing P. MIN 2.15 times the width W 824 (For example, between active areas 708A and 708B of the read port and active area 722 of the storage circuit).

[0053] Furthermore, the mirror line 810 bisects the passive array region 826 of the 2×2 array 814 between the active read port region 708A of bit cell 818L and the active read port region 708A of bit cell 822L. The passive array region 826 extends along the second direction A2 from the active read port region 708A of bit cell 818L to the width W of the active read port region 708A of bit cell 822L. 826 It is also greater than the minimum fin spacing P MIN 2.15 times that.

[0054] Comparing the 2×2 array 800 with the 2×2 array 814, the width W of the passive array region 826 in the 2×2 array 804 is... 826 The width W of the passive array region 812 in the 2×2 array 800 is greater than the width of the passive array region 812. 812 Furthermore, the width W of the first passive bit cell region 824A and the second passive bit cell region 824B is... 824 The width W is greater than the width of the first passive bit cell region 730A and the second passive bit cell region 730B. 730 Due to these combinational differences, the length L of the 2×2 array 800 800 The length L is significantly smaller than that of a 2×2 array 814. 814 ,like Figure 8 As shown.

[0055] As described above, the 2×2 array 800 also includes vertical coupling to Figure 8 The gate contact portion 828 of the gate 830 in the memory, and the region of the gate contact portion 828 in each bit cell 802L, 802U, 806L and 806U at least partially overlaps with the corresponding active region 722 of the memory circuit.

[0056] Figure 9 yes Figure 8The diagram shows a top plan view of the M1 layer 900 used in bit cells 802L and 802U, and a top plan view of the M1 layer 902 used in bit cells 818L and 818U. The M1 layers 900 and 902 include metal tracks 904 extending in a first direction A1. In another exemplary aspect, the number of tracks 904 in the M1 layer 900 of bit cell 802L is less than the number of tracks 904 used in the M1 layer 902 of bit cell 818L. Specifically, the M1 layer 900 of bit cell 802L uses ten (10) tracks 904, while the M1 layer 902 of bit cell 818L uses twelve (12) tracks 902. (See reference...) Figure 9 For each bit in bit cells 802L and 802U, layer M1 900 includes no more than 10 tracks 904 in the 2×2 array 800. Therefore, in addition to having a reduced length L... 800 In addition, another improvement of the 2×2 array 800 over the 2×2 array 814 is that the M1 layer 900 is not crowded like the M1 layer 902.

[0057] Figure 10 An exemplary wireless communication device 1000 is illustrated. The wireless communication device 1000 includes a radio frequency (RF) component formed by one or more integrated circuits (ICs) 1002, wherein any IC 1002 may include an SRAM bit cell array according to any aspect disclosed herein, the SRAM bit cell array including minimized passive bit cell regions, minimized passive array regions, and gate contacts overlapping with active regions of memory circuitry to reduce the length of the array, such as... Figure 4 and Figure 8 As shown in any of the figures. As an example, wireless communication device 1000 may include any of the above-described devices or be incorporated into any of the above-described devices. For example... Figure 10 As shown, the wireless communication device 1000 includes a transceiver 1004 and a data processor 1006. The data processor 1006 may include memory for storing data and program code. The transceiver 1004 includes a transmitter 1008 and a receiver 1010 supporting bidirectional communication. Typically, the wireless communication device 1000 may include any number of transmitters 1008 and / or receivers 1010 for any number of communication systems and frequency bands. All or part of the transceiver 1004 may be implemented on one or more analog ICs, RFICs, mixed-signal ICs, etc.

[0058] Transmitter 1008 or receiver 1010 can be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes frequency conversion between RF and baseband in multiple stages; for example, from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another stage of receiver 1010. In a direct conversion architecture, the signal undergoes frequency conversion between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. Figure 10 In the wireless communication device 1000, the transmitter 1008 and the receiver 1010 are implemented using a direct conversion architecture.

[0059] In the transmission path, the data processor 1006 processes the data to be transmitted and provides I and Q analog output signals to the transmitter 1008. In the exemplary wireless communication device 1000, the data processor 1006 includes digital-to-analog converters (DACs) 1012(1) and 1012(2) for converting the digital signals generated by the data processor 1006 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0060] Within transmitter 1008, low-pass filters 1014(1) and 1014(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 1016(1) and 1016(2) amplify the signals from low-pass filters 1014(1) and 1014(2), respectively, and provide I and Q baseband signals. Upconverter 1018 upconverts the I and Q baseband signals using I and Q transmission (TX) local oscillator (LO) signals from TX LO signal generator 1022 via mixers 1020(1) and 1020(2) to provide upconverted signal 1024. Filter 1026 filters upconverted signal 1024 to remove unwanted signals caused by upconversion and noise in the receiving band. Power amplifier (PA) 1028 amplifies the up-converted signal 1024 from filter 1026 to obtain the desired output power level and provides a transmit RF signal. The transmit RF signal is routed through duplexer or switch 1030 and transmitted via antenna 1032.

[0061] In the receiving path, antenna 1032 receives the signal transmitted by the base station and provides the received RF signal, which is routed through duplexer or switch 1030 and provided to low-noise amplifier (LNA) 1034. Duplexer or switch 1030 is designed to operate at a specific receive (RX) to TX duplexer frequency separation, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 1034 and filtered by filter 1036 to obtain the desired RF input signal. Downconversion mixers 1038(1) and 1038(2) mix the output of filter 1036 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1040 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1042(1) and 1042(2) and further filtered by low-pass filters 1044(1) and 1044(2) to obtain I and Q analog input signals, which are provided to data processor 1006. In this example, data processor 1006 includes analog-to-digital converters (ADCs) 1046(1) and 1046(2) for converting analog input signals into digital signals for further processing by data processor 1006.

[0062] exist Figure 10 In the wireless communication device 1000, a TX LO signal generator 1022 generates I and Q TXLO signals for up-conversion, while an RX LO signal generator 1040 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. A TX phase-locked loop (PLL) circuit 1048 receives timing information from a data processor 1006 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 1022. Similarly, an RXILL circuit 1050 receives timing information from a data processor 1006 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 1040.

[0063] Wireless communication devices 1000 each include an SRAM bit cell array according to any aspect disclosed herein, the SRAM bit cell array including a minimized passive bit cell region, a minimized passive array region, and gate contacts overlapping with the active region of the memory circuit to reduce the length of the array, such as Figure 4 and Figure 8Any of the devices shown in any of the figures can be set up or integrated into any processor-based device. Examples (but are not limited to) include set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotor aircraft.

[0064] On this point, Figure 11 An example of a processor-based system 1100 is shown, which includes an SRAM bit cell array according to any aspect disclosed herein, the SRAM bit cell array including a minimized passive bit cell region, a minimized passive array region, and gate contacts overlapping with active regions of memory circuitry to reduce the length of the array, such as Figure 4 and Figure 8 As shown in any of the figures. In this example, the processor-based system 1100 includes one or more central processing unit (CPU) units 1102, which may also be referred to as CPUs or processor cores, each CPU 1102 including one or more processors 1104. The CPUs 1102 may have cache memories 1106 coupled to the processors 1104 for fast access to temporarily stored data. As an example, the processors 1104 may include an SRAM bit cell array according to any aspect disclosed herein, the SRAM bit cell array including minimized passive bit cell regions, minimized passive array regions, and gate contacts overlapping with active regions of memory circuitry to reduce the length of the array, such as Figure 4 and Figure 8 As shown in any of the figures. Multiple CPUs 1102 are coupled to a system bus 1108 and can interconnect master and slave devices included in the processor-based system 1100. It is known that the multiple CPUs 1102 communicate with these other devices by exchanging address, control, and data information over the system bus 1108. For example, the multiple CPUs 1102 can transmit bus transaction requests to a memory controller 1110, which is an example of a slave device. Although... Figure 11It is not shown in the figure, but multiple system buses 1108 may be provided, each of which constitutes a different structure.

[0065] Other master and slave devices can be connected to system bus 1108. For example... Figure 11 As shown, by way of example, these devices may include a memory system 1112 having a memory controller 1110 and one or more memory arrays 1114, one or more input devices 1116, one or more output devices 1118, one or more network interface devices 1120, and one or more display controllers 1122. Each of the memory system 1112, one or more input devices 1116, one or more output devices 1118, one or more network interface devices 1120, and one or more display controllers 1122 may include an SRAM bit cell array according to any aspect of the aspects disclosed herein, the SRAM bit cell array including a minimized passive bit cell region, a minimized passive array region, and gate contacts overlapping with the active regions of the memory circuitry to reduce the length of the array, such as Figure 4 and Figure 8 As shown in any of the figures. Multiple input devices 1116 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Multiple output devices 1118 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Multiple network interface devices 1120 may be any device configured to allow data exchange with network 1124. Network 1124 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth. TM Networks and the Internet. Multiple network interface devices 1120 can be configured to support any type of communication protocol required.

[0066] The CPU 1102 can also be configured to access the display controller 1122 via the system bus 1108 to control information sent to one or more displays 1126. The display controller 1122 sends information to be displayed to the displays 1126 via one or more video processors 1128, which process the information to be displayed into a format suitable for the displays 1126. The displays 1126 can include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc. The display controller 1122, the displays 1126, and / or the video processors 1128 can include an SRAM bit cell array according to any aspect disclosed herein, the SRAM bit cell array including minimized passive bit cell regions, minimized passive array regions, and gate contacts overlapping with active regions of memory circuitry to reduce the length of the array, such as... Figure 4 and Figure 8 As shown in any of the diagrams.

[0067] Those skilled in the art will further recognize that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the aspects disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. As an example, the master and slave devices described herein can be used in any circuit, hardware component, IC, or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the system as a whole. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as causing a departure from the scope of this disclosure.

[0068] The various illustrative logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but alternatively, it may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0069] The aspects disclosed herein can be embodied in hardware and instructions stored in the hardware, and can reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium can be integrated with the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as discrete components in a remote station, base station, or server.

[0070] It should also be noted that the operational steps described in any exemplary aspect herein are for illustrative and discussion purposes only. The described operations can be performed in many different sequences than those shown. Furthermore, the operations described in a single operational step can actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary aspects can be combined. It should be understood that the operational steps shown in the flowcharts can be modified in many different ways, which will be apparent to those skilled in the art. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0071] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but should be given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory bit cell circuit, comprising: Substrate; A plurality of fins extend on the substrate in a first direction, wherein the minimum center-to-center distance from the first fin among the plurality of fins to the nearest adjacent fin in a second direction orthogonal to the first direction is the minimum fin spacing. A storage circuit configured to store data values, the storage circuit including an active storage circuit region of the substrate, the active storage circuit region including a first subset of the first plurality of fins; A read port circuit is configured to read the data value, the read port circuit including a read port active region of the substrate, the read port active region including a second subset of the first plurality of fins; as well as The passive region is located between the active region of the storage circuit and the active region of the read port. The width of the passive region in the second direction from the active region of the storage circuit to the active region of the read port is between 1.0 and 2.15 times the minimum fin spacing.

2. The memory bit cell circuit according to claim 1, wherein the width of the passive region is between forty-five (45) nanometers (nm) and fifty-five (55) nanometers.

3. The memory bit cell circuit according to claim 1, wherein the minimum center-to-center distance from the first fin to the nearest adjacent fin is a predetermined distance.

4. The memory bit cell circuit according to claim 1, wherein the memory circuit further comprises: A write-access fin field-effect transistor (FinFET) is configured to provide the data value to the memory circuit, the write-access FinFET including a first gate; and A first gate contact portion is vertically coupled to the first gate, and the first gate contact portion includes a region disposed in a vertical interconnect layer above the first gate. At least a portion of the region of the first gate contact overlaps with the active region of the storage circuit.

5. The memory bit cell circuit according to claim 4, wherein the entire region of the first gate contact is above the active region of the memory circuit.

6. The memory bit cell circuit according to claim 1, wherein the passive region includes a non-diffused region.

7. The memory bit cell circuit according to claim 1, wherein the passive region includes at least one passive fin.

8. The memory bit cell circuit according to claim 1, wherein: The storage circuit is configured to store the actual data value and the complement data value; The read port circuit includes a first read port circuit configured to read the two's complement data value; The first read port circuit includes a first read port active region disposed on the substrate at a first end of the storage circuit in the second direction; as well as The memory bit cell circuit further includes a second read port circuit configured to read the actual data value. The second read port circuit includes a second read port active region on the substrate at a second end of the storage circuit in the second direction. The second read port active region includes a third subset of the first plurality of fins.

9. The memory bit cell circuit according to claim 1, wherein: The active region of the storage circuit includes one or more diffusion regions selected from P-type and N-type diffusion regions; and The active area of ​​the read port includes one or more diffusion regions, namely P-type diffusion regions and N-type diffusion regions.

10. The memory bit cell circuit according to claim 1, wherein: The storage circuitry includes a six-transistor (6T) static random access memory (SRAM) bit cell circuitry; and The read port circuit includes a two-transistor (2T) read port circuit.

11. A memory bit cell array circuit, comprising: Substrate; The first memory bit cell circuit includes: A plurality of fins extend on the substrate in a first direction, wherein the minimum center-to-center distance from the first fin among the plurality of fins to the nearest adjacent fin in a second direction orthogonal to the first direction is the minimum fin spacing. A first storage circuit, configured to store a first data value, includes a first active region of the substrate, the first active region including a first subset of the first plurality of fins; and A first read port circuit is configured to read the first data value. The first read port circuit includes a first read port active region on the substrate, and the first read port active region includes a second subset of the first plurality of fins. The first read port circuit is located on the first side of the first storage circuit in the second direction; The second memory bit cell circuit includes: The second plurality of fins extend on the substrate in the first direction; A second storage circuit, configured to store a second data value, includes a second storage circuit active region on the substrate, the second storage circuit active region including a first subset of the second plurality of fins; and A second read port circuit is configured to read the second data value. The second read port circuit includes a second read port active region of the substrate, and the second read port active region includes a second subset of the second plurality of fins. The second read port circuit is located on the second side of the second storage circuit in the second direction; and A passive array region is located between the first read port circuit and the second read port circuit, wherein the width of the passive array region from the first read port active region to the second read port active region is between 1.0 times and 2.15 times the minimum fin spacing.

12. The memory bit cell array circuit according to claim 11, wherein: The first memory bit cell circuit also includes a first passive bit cell region between the active region of the first read port and the active region of the first storage circuit; The width of the first passive bit unit region in the second direction is between 1.0 and 2.15 times the minimum fin spacing; The second memory bit cell circuit further includes a second passive bit cell region between the active region of the second read port and the active region of the second memory circuit; and The width of the second passive bit unit region in the second direction is between 1.0 and 2.15 times the minimum fin spacing.

13. The memory bit cell array circuit according to claim 11, wherein: The first memory bit cell circuit further includes a first write access FinFET configured to provide the first data value to the first memory circuit, the first write access FinFET including a first gate; A first gate contact is vertically coupled to the first gate, the first gate contact including a first region in a vertical interconnect layer disposed above the first gate; and At least a portion of the first region of the first gate contact overlaps with the active region of the first storage circuit.

14. The memory bit cell array circuit according to claim 13, wherein: The second memory bit cell circuit further includes a second write access FinFET configured to provide the second data value to the second memory circuit, the second write access FinFET including a second gate; A second gate contact is vertically coupled to the second gate, the second gate contact including a second region in a vertical interconnect layer disposed above the second gate; and At least a portion of the second region of the second gate contact overlaps with the active region of the second storage circuit.

15. The memory bit cell array circuit according to claim 14, wherein... The first region of the first gate contact completely overlaps with the active region of the first memory circuit; and The second region of the second gate contact completely overlaps with the active region of the second storage circuit.

16. The memory bit cell array circuit according to claim 11, further comprising a first metal (M1) layer, the first metal (M1) layer comprising: Eight metal tracks extending in the first direction are coupled to the first memory bit cell circuit. as well as Eight metal tracks extending in the first direction are coupled to the second memory bit cell circuit.

17. The memory bit cell array circuit according to claim 11, wherein: The first storage circuit is configured to store a first real data value and a first complement data value; The second storage circuit is configured to store the second real data value and the second complement data value; The first read port circuit is configured to read one of the first real data value and the first complement data value; The second read port circuit is configured to read one of the second real data value and the second complement data value; The first memory bit unit circuit further includes a third read port circuit configured to read the other of the first real data value and the first complement data value. The third read port circuit includes a third read port active area disposed on the second side of the first storage circuit in the second direction. as well as The second memory bit cell circuit further includes a fourth read port circuit configured to read the other of the second real data value and the second complement data value. The fourth read port circuit includes a fourth read port active area disposed on the first side of the second storage circuit in the second direction.

18. The memory bit cell array circuit according to claim 17, further comprising a first metal (M1) layer, the first metal (M1) layer comprising: Ten metal tracks extending in the first direction are coupled to the first memory bit cell circuit. as well as Ten metal tracks extending in the first direction are coupled to the second memory bit cell circuit.

19. The memory bit cell array circuit of claim 11, wherein the width of the passive array region is between forty-five (45) nanometers (nm) and fifty-five (55) nanometers.

20. The memory bit array circuit of claim 11, integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multirotor aircraft.

21. A method for manufacturing a memory bit cell array circuit, the method comprising: Forming a substrate; A first memory bit cell circuit is formed, the first memory bit cell circuit comprising: A plurality of fins extend on the substrate in a first direction, wherein the minimum center-to-center distance from the first fin among the plurality of fins to the nearest adjacent fin in a second direction orthogonal to the first direction is the minimum fin spacing. A first storage circuit, configured to store a first data value, includes a first active region of the substrate, the first active region including a first subset of the first plurality of fins; and A first read port circuit is configured to read the first data value. The first read port circuit includes a first read port active region on the substrate, and the first read port active region includes a second subset of the first plurality of fins. The first read port circuit is located on the first side of the first storage circuit in the second direction; A second memory bit cell circuit is formed, the second memory bit cell circuit comprising: The second plurality of fins extend on the substrate in the first direction; A second storage circuit, configured to store a second data value, includes a second storage circuit active region on the substrate, the second storage circuit active region including a first subset of the second plurality of fins; and A second read port circuit is configured to read the second data value. The second read port circuit includes a second read port active region of the substrate, and the second read port active region includes a second subset of the second plurality of fins. The second read port circuit is located on the second side of the second storage circuit in the second direction; and A passive array region is formed between the first read port circuit and the second read port circuit, wherein the width of the passive array region from the first read port active region to the second read port active region is between 1.0 times and 2.15 times the minimum fin spacing.

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