Reduced complexity ldpc decoder with improved error correction and related devices and methods

Abstract

A reduced complexity decoder with improved error correction and related systems, methods, and apparatus are disclosed. An apparatus includes an input and a processing circuit. The input is disposed at a physical layer device to receive a low density parity check (LDPC) frame including bits from a network. The bits correspond to log likelihood ratio (LLR) messages indicating a probability that the bits have a predetermined logical value. The processing circuit is to saturate LLR values of a portion of the LLR messages corresponding to known bits of the LDPC frame to a highest magnitude represented by the LLR messages, and pass the LLR messages between check nodes and message nodes. The message nodes correspond to the bits. The check nodes correspond to parity check equations of a parity check matrix.

Description

[0001] This application claims the benefit of priority date of U.S. Provisional Patent Application Serial No. 63 / 198,358, filed October 13, 2020, pursuant to 35 USC §119(e), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates generally to a decoder with reduced complexity and improved error correction, and more specifically to a low-power, low-density parity-check (LDPC) decoder for use in physical layer devices of networks such as wired local area networks. Background Technology

[0003] The Institute of Electrical and Electronics Engineers (IEEE) specifies the operation of decoders in wired local area networks (such as Ethernet) in the 2.5 / 5G standard (IEEE 802.3bz). Error correction is critical in Ethernet. The 2.5G / 5G standard requires a bit error rate (BER) as low as 10. -12 The LDPC algorithm can be used to achieve this type of low BER. Data from layers higher than the physical layer in the network stack is encoded into LDPC frames by the transmitter (each LDPC frame is 2048 bits in size, of which 325 bits are parity bits and 1723 bits are message bits). These LDPC frames are decoded by the receiver's LDPC decoder upon reception. Attached Figure Description

[0004] Although this disclosure concludes with claims that specifically point out and clearly claim particular examples, the various features and advantages of the examples within the scope of this disclosure can be more readily identified by the following description when read in conjunction with the accompanying drawings:

[0005] Figure 1 It is a block diagram of a communication system 100 based on various examples;

[0006] Figure 2 The examples shown are derived from various sources. Figure 1 The LDPC frame C provided by the transmitter of the communication system;

[0007] Figure 3 The examples shown are derived from various sources. Figure 1 The decoder provides the received data frames with reduced complexity;

[0008] Figure 4 It is based on various examples Figure 1 A block diagram of a decoder for a communication system receiver 104 with reduced complexity;

[0009] Figure 5A simple message passing algorithm with only six check nodes and nine message nodes is shown according to various examples;

[0010] Figure 6 This is a bit error graph showing an example of improved bit error rate and conventional bit error rate according to the examples disclosed herein;

[0011] Figure 7 This is a sub-iteration graph showing examples of improved sub-iteration counts and regular sub-iteration counts;

[0012] Figure 8 This is a frame error counting graph illustrating an improved frame error counting and a regular frame error counting example according to the examples disclosed herein;

[0013] Figure 9 This is a flowchart illustrating methods for decoding LDPC frames according to various examples; and

[0014] Figure 10 This is a block diagram of a circuit, which, in various examples, can be used to implement the various functions, operations, actions, processes, and / or methods disclosed herein. Detailed Implementation

[0015] In the following detailed description, reference is made to the accompanying drawings, which form part of this disclosure, and specific examples of how this disclosure may be practiced are shown by way of example in the drawings. These examples are described in sufficient detail to enable those skilled in the art to practice this disclosure. However, other examples enabled herein may be utilized, and structural, material, and process changes may be made without departing from the scope of this disclosure.

[0016] The illustrations presented herein are not intended to be actual views of any particular method, system, apparatus, or structure, but are merely idealized representations used to describe examples of this disclosure. In some cases, for the convenience of the reader, similar structures or components in the various figures may be kept with the same or similar designations; however, similarity in designations does not necessarily mean that the structures or components are identical in size, composition, construction, or any other property.

[0017] The following description may include examples to assist those skilled in the art in practicing the examples disclosed herein. The use of the terms “exemplary,” “for example,” and “e.g.” means that the description is illustrative, and while the scope of this disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the examples or the scope of this disclosure to the specified parts, steps, features, functions, etc.

[0018] It should be readily understood that the components of the examples described herein and shown in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following description of various examples is not intended to limit the scope of this disclosure, but rather to represent various examples only. While various aspects of these examples are given in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated otherwise.

[0019] Furthermore, the specific embodiments shown and described are merely examples and should not be construed as the only way to implement this disclosure unless otherwise indicated herein. Components, circuits, and functions may be shown in block diagram form so as not to obscure this disclosure with unnecessary detail. Rather, the specific embodiments shown and described are merely exemplary and should not be construed as the only way to implement this disclosure unless otherwise indicated herein. Additionally, block definitions and logical partitioning between blocks are examples of specific embodiments. It will be apparent to those skilled in the art that this disclosure can be practiced with many other partitioning solutions. In most cases, details regarding timing considerations, etc., have been omitted, where such details do not require a full understanding of this disclosure and are within the capabilities of those skilled in the art.

[0020] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and methods. For clarity of presentation and description, some accompanying drawings may show a signal as a single signal. It should be understood by those skilled in the art that a signal may represent a signal bus, wherein the bus may have multiple bit widths, and this disclosure can be implemented on any number of data signals, including a single data signal.

[0021] The various exemplary logic blocks, modules, and circuits described in conjunction with the examples disclosed herein can be implemented or carried out using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to implement the functions described herein. A general-purpose processor (which may also be referred to herein as a “host processor” or simply a “host”) can be a microprocessor, but alternatively, it can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. A general-purpose computer including a processor is considered a special-purpose computer when used by a general-purpose computer to execute computational instructions (e.g., software code, but not limited thereto) related to the examples of this disclosure.

[0022] Examples can be described based on processes depicted as flowcharts, schematic diagrams, structural diagrams, or block diagrams. While a flowchart may describe operable actions as a continuous process, many of these actions may be performed in another sequence, in parallel, or substantially simultaneously. Furthermore, the order of actions can be rearranged. Processes in this document may correspond to methods, threads, functions, procedures, subroutines, subroutines, other structures, or combinations thereof. Furthermore, the methods disclosed herein may be implemented in hardware, software, or both. If implemented in software, these functions may be stored or transferred as one or more instructions or code onto a computer-readable medium. Computer-readable media includes both computer storage media and communication media, which includes any medium that facilitates the transfer of a computer program from one location to another.

[0023] Any reference to elements in this document using names such as “first”, “second”, etc., does not limit the number or order of those elements unless such limitation is explicitly stated. Rather, these names may be used herein as a convenient way to distinguish between two or more elements or instances of elements. Thus, referring to a first element and a second element does not imply that only two elements can be used there, or that the first element must somehow precede the second element. Furthermore, unless otherwise specified, a group of elements may include one or more elements.

[0024] As used herein, the term “substantially” refers to and includes the degree to which a given parameter, attribute, or condition is satisfied with a small degree of variance, such as, for example, within acceptable manufacturing tolerances, as would be understood by one of ordinary skill in the art. By way of example, depending on the specific parameter, attribute, or condition that is substantially satisfied, it may be satisfied with at least 90%, at least 95%, or even at least 99%.

[0025] LDPC decoding passes the incoming soft log-likelihood ratio (LLR) message between the check node and the message node until the algorithm converges. Some calculations of the LLR are performed at the check node. The calculated LLR is then corrected at the message node. There are 384 check nodes and 2048 message nodes specified by 2.5G / 5G. Such a pass of the LLR (from the message node to the check node and back) is referred to in this paper as an "iteration".

[0026] Each iteration is divided into six sub-iterations, and each sub-iteration (occupying 64 check nodes) is executed within one clock cycle. Each sub-layer executes an algorithm comprising Q-computation, R-computation, L-computation, and decision-making as defined below:

[0027] ● Q calculation:

[0028] Q i =Li -R̅ l,i

[0029] ● R calculation:

[0030]

[0031]

[0032] R l,I Normalized with a factor of 0.5

[0033] ● L calculation:

[0034]

[0035] ● Decision:

[0036]

[0037] if v*H T = 0, then the decoding vector v That is correct.

[0038] If the decoded vector is correct at the end of any sub-iteration, the algorithm is determined to have converged and no further execution is performed. Q is initialized to the LLR of the line from the first sub-iteration of the first iteration.

[0039] The decoder can be designed for a maximum number of iterations (e.g., ten iterations, but not limited to). However, once the algorithm converges to an LDPC frame, the design is clock-gated for the remaining clock pairs of that frame.

[0040] The decoding Q-computation, R-computation, L-computation, and decision algorithm uses the soft log-likelihood ratio received from the line for each message bit and uses these LLR values ​​when decoding message bits. Not using known information from the LDPC frames results in decoding using more sub-layer iterations than in the example disclosed herein. For example, for 2.5G / 5G, the last 97 bits before parity checking in each LDPC frame are zero. In the example disclosed herein, the number of error corrections can be improved by using known information from the LDPC frames. For example, the LLR of these 97 messages can be saturated to the most positive value, allowing the algorithm to converge with a reduced number of iterations.

[0041] Compared to the Q-computation, R-computation, L-computation, and decision algorithms discussed above for 2.5G / 5G, the example disclosed in this paper improves error correction by correcting a larger number of bits, thus improving BER for the same SNR signal quality. Furthermore, compared to the Q-computation, R-computation, L-computation, and decision algorithms discussed above, the example disclosed in this paper achieves algorithm convergence in fewer clock cycles. Therefore, clock gating of the design for the remaining sub-iterations can be performed to save power. Moreover, the example disclosed in this paper does not require additional hardware beyond that associated with the Q-computation, R-computation, L-computation, and decision algorithms discussed above.

[0042] For the LDPC algorithm at 2.5G / 5G speeds, each message bit contributes to six different check nodes. Additionally, each check node processes soft LLR messages from 32 different message nodes.

[0043] An LLR message is an indicator of the probability that a received bit is zero or whether a received bit is one. At any message node, a weak LLR message implies a high degree of uncertainty in making a decision regarding that message bit. Nodes with relatively strong LLR messages are referred to as "specific" message nodes in this paper.

[0044] Errors in any message node must be corrected by six different check nodes that contributed to that message node. These six different check nodes may be influenced by 32 incoming messages to each of them. Therefore, the algorithm works according to the criterion that at each check node, a message with a weaker log-likelihood ratio is reinforced by other messages with a relatively strong log-likelihood ratio. LDPC algorithms provide good error correction while keeping the decoder simple. LDPC decoding algorithms exhibit good error correction when they run more iterations. However, more iterations lead to higher power consumption because it takes additional clock cycles for the decoding engine to run through the iterations. Therefore, there is a design trade-off between power consumption and better error correction. The example implementation disclosed in this paper improves bit error correction without increasing power consumption.

[0045] This paper discloses more specific message nodes that contribute to the check node. The strength of these message nodes is improved to provide better error correction. Therefore, the error correction factor and convergence rate are improved by strengthening the message bits specified as static or fixed by the 2.5G / 5G standard. This is achieved using known information from LDPC frames.

[0046] The examples disclosed in this paper provide improvements in the number of uncorrected errors and a reduction in the number of sublayer runs required for algorithm convergence. The improvement in the number of uncorrected errors improves the BER. The reduction in the number of sublayer runs provides significant power savings because the design is clock-gated for those unused sublayers per frame.

[0047] In various examples, the device includes an input and processing circuitry. The input is located at the physical layer to receive LDPC frames comprising bits from the network. These bits correspond to LLR messages indicating the probability that these bits have predetermined logic values. The processing circuitry is used to saturate the LLR value of a portion of the LLR message corresponding to a known bit of the LDPC frame to the highest value represented by the LLR message, and to transmit the LLR message between the check node and the message node. The message node corresponds to the bit. The check node corresponds to the parity check equation of the parity check matrix.

[0048] In various examples, methods for decoding LDPC frames include receiving an LDPC frame at a physical layer device, comprising known bits and unknown bits, wherein the known bits have known values. The method also includes saturating at least a portion of the LLR value of the LLR message corresponding to the known bits to the highest possible value. The LLR message indicates the probability that the bit has a predetermined logical value. The method further includes transmitting LLR messages between check nodes and message nodes, where the message nodes correspond to the bits and the check nodes correspond to the parity check equation of the parity check matrix.

[0049] In various examples, the device includes an input terminal and processing circuitry. The input terminal is used to receive LDPC frames. The LDPC frame includes bits with associated LLR values. A portion of these bits has known values. The LLR value indicates the probability that a bit has a predetermined logic value. The processing circuitry is used to saturate a subset of the LLR values ​​corresponding to at least some of the bits in the portion with known values ​​to the highest possible value; and to correct the bits of the LDPC frame using message nodes and check nodes in response to at least the LLR value. The message node corresponds to the bit. The check node corresponds to the parity check equation of the parity check matrix.

[0050] Figure 1This is a block diagram of a communication system 100 according to various examples. The communication system 100 includes a transmitter 102 and a receiver 104 electrically connected to each other via a network cable 110 (e.g., an Ethernet cable, but not limited thereto). The receiver 104 includes a network interface 108 and a physical layer device 106. The physical layer device 106 includes an input terminal 112 and a decoder 400 for reduced complexity. The input terminal 112 is located at the physical layer device 106 to receive LDPC frames C 200 comprising bits from a network 114 (e.g., a wired local area network, such as an Ethernet network, but not limited thereto). The bits of the LDPC frame C 200 correspond to an LLR message indicating the probability that the bits have a predetermined logical value.

[0051] Physical layer device 106 is used to receive LDPC frame C 200 via network interface 108 and decode LDPC frame C 200 to obtain received data frame s 300. Physical layer device 106 may use processing circuitry to saturate the LLR value of a portion of the LLR message corresponding to a known bit of LDPC frame C 200 to the highest value represented by the LLR message. The processing circuitry may also transmit the LLR message between a check node and a message node. The message node corresponds to the bit. The check node corresponds to the parity check equation of the parity check matrix.

[0052] Figure 2 The examples shown are derived from various sources. Figure 1 The communication system 100 provides an LDPC frame C200 via transmitter 102. The LDPC frame C200 includes... Figure 1 The received data frame s 300, the first parity vector p1202, and the second parity vector p2204. As a non-limiting example, the length of the received data frame s 300 can be 1723 bits, as shown in the following reference. Figure 3 As discussed, and also as a non-limiting example, the first parity vector p1202 and the second parity vector p2204 can be combined to form a total length of 325 bits. The total length of the LDPC frame C 200 can be 2048 bits.

[0053] Figure 3 The examples shown are derived from various sources. Figure 1 The decoder 400 provides the received data frames s 300 with reduced complexity. The received data frames 300 (in...) Figure 3 The diagram also shows (referred to as "s" 300) including an auxiliary bit 302, a first data portion 304, and a second data portion 306. As a non-limiting example, the auxiliary bit 302 may be one bit long, the first data portion 304 may be 1,625 bits long, and the second data portion 306 may be 97 bits long. Figure 3As shown, the known bits of LDPC frame C 200 may include the last ninety-seven bits of LDPC frame C 200 before the parity vectors (first parity vector p1202 and second parity vector p2204). The total length of the received data frame s 300 may be 1,723 bits. The first data portion 304 may include the data transmitted by transmitter 102 ( Figure 1 The data bits transmitted (e.g., message bits, but not limited thereto). According to the 2.5G / 5G standard, the second data portion 306 may be entirely zero. Therefore, the second data portion 306 may include bits with known values ​​(i.e., zero).

[0054] Figure 4 It is based on various examples Figure 1 A block diagram of a reduced-complexity decoder 400 for a receiver 104 of a communication system 100. The reduced-complexity decoder 400 includes processing circuitry 402 to receive LDPC frame C 200, decode LDPC frame C 200, and provide the received data frame s 300. As a non-limiting example, LDPC frame C 200 may be transmitted as a modulated signal (e.g., a pulse amplitude modulation (PAM) signal, but not limited thereto) to input 112 of processing circuitry 402. Also as a non-limiting example, LDPC frame C 200 may be transmitted using a series of analog voltage potential values, each of which is mapped to one or more bits of LDPC frame C 200 (e.g., each voltage potential may correspond to four bits, but is not limited thereto). As a particular non-limiting example, each different analog voltage potential value may be mapped to a different series of four bits. Therefore, processing circuitry 402 may include sampling circuitry 408 to sample LDPC frame C 200 and provide a sampled LDPC frame 412.

[0055] In some cases, attenuation, noise, and other degradations can introduce inconsistencies regarding whether a specific voltage potential value sampled at sampling circuit 408 is related to that to be transmitted by transmitter 102. Figure 1 The voltage potential value transmitted to the sampling circuit 408 has the same uncertainty. Therefore, the LLR message generator 404 includes an LLR message generator 404 to receive the sampled LDPC frame 412 from the sampling circuit 408 and generate an LLR message 410 indicating the probability that the bits of the LDPC frame C 200 have a predetermined logic value.

[0056] Since the second data portion 306 of the received data frame s 300, which is part of the LDPC frame C 200, is known to include zeros, the LLR message generator 404 will saturate the portion of the LLR message 410 corresponding to the bits of the second data portion 306 to the most positive value of the LLR message 410 (e.g., +31.75, but not limited thereto). As a non-limiting example, the most positive value that the LLR message 410 can convey can be +31.75, which corresponds to the highest level of determinism that an LLR message with corresponding bits having zero values ​​can convey.

[0057] Processing circuitry 402 also includes a check node and a message node 406. The check node and message node 406 are used to correct the bits of the received data frame s 300 in response to at least the LLR message 410. The check node corresponds to the parity check equation of the parity check matrix (also referred to herein as the "H matrix"). The message node corresponds to the bits of the LDPC frame C 200. In various examples, each message bit in the message bits contributes to the six check nodes in the check node. The LLR message 410 is passed between the check node and the message node 406 until the deconvergence of the received data frame s 300. For each sub-iteration in which the message is passed between the check node and the message node 406, the LLR message generator 404 may saturate the value of the LLR message 410 corresponding to a known bit of the LDPC frame C 200 (e.g., the second data portion 306, but not limited thereto) to the highest possible positive value (e.g., at the beginning of each sub-iteration, but not limited thereto).

[0058] Compared to the case where the LLR message 410 corresponding to a known value of LDPC frame C 200 is not saturated, the saturation of the LLR message corresponding to a known value can lead to faster (i.e., fewer sub-iterations of the LLR message 410 are passed through the check node and message node 406) and / or more accurate (i.e., fewer bit errors in the received data frame s 300 provided by the check node and message node 406) decoding of the received data frame s 300 from LDPC frame C 200.

[0059] Figure 5 This is a bipartite graph 500 of (2,3)-LDPC codes based on various examples. Bipartite graph 500 illustrates a simple message passing algorithm with only six check nodes and nine message nodes. Message node 504 corresponds to the bits of the received LDPC frame C 200. Check node 502 corresponds to the parity check equation of the parity check matrix (H matrix). Figure 4 The processing circuit 402's verification node and message node 406 can implement verification nodes and message nodes, such as... Figure 5 The bipartite graph 500 includes, but is not limited to, the verification node 502 and the message node 504.

[0060] Figure 6 This is an example of a bit error rate 602 and a conventional bit error rate 604, shown in bit error graph 600, according to the examples disclosed herein. The improved bit error rate 602 is due to the LLR message 410 ( Figure 4 The bit error rate of the decoded received data frame 300 caused by the saturation of the LLR value of the received data frame s 300, which is related to the second data portion 306 of the received data frame s 300. Figure 3 The known value (zero) of the bits in the LLR message 410 is associated with the known value of the bits in the second data portion 306. The normal bit error rate 604 is the bit error rate of the decoded received data frame s 300 due to the failure to saturate the LLR value of the LLR message 410, which is associated with the known value of the bits in the second data portion 306. As can be observed from the bit error rate graph 600, saturating the known value of the LLR message 410 improves (i.e., reduces) the number of uncorrected errors in the received data frame s 300, and also reduces the number of sub-layer runs (sub-iterations) used for algorithm convergence. The improvement in the number of uncorrected errors improves the BER. The reduction in the number of sub-layer runs also results in significant power savings, as the design is clock-gated for those unused sub-layers for each frame.

[0061] Figure 6 The results show that error correction is better at an improved bit error rate of 602 compared to the case corresponding to a standard bit error rate of 604. This was derived by driving 5000 random LDPC frames into two different decoding engines. Figure 6 The graph shows one engine saturating LLR messages corresponding to known values ​​(improved bit error rate 602), and another engine not saturating LLR messages corresponding to known values ​​(normal bit error rate 604). These LDPC frames are corrupted using additive white Gaussian noise (AWGN), which has a variance associated with the various SNR values ​​shown in the graph. The improved bit error rate 602 and the normal bit error rate 604 are plotted relative to these SNR values.

[0062] For an SNR of 23 dB, the number of uncorrected errors at the improved bit error rate of 602 is 16,535 bits less (=32,312-15,777) than at the conventional bit error rate of 604. For an SNR of 23.5 dB, the number of uncorrected errors at the improved bit error rate of 602 is 1,147 bits less (=1,651-504) than at the conventional bit error rate of 604. The improved bit error rate of 602 decreases to zero, essentially zero, exactly halfway between 23.5 and 24, while the conventional bit error rate of 604 may not converge to essentially zero until the SNR is essentially 24.

[0063] Figure 7Sub-iteration graph 700 shows an example of improved sub-iteration count 702 and regular sub-iteration count 704. The improved sub-iteration count 702 is due to the LLR message 410 ( Figure 4 The number of sub-iterations generated by saturating the LLR value of the received data frame s 300 to converge the received data frame s 300, and the message is related to the second data portion 306 of the received data frame s 300. Figure 3 The known value (zero) of the bit in the second data portion 306 is associated with the sub-iteration count 704, which is the number of sub-iterations used to converge the received data frame s 300 due to the failure to saturate the LLR value of the LLR message 410, and is associated with the known value of the bit in the second data portion 306. Figure 7 The example shown corresponds to a maximum of ten iterations and the use of PAM-16 modulation.

[0064] Figure 7 Various examples of improved sub-iteration count 702 with fewer sub-layer runs for convergence compared to the regular sub-iteration count 704 are shown. For example, 704, for an SNR value of 23 dB, the improved sub-iteration count 702 performs 31,410 fewer sub-layer iterations (158,123–126,713) fewer iterations over 5,000 frames to saturate the LLR message 410 than the regular sub-iteration count 704. For an SNR value of 23.5 dB, the improved sub-iteration count 702 performs 10,913 fewer sub-layer iterations (79,937–69,024) fewer iterations over 5,000 frames to saturate the LLR message 410 than the regular sub-iteration count 704. For an SNR value of 23.8, the total number of sublayer iterations under the improved sub-iteration count 702 is 5,412 fewer (59,263–53,855) than that under the regular sub-iteration count 704. For an SNR value of 24, the total number of sublayer iterations under the improved sub-iteration count 702 is 4,201 fewer (51,613–47,412) than that under the regular sub-iteration count 704. For an SNR value of 24.5, the total number of sublayer iterations under the improved sub-iteration count 702 is 2,254 fewer (38,086–35,832) than that under the regular sub-iteration count 704. Clock gating of the decoding engine for each unused sublayer iteration results in significant power savings corresponding to the improved sub-iteration count 702 compared to the regular sub-iteration count 704.

[0065] Specific message nodes in the message nodes (e.g., Figure 5 Message nodes (including, but not limited to, 504) can have stronger LLR values, thus indicating a higher probability of zero or one. To improve error correction, more specific message nodes can be assigned to check nodes (e.g., Figure 5The check node 502 (but not limited to) contributes, and the strength of these message nodes can be higher. Therefore, weaker message nodes can be corrected through multiple iterations. Among the 2048 message nodes, nodes with stronger known LLR values ​​are identified. The LLR values ​​of the known bits corresponding to these nodes are highlighted in each sub-iteration of the algorithm.

[0066] The log-likelihood ratio can be expressed as {(the probability of receiving the message = 0) divided by (the probability of receiving the message = 1)}. If the bit height of the received message may be zero, the LLR value of the message can be the highest positive value of the selected bit width, and if the bit height of the received message may be one, the LLR value of the message can be the highest negative value of the selected bit width.

[0067] Known LLR values ​​can be identified in LDPC frames. According to the 802.3bz standard, the last 97 bits prior to parity checking in each frame are zero. Their contribution to the parity node during decoding can saturate to a maximum positive value at the start of each sub-iteration. Therefore, examples of decoding disclosed herein could include identifying LLR values ​​for each bit with indices (idx) = 1,626 to 1,723. i (1,idx)=31.75, assume L i It has an eight-bit Q(6.2) width. Then, the Q calculation, R calculation, L calculation, and decision algorithms discussed above can be performed.

[0068] This shows that the LLR is saturated to its maximum value at the beginning of each sub-iteration, instead of using the LLR value received from the line. For a Q 6.2 bit width, the saturation value used is +31.75. As a result, the 97-bit optimization disclosed herein differs from the Q calculation, R calculation, L calculation, and decision algorithm described above in that, instead of not saturating the LLR message corresponding to the known bits in the frame and using the log-likelihood ratio of the known bits received from the line, it saturates the LLR message corresponding to the known bits in the frame, instead of using the log-likelihood ratio of the known bits received from the line, at the beginning of each sub-iteration, it saturates the LLR message corresponding to the known bits in the frame. Figure 3 The LLR value of the LLR message corresponding to the known value of the data is saturated. Using the known information (the known value of the second data section 306) can help achieve convergence faster and can also correct more errors within the maximum number of iterations.

[0069] In various examples, a configurable switch can be used to enable and disable the use of known bits from the frame. For example, when the switch is off, the Q, R, L, and decision algorithms described above can be performed without changing the algorithms used for idx = 1626 to 1723. However, when the switch is on, the known bits corresponding to indices idx 1626 to 1723 can be used to saturate the contribution to the check node to the highest positive value (e.g., +31.75, but not limited to this) at the start of a sub-iteration.

[0070] Decoding a randomly selected uncorrectable received frame without saturating the LLR message corresponding to the known 97 bits of the frame, and with or without utilizing the known 97 bits of the frame. The number of uncorrected errors resulting from not utilizing the known 97 bits is eighty. Conversely, the number of uncorrected errors resulting from utilizing the known 97 bits is fifty-five.

[0071] Similarly, the randomly selected correctable received frame is decoded both without utilizing the known 97 bits of the frame and with utilizing the known 97 bits of the frame. Not utilizing the known 97 bits leads to convergence after two iterations and six sub-iterations. However, utilizing the known 97 bits leads to convergence after two iterations and only five sub-iterations.

[0072] Figure 8 This is a frame error counting diagram 800 illustrating an example of an improved frame error count 802 and a regular frame error count 804 according to the examples disclosed herein. The improved frame error count 802 is due to the LLR message 410 ( Figure 4 The frame error count of the decoded received data frame s 300 caused by the saturation of the LLR value of the received data frame s 300, which is related to the second data portion 306 of the received data frame s 300. Figure 3 The known value (zero) of the bit in the second data portion 306 is associated with the frame error count 804, which is the frame error count of the decoded received data frame s 300 caused by the failure to saturate the LLR value of the LLR message 410, and is associated with the known value of the bit in the second data portion 306.

[0073] At an SNR of 23 dB, the improved frame error count 802 is 497 (957-460) less than the standard frame error count 804. At an SNR of 23.5 dB, the improved frame error count 802 is 39 (56-17) less than the standard frame error count 804. At an SNR of 23.8 dB, the improved frame error count 802 is 2 (2-0) less than the standard frame error count 804. The improved frame error count 802 may converge to essentially zero before the standard frame error count 804 (e.g., the improved frame error count 802 converges to zero at 23.8 dB, while the standard frame error count 804 converges to zero at 24 dB, but is not limited thereto).

[0074] Figure 9 This is a flowchart illustrating a method 900 for decoding LDPC frames according to various examples. At operation 902, method 900 includes receiving an LDPC frame at a physical layer device, comprising known bits and unknown bits. The known bits have known values ​​(e.g., zero, but not limited thereto).

[0075] At operation 904, method 900 includes saturating at least a portion of the LLR values ​​of the LLR message corresponding to the known bit to the highest possible value. The LLR message indicates the probability that the bit has a predetermined logical value. In various examples, at operation 906, saturating at least a portion of the LLR values ​​of the LLR message corresponding to the known bit to the highest possible value includes saturating at least a portion of the LLR values ​​corresponding to the known bit to the most positive value (e.g., +31.75, but not limited thereto) corresponding to the highest level of certainty that can be conveyed by the LLR message with the corresponding bit having a zero value. In various examples, at operation 908, saturating at least a portion of the LLR values ​​of the LLR message corresponding to the known bit to the highest possible value includes saturating at least a portion of the LLR values ​​corresponding to the known bit to the most positive value at the beginning of each sub-iteration of transmitting the LLR message between the check node and the message node. In various examples, at operation 914, saturating at least a portion of the LLR values ​​of the LLR message corresponding to the known bit to the highest possible value includes saturating all LLR values ​​corresponding to the known bit to the highest possible value.

[0076] At operation 910, method 900 includes transmitting an LLR message between the check node and the message node. The message node corresponds to the bit. The check node corresponds to the parity check equation of the parity check matrix.

[0077] At operation 912, method 900 includes correcting LDPC frames in response to the transmission of LLR messages between the check node and the message node.

[0078] Those skilled in the art will understand that the functional elements of the examples disclosed herein (e.g., functions, operations, actions, processes and / or methods, but not limited thereto) can be implemented in any suitable hardware, software, firmware or a combination thereof. Figure 10 Non-limiting examples of implementations of the functional elements disclosed herein are shown. In some examples, some or all portions of the functional elements disclosed herein may be executed by hardware specifically configured to perform the functional elements.

[0079] Figure 10 This is a block diagram of circuit 1000, which in some examples can be used to implement the various functions, operations, actions, processes, and / or methods disclosed herein. Circuit 1000 includes one or more processors 1002 (sometimes referred to herein as "processor 1002") operatively coupled to one or more data storage devices (sometimes referred to herein as "storage device 1004"). Storage device 1004 includes machine-executable code 1006 stored thereon, and processor 1002 includes logic circuitry 1008. Machine-executable code 1006 includes information describing functional elements that can be implemented (e.g., executed by) logic circuitry 1008. Logic circuitry 1008 is adapted to implement (e.g., execute) the functional elements described by machine-executable code 1006. When executing the functional elements described by machine-executable code 1006, circuit 1000 should be considered as dedicated hardware configured to execute the functional elements disclosed herein. In some examples, processor 1002 may be used to execute functional elements described by machine executable code 1006 sequentially, simultaneously (e.g., on one or more different hardware platforms) or in one or more parallel process flows.

[0080] When implemented by the logic circuitry 1008 of the processor 1002, the machine-executable code 1006 is used to adapt the processor 1002 to perform the operations of the examples disclosed herein. As a non-limiting example, the machine-executable code 1006 can be used to adapt the processor 1002 to perform... Figure 9 Method 900. Also by way of non-limiting example, machine-executable code 1006 can be used to adapt processor 1002 to perform the operations disclosed herein for the following: Figure 1 Receiver 104 Figure 1 Network interface 108 Figure 1 Physical layer device 106 Figure 1 and Figure 4 Decoder 400 with reduced complexity Figure 4 Sampling circuit 408, Figure 4 LLR message generator 404 and / or Figure 4The verification node and message node 406. As another non-limiting example, machine-executable code 1006 can be used to adapt processor 1002 to implement such verification nodes and message nodes, such as... Figure 5 The verification node 502 and message node 504.

[0081] Processor 1002 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. A general-purpose computer including a processor is considered a special-purpose computer for performing functional elements corresponding to machine-executable code 1006 (e.g., software code, firmware code, hardware description, but not limited thereto) associated with the examples of this disclosure. Note that the general-purpose processor (which may also be referred to herein as a host processor or simply host) may be a microprocessor, but alternatively, processor 1002 may include any conventional processor, controller, microcontroller, or state machine. Processor 1002 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0082] In some examples, storage device 1004 includes volatile data storage devices (e.g., random access memory (RAM)) and non-volatile data storage devices (e.g., flash memory, hard disk drive, solid-state drive, erasable programmable read-only memory (EPROM), but not limited thereto). In some examples, processor 1002 and storage device 1004 may be implemented as a single device (e.g., semiconductor device product, system-on-a-chip (SoC), but not limited thereto). In some examples, processor 1002 and storage device 1004 may be implemented as separate devices.

[0083] In some examples, the machine-executable code 1006 may include computer-readable instructions (e.g., software code, firmware code, but not limited thereto). As a non-limiting example, the computer-readable instructions may be stored in storage device 1004, directly accessed by processor 1002, and executed by processor 1002 using at least logic circuitry 1008. Also as a non-limiting example, the computer-readable instructions may be stored on storage device 1004, transferred to a memory device (not shown) for execution, and executed by processor 1002 using at least logic circuitry 1008. Therefore, in some examples, logic circuitry 1008 includes logic circuitry 1008 that can be configured electrically.

[0084] In some examples, machine-executable code 1006 may describe the hardware (e.g., circuitry) to be implemented in logic circuitry 1008 to perform functional elements. This hardware can be described from any of a range of abstraction levels, from low-level transistor layout to high-level description languages. At high-level abstraction, hardware description languages ​​(HDLs), such as the IEEE standard hardware description language (HDL), can be used. As a non-limiting example, Verilog can be used. ™ SYSTEMVERILOG ™ Or Very Large Scale Integration (VLSI) Hardware Description Language (VHDL) ™ ).

[0085] HDL descriptions can be transformed into descriptions at any of a variety of other levels of abstraction as needed. As a non-limiting example, a high-level description can be transformed into a logic-level description such as Register Transfer Language (RTL), Gate-level (GL) description, layout-level description, or mask-level description. As a non-limiting example, micro-operations to be performed by the hardware logic circuitry of logic circuitry 1008 (e.g., gates, flip-flops, registers, but not limited thereto) can be described in RTL and then transformed into a GL description by a synthesis tool, and the GL description can be transformed into a layout-level description by a placement and routing tool, which corresponds to the physical layout of an integrated circuit, discrete gate or transistor logic unit, discrete hardware unit, or a combination thereof of a programmable logic device. Therefore, in some examples, machine-executable code 1006 may include HDL, RTL, GL descriptions, mask-level descriptions, other hardware descriptions, or any combination thereof.

[0086] In an example where machine executable code 1006 includes a hardware description (at any level of abstraction), a system (not shown, but including storage device 1004) can be used to implement the hardware description described by machine executable code 1006. As a non-limiting example, processor 1002 may include a programmable logic device (e.g., an FPGA or PLC), and logic circuitry 1008 may be electrically controlled to implement circuitry corresponding to the hardware description into logic circuitry 1008. Also as a non-limiting example, logic circuitry 1008 may include hardwired logic components manufactured by a manufacturing system (not shown, but including storage device 1004) according to the hardware description of machine executable code 1006.

[0087] Regardless of whether the machine-executable code 1006 includes computer-readable instructions or a hardware description, the logic circuit 1008 is adapted to execute the functional elements described by the machine-executable code 1006 when implementing the functional elements of the machine-executable code 1006. It should be noted that although the hardware description may not directly describe the functional elements, it indirectly describes the functional elements that the hardware elements described by the hardware description can execute. Example

[0088] The following is a non-exhaustive and non-limiting list of embodiments. Not every embodiment listed below is explicitly and individually indicated to be combinable with all other embodiments listed below and discussed above. However, it is intended that these embodiments be combinable with all other embodiments unless it would be obvious to those skilled in the art that these embodiments are not combinable.

[0089] Example 1: An apparatus comprising: an input terminal disposed at a physical layer device for receiving from a network a low-density parity check (LDPC) frame comprising bits corresponding to a log-likelihood ratio (LLR) message indicating the probability that the bits have predetermined logic values; and processing circuitry configured to: saturate the LLR value of a portion of the LLR message corresponding to a known bit of the LDPC frame to the highest value represented by the LLR message; and transmit the LLR message between a check node and a message node, the message node corresponding to the bits and the check node corresponding to the parity check equation of the parity check matrix.

[0090] Example 2: The device according to Example 1, wherein the known bits of the LDPC frame include the last ninety-seven bits of the LDPC frame before the parity vector of the LDPC frame.

[0091] Example 3: The device according to any one of Examples 1 and 2, wherein the highest value is the most positive value of the LLR message.

[0092] Example 4: The device according to Example 3, wherein the most positive value corresponds to the highest level of certainty that can be conveyed by an LLR message with a corresponding bit having a zero value.

[0093] Example 5: The device according to any one of Examples 3 and 4, wherein the most positive value is +31.75.

[0094] Example 6: The device according to any one of Examples 1 to 5, wherein the logic value of the known bit is zero.

[0095] Example 7: A method for decoding a low-density parity-check (LDPC) frame, the method comprising: receiving an LDPC frame including known bits and unknown bits at a physical layer device, the known bits having known values; saturating the log-likelihood ratio (LLR) values ​​of at least a portion of an LLR message corresponding to the known bits to the highest possible value, the LLR message indicating the probability that the bits have predetermined logical values; and transmitting the LLR message between a check node and a message node, the message node corresponding to the bits and the check node corresponding to the parity-check equation of the parity-check matrix.

[0096] Example 8: The method according to Example 7 includes correcting LDPC frames in response to the transmission of LLR messages between the verification node and the message node.

[0097] Example 9: The method according to any one of Examples 7 and 8, wherein saturating at least a portion of the LLR value of the LLR message corresponding to the known bit to the highest possible value comprises: saturating at least a portion of the LLR value corresponding to the known bit to the most positive value.

[0098] Example 10: The method according to any one of Examples 7 to 9, wherein the known value of the known bit is zero.

[0099] Example 11: The method according to any one of Examples 7 to 10, wherein saturating at least a portion of the LLR value of the LLR message corresponding to the known bit to the highest possible value comprises: at the beginning of each sub-iteration of transmitting the LLR message between the check node and the message node, saturating at least a portion of the LLR of the known bit to the highest possible value.

[0100] Example 12: The method according to any one of Examples 7 to 11, wherein saturating the LLR values ​​of at least a portion of the LLR messages corresponding to the known bits to the highest possible value comprises: saturating the LLR values ​​of all LLR messages corresponding to the known bits to the highest possible value.

[0101] Example 13: An apparatus comprising: an input for receiving a low-density parity-check (LDPC) frame, the LDPC frame including bits having associated log-likelihood ratio (LLR) values, a portion of which have known values, the LLR values ​​indicating the probability that the bits have predetermined logic values; and processing circuitry for: saturating a subset of LLR values ​​corresponding to at least some of the bits in the portion having known values ​​to the highest possible value; and correcting the bits of the LDPC frame using message nodes and check nodes in response to at least the LLR values, the message nodes corresponding to the bits and the check nodes corresponding to the parity-check equation of a parity-check matrix.

[0102] Example 14: The device according to Example 13, wherein the processing circuit saturates a subset of LLR values ​​corresponding to portions of bits having known values ​​to the most positive value.

[0103] Example 15: The device according to any one of Examples 13 and 14, wherein the known value is zero.

[0104] Example 16: The device according to any one of Examples 13 to 15, wherein the LDPC frame includes: a first data portion including message bits; and a second data portion including a portion of bits having known values.

[0105] Example 17: The device according to Example 16, wherein each message bit in the message bits contributes to six check nodes in the check nodes.

[0106] Example 18: The device according to any one of Examples 13 to 17, wherein the LDPC frame includes a first parity vector and a second parity vector.

[0107] Example 19: The device according to any one of Examples 13 to 18, wherein the processing circuit saturates at least a portion of the subset of LLR values ​​corresponding to the portions of bits having known values ​​to the highest possible value at the beginning of each sub-iteration.

[0108] Example 20: The device according to any one of Examples 13 to 19, wherein the processing circuit saturates the LLR value corresponding to all bits of the portion of bits having known values ​​to the highest possible value.

[0109] Example 21: A decoder for a physical layer device, the decoder comprising: an input line configured to receive soft log-likelihood ratio (LLR) messages corresponding to bits of a frame from a wired line of a wired local area network; and logic circuitry configured to: saturate the LLR messages corresponding to known bits of a frame to a maximum positive value; and transmit soft LLR messages corresponding to unknown bits of a frame between a check node and a message node.

[0110] Example 22: The decoder according to Example 21, wherein the known bits of a frame include the last ninety-seven bits preceding the parity vector of that frame.

[0111] Example 23: The decoder according to any one of Examples 21 and 22, wherein the most positive value is +31.75.

[0112] Example 24: A decoder according to any one of Examples 21 to 23, wherein the value of the known bit is zero.

[0113] Example 25: A method for decoding a frame, the method comprising: receiving a frame including known bits and unknown bits at a physical layer device of a wired local area network, the known bits having known values; saturating an LLR message corresponding to the known bits to a maximum positive value; and transmitting a soft LLR message corresponding to the unknown bits between a check node and a message node.

[0114] Conclusion

[0115] As used in this disclosure, the terms "module" or "component" can refer to a specific hardware implementation that performs actions of a module or component and / or software object or software routine that can be stored on and / or executed by general-purpose hardware of a computing system (e.g., computer-readable media, processing apparatus, but not limited thereto). In some examples, the different components, modules, engines, and services described in this disclosure can be implemented as objects or processes (e.g., as separate threads) that execute on a computing system. While some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are also possible and contemplated.

[0116] As used in this disclosure, the term "combination" referring to multiple elements can include any combination of all elements or any combination of various different sub-combinations of certain elements. For example, the phrase "A, B, C, D or combinations thereof" can refer to any one of A, B, C, or D; a combination of each of A, B, C, and D; and any sub-combination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0117] The terms used in this disclosure, and especially in the appended claims (e.g., the body of the appended claims), are generally intended to be “open” terms (e.g., the term “comprising” should be interpreted as “including but not limited to”, the term “having” should be interpreted as “at least having”, and the term “comprising” should be interpreted as “including but not limited to”, without limitation).

[0118] Furthermore, if a specific number of introduced claim statements are anticipated, such an intent will be explicitly stated in the claims, and without such statements, such an intent does not exist. For example, as an aid to understanding, the appended claims may contain the use of the introductory phrases “at least one” and “one or more” to introduce claim statements. However, the use of such phrases should not be construed as implying that a claim statement introduced by the indefinite article “a” or “an” limits any particular claim containing such an introduced claim statement to an example containing only one such statement, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and / or “an” can be interpreted as referring to “at least one” or “one or more”); the same applies to the use of definite articles to introduce claim statements.

[0119] Furthermore, even when a specific number of the introduced claims are explicitly stated, those skilled in the art will recognize that such statements should be interpreted as meaning at least the number stated (e.g., the unmodified statement "two statements" means at least two statements, or two or more statements, in the absence of other modifying elements). Additionally, in instances where conventions such as "at least one of A, B, and C, but not limited thereto" or "one or more of A, B, and C, but not limited thereto" are used, such constructions are generally intended to include, but are not limited to, a single A, a single B, a single C, A and B together, A and C together, B and C together, or A, B, and C together.

[0120] Furthermore, any separate word or phrase presenting two or more alternative terms in the specification, claims, or drawings should be understood to include the possibility of including one term, any one term, or both terms. For example, the phrase "A or B" should be understood to include the possibility of including "A" or "B" or "A and B".

[0121] While this disclosure describes the invention with respect to certain illustrated examples, those skilled in the art will recognize and understand that the invention is not limited thereto. Rather, many additions, deletions, and modifications may be made to the illustrated examples and the examples themselves without departing from the scope of the invention as claimed below and its legal equivalents. Furthermore, features from one example may be combined with features from another example while still being included within the scope of the invention as contemplated by the inventors.

Claims

1. An apparatus for decoding low-density parity-check (LDPC) frames, comprising: An input terminal is provided at a physical layer device to receive the LDPC frame from the network, the LDPC frame comprising bits corresponding to a log-likelihood ratio (LLR) message indicating the probability that the bits have a predetermined logical value. and Processing circuit, the processing circuit being used for: At the start of each sub-iteration of the LLR message transmitted between the verification node and the message node, the LLR value of a portion of the LLR message corresponding to the known bits of the LDPC frame is saturated to the highest value represented by the LLR message. as well as The LLR message is transmitted between the verification node and the message node, where the message node corresponds to the bit and the verification node corresponds to the parity check equation of the parity check matrix.

2. The device of claim 1, wherein the known bits of the LDPC frame include the last ninety-seven bits of the LDPC frame preceding the parity vector of the LDPC frame.

3. The device of claim 1, wherein the highest value is the most positive value of the LLR message.

4. The device of claim 3, wherein the most positive value corresponds to the highest level of certainty that can be conveyed by the LLR message having a corresponding bit value of zero.

5. The device according to claim 3, wherein the most positive value is +31.

75.

6. The device according to claim 1, wherein the logic value of the known bit is zero.

7. A method for decoding low-density parity-check (LDPC) frames, the method comprising: The LDPC frame, comprising known bits and unknown bits, is received at the physical layer device, wherein the known bits have known values. At the beginning of each sub-iteration of transmitting an LLR message between the check node and the message node, the LLR value of at least a portion of the log-likelihood ratio corresponding to the known bit is saturated to the highest possible value, the LLR message indicating the probability that the bit has a predetermined logical value. as well as The LLR message is transmitted between the verification node and the message node, where the message node corresponds to the bit and the verification node corresponds to the parity check equation of the parity check matrix.

8. The method of claim 7, further comprising correcting the LDPC frame in response to the transmission of the LLR message between the verification node and the message node.

9. The method of claim 7, wherein saturating the LLR value of at least a portion of the LLR message corresponding to the known bit to the highest possible value comprises: At least a portion of the LLR value corresponding to the known bit is saturated to the most positive value.

10. The method of claim 7, wherein the known value of the known bit is zero.

11. The method of claim 7, wherein saturating the LLR value of at least a portion of the LLR message corresponding to the known bit to the highest possible value comprises: Saturate the LLR values ​​of all LLR messages corresponding to the known bits to the highest possible value.

12. An apparatus for decoding low-density parity-check (LDPC) frames, comprising: An input terminal is used to receive the LDPC frame, the LDPC frame including bits having an associated log-likelihood ratio (LLR) value, a portion of the bits having a known value, the LLR value indicating the probability that the bit has a predetermined logic value; and Processing circuit, the processing circuit being used for: At the beginning of each sub-iteration, a subset of the LLR values ​​corresponding to at least some bits in the portion of the bits having the known values ​​is saturated to the highest possible value; as well as In response to at least the LLR value, message nodes and check nodes are used to correct the bits of the LDPC frame, the message nodes corresponding to the bits and the check nodes corresponding to the parity check equation of the parity check matrix.

13. The device of claim 12, wherein the processing circuitry saturates the subset of the LLR values ​​corresponding to the portion of the bit having the known value to the most positive value.

14. The device of claim 12, wherein the known value is zero.

15. The device of claim 12, wherein the LDPC frame comprises: The first data portion includes message bits; and The second data portion includes the portion of the bits having the known value.

16. The device of claim 15, wherein each message bit in the message bits contributes to six check nodes in the check nodes.

17. The apparatus of claim 12, wherein the LDPC frame comprises a first parity vector and a second parity vector.

18. The device of claim 12, wherein the processing circuitry saturates the LLR value corresponding to all bits of the portion of the bit having the known value to the highest possible value.

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