A W etching solution with controllable side corrosion of laminated metal and preparation method thereof

Abstract

The present invention relates to a W layer etching solution with controllable side etching of laminated metal and a preparation method thereof. The composition includes an oxidant, an oxygen promoter, a buffer reagent, an inhibitor, a surfactant and ultrapure water. The etching solution uses an oxidant to oxidize W to form an oxide for etching; an inorganic acid is used as a secondary oxidant; a buffer reagent such as ammonium acetate provides a stable etching environment for the etching solution; the inhibitor can inhibit the influence of aluminum ions and copper ions on W etching; the surfactant can reduce the surface tension of the solution and promote the uniformity and integrity of W etching. The present invention provides a W etching solution with controllable side etching of laminated metal and a preparation method thereof. According to the method, the etching solution can not only effectively control the etching of the W layer in the laminated metal, but also achieve the excellent qualities of high etching precision and good etching morphology of W, and ensure that TiN and Ti layer metals are not etched, and AlCu has an extremely low etching rate.

Description

Technical Field

[0001] The invention belongs to the field of electronic chemicals, and in particular relates to a W layer etching solution with controllable side etching of laminated metals and a preparation method thereof. Background Art

[0002] In recent years, with the rapid development of the field of microelectronic device manufacturing, people have higher requirements for electronic equipment, which means that the microelectronic devices in integrated circuits are required to be more miniaturized and integrated.

[0003] The deposition of tungsten metal films is an important part of the semiconductor manufacturing process. Using tungsten metals as conductive materials to achieve interconnection in integrated circuit manufacturing with specially shaped contacts or interconnects is one of the most commonly used methods. When multiple metal layers coexist, in order to etch a certain metal layer in a targeted manner, we usually use PR masks in advance to protect other metal layers. Therefore, the cumbersome and complicated process not only increases the manufacturing cost, but also easily causes undercuts in the multi-layer metal stack structure.

[0004] Based on the above, developing a metal etching solution with high selectivity to W and controllable side etching is conducive to solving the above problems and promoting the development of integrated circuit manufacturing technology. Summary of the invention

[0005] The present invention aims at the etching problems of W layer in laminated metal in the existing semiconductor integrated circuit process, and aims to provide a W etching solution with controllable side etching of laminated metal and its preparation method. To achieve the purpose of the invention, the raw materials of the present invention include: 7-11wt% oxidant, 49-55wt% oxygen promoter; 18-25wt% buffer reagent; 0.05-1wt% inhibitor; 0.01-0.3wt% surfactant, and the rest water.

[0006] In the implementation case, the oxidant is hydrogen peroxide; the oxygen promoter is acetic acid; the buffer reagent is ammonium acetate; the inhibitor is at least one of N-methylpiperidine, N-acyl amino acid, N-acyl amino acid salt and citric acid, glycine and acetic acid; the surfactant is at least one of triethanolammonium dodecyl sulfate, disodium lauryl ether succinate sulfonate, cocamidopropyl betaine, coconut oil monoethanolamide and coconut oil fatty acid diethanolamide.

[0007] In the implementation case, the preparation method of the W etching solution with controllable side etching of laminated metal is as follows: weigh the oxidant, oxygen promoter, buffer agent, inhibitor and ultrapure water respectively in proportion, prepare the etching solution in the order of water, oxidant, oxygen promoter, buffer agent, inhibitor and surfactant, or prepare the etching solution in any order of addition, and cool to room temperature after the mixture is evenly mixed.

[0008] In the implementation case, the etching temperature is 58-63° C.; the etching method is immersion etching; the etching time is 13 min; the pH value of the solution is between the buffer zone of ammonium acetate or acetic acid-ammonium acetate, specifically, the pH value is about 3.5-5.5.

[0009] In the etching method described herein, after removing the exposed W film layer, the ratio of the lateral etching depth of the W layer under the AlCu film layer to the longitudinal etching depth of the exposed W film layer is less than 2.1, or less than 1.5, or less than 1.0. Further, for the preferred composition, the ratio range is less than about 2.1; the lateral etching depth of the W film layer covered by the photoresist is the lateral etching amount, and the lateral etching amount ranges from 200 nm to 820 nm.

[0010] Advantages and beneficial effects of the present invention:

[0011] 1) The invention has a simple formula and simple preparation steps, but can achieve the purpose of controllable side etching of the W layer and highly selective etching without etching the TiN and Ti metal layers, while greatly reducing the etching rate of AlCu and effectively avoiding electrochemical reactions between metal layers; wet etching is performed at a higher temperature for a longer time, and the results show that the etching solution has a stable formula and a stable etching effect.

[0012] 2) In the multi-layer metal stack structure, the etching rate can be effectively controlled by adjusting the formula ratio, and the W layer can still have controllable side etching and high selectivity without etching the TiN and Ti layers, effectively reducing the etching rate of the AlCu layer. The maximum etching rate of the AlCu layer is 11.31nm / min.

[0013] 3) Using hydrogen peroxide as the main oxidant and adding acetic acid as the auxiliary oxidant can not only inhibit the decomposition of hydrogen peroxide and maintain the concentration of hydrogen peroxide at a high level, but also stabilize the etching rate and extend the etching life of the etching solution. Acetic acid provides an acidic environment for the etching reaction, which can promote the dissolution of tungsten oxide and ensure the normal etching reaction of W; acetic acid can form a buffer with ammonium acetate, providing a stable reaction environment for etching; acetic acid can form a passivation film with AlCu, TiN and Ti to protect the metal layer.

[0014] 4) Adding buffer reagents provides a stable etching environment for the etching process, avoiding large differences in etching effects caused by large changes in pH value, and improving the etching accuracy of W and the stability of the etching effect.

[0015] 5) The inhibitor forms complexes with aluminum ions and copper ions in the solution, respectively, inhibiting the etching rate of the AlCu layer and improving the selectivity of W.

[0016] 6) The addition of surfactants can reduce the surface tension of the solution, facilitate the contact between W and the etching solution, and change the lateral etching rate and vertical etching rate of W.

[0017] The etching solution for the controllable W layer of the laminated metal side etching described in the present invention can ensure that the TiN layer and the Ti layer are not etched while etching W efficiently, and the AlCu alloy is hardly etched, that is, the etching solution has extremely high selectivity for W. The etching solution uses an oxidant to oxidize W to form an oxide for etching; an inorganic acid is used as a secondary oxidant, which not only increases the oxidizing property of the oxidant but also provides sufficient hydrogen ions, ensuring good etching performance; buffer reagents such as ammonium acetate provide a stable etching environment for the etching solution, avoiding a large impact of a large change in pH value on the etching rate and etching stability, and stabilizing the etching rate and side etching rate; an inhibitor can inhibit the influence of aluminum ions and copper ions on W etching, ensuring that W has a high etching selectivity relative to other metals; a surfactant can reduce the surface tension of the solution, promote the uniformity and integrity of W etching, and avoid etching residues. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic diagram of the microstructure of a semiconductor device with multiple metal film layers exposed on a silicon substrate, wherein A is a schematic diagram of the microstructure of the test piece before etching, and B is a schematic diagram of the microstructure of the test piece after etching.

[0019] Figure 2 These are SEM test pictures of semiconductor devices before etching, where A is the SEM picture of the multi-layer metal structure sheet before etching, and B is the SEM magnified picture of the multi-layer metal structure sheet before etching.

[0020] Figure 3 SEM image of the AlCu layer at the maximum etching thickness after etching the multi-layer metal structure.

[0021] Figure 4 SEM image of the TiN / Ti layer after etching of the multilayer metal structure sheet.

[0022] Figure 5 Example 1 SEM slice test image.

[0023] Figure 6 Example 2 SEM slice test image.

[0024] Figure 7 Example 3 SEM slice test image.

[0025] Figure 8 Example 4 SEM slice test image.

[0026] Fig. 9 Example 5 SEM slice test image.

[0027] Fig.10 Example 6 SEM slice test image.

[0028] Fig.11 Example 7 SEM slice test image.

[0029] Fig.12 Example 8 SEM slice test image.

[0030] Fig.13 Example 9 SEM slice test image.

[0031] Fig.14 Example 10 SEM slice test image.

[0032] Fig.15 Example 11 SEM slice test image.

[0033] Fig.16 Example 12 SEM slice test image.

[0034] Fig.17 Example 13 SEM slice test image.

[0035] Fig.18 Example 14 SEM slice test image.

[0036] Fig.19 Comparative Example 1 SEM slice test image.

[0037] Fig. 20 Comparative Example 2 SEM slice test image.

[0038] Fig.21 Comparative Example 3 SEM slice test image.

[0039] Fig. 22 Comparative Example 4 SEM slice test image. DETAILED DESCRIPTION

[0040] In order to better understand the present invention, the content of the present invention is further explained below in conjunction with embodiments, but the content of the present invention is not limited to the following examples.

[0041] Example 1

[0042] A W etching solution with controllable side corrosion of laminated metal, the component contents of which are shown in Table 1:

[0043] Table 1 Components and contents of Example 1

[0044]

[0045] Prepare the etching solution according to the components and contents listed in Table 1. Figure 1 and Figure 2The semiconductor device shown in the figure is etched, the etching solution temperature is controlled at 60°C, and the etching time is 13 min. After etching, the multilayer metal structure is cleaned and dried and SEM sliced ​​for testing. The SEM picture is shown in Figure 5 The etching effects are summarized in Table 2. Figure 1 In the embodiment, the AlCu layer is about 5.2 um, the W layer is about 400 nm thick, and the total thickness of TiN / Ti is about 110 nm. The exposed W film layer is etched and / or removed therefrom by the etching solution and etching method of the present invention. Figure 3 This is the state of the AlCu metal layer after etching. The AlCu layer before etching is about 5.2 um, and the maximum thickness of the AlCu layer left after etching is about 5.053 um. The etching thickness is about 147 nm, and the etching rate is about 11.31 nm / min. Figure 4 This is the state of the TiN / Ti layer after etching. Its total thickness before etching is about 110 nm, and its total thickness after etching is about 111 nm. The thickness of the TiN / Ti layer does not change before and after etching, that is, neither the TiN nor the Ti layer is etched.

[0046] During the etching process, the exposed W film layer needs to be completely etched. During this process, the etching solution will laterally etch the W film layer under the photoresist. After etching, cleaning and drying, the semiconductor device is subjected to SEM sectioning test. The SEM picture is as follows: Figure 5 The etching effect is shown in Table 2. In Example 1, the exposed W film layer is completely etched, the side etching amount of the AlCu lower layer W is about 748nm, the etching effect is good, and the ratio of the side etching amount to the W layer thickness is about 1.9.

[0047] Example 2

[0048] The same as in Example 1, except that the content of hydrogen peroxide was adjusted to 9.5%, the inhibitor was adjusted to 0.06% of sodium N-acyl sarcosinate, the surfactant was adjusted to 0.04% of disodium lauryl ether succinate sulfonate, and the contents of the other components remained unchanged, and the method was set to Example 2. The etching steps and testing methods of the semiconductor device were the same as those in Example 1.

[0049] SEM test results are shown in Figure 6 The etching effect is shown in Table 2. Compared with Example 1, the side etching amount in this embodiment is increased by about 815 nm, the etching effect is better, and the ratio of the side etching amount to the W layer thickness is about 2.0.

[0050] Example 3

[0051] Same as Example 1, HAc was adjusted to 52.4%, and the contents of other components remained unchanged, which was set as Example 3. The etching steps and testing methods of the semiconductor device were the same as those in Example 1.

[0052] SEM test results are shown in Figure 7The etching effect is shown in Table 2. Compared with Example 1, the side etching amount in this embodiment is increased by about 802 nm, the etching effect is better, and the ratio of the side etching amount to the W layer thickness is about 2.0.

[0053] Example 4

[0054] Same as in Example 1, the content of ammonium acetate was adjusted to 20.5%, and the contents of other components remained unchanged, which was set as Example 4. The etching steps and testing methods of the semiconductor device were the same as those in Example 1.

[0055] SEM test results are shown in Figure 8 The etching effect is shown in Table 2. Compared with Example 1, the side etching amount in this embodiment is increased by about 779 nm, the etching effect is better, and the ratio of the side etching amount to the W layer thickness is about 1.8.

[0056] Example 5

[0057] Same as Example 1, HAc is adjusted to 52.5%, ammonium acetate is adjusted to 21.5%, and the contents of other components remain unchanged, which is set to Example 5. The semiconductor device etching steps and testing methods are the same as Example 1.

[0058] SEM test results are shown in Fig. 9 The etching effect is shown in Table 2. Compared with Example 1, the side etching amount in this embodiment is increased by about 753 nm, the etching effect is better, and the ratio of the side etching amount to the W layer thickness is about 1.9.

[0059] Example 6

[0060] The same as Example 1, except that the inhibitor was adjusted to 0.5% of N-acyl glutamic acid, the surfactant was adjusted to 0.06% of cocamidopropyl betaine, and the contents of other components remained unchanged, and the method was set to Example 6. The semiconductor device etching steps and testing methods were the same as those in Example 1.

[0061] SEM test results are shown in Fig.10 The etching effect is shown in Table 2. Compared with Example 1, the side etching amount in this embodiment is reduced by about 547 nm, the etching effect is excellent, and the ratio of the side etching amount to the W layer thickness is about 1.4.

[0062] Example 7

[0063] The same as in Example 1, except that HAc was adjusted to 51.5%, ammonium acetate was adjusted to 23.5%, the inhibitor was adjusted to 0.30% of glycine, the surfactant was adjusted to 0.06% of coconut oil monoethanolamide 0.1%, and the contents of the other components remained unchanged, and the semiconductor device etching steps and testing methods were the same as in Example 1.

[0064] SEM test results are shown in Fig.11The etching effect is shown in Table 2. Compared with Example 1, the side etching amount in this embodiment is reduced by about 368 nm, the etching effect is excellent, and the ratio of the side etching amount to the W layer thickness is about 0.9.

[0065] Example 8

[0066] The same as in Example 1, except that HAc was adjusted to 52.5%, ammonium acetate was adjusted to 23.5%, the inhibitor was adjusted to 0.6% citric acid, the surfactant was adjusted to 0.12% coconut oil monoethanolamide, and the contents of the other components remained unchanged, and the method was set to Example 8. The etching steps and testing methods of the semiconductor device were the same as those in Example 1.

[0067] SEM test results are shown in Fig.12 The etching effect is shown in Table 2. Compared with Example 1, the side etching amount in this embodiment is reduced by about 279 nm, the etching effect is excellent, and the ratio of the side etching amount to the W layer thickness is about 0.7.

[0068] Example 9

[0069] The same as in Example 1, except that HAc was adjusted to 52.5%, ammonium acetate was adjusted to 21.8%, the surfactant was adjusted to 0.18% of coconut oil fatty acid diethanolamide, and the contents of the other components remained unchanged, and the method was set to Example 9. The semiconductor device etching steps and testing methods were the same as in Example 1.

[0070] SEM test results are shown in Fig.13 The etching effect is shown in Table 2. Compared with Example 1, the side etching amount in this embodiment is reduced by about 223 nm, the etching effect is excellent, and the ratio of the side etching amount to the W layer thickness is about 0.6.

[0071] Example 10

[0072] The same as in Example 1, except that the inhibitor is adjusted to 0.23% of N-methylpiperidine, the surfactant is adjusted to 0.3% of sodium N-lauroylglycine, and the contents of the other components remain unchanged, and the method is set to Example 10. The semiconductor device etching steps and testing methods are the same as in Example 1.

[0073] SEM test results are shown in Fig.14 The etching effect is shown in Table 2. Compared with Example 1, the side etching amount in this embodiment is reduced by about 414 nm, the etching effect is excellent, and the ratio of the side etching amount to the W layer thickness is about 1.0.

[0074] Embodiment 11

[0075] Same as Example 1, except that the hydrogen peroxide was adjusted to 8.1, the inhibitor was adjusted to 0.20% coconut oil monoethanolamide, and the contents of other components remained unchanged, and the method was set to Example 11. The semiconductor device etching steps and testing methods were the same as those in Example 1.

[0076] SEM test results are shown in Fig.15 The etching effect is shown in Table 2. Compared with Example 1, the side etching amount in this embodiment is reduced by about 480 nm, the etching effect is excellent, and the ratio of the side etching amount to the W layer thickness is about 1.2.

[0077] Example 12

[0078] Based on Example 1, the hydrogen peroxide was adjusted to 7.65%, the surfactant was adjusted to 0.15% coconut oil fatty acid diethanolamide, and the contents of the other components remained unchanged, and it was set to Example 12. The semiconductor device etching steps and testing methods were the same as those in Example 1.

[0079] SEM test results are shown in Fig.16 The etching effect is shown in Table 2. Compared with Example 1, the side etching amount is reduced by about 463 nm, the etching effect is excellent, and the ratio of the side etching amount to the W layer thickness is about 1.2.

[0080] Embodiment 13

[0081] Same as Example 1, the hydrogen peroxide is adjusted to 8.5%, the inhibitor is adjusted to 0.21% citric acid, the surfactant is adjusted to 0.18% sodium N-fatty acyl glutamate, and the contents of other components remain unchanged, which is set to Example 13. The semiconductor device etching steps and testing methods are the same as those in Example 1.

[0082] SEM test results are shown in Fig.17 The etching effect is shown in Table 2. Compared with Example 1, the side etching amount in this embodiment is reduced by about 569 nm, the etching effect is excellent, and the ratio of the side etching amount to the W layer thickness is about 1.4.

[0083] Embodiment 14

[0084] The same as in Example 1, except that HAc was adjusted to 53.4%, the inhibitor was adjusted to 0.10% glutamic acid, the surfactant was adjusted to 0.12% triethanolammonium dodecyl sulfate, and the contents of the other components remained unchanged, and the method was set to Example 14. The semiconductor device etching steps and testing methods were the same as in Example 1.

[0085] SEM test results are shown in Fig.18 The etching effect is shown in Table 2. Compared with Example 1, the side etching amount in this embodiment is reduced by about 625 nm, the etching effect is better, and the ratio of the side etching amount to the W layer thickness is about 1.6.

[0086] Comparative Example 1

[0087] The same as Example 1, only the hydrogen peroxide was adjusted to 13%, and the contents of other components remained unchanged, which was set as Comparative Example 1. The semiconductor device etching steps and testing methods were the same as those in Example 1.

[0088] SEM test results are shown in Fig.19 The etching effect is shown in Table 2. Compared with Example 1, the side etching amount in this embodiment is increased by about 1228 nm, the etching effect is poor, and the ratio of the side etching amount to the W layer thickness is about 3.1.

[0089] Comparative Example 2

[0090] Same as in Example 1, the etching temperature was adjusted to 70° C., and the contents of other components remained unchanged, which was set as Comparative Example 2. The etching steps and testing methods of the semiconductor device were the same as in Example 1.

[0091] SEM test results are shown in Fig. 20 The etching effect is shown in Table 2. Compared with Example 1, the side etching amount in this embodiment is increased by about 1697 nm, the etching effect is poor, and the ratio of the side etching amount to the W layer thickness is about 4.2.

[0092] Comparative Example 3

[0093] The same as Example 1, except that only the surfactant is removed, and the contents of other components remain unchanged, is set as Comparative Example 3, and the semiconductor device etching steps and testing methods are the same as those in Example 1.

[0094] SEM test results are shown in Fig.21 The etching effect is shown in Table 2. Compared with Example 1, the side etching amount in this embodiment is increased by about 1038 nm, the etching effect is poor, and the ratio of the side etching amount to the W layer thickness is about 2.6.

[0095] Comparative Example 4

[0096] The same as in Example 1, except that the acetic acid is adjusted to 30%, and the ammonium acetate is adjusted to 10%, is set as Comparative Example 4, and the semiconductor device etching steps and testing methods are the same as in Example 1.

[0097] SEM test results are shown in Fig. 22 The etching effect is shown in Table 2. Compared with Example 1, the side etching amount in this embodiment is increased by about 949 nm, the etching effect is poor, and the ratio of the side etching amount to the W layer thickness is about 2.4.

[0098] Table 2 Etching effect of each embodiment

[0099]

[0100] Obviously, the above embodiments are only examples for clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the protection scope of the invention.

Claims

1. A W layer etching solution with controllable side etching of laminated metal, characterized in that: The etching solution comprises: 7-11 wt% of oxidant hydrogen peroxide; 49-55 wt% of oxygen-promoting agent acetic acid; 18-25 wt% of buffer reagent ammonium acetate; 0.05-1 wt% of inhibitor; 0.01-0.3 wt% of surfactant, and the rest is water, wherein the inhibitor is at least one of N-methylpiperidine and N-acylamino acid, and the surfactant is at least one of triethanolammonium dodecyl sulfate, disodium lauryl ether succinate sulfonate, cocamidopropyl betaine, coconut oil monoethanolamide and coconut oil fatty acid diethanolamide.

2. The W layer etching solution with controllable side etching relative to the laminated metal according to claim 1 is used in etching semiconductor materials containing AlCu, W, TiN and Ti.

Images