Pass-gate driver

Abstract

Transmission gate drivers are disclosed. A driver (200) includes a low-resistance charge path (MP3, MP4, MP5) between a supply voltage rail (205) and a first output node (250), a high-resistance charge path (MP3, MP2) between the supply voltage rail and the first output node, an inverter (240) coupled to the first output node and configured to enable and disable the low-resistance charge path, and a high-resistance discharge path (MN2, MN3) between the first output node and a second output node. In some implementations, the first output node is coupled to a control terminal of a transmission gate transistor (145). The low-resistance charge path charges a voltage on the first output node to a threshold voltage of the transmission gate transistor, and the high-resistance charge path charges the voltage on the first output node to greater than the threshold voltage of the transmission gate transistor. The high-resistance discharge path discharges the voltage on the first output node.

Description

Background Technology

[0001] Digital low-dropout (LDO) regulators comprise an array of transmission gate switches driven by a series of drivers. The transmission gate switches are slowly turned on and off via a shallow ramp in the gate voltage to prevent strong transients in the current flowing through the transmission gate switches and ringing in the regulated output voltage due to parasitic inductance of the integrated circuit. However, the shallow ramp and slow turn-on time introduce a "dead time" when the gate-source voltage of a particular transmission gate switch is charged from ground to the threshold voltage at which the transistor is significantly turned on, thus affecting the stability of the digital LDO regulator. Summary of the Invention

[0002] A driver includes a low-resistance charging path between a power supply voltage rail and a first output node, a high-resistance charging path between the power supply voltage rail and the first output node, an inverter coupled to the first output node and configured to enable and disable the low-resistance charging path, and a high-resistance discharging path between the first output node and a second output node. In some embodiments, the first output node is coupled to a control terminal of a transmission gate transistor. The low-resistance charging path charges the voltage at the first output node to a threshold voltage of the transmission gate transistor, and the high-resistance charging path charges the voltage at the first output node to a value greater than the threshold voltage of the transmission gate transistor. The high-resistance discharging path discharges the voltage at the first output node.

[0003] In some embodiments, the high-resistance discharge path includes a first transistor and a second transistor. The first transistor has a first control terminal for receiving a bias voltage, a first current terminal coupled to a first output node, and a second current terminal. The second transistor has a second control terminal for receiving a control signal, a third current terminal coupled to the second current terminal, and a fourth current terminal coupled to a second output node. In some embodiments, the aspect ratio of the first transistor is less than 1.

[0004] In some embodiments, the inverter includes a first transistor and a second transistor. The first transistor has a first control terminal coupled to a first output node, a first current terminal coupled to a power supply voltage rail, and a second current terminal. The second transistor has a second control terminal coupled to the first output node, a third current terminal coupled to the second current terminal, and a fourth current terminal coupled to the second output node. In some embodiments, the first output node is configured to be coupled to the control terminal of a transmission gate transistor, and the characteristics of the second transistor are selected to match the characteristics of the transmission gate transistor.

[0005] In some embodiments, the inverter is a first inverter, and the low-resistance charging path includes three transistors and a second inverter. The first transistor has a first control terminal for receiving a control signal, a first current terminal coupled to a power supply voltage rail, and a second current terminal. The second transistor has a second control terminal, a third current terminal coupled to the second current terminal, and a fourth current terminal. The third transistor has a third control terminal for receiving a bias voltage, a fifth current terminal coupled to the fourth current terminal, and a sixth current terminal coupled to a first output node. The second inverter has an input coupled to the output of the first inverter and an output coupled to the second control terminal.

[0006] In some embodiments, the high-resistance charging path includes a first transistor and a fourth transistor of the low-resistance charging path. The fourth transistor has a fourth control terminal for receiving a bias voltage, a seventh current terminal coupled to a second current terminal, and an eighth current terminal coupled to a first output node. In some embodiments, the aspect ratio of the fourth transistor is less than 1. Attached Figure Description

[0007] To describe the various examples in detail, reference will now be made to the accompanying drawings, in which:

[0008] Figure 1A An example system using a digital low differential pressure regulator is shown.

[0009] Figure 1B Show Figure 1A The system shown has a digital low differential pressure regulator.

[0010] Figure 2 An example transmission gate driver with slew rate control is shown.

[0011] Figure 3 Show Figure 2 The waveform of the signal in the transmission gate driver is shown.

[0012] Figure 4 An example transmission gate driver with slew rate control and reduced cross current is shown.

[0013] The same reference numerals are used in the accompanying drawings for features that are (functionally and / or structurally) the same or similar. Detailed Implementation

[0014] The described driver circuit achieves fast turn-on and a slow slew rate to reduce transients in the current flowing through the transmission gate switch driven by the driver circuit. One driver circuit includes six transistors and two inverters. A first transistor is coupled to a power supply voltage rail and has a first control terminal configured to receive a control signal. A second transistor is coupled between the first transistor and a first output node configured to be coupled to the control terminal of the transmission gate switch, and has a second control terminal configured to receive a first bias voltage, such that it remains on. The first and second transistors form a high-resistance charging path for the voltage at the first output node.

[0015] A third transistor is coupled to the first output node and has a third control terminal configured to receive a second bias voltage, thereby keeping it on. A fourth transistor is coupled between the third transistor and the second output node and has a fourth control terminal configured to receive a control signal. The third and fourth transistors form a high-resistance discharge path for the voltage on the first output node.

[0016] The fifth transistor is coupled to the first and second transistors and has a fifth control terminal. The sixth transistor is coupled between the fifth transistor and the first output node and has a sixth control terminal configured to receive a first bias voltage, such that it remains on. The first, fifth, and sixth transistors form a low-resistance charging path for the voltage at the first output node.

[0017] The first inverter includes a seventh transistor and an eighth transistor. The seventh transistor is coupled to a power supply voltage rail and has a seventh control terminal coupled to a first output node. The eighth transistor is coupled between the seventh transistor and a second output node and has an eighth control terminal coupled to the first output node. The second inverter is coupled to the output of the first inverter and is coupled to a fifth control terminal.

[0018] Figure 1A An example system 100 using a digital low-dropout (LDO) regulator 115 is shown. The system 100 includes a battery 105, a DC / DC converter 110, the digital LDO regulator 115, and additional components 120 (e.g., a load). The DC / DC converter 110 converts the power stored in the battery 105 into a voltage supplied to the digital LDO regulator 115. The digital LDO regulator 115 generates a regulated output voltage independent of load impedance, variations in the input voltage from the DC / DC converter 110, temperature, etc. The additional components 120 may include an image sensor, a processor, a controller, and / or other components that rely on a stable power supply voltage, which receives the stable power supply voltage from the digital LDO regulator 115.

[0019] Figure 1BAn example digital low-dropout (LDO) regulator 115 is shown, which includes a transmission gate switch array 140, a capacitor C150, an analog-to-digital converter (ADC) 155, a digital loop filter 160, and a transmission gate driver 170. The transmission gate switch array 140 includes N transistors M 145A-145N, which may be metal-oxide-semiconductor field-effect transistors (MOSFETs). Accordingly, in one example, M 145A-145N are n-type MOSFETs (NMOS). In other examples, one or more of M 145A-145N are PMOS or bipolar junction transistors (BJTs). A BJT includes a base corresponding to the gate terminal of a MOSFET and collector and emitter corresponding to the drain and source terminals of a MOSFET. The base of the BJT and the gate terminal of the MOSFET are also referred to as control inputs. The collector and emitter of the BJT and the drain and source terminals of the MOSFET are also referred to as current terminals.

[0020] The drain terminal of M145A-145N is coupled to the input voltage node Vin 125 via an on-chip decoupling 130A, which is represented by inductor LA134A and capacitor CA 138A. Inductor LA134A is coupled between the input voltage node Vin 125 and the drain terminal of M145A-145N, and capacitor CA138A is coupled between inductor LA134A, the drain terminal of M145A-145N, and ground 198. The source terminal of M145A-145N is coupled to the regulated output voltage node Vreg 195. The gate terminal of M145A-145N is coupled to the corresponding driver 175A-175N in the transmission gate driver 170 and configured to receive the corresponding gate voltage Vg 180A-180N.

[0021] The regulated output voltage node Vreg195 is supplied to other components in the integrated circuit, including the LDO regulator 115, via an on-chip decoupling 130B, represented as an inductor LB 134B and a capacitor CB 138B. The inductor LB 134B is coupled in series with the capacitor CB 138B, which is further coupled to ground 198. A capacitor C 150 is coupled between Vreg 195 and ground 198. The ADC 155 has an input coupled to Vreg 195 and an output coupled to a digital loop filter 160, which generates N control signals CTL165A-165N for the gate drivers 175A-175N.

[0022] The slow turn-on and turn-off of switches M145A-145N in the transmission gate switch array 140 via a shallow ramp in the gate voltages Vg 180A-180N prevents strong transients in the current Ipass 190 flowing through switches M145A-145N and ringing in the regulated output voltage Vreg 195 due to the parasitic inductance of the on-chip couplings 130A-130B. However, the slow slew rate adds a "dead time" amount as the gate-source voltage of a particular transistor is charged from ground to the threshold voltage at which the transistor is significantly turned on, thus affecting the stability of the digital LDO 115.

[0023] Figure 2 An example transmission gate driver 200 with slew rate control is shown (e.g., any of gate drivers 175N-175A). For ease of illustration, the example transmission gate driver 200 is described herein as... Figure 1A The example digital LDO regulator 115 shown is related to and combined with similar Figure 1B An example transmission gate switch M145 is used to illustrate this. The transmission gate driver 200 includes a first inverter 230 and a second inverter 240 having transistors MP1 and MN1, and transistors MP2-MP5 and MN2-MN3. In this example, MN1-MN3 are NMOS, while MP1-MP5 are PMOS. In other examples, one or more of MN1-MN3 are PMOS or BJT, and / or one or more of MP1-MP5 are NMOS or BJT. Transistor MN1 is selected to have substantially the same characteristics as M145, such as threshold voltage, geometry, rotation, bias, etc.

[0024] In inverter 230, the source terminal of MP1 is configured to receive a power supply voltage Vdd 205, which in some embodiments is a boosted voltage provided by a charge pump. The drain terminal of MP1 is coupled to node B, and the drain terminal of MN1 is also coupled to node B. The source terminal of MN1 is coupled to a regulated output voltage node Vreg 195. The gate terminals of MP1 and MN1 are coupled together and coupled to node A, and the gate terminal of M 145 is also coupled to node A. The voltage at node A is the gate voltage Vg 250 for M 145. The voltage Vinv 260 at node B is provided to the input of the second inverter 240, and the output of inverter 240 is provided to the gate terminal of MP4.

[0025] The source terminal of MP3 is configured to receive a power supply voltage Vdd 205, and the drain terminal of MP3 is coupled to the source terminal of MP2. The gate terminal of MP3 is configured to receive a power supply voltage Vdd 205. Figure 1BThe digital loop filter 160 shown receives control signal CTL165. The drain terminal of MP2 is coupled to node A, and the gate terminal of MP2 is configured to receive a low bias voltage Vbias_low210, keeping MP2 on. The drain terminal of MN2 is coupled to node A, and the source terminal of MN2 is coupled to the drain terminal of MN3. The gate terminal of MN2 is configured to receive a high bias voltage Vbias_high215, keeping MN2 on. The drain terminal of MN3 is coupled to Vreg195, and the gate terminal of MN3 is configured to receive control signal CTL165.

[0026] The source terminal of MP4 is coupled between the drain terminal of MP3 and the source terminal of MP2, and the drain terminal of MP4 is coupled to the source terminal of MP5. The drain terminal of MP5 is coupled to node A, and the gate terminal of MP5 is configured to receive a low bias voltage Vbias_low 210. The control signal CTL 165 indicates whether the transmission gate switch M 145 should be turned on or off. In some examples, the control signal CTL 165 is active low for the transmission gate switch M 145. In response to CTL 165 indicating that switch M 145 should be turned on, MN3 is turned off and acts as an open switch, thereby disconnecting the connection from Vreg 195 via MN2 to the gate terminals of node A and M145. MP3 is turned on and acts as a closed switch, thereby connecting the gate terminals of node A and M145 to Vdd 205 via MP2.

[0027] In response to CTL 165 indicating that switch M 145 should be turned off, MN3 is turned on and acts as a closed switch, thereby coupling the gate terminals of nodes A and M 145 to Vreg 195 via MN2. MP3 is turned off and acts as an open switch, thereby disconnecting the connection from Vdd 205 to the gate terminals of nodes A and M 145 via MP2. The high-resistance paths of MN2 and MN3 ensure a slow decrease in the voltage of Vg 250, preventing strong transients in the Ipass270. Transistors MP2 and MN2 have a width-to-length ratio of less than 1 and act as resistors, thereby reducing the slew rate. Additionally, MP2 and MN2 remain on, thereby reducing charge injection at node A.

[0028] MN1 acts as a detector for the transmission gate transistor M145. When M145 is on but not significantly conducting (i.e., Vg250 is less than the threshold voltage of M145), the voltage Vinv260 at node B is logic high, causing the output of inverter 240 to be logic low. MP4 is on and acts as a closed switch, allowing current to flow through the low-resistance paths of MP3, MP4, and MP5 to increase Vg250 at node A. As MN1 and M145 become significantly conducting (i.e., Vg250 is greater than the threshold voltage of M145), the voltage Vinv260 at node B is logic low, causing the output of inverter 240 to be logic high. MP4 is off and acts as an open switch, allowing current to flow through the high-resistance paths of MP3 and MP2 to increase Vg250 at node A.

[0029] The low-resistance paths via MP3, MP4, and MP5 allow Vg 250 to rapidly increase to the threshold voltage of M 145 and reduce the "dead time" before the transmission gate switch M 145 is turned on. Once Vg 250 reaches the threshold voltage of M 145, the high-resistance paths via MP3 and MP2 ensure a slow ramp in Vg 250, thus preventing strong transients in the current Ipass 270 passing through switch M 145. Figure 3 It shows Figure 2 The waveform 300 of the signals in the transmission gate driver 200 shown includes the control signal CTL 165, the gate voltage Vg 250 at node A, the voltage Vinv 260 at node B, and the current Ipass 270 passing through the transmission gate switch M145.

[0030] The control signal CTL 165 transitions from logic high to logic low at time t0, indicating that the transmission gate transistor M 145 is to be turned on. Between time t0 and time t1, the gate voltage Vg 250 is charged from ground to the threshold voltage of transistor M 145 through low-resistance paths MP3, MP4, and MP5. For most of the period between t0 and t1, voltage Vinv 260 is logic high until it decreases to logic low at time t1 as Vg 250 approaches the threshold voltage, thus switching the transmission gate driver 200 from the low-resistance path to the high-resistance paths MP3 and MP2. After time t1, Vg 250 increases slowly to prevent strong transients in the current Ipass 270 flowing through the transmission gate transistor M 145. The current Ipass 270 increases slowly throughout t0, t1, and thereafter, indicating a fast but gentle turn-on of transistor M 145.

[0031] Figure 4 An example transmission gate driver 400 with slew rate control and reduced cross current is shown. The example transmission gate driver 400 is similar to... Figure 2 The transmission gate driver 200 is shown, but also includes an inverter 410 and transistors MP6 and MN4. In this example, transistor MP6 is a PMOS and transistor MN4 is an NMOS. In other examples, MP6 is an NMOS or a BJT, and / or MN4 is a PMOS or a BJT. The source terminal of MP6 is configured to receive a supply voltage Vdd 205, which is a boost voltage from a charge pump. The drain terminal of MP6 is coupled to the source terminal of MP1 in inverter 230. The drain terminal of MN4 is coupled to the source terminal of MN1, and the source terminal of MN4 is coupled to Vreg 195.

[0032] Inverter 410 receives control signal CTL 165 and inverts the control signal. The 420 output is sent to the gate terminals of MP6 and MN4. When CTL 165 indicates that transistor M145 is to be turned on, the control signal... 420 causes MN4 to be turned on and acts as a closed switch between transistor MN1 and Vreg 195, and causes MP6 to be turned off and acts as an open switch between power supply voltage node Vdd 205 and the source terminal of MP6. Figure 3 During the rapid transition between time t0 and t1, as described in the diagram, transistors MP6 and MN4 dominate the behavior of inverter 230, and during the slow transition after time t1, transistors MP1 and MN1 dominate the behavior of inverter 230. After the transition, either MN4 or MP6 is immediately turned on, and node A has not yet been charged to Vdd 205 or discharged to Vreg 195.

[0033] When CTL 165 transitions from logic high to logic low, MN4 turns on, and MN1 is not yet on. MP1 remains on, and MP6 immediately turns off to prevent current from the supply voltage rail Vdd 205. Node A is rapidly charged, primarily through the low-resistance path containing MP3, MP4, and MP5, and partially through the high-resistance path containing MP3 and MP2, until MN1 turns on. During this transition, node B is not directly driven and remains at approximately the supply voltage Vdd 205 due to parasitic capacitance. As MN1 begins to turn on, node B discharges, thereby turning off MP4 via inverter 240. The high-resistance path containing MP3 and MP2 continues to charge node A. This also turns off MP1.

[0034] When CTL 165 transitions from logic low to logic high, MP6 turns on and MN4 turns off. MP1 and MP3 turn off, and MN1 and MN3 turn on. During this transition, node B is not directly driven and remains at a voltage approximately equal to Vreg195 due to parasitic capacitance. Node A discharges through MN2 and MN3. As MP1 becomes on, node B is charged via MP1 and MP6 and turns on MP4, which has little effect because MP3 is off at the start of the transition. Transistors MP6 and MN4 reduce the cross current through inverter 230, thereby reducing the total current drawn from the charge pump to provide the boost supply voltage Vdd 205.

[0035] In this specification, the term "coupling" may encompass a connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B via a direct connection; or (b) in a second example, if the intermediary component C does not alter the functional relationship between device A and device B, then device A is coupled to device B via the intermediary component C such that a control signal generated by device A via device A controls device B.

[0036] A device “configured” to perform a task or function may be configured by the manufacturer at manufacturing time (e.g., programmed and / or hardwired) to perform that function, and / or may be configured (or reconfigured) by the user after manufacturing to perform that function and / or other additional or alternative functions. This configuration may be through firmware and / or software programming of the device, through the construction and / or layout of the device’s hardware components and interconnects, or a combination thereof.

[0037] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless otherwise stated to the contrary, these terms are generally used to mean an interconnect or endpoint between device elements, circuit elements, integrated circuits, devices, or other electronic components or semiconductor parts.

[0038] The circuits or devices described herein that include certain components can alternatively be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage sources and / or current sources) can alternatively include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and can be adapted to be coupled to at least some of the passive elements and / or sources during or after manufacturing, for example by an end user and / or a third party, to form the described structure.

[0039] While this article describes the use of specific transistors, other transistors (or equivalent devices) can be used alternatively. For example, a p-type metal-oxide-semiconductor field-effect transistor (“MOSFET”) can be used instead of an n-type MOSFET with little or no change to the circuit. Furthermore, other types of transistors (such as bipolar junction transistors (BJTs)) can be used.

[0040] The circuits described herein can be reconfigured to include additional or different components to provide at least partially similar functionality to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component can be replaced, respectively, with multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component can be replaced, respectively, with multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0041] The phrase “grounding” as used in the foregoing description includes chassis grounding, earth grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of grounding connection applicable to or suited to the teachings of this specification. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a numerical value means + / - 10% of that value. Within the scope of the claims, modifications to the examples described are possible, and other examples are also possible.

[0042] Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are also possible.

Claims

1. A driver circuit comprising: The first transistor has a first control terminal coupled to an input node, a first current terminal coupled to a power supply voltage rail, and a second current terminal. The second transistor has a second control terminal configured to receive a first bias voltage, a third current terminal coupled to the second current terminal, and a fourth current terminal coupled to the first output node. The third transistor has a third control terminal configured to receive a second bias voltage, a fifth current terminal coupled to the first output node, and a sixth current terminal. The fourth transistor has a fourth control terminal coupled to the input node, a seventh current terminal coupled to the sixth current terminal, and an eighth current terminal coupled to the second output node. The fifth transistor has a fifth control terminal, a ninth current terminal coupled to the second current terminal and the third current terminal, and a tenth current terminal; The sixth transistor has a sixth control terminal configured to receive the first bias voltage, an eleventh current terminal coupled to the tenth current terminal, and a twelfth current terminal coupled to the first output node. The first inverter includes: The seventh transistor has a seventh control terminal coupled to the first output node, a thirteenth current terminal coupled to the power supply voltage rail, and a fourteenth current terminal. An eighth transistor having an eighth control terminal coupled to the first output node, a fifteenth current terminal coupled to the fourteenth current terminal, and a sixteenth current terminal coupled to the second output node; and The second inverter has an input coupled to the fourteenth and fifteenth current terminals and an output coupled to the fifth control terminal. The first transistor, the fifth transistor, and the sixth transistor include a low-resistance charging path from the power supply voltage rail to the first output node, and the first transistor and the second transistor include a high-resistance charging path from the power supply voltage rail to the first output node.

2. The driver circuit of claim 1, wherein the first output node is configured to be coupled to the control terminal of the transmission gate transistor, and wherein the characteristics of the eighth transistor are matched with the characteristics of the transmission gate transistor.

3. The driver circuit according to claim 1, wherein the width-to-length ratio of the second transistor is less than 1, and wherein the width-to-length ratio of the third transistor is less than 1.

4. The driver circuit according to claim 1, wherein the first transistor, the second transistor, the fifth transistor, the sixth transistor and the seventh transistor comprise p-type metal-oxide-semiconductor field-effect transistors, i.e., p-type MOSFETs, and wherein the third transistor, the fourth transistor and the eighth transistor comprise n-type MOSFETs.

5. The driver circuit of claim 4, wherein the first bias voltage is configured to keep the second transistor and the sixth transistor on.

6. The driver circuit of claim 4, wherein the second bias voltage is configured to keep the third transistor on.

7. The driver circuit according to claim 1, further comprising: A third inverter has an input coupled to the input node and an output; A ninth transistor, which is coupled between the power supply voltage rail and the thirteenth current terminal and has a ninth control terminal coupled to the output of the third inverter; as well as The tenth transistor is coupled between the sixteenth current terminal and the second output node and has a tenth control terminal coupled to the output of the third inverter.

8. A circuit comprising: A first transistor, which is coupled to a power supply voltage rail and has a first control terminal coupled to an input node; A second transistor is coupled between the first transistor and the first output node, and the second transistor has a second control terminal configured to receive a first bias voltage. A third transistor is coupled to the first output node and has a third control terminal configured to receive a second bias voltage. A fourth transistor, coupled between the third transistor and the second output node, the fourth transistor having a fourth control terminal coupled to the input node; A fifth transistor, which is coupled to the first transistor and the second transistor and has a fifth control terminal; A sixth transistor, coupled between the fifth transistor and the first output node, the sixth transistor having a sixth control terminal configured to receive the first bias voltage; The first inverter includes: A seventh transistor, which is coupled to the power supply voltage rail and has a seventh control terminal coupled to the first output node; An eighth transistor, coupled between the seventh transistor and the second output node, the eighth transistor having an eighth control terminal coupled to the first output node; and The second inverter is coupled to the seventh transistor and the eighth transistor and to the fifth control terminal. The first transistor, the fifth transistor, and the sixth transistor include a low-resistance charging path from the power supply voltage rail to the first output node, and the first transistor and the second transistor include a high-resistance charging path from the power supply voltage rail to the first output node.

9. The circuit of claim 8, wherein the first output node is configured to be coupled to the control terminal of the transmission gate transistor, and wherein the characteristics of the eighth transistor are matched with the characteristics of the transmission gate transistor.

10. The circuit according to claim 9, further comprising: The transmission gate transistor is coupled between the input voltage and the second output node; A capacitor is coupled between the second output node and the ground node; An analog-to-digital converter, or ADC, has an input coupled to the second output node and an output; as well as A digital filter circuit having an input coupled to the output of the ADC and an output coupled to the input node.

11. The circuit of claim 8, wherein the width-to-length ratio of the second transistor is less than 1, and wherein the width-to-length ratio of the third transistor is less than 1.

12. The circuit of claim 8, wherein the first transistor, the second transistor, the fifth transistor, the sixth transistor, and the seventh transistor comprise p-type metal-oxide-semiconductor field-effect transistors, i.e., p-type MOSFETs, and wherein the third transistor, the fourth transistor, and the eighth transistor comprise n-type MOSFETs.

13. The circuit of claim 12, wherein the first bias voltage is configured to keep the second transistor and the sixth transistor on, and wherein the second bias voltage is configured to keep the third transistor on.

14. The circuit according to claim 8, further comprising: A third inverter has an input coupled to the input node and an output; A ninth transistor, coupled between the power supply voltage rail and the seventh transistor, the ninth transistor having a ninth control terminal coupled to the output of the third inverter; as well as A tenth transistor, coupled between the eighth transistor and the second output node, the tenth transistor having a tenth control terminal coupled to the output of the third inverter.

15. A driver comprising: A low-resistance charging path between the power supply voltage rail and the first output node; The high-resistance charging path between the power supply voltage rail and the first output node; An inverter coupled to the first output node and configured to enable the low-resistance charging path when the voltage on the first output node is lower than a first voltage and to disable the low-resistance charging path to enable the high-resistance charging path when the voltage on the first output node is higher than the first voltage. as well as A high-resistance discharge path between the first output node and the second output node.

16. The driver according to claim 15, wherein: The first output node is configured to be coupled to the control terminal of a transmission gate transistor, wherein the first voltage is the threshold voltage of the transmission gate transistor; The low-resistance charging path charges the voltage at the first output node to the threshold voltage of the transmission gate transistor; The high-resistance charging path charges the voltage at the first output node to a level greater than the threshold voltage; and The high-resistance discharge path discharges the voltage on the first output node.

17. The driver of claim 16, wherein the high-resistance discharge path comprises: The first transistor has a first control terminal configured to receive a bias voltage, a first current terminal coupled to the first output node, and a second current terminal. as well as The second transistor has a second control terminal configured to receive a control signal, a third current terminal coupled to the second current terminal, and a fourth current terminal coupled to the second output node.

18. The driver of claim 17, wherein the aspect ratio of the first transistor is less than 1.

19. The driver of claim 16, wherein the inverter comprises: The first transistor has a first control terminal coupled to the first output node, a first current terminal coupled to the power supply voltage rail, and a second current terminal. as well as The second transistor has a second control terminal coupled to the first output node, a third current terminal coupled to the second current terminal, and a fourth current terminal coupled to the second output node.

20. The driver of claim 19, wherein the first output node is configured to be coupled to a control terminal of a transmission gate transistor, and wherein the characteristics of the second transistor are matched with the characteristics of the transmission gate transistor.

21. The driver of claim 16, wherein the low-resistance charging path comprises: The first transistor has a first control terminal configured to receive a control signal, a first current terminal coupled to the power supply voltage rail, and a second current terminal. The second transistor has a second control terminal, a third current terminal coupled to the second current terminal, and a fourth current terminal; as well as The third transistor has a third control terminal configured to receive a bias voltage, a fifth current terminal coupled to the fourth current terminal, and a sixth current terminal coupled to the first output node. The inverter mentioned above is the first inverter; and The driver further includes a second inverter having an input coupled to the output of the first inverter and an output coupled to the second control terminal.

22. The driver of claim 21, wherein the high-resistance charging path comprises: The first transistor; as well as The fourth transistor has a fourth control terminal configured to receive the bias voltage, a seventh current terminal coupled to the second current terminal, and an eighth current terminal coupled to the first output node.

23. The driver of claim 22, wherein the aspect ratio of the fourth transistor is less than 1.

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