Implementation method of low power mode of processor core

Abstract

This invention discloses a method for implementing a low-power mode for a processor core, comprising the following steps: S1, the processor core receives a signal to switch power modes; S2, the processor clears all instructions in the processor core's pipeline; S3, the processor core selects the low-power state to switch to by configuring registers in the processor core; S4, the processor resumes operation in its default state. The novel low-power mode proposed in this invention reduces the maximum number of instructions that can coexist in the pipeline by disabling some physical registers and renaming the mapping table, and further reduces power consumption by disabling some issue queues, thereby reducing processor power consumption without significantly degrading processor performance.

Description

Technical Field

[0001] This invention belongs to the field of computer data processing technology and relates to a method for implementing a low-power mode for a processor core. Background Technology

[0002] For embedded processors, power consumption is a key performance indicator. Most embedded processors on the market today need to support multiple power consumption modes to cope with different application scenarios, and implement different power and performance limits for different scenarios, so as to achieve the longest possible battery life.

[0003] Currently, processor cores have two low-power modes: 1. Primarily by reducing the processor core's main clock frequency through clock configuration, thereby reducing the frequency of register flips within the processor core per unit time and decreasing the processor core's dynamic power consumption. 2. By disabling certain logic blocks to reduce the processor's static power consumption.

[0004] Existing technologies have at least the following drawbacks: Traditional low-power mode 1 for processors directly reduces the processor core's clock speed, which in turn reduces the number of instructions processed per unit time. The rate of decrease in the number of instructions processed per unit time is directly proportional to the rate of decrease in the processor's clock speed. While this reduces power consumption significantly, it severely impacts processor performance. For low-power mode 2, disabling logic blocks is not applicable to all modules within the processor core. Most approaches involve disabling the massively parallel multipliers within the processor core and replacing them with lower-power multi-cycle multipliers. This has no effect on other components within the processor core, thus limiting the power reduction. Summary of the Invention

[0005] To address the above problems, the technical solution of this invention is a method for implementing a low-power mode for a processor core, comprising the following steps:

[0006] S1, the processor core receives a signal to switch power consumption modes;

[0007] S2, the processor clears all instructions in the processor core pipeline;

[0008] S3 selects the low-power state to switch by configuring the registers in the processor core;

[0009] S4 restores the processor to its default operating state.

[0010] Preferably, the signal to enter low-power mode received in S1 includes: a signal to switch power mode via a custom instruction and a signal to switch power mode via an external interrupt.

[0011] Preferably, step S2 specifically includes the following steps:

[0012] S21: After receiving a signal to switch power consumption modes, the processor stops fetching instructions to ensure that no more instructions continue to enter the pipeline.

[0013] S22, the processor continues processing instructions that have entered the pipeline;

[0014] S23, receive a signal that the reordering buffer is empty.

[0015] Preferably, in step S22, power consumption switching is performed using a custom instruction. This requires waiting for the instruction to become the earliest instruction to enter the reordering buffer, clearing all instructions newer than this instruction in the reordering buffer, and then issuing a signal that the reordering buffer is empty.

[0016] Preferably, if the power consumption is switched via an interrupt in S22, no further processing is required; the process can simply wait for all instructions in the pipeline to be processed and the reordering buffer to be empty.

[0017] Preferably, step S3 specifically includes the following steps:

[0018] S31, Modify the renaming module logic to limit the maximum number of renamings;

[0019] S32, shut down some of the transmission queues and the corresponding processing modules.

[0020] Preferably, step S31 specifically involves, according to the mode to be switched, changing the maximum number of instructions allowed to be renamed by modifying the processor core registers, changing the size of the physical registers in the reordering buffer, closing some physical registers according to the specific mode to be switched, and modifying the judgment logic in the renaming module for determining whether the reordering buffer is empty or full.

[0021] Preferably, step S31 specifically includes the following steps:

[0022] S311, after instruction decoding, enters the renaming module;

[0023] S312, the renaming module queries the number of target registers that have been used in the renaming module;

[0024] If the processor is in a power consumption mode within the preset range, proceed to S313 to determine whether the number of target registers used is less than N; if yes, proceed to S315; otherwise, proceed to S316.

[0025] If the processor is in low-power mode, proceed to S314 to determine if the number of used target registers is less than M; if yes, proceed to S315; otherwise, proceed to S316.

[0026] S315 sends the renamed command to the launch queue;

[0027] S316, Stop renaming all modules previously renamed;

[0028] Where N is the number of physical registers of the processor core, and M is the number of physical registers remaining after some physical registers are disabled in low-power mode. M is greater than 1 and less than N.

[0029] Preferably, step S32 specifically involves closing some duplicate transmission queues and their corresponding processing modules according to the specific mode to be switched, and disabling the data forwarding between the closed transmission queues.

[0030] Preferably, in step S4, if the interrupt signal is received as the power consumption mode switching signal in step S1, then the interrupt signal needs to be pulled low to indicate the end of the switching.

[0031] This invention presents a novel design approach for a low-power mode for processor cores. Currently, most processor cores on the market support low-power modes, typically implemented using two methods: one reduces dynamic power consumption by lowering the processor core frequency, and the other reduces static power consumption by disabling certain logic circuits. This invention proposes a novel low-power mode implementation for superscalar processor cores, specifically tailored to their microarchitectural characteristics. By using a custom instruction set or external interrupts to control the processor core, some physical registers are disabled, the number of rename instructions is reduced, and some issue queues and pipelines are shut down, thereby decreasing the number of instructions in the processor core. This achieves a reduction in processor core power consumption without lowering the core frequency, thus minimizing performance degradation while reducing overall power consumption.

[0032] It also includes at least the following advantages:

[0033] 1) Compared with traditional frequency reduction methods, the performance degradation of the processor core is not significant.

[0034] 2) Multiple modes can be configured to limit the maximum number of renames to different values, allowing for flexible control of power consumption and performance.

[0035] 3) The implementation is flexible and will not put too much burden on the processor design. It can be implemented in the form of a state machine.

[0036] 4) Diverse triggering methods. Attached Figure Description

[0037] Figure 1 This is a flowchart illustrating the steps of a method for implementing a processor core low-power mode according to an embodiment of the present invention.

[0038] Figure 2 This is a flowchart illustrating the specific steps of step S31 of the method for implementing the low-power mode of the processor core in an embodiment of the present invention. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0040] Conversely, this invention encompasses any substitutions, modifications, equivalent methods, and solutions made within the spirit and scope of the invention as defined in the claims. Furthermore, to provide a better understanding of the invention, certain specific details are described in detail below. However, those skilled in the art will fully understand the invention even without these detailed descriptions.

[0041] Superscalar processors typically have several times more physical registers than the number of logical registers specified in the standard instruction set. When processing instructions, they work in conjunction with modules such as register renaming and cache reordering to break the order between instructions. In the instructions that enter the processor sequentially, they seek the maximum degree of parallelism without affecting the instruction result, thereby improving the processor's processing efficiency.

[0042] The general processing flow of a superscalar processor includes: after the instruction enters the processor through the instruction fetch module, it undergoes decoding, renaming, issuing, processing, reordering, and committing. During the decoding phase, the instruction obtains two source operands or a source register and a destination register. In the renaming phase, an available physical register is selected as the new destination register of the instruction using the names of available physical registers provided by the reordering buffer module. The renaming mapping table is then consulted to find the renamed name of the source register to ensure its correct value. Finally, the renamed source register name and destination register name are recorded and sent to the issue module.

[0043] In the sending module, each instruction is sent to the processing module when the source operands are ready. After the processing module obtains the operation result, it enters the reordering buffer module and waits for submission.

[0044] The design philosophy of superscalar processors is to find instructions with independent data dependencies within a sequential instruction sequence and execute them in parallel, allowing multiple instructions to be executed simultaneously in each cycle. After renaming, instructions can enter a issue queue to wait. Instructions waiting in the issue queue can only enter the processing module for computation after their data is ready. After computation, they are placed in a reordering buffer and submitted in their original order. Therefore, the principle of this invention is to flexibly adjust the range of instructions with no data dependencies that the processor core searches for by limiting the maximum number of instruction renamings, thereby reducing the number of instructions processed by the processor core per unit time and decreasing the processor's dynamic power consumption. Unlike traditional low-power modes, reducing the maximum allowed number of renamed instructions by a factor does not lead to a factor that reduces processor performance, thus ensuring processor performance in low-power mode.

[0045] The novel low-power mode proposed in this invention reduces the maximum number of instructions that can coexist in the pipeline by disabling some physical registers and renaming the mapping table, and can further reduce power consumption by disabling some issue queues. This allows for a reduction in processor power consumption without a significant decrease in processor performance.

[0046] See Figure 1 The technical solution of this invention, as an embodiment of the invention, is a flowchart of a method for implementing a low-power mode for a processor core, comprising the following steps:

[0047] S1, the processor core receives a signal to switch power consumption modes;

[0048] S2, the processor clears all instructions in the processor core pipeline;

[0049] S3 selects the low-power state to switch by configuring the registers in the processor core;

[0050] S4 restores the processor to its default operating state.

[0051] The signals received in S1 to enter low-power mode include: signals to switch power modes via custom instructions and signals to switch power modes via external interrupts.

[0052] S2 specifically includes the following steps:

[0053] S21: After receiving a signal to switch power consumption modes, the processor stops fetching instructions to ensure that no more instructions continue to enter the pipeline.

[0054] S22, the processor continues processing instructions that have entered the pipeline;

[0055] S23, receive a signal that the reordering buffer is empty.

[0056] In S22, power switching is performed through a custom instruction. It needs to wait for this instruction to become the earliest instruction to enter the reordering buffer, and clear all instructions newer than this instruction in the reordering buffer. After completion, a signal indicating that the reordering buffer is empty is issued.

[0057] In S22, power consumption is switched via interrupts, so no further processing is needed. Just wait for all instructions in the pipeline to finish processing and for the reordering buffer to be empty.

[0058] S3 specifically includes the following steps:

[0059] S31, Modify the renaming module logic to limit the maximum number of renamings;

[0060] S32, shut down some of the transmission queues and the corresponding processing modules.

[0061] Specifically, S31 modifies the maximum number of instructions that the renaming module is allowed to rename by changing the processor core registers according to the mode to be switched. At the same time, it changes the size of the physical registers in the reordering buffer. Depending on the specific mode to be switched, it disables some physical registers and modifies the logic in the renaming module for judging whether the reordering buffer is empty or full.

[0062] See Figure 2 S31 specifically includes the following steps:

[0063] S311, after instruction decoding, enters the renaming module;

[0064] S312, the renaming module queries the number of target registers that have been used in the renaming module;

[0065] If the processor is in a power consumption mode within the preset range, proceed to S313 to determine whether the number of target registers used is less than N; if yes, proceed to S315; otherwise, proceed to S316.

[0066] If the processor is in low-power mode, proceed to S314 to determine if the number of used target registers is less than M; if yes, proceed to S315; otherwise, proceed to S316.

[0067] S315 sends the renamed command to the launch queue;

[0068] S316, stop renaming all modules before, and wait for the previous condition to be met, that is, the number of target registers used is less than M;

[0069] Where N is the number of physical registers in the processor core, and M is the number of physical registers remaining after some physical registers are disabled in low-power mode. M is greater than 1 and less than N, and is usually an integer power of 2. Multiple low-power modes can be configured, each with a different M.

[0070] Specifically, S32 shuts down some duplicate transmission queues and their corresponding processing modules according to the specific mode to be switched, and disables the data forwarding between the closed transmission queues.

[0071] If, in step S1, the interrupt signal is received as the power consumption mode switching signal, then the interrupt signal needs to be pulled low to indicate that the switching is over.

[0072] This invention provides a low-power mode that conforms to the microarchitecture design of superscalar processors. It achieves processor power consumption control through non-frequency reduction and also controls power consumption by reducing the number of instructions entering the pipeline simultaneously by changing the maximum number of renaming instructions.

[0073] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for implementing a low-power mode for a processor core, characterized in that, Includes the following steps: S1, the processor core receives a signal to switch power consumption modes; S2, the processor clears all instructions in the processor core pipeline; S3 selects the low-power state to switch by configuring the registers in the processor core; S4 restores the processor to its default operating state; The signals received in S1 to enter low-power mode include: signals to switch power mode via a custom instruction and signals to switch power mode via an external interrupt; S2 specifically includes the following steps: S21: After receiving a signal to switch power consumption modes, the processor stops fetching instructions to ensure that no more instructions continue to enter the pipeline. S22, the processor continues processing instructions that have entered the pipeline; S23, receive the signal that the reordering buffer is empty; In S22, power consumption switching is performed through a custom instruction. It is necessary to wait for this instruction to become the earliest instruction to enter the reordering buffer, and clear all instructions newer than this instruction in the reordering buffer. After completion, a signal that the reordering buffer is empty is issued. In S22, power consumption is switched via interrupt, so no further processing is needed. Just wait for all instructions in the pipeline to be processed and the reordering buffer to be empty. S3 specifically includes the following steps: S31, Modify the renaming module logic to limit the maximum number of renamings; S32, shut down some of the transmission queues and the corresponding processing modules; Specifically, S31 involves modifying the processor core registers to change the maximum number of instructions allowed to be renamed by the renaming module, according to the mode to be switched, while also changing the size of the physical registers in the reordering buffer. Depending on the specific mode to be switched, some physical registers are disabled, and the logic for judging whether the reordering buffer is empty or full in the renaming module is modified. S31 specifically includes the following steps: S311, after instruction decoding, enters the renaming module; S312, the renaming module queries the number of target registers that have been used in the renaming module; If the processor is in a power consumption mode within the preset range, proceed to S313 to determine whether the number of target registers used is less than N; if yes, proceed to S315; otherwise, proceed to S316. If the processor is in low-power mode, proceed to S314 to determine if the number of used target registers is less than M; if yes, proceed to S315; otherwise, proceed to S316. S315 sends the renamed command to the launch queue; S316, Stop renaming all modules before; Where N is the number of physical registers of the processor core, and M is the number of physical registers remaining after some physical registers are disabled in low-power mode. M is greater than 1 and less than N.

2. The method for implementing the processor core low-power mode according to claim 1, characterized in that, Specifically, S32 involves closing some duplicate transmission queues and their corresponding processing modules according to the specific mode to be switched, and disabling the data forwarding between the closed transmission queues.

3. The method for implementing the processor core low-power mode according to claim 1, characterized in that, If, in step S1, the interrupt signal is received as the power consumption mode switching signal, then in step S4, the interrupt signal needs to be pulled low to indicate that the switching is over.

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