一种RiscV MCU的编译方法及装置

By compiling the soft-core IP and software code of the RiscV MCU in an integrated or independent manner, a bitstream file containing the soft-core IP and software code is generated, which solves the problem of cumbersome management and operation in the existing technology and achieves the effect of simplifying management and operation.

CN116339740BActive Publication Date: 2026-07-17SHANDONG GOWIN SEMICON TECH CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
SHANDONG GOWIN SEMICON TECH CO LTD
Filing Date
2023-01-13
Publication Date
2026-07-17

AI Technical Summary

Technical Problem

In existing technologies, the soft core IP and software code compilation files of RiscV MCUs are separate, which leads to cumbersome management and operation.

Method used

This paper provides a compilation method for RiscV MCUs, which generates a bitstream file containing soft core IP and software code through integrated compilation or separate compilation and merging, simplifying management.

Benefits of technology

The generated bitstream file is easy to manage and simple to operate, reducing the tedious steps of downloading and running.

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Abstract

一种RiscV MCU的编译方法及装置，包括：获取RiscV MCU的软核IP以及RiscV MCU的软件代码；其中，所述RiscV MCU的软核IP基于FPGA实现；对所述RiscV MCU的软核IP和所述RiscV MCU的软件代码进行一体化编译，得到包含RiscV MCU的软核IP和RiscV MCU的软件代码的比特流文件，或者，对所述RiscV MCU的软核IP和所述RiscV MCU的软件代码分别编译再进行合并，得到包含RiscV MCU的软核IP和RiscV MCU软件代码的比特流文件。本公开实施例能够产生同时包含MCU软核IP的和MCU软件代码的编译文件，从而方便后续管理。
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