A multi-processor bus communication system and method and satellite on-board computer

Abstract

This invention discloses a multiprocessor bus communication system and method, as well as a satellite-borne computer. The communication system includes several processors and an FPGA module. The FPGA module includes a bus arbitration module, a dual-machine FIFO module, a processor interface control module, and functional modules. Several processors are communicatively connected to the bus arbitration module. The dual-machine FIFO module is communicatively connected to the bus arbitration module and is used to store the operation data of the current processor and exchange the stored data with the next processor. The signal input terminal of the processor interface control module is communicatively connected to the bus arbitration module, and the signal output terminal of the processor interface control module is communicatively connected to several functional modules. The bus arbitration module monitors the status of any processor in real time and switches the bus of the current processor to the FPGA. The dual-machine FIFO module realizes the storage and exchange of operation data between different processors, fulfilling the communication needs of multiple processors and a single FPGA.

Description

Technical Field

[0001] This invention belongs to the field of communication and digital signal processing, and relates to a multiprocessor bus communication system and communication method, as well as a satellite-borne computer. Background Technology

[0002] Embedded computers are the core of aerospace electronic systems. To adapt to the harsh space operating environment, high reliability is one of the most important requirements. Therefore, aerospace embedded computers often employ a dual-machine redundant cold standby design to cope with the complex and harsh space radiation environment. As the complexity of aerospace electronic systems increases, aerospace embedded computers often use a processor-FPGA combined architecture to implement complex functions. However, in redundancy design, both the processor and the FPGA are redundant, which increases design cost and system power consumption, hindering product miniaturization. FPGAs themselves have radiation resistance measures; therefore, in redundancy design, the processor can be redundant, while the FPGA can be designed as a standalone, always-on system. This can reduce cost and power consumption while ensuring system reliability, which is beneficial for computer miniaturization. However, when two processors simultaneously perform read / write operations on a single FPGA, bus conflicts occur, leading to communication failures. To adapt to communication between a single FPGA and multiple processors, a multi-processor bus switching method and system based on FPGA is needed. Summary of the Invention

[0003] To address the problems existing in the prior art, this invention provides a multiprocessor bus communication system and method, as well as a satellite-borne computer, thereby effectively solving the technical problem of conflicts in multiprocessor access to a single FPGA.

[0004] This invention is achieved through the following technical solution:

[0005] A multiprocessor bus communication system includes several processors and an FPGA module;

[0006] The FPGA module includes a bus arbitration module, a dual-machine FIFO module, a processor interface control module, and functional modules.

[0007] The processors are communicatively connected to the bus arbitration module.

[0008] The dual-machine FIFO module is communicatively connected to the bus arbitration module. The dual-machine FIFO module is used to store the operation data of the current shift processor and exchange the stored data with the next shift processor.

[0009] The signal input terminal of the processor interface control module is communicatively connected to the bus arbitration module, and the signal output terminal of the processor interface control module is communicatively connected to several functional modules.

[0010] Preferably, the communication system includes several functional modules, and the signal input terminals of the several functional modules are all connected to the signal output terminal of the processor interface control module.

[0011] A satellite-borne computer includes the aforementioned FPGA-based multiprocessor bus communication system.

[0012] In the preferred embodiment of the communication method of the multiprocessor bus communication system described above, when the bus arbitration module detects that any processor is the on-duty processor, the bus arbitration module switches the bus of the on-duty processor to the processor interface control module, and the functional module receives the instructions of the on-duty processor; and before the detection result of the bus arbitration module changes, the functional module executes the program according to the current instructions.

[0013] Preferably, the FPGA module is in stand-alone, always-on mode.

[0014] Preferably, when the bus arbitration module detects that no processor is on duty, the current internal bus determines the current on-duty bus according to the previous arbitration result, and the functional module executes the program according to the previously set inertial procedure.

[0015] Preferably, during the arbitration process of the currently active processor, the bus arbitration module monitors the power-on status of any processor according to priority and dynamically switches the bus usage rights.

[0016] Preferably, the plurality of processors communicate with the bus arbitration module via a power-on status and status signal bus.

[0017] Preferably, when the dual-machine FIFO module detects that any processor is the current processor and that the current processor is starting for the first time, the current processor configures the FPGA according to the loading program, changes the status flag, and writes the operation data into the dual-machine FIFO module; when the dual-machine FIFO module detects that any current processor is not starting for the first time, the current processor reads the data in the dual-machine FIFO module, obtains the operation data of the previous processor, continues to configure the FPGA according to the program, and writes the operation data into the dual-machine FIFO.

[0018] Preferably, the bus arbitration module determines whether the processor on duty is accessing the dual-machine FIFO module or the functional module by using the offset address issued by the bus arbitration module accessed by any processor.

[0019] Compared with the prior art, the present invention has the following beneficial technical effects:

[0020] A multiprocessor bus communication system includes an FPGA module comprising a bus arbitration module and a dual-machine FIFO module. The bus arbitration module can monitor the status of any processor in real time and intelligently switch the bus of the current processor to the FPGA, thus fulfilling the communication needs of multiple processors with a single FPGA. In addition, the dual-machine FIFO module enables the storage and exchange of operation data between different current processors. The current processor can obtain the operation data of the previous current processor through the dual-machine FIFO module inside the FPGA, allowing the FPGA to automatically switch the processor bus without interrupting its function. This effectively avoids bus conflicts that occur when multiple processors access a single FPGA, and realizes the communication function between a single FPGA and multiple processors. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a structural block diagram of a multiprocessor bus communication system based on FPGA according to the present invention;

[0023] Figure 2 This is a flowchart of the bus arbitration process in this invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0025] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0026] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0027] In the description of the embodiments of the present invention, it should be noted that if terms such as "upper," "lower," "horizontal," or "inner" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, terms such as "first" and "second" are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0028] Furthermore, the use of the term "horizontal" does not imply that the component must be absolutely horizontal, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0029] In the description of the embodiments of the present invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific circumstances.

[0030] The present invention will now be described in further detail with reference to the accompanying drawings:

[0031] like Figure 1 As shown, an FPGA-based multiprocessor bus communication system includes several processors and an FPGA module. The FPGA module includes a bus arbitration module, a dual-machine FIFO module, a processor interface control module, and functional modules. Several processors are communicatively connected to the bus arbitration module. The dual-machine FIFO module is used to store the operation data of the current processor during its shift and to exchange the stored data with the next processor during its shift. The signal input terminal of the processor interface control module is communicatively connected to the bus arbitration module, and the signal output terminal of the processor interface control module is communicatively connected to several functional modules. There can be several functional modules, and the signal input terminals of all functional modules are connected to the signal output terminal of the processor interface control module.

[0032] The aforementioned FPGA-based multiprocessor bus communication system can be used for satellite onboard computers, fulfilling the design requirements of miniaturization and low cost for satellite onboard computers.

[0033] The processor boards containing the aforementioned processors feature a dual-machine cold standby redundancy design, while the I / O board housing the FPGA features a single-machine always-on design. The FPGA determines the currently active CPU by real-time monitoring the power-on status of the processors (CPUA, CPUB) on the two processor boards and switches the internal bus access to the active CPU. The active CPU can seamlessly take over control of the FPGA by storing and exchanging operation data through the dual-machine FIFO. CPUA and CPUB are the two processors in the dual-machine cold standby configuration, while the FPGA is a single-machine always-on design. CPUA and CPUB communicate with the FPGA through power-on status and bus signals. The FPGA's bus arbitration module monitors the status of CPUA and CPUB in real-time, determining the active CPU based on their status. The FPGA then uses the offset address accessed by the CPU to determine whether the active CPU is accessing the dual-machine FIFO or other FPGA functional modules.

[0034] The technical solution of this invention is that the FPGA monitors the status of each processor in real time, determines the processor currently on duty, and then automatically switches the FPGA's bus usage rights to the on-duty processor. After assuming its shift, the on-duty processor can obtain the operation data of the previous on-duty processor by reading the dual-machine FIFO module inside the FPGA, and can update the current operation data in the dual-machine FIFO in real time for use by the next on-duty processor. This allows the FPGA to maintain its own functionality during bus switching, realizing communication between a single FPGA and multiple processors.

[0035] like Figure 2 As shown, the FPGA bus arbitration module arbitrates the CPUA and CPUB buses. If the arbitration result indicates that neither CPUA nor CPUB is on duty, the current internal bus is determined to be the on-duty bus according to the previous arbitration result, and the FPGA functional module executes the program according to the previously set inertial procedure. If the arbitration result indicates that CPUA is the on-duty CPU, the FPGA switches the CPUA bus to the processor interface control module, and the FPGA functional module can receive instructions from the CPUA bus. If the arbitration result indicates that CPUB is the on-duty CPU, the FPGA switches the CPUB bus to the processor interface control module, and the FPGA functional module can receive instructions from the CPUB bus. Before the bus arbitration result changes, the FPGA functional module executes the program according to the previous instructions inertially. This control mode ensures that when the system experiences a fault in CPUA or CPUB and a bus switching operation is required, the FPGA function will not be interrupted but will continue to execute, cutting off the impact of upstream faults on downstream processes.

[0036] The arbitration method of the bus arbitration module is as follows: Figure 2 As shown:

[0037] 1) After the FPGA is powered on, proceed to step 2;

[0038] 2) The FPGA automatically monitors the power-on status of CPUA. If it is valid, proceed to step 3; otherwise, proceed to step 4.

[0039] 3) The FPGA determines that CPUA is the CPU on duty and proceeds to step 2;

[0040] 4) The FPGA automatically monitors the power-on status of CPUB. If it is valid, proceed to step 5; otherwise, proceed to step 2.

[0041] 5) The FPGA determines that CPUB is the CPU on duty and proceeds to step 2.

[0042] During bus arbitration, the FPGA continuously monitors the power-on status of CPUA and CPUB according to priority, dynamically switching bus usage rights. The FPGA's internal bus inertially executes the previous bus arbitration result until the arbitration result changes, at which point the FPGA switches internal bus usage rights according to the arbitration result.

[0043] The dual-machine FIFO module enables the storage and exchange of operation data for CPUA and CPUB during their first startup, based on whether CPUA and CPUB are in their first startup status.

[0044] After the FPGA powers on and resets, the status flag defaults to first startup. If the FPGA determines that CPUA is the active CPU and can take over the internal bus, CPUA can read the status flag to confirm this is the first startup. CPUA then configures the FPGA according to the loading program, changes the status flag, and writes the operation data into the dual-machine FIFO. Subsequently, if CPUA malfunctions, rendering its power-on status invalid while CPUB's power-on status is valid, and the FPGA determines that CPUB is the active CPU and can take over the internal bus, CPUB can read the status flag to confirm this is not the first startup. CPUB can then read the dual-machine FIFO data to obtain the operation data from CPUA during its shift, continue configuring the FPGA according to the program, and write the operation data into the dual-machine FIFO. In this operating mode, the subsequent active CPU can obtain the operation data from the previous active CPU through the dual-machine FIFO and record the current operation in the dual-machine FIFO, ensuring that CPUA and CPUB can automatically alternate control of the FPGA.

[0045] The processor interface control module parses the bus data for the current shift and sends the parsing commands to the functional modules, which then perform the corresponding functions.

[0046] The workflow of the bus switching system is as follows:

[0047] 1) After power-on, CPUA is powered on by default and the power-on status signal is valid, while CPUB is powered off by default and the power-on status signal is invalid. Proceed to step 2.

[0048] 2) After the FPGA detects that CPUA is the on-duty CPU, it switches the FPGA's internal bus usage rights to CPUA and proceeds to step 3.

[0049] 3) After CPUA reads the status flag, it configures the FPGA according to the loading program and writes the operation data into the dual-machine FIFO in real time. If CPUA fails during operation, it will proceed to step 4.

[0050] 4) CPUA is powered off, and the power-on signal is invalid; CPUB is powered on, and the power-on signal is valid. Proceed to step 5.

[0051] 5) After the FPGA detects that CPUB is the on-duty CPU, it switches the FPGA's internal bus usage right to CPUB and proceeds to step 6.

[0052] 6) After reading the status flag, CPUB reads the dual-machine FIFO, obtains the previous operation data, and continues to operate on the FPGA. It also writes the operation data into the dual-machine FIFO in real time. If CPUB fails during operation, it proceeds to step 7.

[0053] 7) CPUB is powered off, and the power-on signal is invalid; CPUA is powered on, and the power-on signal is valid. Proceed to step 8.

[0054] 8) After the FPGA detects that CPUA is the on-duty CPU, it switches the FPGA's internal bus usage right to CPUA and proceeds to step 9.

[0055] 9) After CPUA reads the status flag, it reads the dual-machine FIFO, obtains the previous operation data, and continues to operate on the FPGA. It writes the operation data into the dual-machine FIFO in real time. If CPUA fails during operation, it will proceed to step 4.

[0056] In the bus switching system, the FPGA monitors the status of each processor in real time, determines the processor currently in charge, and automatically switches the FPGA's bus usage rights to the current processor. The current processor can obtain the operation data of the previous processor through the FPGA's internal dual-machine FIFO, enabling the FPGA to automatically switch processor buses without interrupting its functions.

[0057] This invention can monitor the status of two processors in real time through a bus arbitration module, and intelligently switch the bus of the current processor to the FPGA to realize the communication needs of two processors and a single FPGA; through a dual-machine FIFO, the storage and exchange of operation data between different current processors can be realized.

[0058] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A multiprocessor bus communication system, characterized in that, Includes several processors and FPGA modules; The FPGA module includes a bus arbitration module, a dual-machine FIFO module, a processor interface control module, and functional modules. The processors are communicatively connected to the bus arbitration module. The dual-machine FIFO module is communicatively connected to the bus arbitration module. The dual-machine FIFO module is used to store the operation data of the current shift processor and exchange the stored data with the next shift processor. The signal input terminal of the processor interface control module is communicatively connected to the bus arbitration module, and the signal output terminal of the processor interface control module is communicatively connected to several functional modules. The bus arbitration module is configured to monitor the status of the plurality of processors in real time and determine the processor that should be on duty based on the status of the processors. If it is determined that the processor should be on duty at the moment, then the bus of the processor that should be on duty at the moment is switched to the processor interface control module. If none of the aforementioned processors are on duty, the current bus on duty will be determined according to the previous arbitration result, and the functional module will execute the program according to the previous instructions. The FPGA module is configured to access the offset address through the processor to determine whether the processor on duty is accessing the dual-machine FIFO module or other FPGA functional modules. The dual-machine FIFO module enables the storage and exchange of operation data between different on-duty processors. The on-duty processor obtains the operation data of the previous on-duty processor through the dual-machine FIFO module, so that the FPGA can automatically switch the processor bus without interrupting the function.

2. The multiprocessor bus communication system according to claim 1, characterized in that, The communication system includes several functional modules, and the signal input terminals of the several functional modules are all connected to the signal output terminal of the processor interface control module.

3. A satellite-borne computer, characterized in that, The system includes a multiprocessor bus communication system as described in any one of claims 1 to 2.

4. The communication method of the multiprocessor bus communication system according to any one of claims 1 to 2, characterized in that, When the bus arbitration module detects that any processor is the on-duty processor, the bus arbitration module switches the bus of the on-duty processor to the processor interface control module, and the functional module receives the instructions of the on-duty processor; and before the detection result of the bus arbitration module changes, the functional module executes the program according to the current instructions.

5. The communication method of a multiprocessor bus communication system according to claim 4, characterized in that, The FPGA module is in stand-alone, always-on mode.

6. The communication method of a multiprocessor bus communication system according to claim 4, characterized in that, When the bus arbitration module detects that no processor is on duty, the current internal bus determines the current bus on duty based on the previous arbitration result, and the functional module executes the program according to the previously set inertial procedure.

7. The communication method of a multiprocessor bus communication system according to claim 4, characterized in that, During the arbitration process of the currently active processor, the bus arbitration module monitors the power-on status of any processor according to priority and dynamically switches the bus usage rights.

8. The communication method of a multiprocessor bus communication system according to claim 4, characterized in that, The processors communicate with the bus arbitration module via a power-on status and status signal bus.

9. The communication method of a multiprocessor bus communication system according to claim 8, characterized in that, When the dual-machine FIFO module detects that any processor is the current processor and that this is the first time it has started, the current processor configures the FPGA according to the loading program, changes the status flag, and writes the operation data into the dual-machine FIFO module. When the dual-machine FIFO module detects that any current processor is not starting for the first time, the current processor reads the data in the dual-machine FIFO module, obtains the operation data of the previous processor, continues to configure the FPGA according to the program, and writes the operation data into the dual-machine FIFO.

10. The communication method of a multiprocessor bus communication system according to claim 4, characterized in that, The bus arbitration module determines whether the processor on duty is accessing the dual-machine FIFO module or a functional module by using the offset address issued by the bus arbitration module when accessed by any processor.

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