A method, system, storage medium and device for improving chip verification efficiency

Abstract

The application provides a method, system, storage medium and equipment for improving chip verification efficiency, the method comprising: for the implementation process of a chip in FPGA prototype verification, displaying and sequentially executing multiple stages of the implementation process through a man-machine interface; starting the execution of the current stage through a button of the interface, and synchronously running corresponding analysis instructions to analyze the execution of the current stage, and displaying the analysis result in a suggestion window of the interface; optimizing the current stage based on the analysis result, and continuing to execute the previous step through the button after optimization is completed until the final analysis result meets the verification requirement. The application can display the design problems and suggestions existing in the implementation process through an intuitive man-machine interface to the designer and the verifier, so that the designer rechecks, modifies and optimizes the design according to the suggestions and the exposed design problems, and the purpose of improving the timing convergence efficiency and performance target of the design is achieved.

Description

Technical Field

[0001] This invention relates to the field of chip verification technology, and in particular to a method, system, storage medium and device for improving chip verification efficiency. Background Technology

[0002] FPGA (Field Programmable Gate Array) prototyping is currently the mainstream and mature chip verification method. It verifies the functionality of ASICs by porting RTL (Register Transfer Level) circuitry to the FPGA. Driver development begins after the chip's basic functionality is verified and continues until the chip design is completed and delivered to the die. Once the chip is delivered, the application can be easily adapted to the FPGA version of the driver, allowing for seamless application onboarding to SoC (System on Chip) chips, thus perfectly controlling the SoC's time-to-market.

[0003] As ASIC designs become increasingly larger and more complex, single-chip FPGAs can no longer meet prototyping requirements, leading to the emergence of multi-chip FPGA verification. Synopsys and S2C are well-known and widely used manufacturers of high-performance, high-capacity FPGA-based prototyping platforms specifically designed for ASIC / SoC design. Before a chip is released, it undergoes a complex process involving repeated design input, functional simulation, modification and optimization, followed by design synthesis, design implementation, and placement and routing. Synopsys and S2C provide industry-standard manual or automated development workflows to address these processes. These workflows primarily achieve three stages, as follows:

[0004] In the first stage, the EDA (Electronic Design Automation) development kits from various prototype verification vendors complete the Partition and Synthesis of the project according to the developer's constraints. In the second stage, the generated netlist files are imported into the Vivado tool to complete the Implementation stage, which mainly involves placement, routing, generating downloadable files, and timing optimization. The final stage is to generate downloadable files and relevant adaptation files for the verification platform.

[0005] In the prototyping design flow, the second stage, Implementation, is completed using the Vivado tool. Implementation is also the most repetitive, tedious, and difficult part of the entire design flow. The choice of placement, routing, and timing optimization strategies in this stage directly affects the progress and quality of the prototyping design. In addition, if a design needs to be implemented in segments, the implementation work will be carried out simultaneously on multiple FPGA chips. In terms of workload and implementation difficulty, this part of the work is the most time-consuming. The automated implementation flow provided by prototyping vendors such as Synopsys and S2C has two major problems with the implementation strategies used: 1. The implementation strategies are rigid and inflexible, failing to select the optimal timing optimization strategy based on the actual timing of the design, making it difficult for the FPGA design to achieve the expected performance goals, thus affecting the progress of the entire verification work; 2. The scripts provided in the implementation flow are redundant and difficult to maintain, requiring a high level of knowledge from the verification personnel, thus affecting the efficiency of the verification work.

[0006] In summary, when using prototyping platforms provided by vendors such as Synopsys and S2C, the following issues need to be addressed: how to maximize the impact on the design in the early stages of development; how to identify design problems early, quickly, and accurately at the beginning of implementation; how to quickly acquire and select appropriate and accurate implementation strategies to achieve rapid timing convergence; how to present the current design status to designers and verifiers in a flexible, simple, and intuitive way; and how to use a general, guiding method to improve the efficiency of implementation in the prototyping verification process, enhance timing convergence efficiency, and optimize verification processes and methods. Summary of the Invention

[0007] In view of this, the purpose of this invention is to provide a method, system, storage medium and device for improving chip verification efficiency, so as to discover existing problems as early as possible in the chip design and development process and improve the FPGA prototype verification efficiency of the chip.

[0008] To achieve the above objectives, the present invention provides a method for improving chip verification efficiency, comprising the following steps:

[0009] For the chip implementation process in FPGA prototype verification, multiple stages of the implementation process are displayed and executed sequentially through a human-computer interaction interface.

[0010] The current stage can be started by clicking the button on the interface, and the corresponding analysis instructions will be run simultaneously to analyze the execution status of the current stage and display the analysis results in the suggestion window of the interface.

[0011] Based on the analysis results, the current stage is optimized, and after the optimization is completed, the previous step is continued by clicking the button until the final analysis results meet the verification requirements.

[0012] In some embodiments, the current stage is initiated via a button on the interface, and the corresponding analysis instructions are run synchronously to analyze the execution status of the current stage. The analysis results are then displayed in the suggestion window of the interface, including:

[0013] The initial inspection phase can be initiated via a button on the interface, and a quality assessment command can be run simultaneously to analyze the execution of the initial inspection phase.

[0014] Upon completion of the quality assessment command, the timing convergence value of the chip design and the items to be reviewed are displayed in the suggestion window. The timing convergence value is used to determine the degree of convergence of the chip design timing, and the items to be reviewed are those that have problems in the RTL design and synthesis stages.

[0015] In some embodiments, starting the execution of the current stage via a button on the interface and simultaneously running the corresponding analysis instructions to analyze the execution status of the current stage and displaying the analysis results in the suggestion window of the interface also includes:

[0016] The optimization design phase can be initiated by using the buttons on the interface, and failure query instructions, quality suggestion instructions, and timing summary instructions can be run simultaneously to analyze the execution of the optimization design phase.

[0017] In response to the completion of the failed query command, a resource usage table is displayed in the suggestion window. The resource usage table includes the recommended resource usage ratio, the actual resource usage ratio, and the review status.

[0018] In response to the completion of the quality recommendation command, a new optimization recommendation is displayed in the recommendation window. The new optimization recommendation is a cumulative information of the quality optimization recommendations in the previous stage and the current stage.

[0019] In response to the completion of the timing summary command, it checks whether the worst negative timing margin value in the suggestion window is negative. If it is negative, it displays the abnormal indicators in the optimization design phase in the suggestion window, and after analyzing the abnormal indicators through the database analysis module, it displays the corresponding optimization suggestions in the suggestion window.

[0020] In some embodiments, starting the execution of the current stage via a button on the interface and simultaneously running the corresponding analysis instructions to analyze the execution status of the current stage and displaying the analysis results in the suggestion window of the interface also includes:

[0021] The layout design phase can be initiated by using the buttons on the interface, and hardware usage instructions, design analysis instructions, quality suggestion instructions, and timing summary instructions can be run simultaneously to analyze the execution of the layout design phase.

[0022] In response to the completion of hardware usage instructions, the utilization rate of various resources inside the FPGA is displayed in the suggestion window;

[0023] In response to the completion of the design analysis instructions, the logic level and congestion level of the chip design are displayed in the suggestion window.

[0024] In some embodiments, starting the execution of the current stage via a button on the interface and simultaneously running the corresponding analysis instructions to analyze the execution status of the current stage and displaying the analysis results in the suggestion window of the interface also includes:

[0025] The cabling design phase is initiated by using the buttons on the interface, and design analysis instructions, quality recommendation instructions, and timing summary instructions are run simultaneously to analyze the execution of the cabling design phase. The analysis results are displayed in the recommendation window of the interface, including the values ​​of worst-case negative timing margin and worst-case hold timing margin.

[0026] In some embodiments, the method further includes:

[0027] The shape, color, and on / off state of the button can be set to indicate the execution status at different stages.

[0028] In some embodiments, the interface includes an instruction window for displaying analysis instructions.

[0029] Another aspect of the present invention provides a system for improving chip verification efficiency, comprising:

[0030] The display module is configured to display the implementation process of the chip in the FPGA prototype verification, and executes multiple stages of the implementation process sequentially through the human-computer interaction interface.

[0031] The execution module is configured to initiate the execution of the current stage via a button on the interface, and simultaneously run the corresponding analysis commands to analyze the execution status of the current stage and display the analysis results in the suggestion window of the interface; and

[0032] The optimization module is configured to optimize the current stage based on the analysis results, and after the optimization is completed, continue to execute the previous step by clicking the button until the final analysis results meet the verification requirements.

[0033] In another aspect, the present invention provides a computer-readable storage medium storing computer program instructions that, when executed by a processor, implement the above-described method.

[0034] In another aspect, the present invention provides a computer device including a memory and a processor, wherein the memory stores a computer program that, when executed by the processor, performs the above-described method.

[0035] The present invention has at least the following beneficial technical effects:

[0036] The present invention provides a method for improving chip verification efficiency. This method displays and sequentially executes multiple stages of the implementation process through a human-computer interaction interface. Each stage is initiated via buttons on the interface, and corresponding analysis instructions are run synchronously. The analysis results are displayed in the interface's suggestion window, and optimization is performed based on the analysis results. This method presents design problems and suggestions in the implementation process to designers and verifiers through an intuitive human-computer interaction interface. Designers can then re-examine, modify, and optimize their designs based on these suggestions and the exposed design problems, thereby improving design timing convergence efficiency and performance targets. Furthermore, it helps reduce the manpower and time investment in the chip verification process. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of a method for improving chip verification efficiency according to an embodiment of the present invention;

[0039] Figure 2 This is a schematic diagram of a human-computer interaction interface provided according to an embodiment of the present invention;

[0040] Figure 3 This is a flowchart illustrating a method for improving chip verification efficiency according to an embodiment of the present invention.

[0041] Figure 4 This is a schematic diagram of a system for improving chip verification efficiency according to an embodiment of the present invention;

[0042] Figure 5 A schematic diagram of a computer-readable storage medium for implementing a method for improving chip verification efficiency according to an embodiment of the present invention;

[0043] Figure 6 This is a schematic diagram of the hardware structure of a computer device for performing a method to improve chip verification efficiency according to an embodiment of the present invention. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0045] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two different entities or different parameters with the same name. Therefore, "first" and "second" are merely for convenience of expression and should not be construed as limiting the embodiments of the present invention. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as other steps or units inherent in a process, method, system, product, or device that includes a series of steps or units.

[0046] Based on the above objectives, a first aspect of the present invention provides an embodiment of a method for improving chip verification efficiency. Figure 1 The diagram shown is an embodiment of the method for improving chip verification efficiency provided by the present invention. Figure 1 As shown, the embodiments of the present invention include the following steps:

[0047] Step S10: For the chip implementation process in FPGA prototype verification, the implementation process is displayed and executed sequentially through the human-computer interaction interface.

[0048] Step S20: Start the execution of the current stage through the button on the interface, and run the corresponding analysis command synchronously to analyze the execution status of the current stage and display the analysis results in the suggestion window of the interface;

[0049] Step S30: Optimize the current stage based on the analysis results, and continue to execute the previous step by pressing the button after the optimization is completed, until the final analysis results meet the verification requirements.

[0050] In the design flow of FPGA (Field Programmable Gate Array, a semi-custom circuit in the field of application-specific integrated circuits) prototyping, the second stage, the Implementation stage, is completed in the Vivado tool. The implementation stage is often the most repetitive, tedious, and difficult part of the entire design flow. The choice of placement, routing, and timing optimization strategies in this stage directly affects the progress and quality of the prototyping design. The basic stages of design implementation in the commonly used FPGA prototyping Vivado tool include: RTL_design, Synthesis, Opt_design, Place_design, Phys_opt_design, Route_design, and Generate_bitstream.

[0051] Typically, many FPGA designs fail to achieve their expected performance targets for various reasons. The following are some of the main reasons: (1) poor timing constraints; (2) excessive resource utilization; (3) too many control sets; (4) failure to use optimal clock settings; (5) too many logic layers; (6) poor layout planning; (7) routing congestion; (8) excessive signal fan-out.

[0052] The method for improving chip verification efficiency according to this invention displays and executes multiple stages of the implementation process sequentially through a human-computer interaction interface. Each stage is initiated and executed via buttons on the interface, and corresponding analysis instructions are run synchronously. The analysis results are displayed in the suggestion window of the interface, and then the current stage is optimized based on the analysis results. This method can present design problems and suggestions in the implementation process to designers and verifiers through an intuitive human-computer interaction interface, allowing designers to re-examine, modify, and optimize the design based on these suggestions and the exposed design problems. This achieves the goal of improving design timing convergence efficiency and performance targets, and helps reduce the manpower and time investment in the chip verification process.

[0053] In some embodiments, starting the execution of the current stage via a button on the interface and simultaneously running the corresponding analysis command to analyze the execution status of the current stage and displaying the analysis results in the suggestion window of the interface includes: starting the execution of the initial inspection stage via a button on the interface and simultaneously running the quality assessment command to analyze the execution status of the initial inspection stage; in response to the completion of the quality assessment command, displaying the timing convergence value of the chip design and the items to be reviewed in the suggestion window, wherein the timing convergence value is used to determine the degree of convergence of the chip design timing, and the items to be reviewed are the items that have problems in the RTL design stage and the synthesis stage.

[0054] In some embodiments, starting the execution of the current stage via a button on the interface and simultaneously running the corresponding analysis commands to analyze the execution status of the current stage, and displaying the analysis results in the suggestion window of the interface, also includes: starting the execution of the optimization design stage via a button on the interface and simultaneously running the failure query command, the quality suggestion command, and the time series summary command to analyze the execution status of the optimization design stage; in response to the completion of the failure query command, displaying a resource usage table in the suggestion window, which includes the recommended resource usage ratio, the actual resource usage ratio, and the review status; in response to the completion of the quality suggestion command, displaying new optimization suggestions in the suggestion window, which are the cumulative information of the quality optimization suggestions of the previous stage and the current stage; in response to the completion of the time series summary command, determining whether the value of the worst negative time series margin in the suggestion window is negative, and if it is negative, displaying the abnormal indicators of the optimization design stage in the suggestion window, and after analyzing the abnormal indicators through the database analysis module, displaying the corresponding optimization suggestions in the suggestion window.

[0055] In some embodiments, starting the current stage via a button on the interface and simultaneously running corresponding analysis instructions to analyze the execution status of the current stage and displaying the analysis results in the suggestion window of the interface also includes: starting the layout design stage via a button on the interface and simultaneously running hardware usage instructions, design analysis instructions, quality suggestion instructions, and timing summary instructions to analyze the execution status of the layout design stage; in response to the completion of the hardware usage instructions, displaying the utilization rate of various resources inside the FPGA in the suggestion window; and in response to the completion of the design analysis instructions, displaying the logic level and congestion level of the chip design in the suggestion window.

[0056] In some embodiments, starting the execution of the current stage via a button on the interface and simultaneously running the corresponding analysis instructions to analyze the execution status of the current stage and displaying the analysis results in the suggestion window of the interface also includes starting the execution of the cabling design stage via a button on the interface and simultaneously running the design analysis instructions, quality suggestion instructions, and timing summary instructions to analyze the execution status of the cabling design stage and displaying the analysis results in the suggestion window of the interface. The analysis results include the values ​​of worst-case negative timing margin and worst-case hold timing margin.

[0057] In some embodiments, the method further includes: representing the execution state of different stages by setting the shape, color, and on / off state of the button.

[0058] In some embodiments, the interface includes an instruction window for displaying analysis instructions.

[0059] Specific embodiments of the method for improving chip verification efficiency of the present invention are as follows:

[0060] The design framework of this embodiment mainly includes three parts: Front_IDE (front-end integrated development environment) module, database_analysis (database analysis) module, and control_console (control console) module. The Front_IDE module completes the synthesis, compilation, layout, routing, and generation of download files in non-engineering mode; the database_analysis module extracts, filters, matches, and outputs design optimization suggestions in the background; the control_console module displays design status information, design optimization suggestions, and allows input of design optimization commands, serving as a human-computer interaction interface.

[0061] Figure 2 A schematic diagram of a human-computer interaction interface is shown. (For example...) Figure 2As shown, the human-computer interaction interface of the control_console module mainly consists of three parts: the control and status display window, the suggested optimization strategy display window, and the Tcl console window. The control and status display window arranges the main steps of the Vivado design flow from top to bottom: Initial_design_check, Optimization_design, Place_design, Route_design, Phys_opt_design, and Generate bitstream. The circular indicator to the right of each rectangular step button (except for Phys_opt_design in the interactive interface, which is a status bar that only displays the status; if the instruction needs to be executed, it flashes green; after execution, it returns to the initial state) is a status indicator light. When the step is in the "not executing" or "execution completed" state, it displays a white background with a black circle; when the step is executing, it displays a green background with a flashing black circle. The upper right corner of the interactive interface is the Tclconsole window, used for inputting design analysis instructions. The bottom right corner of the interactive interface is the suggestions window. After a Vivado step has finished running, the window displays the usage of the optimization strategies suggested in the design, based on the analysis results and suggestions from the database analysis module, for the designer's reference and use.

[0062] Figure 3 A flowchart illustrating a method for improving chip verification efficiency is shown. (For example...) Figure 3 As shown, the workflow of the console module is as follows:

[0063] 1) In the RTL_design phase, the designer completes the writing, syntax checking, and functional simulation of the RTL (Register Transfer Level) code according to the design requirements.

[0064] 2) In the Synthesis stage, the fully functional RTL code designed in the RTL_design stage is ported to the prototype verification EDA (Electronic Design Automation) provided by prototype verification vendors such as Synopsys and S2C to complete the compilation, splitting and synthesis of the design.

[0065] 3) Clicking the "Initial design check" button in the console module's human-machine interface will trigger the `report_qor_assessment` command. After execution, this command will give a score between 1 and 5 (i.e., timing convergence value). A higher score indicates that the design timing is more likely to converge. A score of 1 or 2 indicates the design is unlikely to converge; a score of 3 indicates the design convergence is unlikely. This command will also provide preliminary statistics on the usage of various resources in the FPGA. This information will be displayed in the "message and suggestions" section of the console module's human-machine interface. Design and verification personnel should pay special attention to items marked "REVIEW" and use this information as a basis for checking RTL design and synthesis.

[0066] 4) In the Opt_design phase, clicking the Opt_design button will automatically run three commands: report_failfast (failure query command), report_qor_suggestions (quality suggestion command), and report_timing_summary (timing summary command). After the report_failfast command completes, a table will appear in the suggestions window. This table reflects the project's resource usage, including the reference (recommended) ratio, actual ratio, and status. Only when the actual usage rates of each item meet the reference can the subsequent processes of the project be relatively reliable. We should pay particular attention to items with a status of "REVIEW," as this indicates that the reference recommended values ​​have been exceeded, potentially posing a risk. Simultaneously, optimization suggestions are provided for several key items such as LUT_Combining and Control Sets. The `report_qor_suggestions` command accumulates the optimization suggestions from the previous run with those from the current run to generate a new optimization suggestion. This command can be executed at any stage of the implementation process. The generated optimization suggestions, `RQSPreSynth.tcl` and `RQSImplCommon.tcl`, are then applied to the Synthesis and Opt_design phases of the design. The generated optimization suggestions are also displayed in the suggestion window for designers to view, filter, and use. After `report_timing_summary` runs, if WNS (Worst Negative Slack) < 0 ns, the command will by default display 30 timing violation path information, timing checks, setup timing, and hold timing summaries in the suggestion window. Simultaneously, the `Database_analysis` module analyzes these timing summaries and provides optimization strategies for factors such as Logic Delay, Net Delay, Clock Skew, and Clock Uncertainty, displaying the corresponding optimization command strategies and suggestions in the console module's suggestion window.

[0067] 5) In the Place_design stage, clicking the Place_design button will automatically run four commands: report_utilization, report_design_analysis, report_qor_suggestions, and report_timing_summary. The usage of report_qor_suggestions and report_timing_summary is the same as described in the Opt_design stage. The report_utilization command analyzes the utilization rate of various resources within the FPGA. report_design_analysis analyzes factors such as the design's logic level, congestion, and congestion level. Similarly, after analyzing these timing summaries and factors, the database analysis module displays the corresponding optimization command strategies and suggestions in the console module's suggestion window. Additionally, if the phys_opt_design command needs to be executed, the phys_opt_design button in the console module will flash green; after execution, it will return to its initial state.

[0068] 6) Route_design stage: In this stage, first click the Route_design button to execute three commands: report_design_analysis, report_qor_suggestions, and report_timing_summary. The workflow of the database analysis and console module in this stage is the same as that in the Place_design stage.

[0069] 7) In the Generate_bitstream stage, the download file is generated.

[0070] In the design framework proposed in this embodiment, the Vivado tool is the executor of various instructions and optimization strategies, and finally uploads the .log and .rpt files from the design flow to the database analysis module. The database analysis module acts like a large database, analyzing and summarizing the .log and .rpt files uploaded by Vivado according to pre-set conditions. Finally, it displays information such as timing violations, logic levels, congestion, congestion levels, and resource utilization, along with corresponding optimization methods and strategies, in the suggestion window of the console module. This provides designers with quick directions and methods for design optimization, improving the efficiency of chip prototype verification.

[0071] A second aspect of this invention also provides a system for improving chip verification efficiency. Figure 4 The diagram shown is a schematic representation of an embodiment of the system for improving chip verification efficiency provided by the present invention. Figure 4 As shown, a system for improving chip verification efficiency includes: a display module 10, configured to display and sequentially execute multiple stages of the implementation process of a chip in FPGA prototype verification through a human-machine interface; an execution module 20, configured to start the execution of the current stage through a button on the interface, and simultaneously run the corresponding analysis instructions to analyze the execution status of the current stage, and display the analysis results in the suggestion window of the interface; and an optimization module 30, configured to optimize the current stage based on the analysis results, and continue to execute the previous step through a button after optimization, until the final analysis result meets the verification requirements.

[0072] A third aspect of the present invention also provides a computer-readable storage medium. Figure 5 A schematic diagram of a computer-readable storage medium illustrating a method for improving chip verification efficiency according to an embodiment of the present invention is shown. Figure 5 As shown, the computer-readable storage medium 3 stores computer program instructions 31. When executed by a processor, the computer program instructions 31 implement the method of any of the above embodiments.

[0073] It should be understood that, where there is no conflict, all the embodiments, features and advantages described above for the method of improving chip verification efficiency according to the present invention are equally applicable to the system and storage medium for improving chip verification efficiency according to the present invention.

[0074] A fourth aspect of the present invention also provides a computer device, including as follows: Figure 6 The memory 402 and processor 401 shown are provided. The memory 402 stores a computer program that, when executed by the processor 401, implements the method of any of the above embodiments.

[0075] like Figure 6 The diagram shown is a hardware structure schematic of an embodiment of a computer device for executing a method to improve chip verification efficiency provided by the present invention. Figure 6 Taking the computer device shown as an example, this computer device includes a processor 401 and a memory 402, and may also include an input device 403 and an output device 404. The processor 401, memory 402, input device 403, and output device 404 can be connected via a bus or other means. Figure 6 Taking a bus connection as an example, input device 403 can receive input digital or character information, as well as generate key signal inputs related to user settings and function control of the system to improve chip verification efficiency. Output device 404 may include display devices such as a display screen.

[0076] Memory 402, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the method for improving chip verification efficiency in this embodiment. Memory 402 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created by using the method for improving chip verification efficiency, etc. In addition, memory 402 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 402 may optionally include memory remotely located relative to processor 401, and these remote memories can be connected to the local module via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0077] The processor 401 executes various functional applications and data processing of the server by running non-volatile software programs, instructions and modules stored in the memory 402, thereby realizing the method of improving chip verification efficiency in the above method embodiment.

[0078] Finally, it should be noted that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functionality of the various illustrative components, blocks, modules, circuits, and steps has been generally described. Whether this functionality is implemented as software or as hardware depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art can implement the functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the embodiments disclosed herein.

[0079] The various exemplary logic blocks, modules, and circuits described herein can be implemented or performed using the following components designed to perform the functions herein: general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP, and / or any other such configuration.

[0080] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0081] It should be understood that, as used herein, the singular form "a" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the associatedly listed items. The embodiment numbers disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0082] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A method for improving chip verification efficiency, characterized in that, Includes the following steps: For the chip implementation process in FPGA prototype verification, multiple stages of the implementation process are displayed and executed sequentially through a human-computer interaction interface. The current stage is initiated by clicking the button on the interface, and the corresponding analysis instructions are run synchronously to analyze the execution status of the current stage and display the analysis results in the suggestion window of the interface. Based on the analysis results, the current stage is optimized, and after the optimization is completed, the previous step is continued by the button until the final analysis results meet the verification requirements. The current stage is initiated by clicking the button on the interface, and the corresponding analysis instructions are executed synchronously to analyze the execution status of the current stage. The analysis results are then displayed in the suggestion window of the interface, including: The initial inspection phase is initiated by clicking the button on the interface, and a quality assessment command is executed simultaneously to analyze the execution of the initial inspection phase. Upon completion of the quality assessment instruction, the timing convergence value of the chip design and the items to be reviewed are displayed in the suggestion window. The timing convergence value is used to determine the degree of convergence of the chip design timing, and the items to be reviewed are those that have problems in the RTL design and synthesis stages. The optimization design phase is initiated by clicking the button on the interface, and failure query instructions, quality suggestion instructions, and timing summary instructions are run simultaneously to analyze the execution status of the optimization design phase. In response to the completion of the failed query instruction, a resource usage table is displayed in the suggestion window. The resource usage table includes the recommended resource usage ratio, the actual resource usage ratio, and the review status. In response to the completion of the quality recommendation instruction, a new optimization recommendation is displayed in the recommendation window. The new optimization recommendation is the cumulative information of the quality optimization recommendations of the previous stage and the quality optimization recommendations of the current stage. In response to the completion of the timing summary instruction, it is determined whether the value of the worst negative timing margin in the suggestion window is negative. If it is negative, the abnormal indicators of the optimization design stage are displayed in the suggestion window, and the corresponding optimization suggestions are displayed in the suggestion window after the abnormal indicators are analyzed by the database analysis module.

2. The method according to claim 1, characterized in that, The process of initiating the current stage via a button on the interface and simultaneously running the corresponding analysis commands to analyze the execution status of the current stage, and displaying the analysis results in the suggestion window of the interface, also includes: The layout design phase is initiated by clicking the button on the interface, and hardware usage instructions, design analysis instructions, quality suggestion instructions, and timing summary instructions are run simultaneously to analyze the execution of the layout design phase. In response to the completion of the hardware usage instruction, the utilization rate of various resources inside the FPGA is displayed in the suggestion window; Upon completion of the design analysis command, the logic level and congestion level of the chip design are displayed in the suggestion window.

3. The method according to claim 1, characterized in that, The process of initiating the current stage via a button on the interface and simultaneously running the corresponding analysis commands to analyze the execution status of the current stage, and displaying the analysis results in the suggestion window of the interface, also includes: The routing design phase is initiated by clicking the button on the interface, and design analysis instructions, quality recommendation instructions, and timing summary instructions are run simultaneously to analyze the execution of the routing design phase. The analysis results are displayed in the recommendation window of the interface, and the analysis results include the values ​​of worst-case negative timing margin and worst-case hold timing margin.

4. The method according to claim 1, characterized in that, Also includes: The shape, color, and on / off state of the button can be set to indicate the execution status at different stages.

5. The method according to claim 1, characterized in that, The interface includes a command window, which is used to display the analysis commands.

6. A system for improving chip verification efficiency, characterized in that, include: The display module is configured to display the implementation process of the chip in the FPGA prototype verification through a human-computer interaction interface and execute multiple stages of the implementation process in sequence. The execution module is configured to initiate the execution of the current stage via a button on the interface, and simultaneously run the corresponding analysis instructions to analyze the execution status of the current stage and display the analysis results in the suggestion window of the interface. as well as The optimization module is configured to optimize the current stage based on the analysis results, and continue to execute the previous step via the button after the optimization is completed, until the final analysis results meet the verification requirements. The execution module is also configured to: The initial inspection phase is initiated by clicking the button on the interface, and a quality assessment command is executed simultaneously to analyze the execution of the initial inspection phase. Upon completion of the quality assessment instruction, the timing convergence value of the chip design and the items to be reviewed are displayed in the suggestion window. The timing convergence value is used to determine the degree of convergence of the chip design timing, and the items to be reviewed are those that have problems in the RTL design and synthesis stages. The optimization design phase is initiated by clicking the button on the interface, and failure query instructions, quality suggestion instructions, and timing summary instructions are run simultaneously to analyze the execution status of the optimization design phase. In response to the completion of the failed query instruction, a resource usage table is displayed in the suggestion window. The resource usage table includes the recommended resource usage ratio, the actual resource usage ratio, and the review status. In response to the completion of the quality recommendation instruction, a new optimization recommendation is displayed in the recommendation window. The new optimization recommendation is the cumulative information of the quality optimization recommendations of the previous stage and the quality optimization recommendations of the current stage. In response to the completion of the timing summary instruction, it is determined whether the value of the worst negative timing margin in the suggestion window is negative. If it is negative, the abnormal indicators of the optimization design stage are displayed in the suggestion window, and the corresponding optimization suggestions are displayed in the suggestion window after the abnormal indicators are analyzed by the database analysis module.

7. A computer-readable storage medium, characterized in that, The system stores computer program instructions that, when executed by a processor, implement the method as described in any one of claims 1-5.

8. A computer device, comprising a memory and a processor, characterized in that, The memory stores a computer program, which, when executed by the processor, performs the method as described in any one of claims 1-5.

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