Method for delay-driven floor assignment in very large scale integration
By introducing a delay-driven layer allocation method, priority calculation, and congestion cost adjustment into VLSI, the problem of uneven utilization of routing resources during layer allocation is solved, resulting in lower latency and fewer vias, thus improving chip design quality.
CN116341473BActive Publication Date: 2026-07-03FUZHOU UNIV
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- FUZHOU UNIV
- Filing Date
- 2022-11-12
- Publication Date
- 2026-07-03
Smart Images
Figure CN116341473B_ABST
Abstract
This invention proposes a delay-driven layer allocation method for VLSI (Very Large Scale Integration) systems, improving the use of non-default rule lines and aiming to guide net routing density balance during the layer allocation process. The method calculates net priorities based on the 2D routing results of the overall routing phase, prioritizing nets with higher priorities. A congestion cost adjustment strategy is used to evaluate the average routing situation of nets on grid edges for all nets. Simultaneously, an objective function adjustment strategy incorporates the usage of 3D grid edges into the objective function, reducing edge overflow during layer allocation and improving the quality of layer allocation. The method includes the following steps: Step S1, Priority-Driven Layer Allocation Phase; Step S2, Layer Allocation Phase Based on Routing Density Balance; Step S3, Post-Optimization Phase. This invention focuses on improving the use of non-default rule lines, guiding net routing density balance during the layer allocation process.
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